@@ -15564,26 +15564,6 @@ static void ggml_sycl_mul_mat_batched_sycl(const ggml_tensor *src0,
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const int64_t r2 = ne12/ne02;
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const int64_t r3 = ne13/ne03;
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- #if 0
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- // use syclGemmEx
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- {
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- for (int i13 = 0; i13 < ne13; ++i13) {
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- for (int i12 = 0; i12 < ne12; ++i12) {
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- int i03 = i13 / r3;
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- int i02 = i12 / r2;
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-
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- SYCL_CHECK(
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- syclGemmEx(g_sycl_handles[g_main_device], CUBLAS_OP_T, CUBLAS_OP_N,
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- ne01, ne11, ne10,
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- alpha, (const char *) src0_as_f16 + i02*src0->nb[2] + i03*src0->nb[3] , SYCL_R_16F, nb01/sizeof(half),
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- (const char *) src1_as_f16 + i12*src1->nb[2]/2 + i13*src1->nb[3]/2, SYCL_R_16F, nb11/sizeof(float),
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- beta, ( char *) dst_t + i12*nbd2 + i13*nbd3, cu_data_type, ne01,
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- cu_compute_type,
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- CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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- }
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- }
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- }
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- #else
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if (r2 == 1 && r3 == 1 && src0->nb[2]*src0->ne[2] == src0->nb[3] && src1->nb[2]*src1->ne[2] == src1->nb[3]) {
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// there is no broadcast and src0, src1 are contiguous across dims 2, 3
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SYCL_CHECK(CHECK_TRY_ERROR(dpct::gemm_batch(
@@ -15595,7 +15575,6 @@ static void ggml_sycl_mul_mat_batched_sycl(const ggml_tensor *src0,
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nb11 / nb10, nb12 / nb10, beta,
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(char *)dst_t, cu_data_type, ne01, nb2 / nb0,
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ne12 * ne13, cu_compute_type)));
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- g_sycl_handles[g_main_device]->wait();
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} else {
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const int ne23 = ne12*ne13;
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@@ -15626,7 +15605,7 @@ static void ggml_sycl_mul_mat_batched_sycl(const ggml_tensor *src0,
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nb02, nb03, nb12_scaled, nb13_scaled,
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nbd2, nbd3, r2, r3, item_ct1);
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});
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- }).wait() ;
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+ });
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}
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SYCL_CHECK(CHECK_TRY_ERROR(dpct::gemm_batch(
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*g_sycl_handles[g_main_device], oneapi::mkl::transpose::trans,
@@ -15637,9 +15616,7 @@ static void ggml_sycl_mul_mat_batched_sycl(const ggml_tensor *src0,
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dpct::library_data_t::real_half, nb11 / nb10, beta,
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(void **)(ptrs_dst.get() + 0 * ne23), cu_data_type, ne01, ne23,
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cu_compute_type)));
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- g_sycl_handles[g_main_device]->wait();
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}
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- #endif
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if (no_mixed_dtypes) {
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const to_fp32_sycl_t to_fp32_sycl = ggml_get_to_fp32_sycl(GGML_TYPE_F16);
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