arm: Add support for Arm Cortex-M85 CPU.

This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is
an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default.

-mpcu=cortex-m85 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp.

Also following options are provided to disable default features.
+nomve.fp (disables MVE Floating point)
+nomve (disables MVE Integer and MVE Floating point)
+nodsp (disables dsp, MVE Integer and MVE Floating point)
+nopacbti (disables pacbti)
+nofp (disables floating point and MVE floating point)

gcc/ChangeLog:

2022-08-12  Srinath Parvathaneni  <[email protected]>

	* config/arm/arm-cpus.in (cortex-m85): Define new CPU.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m85.
	* (-mfix-cmse-cve-2021-35465): Likewise.

gcc/testsuite/ChangeLog:

2022-08-12  Srinath Parvathaneni  <[email protected]>

	* gcc.target/arm/multilib.exp: Add tests for cortex-m85.

Author: sripar01

gcc/config/arm/arm-cpus.in

@@ -1672,6 +1672,21 @@ begin cpu star-mc1
  costs v7m
 end cpu star-mc1
 
+begin cpu cortex-m85
+ cname cortexm85
+ tune flags LDSCHED
+ architecture armv8.1-m.main+pacbti+mve.fp+fp.dp
+ option nopacbti remove pacbti
+ option nomve.fp remove mve_float
+ option nomve remove mve mve_float
+ option nofp remove ALL_FP mve_float
+ option nodsp remove MVE mve_float
+ isa quirk_no_asmcpu quirk_vlldm
+ costs v7m
+ part 0xd23
+ vendor 41
+end cpu cortex-m85
+
 # V8 R-profile implementations.
 begin cpu cortex-r52
  cname cortexr52

gcc/config/arm/arm-tables.opt

@@ -288,6 +288,9 @@ Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55)
 EnumValue
 Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1)
 
+EnumValue
+Enum(processor_type) String(cortex-m85) Value( TARGET_CPU_cortexm85)
+
 EnumValue
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
 

gcc/config/arm/arm-tune.md

@@ -46,9 +46,10 @@
 	cortexa73cortexa53,cortexa55,cortexa75,
 	cortexa76,cortexa76ae,cortexa77,
 	cortexa78,cortexa78ae,cortexa78c,
-	cortexa710,cortexx1,cortexx1c,neoversen1,
-	cortexa75cortexa55,cortexa76cortexa55,neoversev1,
-	neoversen2,cortexm23,cortexm33,
-	cortexm35p,cortexm55,starmc1,
-	cortexr52,cortexr52plus"
+	cortexa710,cortexx1,cortexx1c,
+	neoversen1,cortexa75cortexa55,cortexa76cortexa55,
+	neoversev1,neoversen2,cortexm23,
+	cortexm33,cortexm35p,cortexm55,
+	starmc1,cortexm85,cortexr52,
+	cortexr52plus"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))

gcc/doc/invoke.texi

@@ -22097,8 +22097,8 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus},
 @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
-@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-x1}, @samp{cortex-x1c},
-@samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
+@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1},
+@samp{cortex-x1c}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
 @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
 @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626},
@@ -22162,17 +22162,22 @@ The following extension options are common to the listed CPUs:
 
 @table @samp
 @item +nodsp
-Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}
-and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE)
-integer and single precision floating-point instructions on @samp{cortex-m55}.
+Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p},
+@samp{cortex-m55} and @samp{cortex-m85}. Also disable the M-Profile Vector
+Extension (MVE) integer and single precision floating-point instructions on
+@samp{cortex-m55} and @samp{cortex-m85}.
+
+@item +nopacbti
+Disable the Pointer Authentication and Branch Target Identification Extension
+on @samp{cortex-m85}.
 
 @item +nomve
 Disable the M-Profile Vector Extension (MVE) integer and single precision
-floating-point instructions on @samp{cortex-m55}.
+floating-point instructions on @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +nomve.fp
 Disable the M-Profile Vector Extension (MVE) single precision floating-point
-instructions on @samp{cortex-m55}.
+instructions on @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +cdecp0, +cdecp1, ... , +cdecp7
 Enable the Custom Datapath Extension (CDE) on selected coprocessors according
@@ -22184,7 +22189,8 @@ Disables the floating-point instructions on @samp{arm9e},
 @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
 @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}
-and @samp{cortex-m55}.
+@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p},
+@samp{cortex-m55} and @samp{cortex-m85}.
 Disables the floating-point and SIMD instructions on
 @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
@@ -22524,9 +22530,9 @@ Development Tools Engineering Specification", which can be found on
 Mitigate against a potential security issue with the @code{VLLDM} instruction
 in some M-profile devices when using CMSE (CVE-2021-365465).  This option is
 enabled by default when the option @option{-mcpu=} is used with
-@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55} or @code{star-mc1}.
-The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable
-the mitigation.
+@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55}, @code{cortex-m85}
+or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} can be used
+to disable the mitigation.
 
 @item -mstack-protector-guard=@var{guard}
 @itemx -mstack-protector-guard-offset=@var{offset}

gcc/testsuite/gcc.target/arm/multilib.exp

@@ -524,6 +524,11 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp"
 	{-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp"
+	{-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m85+nopacbti+nodsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m85+nopacbti+nomve.fp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard"
 	{-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+dp/hard"
 	{-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard"
@@ -549,6 +554,15 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard"
 	{-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
 	{-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard"
+	{-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m85+nopacbti+nodsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+mve/hard"
+	{-mcpu=cortex-m85+nopacbti+nomve.fp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m85 -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard"
+	{-mcpu=cortex-m85+nomve.fp -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard}  "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard"
+	{-mcpu=cortex-m85+nomve -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard}  "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard"
+	{-mcpu=cortex-m85+nodsp -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard}  "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard"
 	{-mcpu=cortex-m0 -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp"
 	{-mcpu=cortex-m1 -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp"
 	{-mcpu=cortex-m3 -mfpu=auto -mfloat-abi=softfp} "thumb/v7-m/nofp"
@@ -598,6 +612,15 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp"
 	{-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp"
 	{-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp"
+	{-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=softfp}  "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m85+nopacbti+nodsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m85+nopacbti+nomve.fp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m85 -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp"
+	{-mcpu=cortex-m85+nomve.fp -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp}  "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp"
+	{-mcpu=cortex-m85+nomve -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp}  "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp"
+	{-mcpu=cortex-m85+nodsp -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp}  "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp"
 	{-march=armv6-m -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp"
 	{-march=armv7-m -mfpu=auto -mfloat-abi=soft} "thumb/v7-m/nofp"
 	{-march=armv7e-m -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp"