[ESP32P4] Fix imm ranges.

sstefan1 · sstefan1 · commit 5df1c75d1345 · 2025-08-07T14:08:35.000+02:00
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -516,6 +516,11 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            ((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
   }
 
+  bool isOffset_256_2() const {
+    return isImm(-256, 254) &&
+           ((cast<MCConstantExpr>(getImm())->getValue() & 0x1) == 0);
+  }
+
   bool isOffset_256_4() const {
     return isImm(-512, 508) &&
            ((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -511,6 +511,14 @@ static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, int64_t Imm,
                                                int64_t Address,
                                                const void *Decoder);
 
+static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
+                                              int64_t Address,
+                                              const void *Decoder);
+
+static DecodeStatus decodeOffset_256_2Operand(MCInst &Inst, int64_t Imm,
+                                              int64_t Address,
+                                              const void *Decoder);
+
 static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm,
                                               int64_t Address,
                                               const void *Decoder);
@@ -701,11 +709,27 @@ static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, int64_t Imm,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm,
+static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
+                                      int64_t Address, const void *Decoder) {
+  assert(isUInt<8>(Imm) && "Invalid immediate");
+  Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_256_2Operand(MCInst &Inst, int64_t Imm,
                                               int64_t Address,
                                               const void *Decoder) {
   assert(isInt<16>(Imm) && "Invalid immediate");
-  auto ImmSigned = SignExtend64<4>(Imm);
+  auto ImmSigned = SignExtend64<8>(Imm);
+  Inst.addOperand(MCOperand::createImm(ImmSigned * 2));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm,
+                                              int64_t Address,
+                                              const void *Decoder) {
+  assert(isInt<32>(Imm) && "Invalid immediate");
+  auto ImmSigned = SignExtend64<8>(Imm);
   Inst.addOperand(MCOperand::createImm(ImmSigned * 4));
   return MCDisassembler::Success;
 }
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -415,6 +415,19 @@ void RISCVInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI,
   }
 }
 
+void RISCVInstPrinter::printOffset_256_2_AsmOperand(const MCInst *MI, int OpNum,
+  const MCSubtargetInfo &STI,
+  raw_ostream &O) {
+if (MI->getOperand(OpNum).isImm()) {
+int64_t Value = MI->getOperand(OpNum).getImm();
+assert((Value >= -256 && Value <= 254 && (Value & 0x1) == 0) &&
+       "Invalid argument, value must be in range [-256,254], first 1 bits "
+       "should be zero");
+O << Value;
+} else
+printOperand(MI, OpNum, STI, O);
+}
+
 void RISCVInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
                                                     const MCSubtargetInfo &STI,
                                                     raw_ostream &O) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -91,6 +91,8 @@ class RISCVInstPrinter : public MCInstPrinter {
   void printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O);
+  void printOffset_256_2_AsmOperand(const MCInst *MI, int OpNum,
+                                    const MCSubtargetInfo &STI, raw_ostream &O);
   void printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
                                     const MCSubtargetInfo &STI, raw_ostream &O);
 };
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -135,6 +135,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
   int16_t getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
+  
+  int16_t getOffset_256_2OpValue(const MCInst &MI, unsigned OpNo,
+                                  SmallVectorImpl<MCFixup> &Fixups,
+                                  const MCSubtargetInfo &STI) const;
 
   int16_t getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
@@ -729,6 +733,19 @@ RISCVMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo,
   return Res / 16;
 }
 
+int16_t
+RISCVMCCodeEmitter::getOffset_256_2OpValue(const MCInst &MI, unsigned OpNo,
+                                           SmallVectorImpl<MCFixup> &Fixups,
+                                           const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  int16_t Res = static_cast<int16_t>(MO.getImm());
+
+  assert(((Res >= -256) && (Res <= 254) && ((Res & 0x1) == 0)) &&
+         "Unexpected operand value!");
+
+  return Res / 2;
+}
+
 int16_t
 RISCVMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
                                            SmallVectorImpl<MCFixup> &Fixups,
diff --git a/llvm/lib/Target/RISCV/RISCVESP32P4Operands.td b/llvm/lib/Target/RISCV/RISCVESP32P4Operands.td
@@ -53,7 +53,15 @@ def offset_256_16: Immediate<i32, [{ return (Imm >= -2048 && Imm <= 2032) && ((I
   let DecoderMethod = "decodeOffset_256_16Operand";
 }
 
-// offset_256_4 predicate - 4-bit signed immediate in the range [-512,508] with an interval
+// offset_256_2 predicate - 8-bit signed immediate in the range [-256,254] with an interval
+// of 2.
+def Offset_256_2_AsmOperand: P4ImmAsmOperand<"Offset_256_2">;
+def offset_256_2: Immediate<i32, [{ return (Imm >= -256 && Imm <= 254) && ((Imm & 0x1) == 0); }], "Offset_256_2_AsmOperand"> {
+  let EncoderMethod = "getOffset_256_2OpValue";
+  let DecoderMethod = "decodeOffset_256_2Operand";
+}
+
+// offset_256_4 predicate - 8-bit signed immediate in the range [-512,508] with an interval
 // of 4.
 def Offset_256_4_AsmOperand: P4ImmAsmOperand<"Offset_256_4">;
 def offset_256_4: Immediate<i32, [{ return (Imm >= -512 && Imm <= 508) && ((Imm & 0x3) == 0); }], "Offset_256_4_AsmOperand"> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td b/llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td
@@ -12527,7 +12527,7 @@ def ESP_LDQA_U8_128_XP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2,
 				"!esp_ldqa_u8_128_xp_p $rs1, $rs2",
 			[(set GPRPIE:$rs1r, (int_riscv_esp_ldqa_u8_128_xp GPRPIE:$rs2, GPRPIE:$rs1))]>;
 
-def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564),
+def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_2:$off2564),
                    "esp.vldbc.16.ip\t $qu, $rs1, $off2564", []> 
 {
   bits<5> rs1;
@@ -12566,7 +12566,7 @@ def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1,
 }
 
 let usesCustomInserter = 1, Constraints = "$rs1r = $rs1" in 
-def ESP_VLDBC_16_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu),
+def ESP_VLDBC_16_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_2:$off2564, imm8:$qu),
 				"!esp_vldbc_16_ip_p $qu, $rs1, $off2564",
 			[(set GPRPIE:$rs1r, (int_riscv_esp_vldbc_16_ip GPRPIE:$rs1, timm:$off2564, timm:$qu))]>;
 
@@ -12705,7 +12705,7 @@ def ESP_VLDBC_32_XP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPR
 				"!esp_vldbc_32_xp_p $qu, $rs1, $rs2",
 			[(set GPRPIE:$rs1r, (int_riscv_esp_vldbc_32_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu))]>;
 
-def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564),
+def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, imm8:$off2564),
                    "esp.vldbc.8.ip\t $qu, $rs1, $off2564", []> 
 {
   bits<5> rs1;
@@ -12744,7 +12744,7 @@ def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, o
 }
 
 let usesCustomInserter = 1, Constraints = "$rs1r = $rs1" in 
-def ESP_VLDBC_8_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu),
+def ESP_VLDBC_8_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, imm8:$off2564, imm8:$qu),
 				"!esp_vldbc_8_ip_p $qu, $rs1, $off2564",
 			[(set GPRPIE:$rs1r, (int_riscv_esp_vldbc_8_ip GPRPIE:$rs1, timm:$off2564, timm:$qu))]>;
 
diff --git a/llvm/test/CodeGen/RISCV/esp32p4.ll b/llvm/test/CodeGen/RISCV/esp32p4.ll
@@ -470,7 +470,7 @@ define void @test(){
 ; CHECK-NEXT:    li a1, 6
 ; CHECK-NEXT:    esp.vldbc.32.xp q3, a1, a5
 ; CHECK-NEXT:    li a1, 6
-; CHECK-NEXT:    esp.vldbc.8.ip q4, a1, -492
+; CHECK-NEXT:    esp.vldbc.8.ip q4, a1, -112
 ; CHECK-NEXT:    li a1, 9
 ; CHECK-NEXT:    esp.vldbc.8.xp q6, a1, a5
 ; CHECK-NEXT:    li a1, 10
@@ -867,7 +867,7 @@ define void @test(){
 	%142 = tail call i32 @llvm.riscv.esp.vldbc.16.xp(i32 3, i32 2, i32 2)
 	%143 = tail call i32 @llvm.riscv.esp.vldbc.32.ip(i32 8, i32 396, i32 5)
 	%144 = tail call i32 @llvm.riscv.esp.vldbc.32.xp(i32 14, i32 6, i32 3)
-	%145 = tail call i32 @llvm.riscv.esp.vldbc.8.ip(i32 6, i32 -492, i32 4)
+	%145 = tail call i32 @llvm.riscv.esp.vldbc.8.ip(i32 6, i32 -112, i32 4)
 	%146 = tail call i32 @llvm.riscv.esp.vldbc.8.xp(i32 14, i32 9, i32 6)
 	%147 = tail call i32 @llvm.riscv.esp.vldext.s16.ip(i32 10, i32 32, i32 6, i32 2)
 	%148 = tail call i32 @llvm.riscv.esp.vldext.s16.xp(i32 11, i32 0, i32 2, i32 6)
diff --git a/llvm/test/MC/RISCV/esp32p4-valid.s b/llvm/test/MC/RISCV/esp32p4-valid.s
@@ -570,16 +570,16 @@ esp.ldqa.u8.128.ip a2, 1200
 # CHECK: esp.ldqa.u8.128.ip	 a2, 1200       # encoding: [0xbb,0x56,0x42,0x20]
 esp.ldqa.u8.128.xp a2, a5
 # CHECK: esp.ldqa.u8.128.xp	 a2, a5         # encoding: [0x5b,0x50,0x72,0x13]
-esp.vldbc.16.ip q4, a3, 408
-# CHECK: esp.vldbc.16.ip	 q4, a3, 408            # encoding: [0x3b,0xb0,0x32,0xb6]
+esp.vldbc.16.ip q4, a3, 200
+# CHECK: esp.vldbc.16.ip	 q4, a3, 200            # encoding: [0x3b,0xb0,0x22,0xb6]
 esp.vldbc.16.xp q5, a2, a1
 # CHECK: esp.vldbc.16.xp	 q5, a2, a1             # encoding: [0x5f,0x54,0x32,0x96]
 esp.vldbc.32.ip q6, a2, -176
 # CHECK: esp.vldbc.32.ip	 q6, a2, -176           # encoding: [0x3b,0x38,0xa2,0xce]
 esp.vldbc.32.xp q0, a1, a2
 # CHECK: esp.vldbc.32.xp	 q0, a1, a2             # encoding: [0x5f,0xc0,0x41,0x8e]
-esp.vldbc.8.ip q6, a0, 200
-# CHECK: esp.vldbc.8.ip	 q6, a0, 200            # encoding: [0x3b,0x38,0x91,0x16]
+esp.vldbc.8.ip q6, a0, 112
+# CHECK: esp.vldbc.8.ip	 q6, a0, 112            # encoding: [0x3b,0x38,0x81,0x36]
 esp.vldbc.8.xp q5, a4, a2
 # CHECK: esp.vldbc.8.xp	 q5, a4, a2             # encoding: [0x5f,0x54,0x43,0x86]
 esp.vldext.s16.ip q4, q1, a3, -112
