@@ -57,33 +57,36 @@ extern void tcpipInit();
5757static eth_clock_mode_t eth_clock_mode = ETH_CLK_MODE;
5858
5959#if CONFIG_ETH_RMII_CLK_INPUT
60+ /*
6061static void emac_config_apll_clock(void)
6162{
62- /* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) */
63+ // apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
6364 rtc_xtal_freq_t rtc_xtal_freq = rtc_clk_xtal_freq_get();
6465 switch (rtc_xtal_freq) {
6566 case RTC_XTAL_FREQ_40M: // Recommended
66- /* 50 MHz = 40MHz * (4 + 6) / (2 * (2 + 2) = 50.000 */
67- /* sdm0 = 0, sdm1 = 0, sdm2 = 6, o_div = 2 */
67+ // 50 MHz = 40MHz * (4 + 6) / (2 * (2 + 2) = 50.000
68+ // sdm0 = 0, sdm1 = 0, sdm2 = 6, o_div = 2
6869 rtc_clk_apll_enable(true, 0, 0, 6, 2);
6970 break;
7071 case RTC_XTAL_FREQ_26M:
71- /* 50 MHz = 26MHz * (4 + 15 + 118 / 256 + 39/65536) / ((3 + 2) * 2) = 49.999992 */
72- /* sdm0 = 39, sdm1 = 118, sdm2 = 15, o_div = 3 */
72+ // 50 MHz = 26MHz * (4 + 15 + 118 / 256 + 39/65536) / ((3 + 2) * 2) = 49.999992
73+ // sdm0 = 39, sdm1 = 118, sdm2 = 15, o_div = 3
7374 rtc_clk_apll_enable(true, 39, 118, 15, 3);
7475 break;
7576 case RTC_XTAL_FREQ_24M:
76- /* 50 MHz = 24MHz * (4 + 12 + 255 / 256 + 255/65536) / ((2 + 2) * 2) = 49.499977 */
77- /* sdm0 = 255, sdm1 = 255, sdm2 = 12, o_div = 2 */
77+ // 50 MHz = 24MHz * (4 + 12 + 255 / 256 + 255/65536) / ((2 + 2) * 2) = 49.499977
78+ // sdm0 = 255, sdm1 = 255, sdm2 = 12, o_div = 2
7879 rtc_clk_apll_enable(true, 255, 255, 12, 2);
7980 break;
8081 default: // Assume we have a 40M xtal
8182 rtc_clk_apll_enable(true, 0, 0, 6, 2);
8283 break;
8384 }
8485}
86+ */
8587#endif
8688
89+ /*
8790static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
8891#if CONFIG_IDF_TARGET_ESP32
8992 if(eth_clock_mode > ETH_CLOCK_GPIO17_OUT){
@@ -168,7 +171,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
168171#endif
169172 return ESP_OK;
170173}
171-
174+ */
172175
173176
174177/* *
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