fix(spi): Fix bus clock for ESP32-P4

Author: P-R-O-C-H-Y

cores/esp32/esp32-hal-spi.c

@@ -60,6 +60,7 @@
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/ets_sys.h"
 #include "esp32p4/rom/gpio.h"
+#include "hal/spi_ll.h"
 #else
 #error Target CONFIG_IDF_TARGET is not supported
 #endif
@@ -639,9 +640,6 @@ spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t
   } else if (spi_num == HSPI) {
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST);
-  } else {
-    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
-    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
   }
 #elif CONFIG_IDF_TARGET_ESP32S3
   if (spi_num == FSPI) {
@@ -662,6 +660,29 @@ spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
   }
+#elif CONFIG_IDF_TARGET_ESP32P4
+  if (spi_num == FSPI) {
+    PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_GPSPI2_MODULE, ref_count) {
+      if (ref_count == 0) {
+        PERIPH_RCC_ATOMIC() {
+          spi_ll_enable_bus_clock(SPI2_HOST, true);
+          spi_ll_reset_register(SPI2_HOST);
+          spi_ll_enable_clock(SPI2_HOST, true);
+
+        }
+      }
+    }
+  } else if (spi_num == HSPI) {
+    PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_GPSPI3_MODULE, ref_count) {
+      if (ref_count == 0) {
+        PERIPH_RCC_ATOMIC() {
+          spi_ll_enable_bus_clock(SPI3_HOST, true);
+          spi_ll_reset_register(SPI3_HOST);
+          spi_ll_enable_clock(SPI3_HOST, true);
+        }
+      }
+    }
+  }
 #elif defined(__PERIPH_CTRL_ALLOW_LEGACY_API)
   periph_ll_reset(PERIPH_SPI2_MODULE);
   periph_ll_enable_clk_clear_rst(PERIPH_SPI2_MODULE);