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cores/esp8266/core_esp8266_features.cpp: Make precache() cleaner and more efficient #8903

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Apr 5, 2023
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14 changes: 7 additions & 7 deletions cores/esp8266/core_esp8266_features.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -38,13 +38,13 @@ void precache(void *f, uint32_t bytes) {
// page (ie 1 word in 8) for this to work.
#define CACHE_PAGE_SIZE 32

uint32_t a0;
__asm__("mov.n %0, a0" : "=r"(a0));
uint32_t lines = (bytes/CACHE_PAGE_SIZE)+2;
volatile uint32_t *p = (uint32_t*)((f ? (uint32_t)f : a0) & ~0x03);
uint32_t x;
for (uint32_t i=0; i<lines; i++, p+=CACHE_PAGE_SIZE/sizeof(uint32_t)) x=*p;
(void)x;
uint32_t lines = (bytes / CACHE_PAGE_SIZE) + 2;
uint32_t *p = (uint32_t*)((uint32_t)(f ? f : __builtin_return_address(0)) & ~0x03);
do {
__asm__ volatile ("" : : "r"(*p)); // guarantee that the value of *p will be in some register (forced load)
p += CACHE_PAGE_SIZE / sizeof(uint32_t);
} while (--lines);
__sync_synchronize(); // full memory barrier, mapped to MEMW in Xtensa
}

/** based on efuse data, we could determine what type of chip this is
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