Add support for interrupt handling

.gitignore

@@ -1,5 +1,5 @@
 /target
 **/*.rs.bk
 Cargo.lock
-svd/esp32.svd
+#svd/esp32.svd
 src/

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "esp32"
-version = "0.2.2"
+version = "0.3.0"
 authors = ["Scott Mabin <[email protected]>"]
 edition = "2018"
 readme = "README.md"
@@ -21,4 +21,10 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 bare-metal = "0.2"
-vcell = "0.1"
+vcell = "0.1"
+xtensa-lx6-rt = { git = "https://github.com/esp-rs/xtensa-lx6-rt.git" }
+
+[features]
+default=["rt"]
+
+rt=[]

Makefile

@@ -12,7 +12,7 @@ patch:
 	mv svd/$(BASE).patched svd/$(OUTPUT)
 
 generate:
-	svd2rust --target none -i svd/$(OUTPUT)
+	svd2rust --target esp32 -i svd/$(OUTPUT)
 
 form:
 	form -i lib.rs -o src/
@@ -23,4 +23,4 @@ fmt:
 
 build:
 	cargo clean
-	cargo build
+	cargo xbuild --target xtensa-esp32-none-elf

build.rs

@@ -0,0 +1,16 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

device.x

@@ -0,0 +1,76 @@
+PROVIDE(WIFI_MAC_INTR = DefaultHandler);
+PROVIDE(WIFI_MAC_NMI = DefaultHandler);
+PROVIDE(WIFI_BB_INTR = DefaultHandler);
+PROVIDE(BT_MAC_INTR = DefaultHandler);
+PROVIDE(BT_BB_INTR = DefaultHandler);
+PROVIDE(BT_BB_NMI = DefaultHandler);
+PROVIDE(RWBT_INTR = DefaultHandler);
+PROVIDE(RWBLE_INTR = DefaultHandler);
+PROVIDE(RWBT_NMI = DefaultHandler);
+PROVIDE(RWBLE_NMI = DefaultHandler);
+PROVIDE(SLC0_INTR = DefaultHandler);
+PROVIDE(SLC1_INTR = DefaultHandler);
+PROVIDE(UHCI0_INTR = DefaultHandler);
+PROVIDE(UHCI1_INTR = DefaultHandler);
+PROVIDE(TG0_T0_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG0_T1_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG0_WDT_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG0_LACT_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG1_T0_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG1_T1_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG1_WDT_LEVEL_INTR = DefaultHandler);
+PROVIDE(TG1_LACT_LEVEL_INTR = DefaultHandler);
+PROVIDE(GPIO_INTR = DefaultHandler);
+PROVIDE(GPIO_NMI = DefaultHandler);
+PROVIDE(FROM_CPU_INTR0 = DefaultHandler);
+PROVIDE(FROM_CPU_INTR1 = DefaultHandler);
+PROVIDE(FROM_CPU_INTR2 = DefaultHandler);
+PROVIDE(FROM_CPU_INTR3 = DefaultHandler);
+PROVIDE(SPI0_INTR = DefaultHandler);
+PROVIDE(SPI1_INTR = DefaultHandler);
+PROVIDE(SPI2_INTR = DefaultHandler);
+PROVIDE(SPI3_INTR = DefaultHandler);
+PROVIDE(I2S0_INTR = DefaultHandler);
+PROVIDE(I2S1_INTR = DefaultHandler);
+PROVIDE(UART0_INTR = DefaultHandler);
+PROVIDE(UART1_INTR = DefaultHandler);
+PROVIDE(UART2_INTR = DefaultHandler);
+PROVIDE(SDIO_HOST_INTR = DefaultHandler);
+PROVIDE(ETH_MAC_INTR = DefaultHandler);
+PROVIDE(PWM0_INTR = DefaultHandler);
+PROVIDE(PWM1_INTR = DefaultHandler);
+PROVIDE(PWM2_INTR = DefaultHandler);
+PROVIDE(PWM3_INTR = DefaultHandler);
+PROVIDE(LEDC_INTR = DefaultHandler);
+PROVIDE(EFUSE_INTR = DefaultHandler);
+PROVIDE(CAN_INTR = DefaultHandler);
+PROVIDE(RTC_CORE_INTR = DefaultHandler);
+PROVIDE(RMT_INTR = DefaultHandler);
+PROVIDE(PCNT_INTR = DefaultHandler);
+PROVIDE(I2C_EXT0_INTR = DefaultHandler);
+PROVIDE(I2C_EXT1_INTR = DefaultHandler);
+PROVIDE(RSA_INTR = DefaultHandler);
+PROVIDE(SPI1_DMA_INTR = DefaultHandler);
+PROVIDE(SPI2_DMA_INTR = DefaultHandler);
+PROVIDE(SPI3_DMA_INTR = DefaultHandler);
+PROVIDE(WDT_INTR = DefaultHandler);
+PROVIDE(TIMER1_INTR = DefaultHandler);
+PROVIDE(TIMER2_INTR = DefaultHandler);
+PROVIDE(TG0_T0_EDGE_INTR = DefaultHandler);
+PROVIDE(TG0_T1_EDGE_INTR = DefaultHandler);
+PROVIDE(TG0_WDT_EDGE_INTR = DefaultHandler);
+PROVIDE(TG0_LACT_EDGE_INTR = DefaultHandler);
+PROVIDE(TG1_T0_EDGE_INTR = DefaultHandler);
+PROVIDE(TG1_T1_EDGE_INTR = DefaultHandler);
+PROVIDE(TG1_WDT_EDGE_INTR = DefaultHandler);
+PROVIDE(TG1_LACT_EDGE_INTR = DefaultHandler);
+PROVIDE(MMU_IA_INTR = DefaultHandler);
+PROVIDE(MPU_IA_INTR = DefaultHandler);
+PROVIDE(CACHE_IA_INTR = DefaultHandler);
+PROVIDE(INTERNAL_TIMER0_INTR = DefaultHandler);
+PROVIDE(INTERNAL_SOFTWARE_LEVEL_1_INTR = DefaultHandler);
+PROVIDE(INTERNAL_PROFILING_INTR = DefaultHandler);
+PROVIDE(INTERNAL_TIMER1_INTR = DefaultHandler);
+PROVIDE(INTERNAL_TIMER2_INTR = DefaultHandler);
+PROVIDE(INTERNAL_SOFTWARE_LEVEL_3_INTR = DefaultHandler);
+