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Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A (#95337)
* Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A * INS_OPTS_SCALABLE_n_TO_SIMD_SCALAR Change-Id: I068d2761af40d22f8850e64d136a81275ce4ca5f * placeholder * Block out unsupported instructions * nits
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‎src/coreclr/jit/codegenarm64.cpp‎

Lines changed: 117 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5437,6 +5437,7 @@ void CodeGen::genProfilingLeaveCallback(unsigned helper)
54375437
// #define ALL_ARM64_EMITTER_UNIT_TESTS_GENERAL
54385438
// #define ALL_ARM64_EMITTER_UNIT_TESTS_ADVSIMD
54395439
// #define ALL_ARM64_EMITTER_UNIT_TESTS_SVE
5440+
// #define ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
54405441

54415442
#if defined(DEBUG)
54425443
void CodeGen::genArm64EmitterUnitTests()
@@ -10194,11 +10195,11 @@ void CodeGen::genArm64EmitterUnitTests()
1019410195

1019510196
// IF_SVE_CN_3A
1019610197
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15,
10197-
INS_OPTS_SCALABLE_H_TO_SIMD); /* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10198+
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
1019810199
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16,
10199-
INS_OPTS_SCALABLE_S_TO_SIMD); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10200+
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
1020010201
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17,
10201-
INS_OPTS_SCALABLE_D_TO_SIMD); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10202+
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
1020210203

1020310204
// IF_SVE_CO_3A
1020410205
// Note: EA_4BYTE used for B and H (destination register is W)
@@ -10299,21 +10300,23 @@ void CodeGen::genArm64EmitterUnitTests()
1029910300

1030010301
// IF_SVE_HJ_3A
1030110302
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14,
10302-
INS_OPTS_SCALABLE_H_TO_SIMD); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10303+
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
1030310304
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13,
10304-
INS_OPTS_SCALABLE_S_TO_SIMD); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10305+
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
1030510306
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12,
10306-
INS_OPTS_SCALABLE_D_TO_SIMD); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10307+
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
10308+
1030710309
// IF_SVE_HL_3A
1030810310
theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11,
1030910311
INS_OPTS_SCALABLE_H); /* FABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
1031010312
theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_SCALABLE, REG_V25, REG_P2, REG_V10,
1031110313
INS_OPTS_SCALABLE_S); /* FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
10312-
// These are not yet supported by capstone.
10313-
// theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D);
10314+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10315+
theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D);
1031410316
/* FAMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
10315-
// theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H);
10316-
/* FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
10317+
theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H);
10318+
/* FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
10319+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
1031710320
theEmitter->emitIns_R_R_R(INS_sve_fdiv, EA_SCALABLE, REG_V28, REG_P0, REG_V7,
1031810321
INS_OPTS_SCALABLE_S); /* FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
1031910322
theEmitter->emitIns_R_R_R(INS_sve_fdivr, EA_SCALABLE, REG_V29, REG_P1, REG_V6,
@@ -10337,6 +10340,110 @@ void CodeGen::genArm64EmitterUnitTests()
1033710340
theEmitter->emitIns_R_R_R(INS_sve_fsubr, EA_SCALABLE, REG_V6, REG_P4, REG_V29,
1033810341
INS_OPTS_SCALABLE_D); /* FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
1033910342

10343+
// IF_SVE_AF_3A
10344+
theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0,
10345+
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* ANDV <V><d>, <Pg>, <Zn>.<T> */
10346+
theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1,
10347+
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* EORV <V><d>, <Pg>, <Zn>.<T> */
10348+
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2,
10349+
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */
10350+
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3,
10351+
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */
10352+
10353+
// IF_SVE_AG_3A
10354+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10355+
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_1BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
10356+
/* ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10357+
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_2BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H_TO_SIMD_VECTOR);
10358+
/* EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10359+
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_4BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S_TO_SIMD_VECTOR);
10360+
/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10361+
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D_TO_SIMD_VECTOR);
10362+
/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10363+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10364+
10365+
// IF_SVE_AI_3A
10366+
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2,
10367+
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
10368+
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3,
10369+
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
10370+
theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4,
10371+
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* UADDV <Dd>, <Pg>, <Zn>.<T> */
10372+
10373+
// IF_SVE_AJ_3A
10374+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10375+
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_V7, REG_P22, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
10376+
/* ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10377+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10378+
10379+
// IF_SVE_AK_3A
10380+
theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4,
10381+
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* SMAXV <V><d>, <Pg>, <Zn>.<T> */
10382+
theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14,
10383+
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* SMINV <V><d>, <Pg>, <Zn>.<T> */
10384+
theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24,
10385+
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* UMAXV <V><d>, <Pg>, <Zn>.<T> */
10386+
theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31,
10387+
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* UMINV <V><d>, <Pg>, <Zn>.<T> */
10388+
10389+
// IF_SVE_AL_3A
10390+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10391+
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_1BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
10392+
/* SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10393+
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_2BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H_TO_SIMD_VECTOR);
10394+
/* SMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10395+
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_4BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S_TO_SIMD_VECTOR);
10396+
/* UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10397+
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D_TO_SIMD_VECTOR);
10398+
/* UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
10399+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
10400+
10401+
// IF_SVE_AP_3A
10402+
theEmitter->emitIns_R_R_R(INS_sve_cls, EA_SCALABLE, REG_V31, REG_P0, REG_V0,
10403+
INS_OPTS_SCALABLE_B); /* CLS <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10404+
theEmitter->emitIns_R_R_R(INS_sve_clz, EA_SCALABLE, REG_V30, REG_P1, REG_V1,
10405+
INS_OPTS_SCALABLE_H); /* CLZ <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10406+
theEmitter->emitIns_R_R_R(INS_sve_cnot, EA_SCALABLE, REG_V29, REG_P2, REG_V2,
10407+
INS_OPTS_SCALABLE_S); /* CNOT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10408+
theEmitter->emitIns_R_R_R(INS_sve_cnt, EA_SCALABLE, REG_V28, REG_P3, REG_V3,
10409+
INS_OPTS_SCALABLE_D); /* CNT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10410+
theEmitter->emitIns_R_R_R(INS_sve_fabs, EA_SCALABLE, REG_V27, REG_P4, REG_V4,
10411+
INS_OPTS_SCALABLE_H); /* FABS <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10412+
theEmitter->emitIns_R_R_R(INS_sve_fneg, EA_SCALABLE, REG_V26, REG_P5, REG_V5,
10413+
INS_OPTS_SCALABLE_S); /* FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10414+
theEmitter->emitIns_R_R_R(INS_sve_not, EA_SCALABLE, REG_V25, REG_P6, REG_V6,
10415+
INS_OPTS_SCALABLE_B); /* NOT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10416+
10417+
// IF_SVE_AQ_3A
10418+
theEmitter->emitIns_R_R_R(INS_sve_abs, EA_SCALABLE, REG_V24, REG_P7, REG_V7,
10419+
INS_OPTS_SCALABLE_B); /* ABS <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10420+
theEmitter->emitIns_R_R_R(INS_sve_neg, EA_SCALABLE, REG_V23, REG_P0, REG_V8,
10421+
INS_OPTS_SCALABLE_S); /* NEG <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10422+
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_SCALABLE, REG_V22, REG_P1, REG_V9,
10423+
INS_OPTS_SCALABLE_H); /* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10424+
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_SCALABLE, REG_V22, REG_P1, REG_V9,
10425+
INS_OPTS_SCALABLE_S); /* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10426+
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_SCALABLE, REG_V22, REG_P1, REG_V9,
10427+
INS_OPTS_SCALABLE_D); /* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10428+
theEmitter->emitIns_R_R_R(INS_sve_sxth, EA_SCALABLE, REG_V21, REG_P2, REG_V10,
10429+
INS_OPTS_SCALABLE_S); /* SXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10430+
theEmitter->emitIns_R_R_R(INS_sve_sxth, EA_SCALABLE, REG_V21, REG_P2, REG_V10,
10431+
INS_OPTS_SCALABLE_D); /* SXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10432+
theEmitter->emitIns_R_R_R(INS_sve_sxtw, EA_SCALABLE, REG_V20, REG_P3, REG_V11,
10433+
INS_OPTS_SCALABLE_D); /* SXTW <Zd>.D, <Pg>/M, <Zn>.D */
10434+
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_SCALABLE, REG_V19, REG_P4, REG_V12,
10435+
INS_OPTS_SCALABLE_H); /* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10436+
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_SCALABLE, REG_V19, REG_P4, REG_V12,
10437+
INS_OPTS_SCALABLE_S); /* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10438+
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_SCALABLE, REG_V19, REG_P4, REG_V12,
10439+
INS_OPTS_SCALABLE_D); /* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10440+
theEmitter->emitIns_R_R_R(INS_sve_uxth, EA_SCALABLE, REG_V18, REG_P5, REG_V13,
10441+
INS_OPTS_SCALABLE_S); /* UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10442+
theEmitter->emitIns_R_R_R(INS_sve_uxth, EA_SCALABLE, REG_V18, REG_P5, REG_V13,
10443+
INS_OPTS_SCALABLE_D); /* UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
10444+
theEmitter->emitIns_R_R_R(INS_sve_uxtw, EA_SCALABLE, REG_V17, REG_P6, REG_V14,
10445+
INS_OPTS_SCALABLE_D); /* UXTW <Zd>.D, <Pg>/M, <Zn>.D */
10446+
1034010447
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE
1034110448

1034210449
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS

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