@@ -9255,15 +9255,15 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
92559255 case NI_AVX_LoadAlignedVector256:
92569256 case NI_AVX512_LoadAlignedVector512:
92579257 {
9258- // In minOpts , we need to ensure that an unaligned address will fault when an explicit LoadAligned is used.
9259- // Non-VEX encoded instructions will fault if an unaligned SIMD16 load is contained but will not for scalar
9260- // loads, and VEX-encoded instructions will not fault for unaligned loads in any case.
9258+ // For debug code , we need to ensure that an unaligned address will fault when an explicit LoadAligned is
9259+ // used. Non-VEX encoded instructions will fault if an unaligned SIMD16 load is contained but will not for
9260+ // scalar loads, and VEX-encoded instructions will not fault for unaligned loads in any case.
92619261 //
92629262 // When optimizations are enabled, we want to contain any aligned load that is large enough for the parent's
92639263 // requirement.
92649264
9265- return (supportsSIMDLoad &&
9266- (( !comp->canUseVexEncoding () && expectedSize == genTypeSize (TYP_SIMD16)) || !comp-> opts . MinOpts ( )));
9265+ return (supportsSIMDLoad && (comp-> opts . OptimizationEnabled () ||
9266+ ( !comp->canUseVexEncoding () && expectedSize == genTypeSize (TYP_SIMD16))));
92679267 }
92689268
92699269 case NI_X86Base_LoadScalarVector128:
@@ -9279,7 +9279,7 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
92799279 case NI_AVX2_BroadcastScalarToVector256:
92809280 case NI_AVX512_BroadcastScalarToVector512:
92819281 {
9282- if (comp->opts .MinOpts () || !comp->canUseEmbeddedBroadcast ())
9282+ if (! comp->opts .Tier0OptimizationEnabled () || !comp->canUseEmbeddedBroadcast ())
92839283 {
92849284 return false ;
92859285 }
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