Skip to content

SystemVerilog: IDs and classes for the explicit casts #876

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Dec 4, 2024

Conversation

kroening
Copy link
Member

@kroening kroening commented Dec 4, 2024

SystemVerilog offers the following explicit casts:

  • const cast
  • size cast
  • signing cast
  • type casts for simple types and strings

This unifies the naming of the IDs and introduces classes for the missing casts.

@kroening kroening force-pushed the verilog-explicit-casts branch 3 times, most recently from a512342 to a40b691 Compare December 4, 2024 12:20
@kroening kroening marked this pull request as ready for review December 4, 2024 13:00
SystemVerilog offers the following explicit casts:
* const cast
* size cast
* signing cast
* type casts for simple types and strings

This unifies the naming of the IDs and introduces classes for the missing
casts.
@kroening kroening force-pushed the verilog-explicit-casts branch from a40b691 to 178e6d1 Compare December 4, 2024 13:07
@tautschnig tautschnig merged commit 7c7e7e2 into main Dec 4, 2024
9 checks passed
@tautschnig tautschnig deleted the verilog-explicit-casts branch December 4, 2024 13:48
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants