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Verilog: typechecking for relations #667

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Merged
merged 1 commit into from
Sep 9, 2024
Merged

Verilog: typechecking for relations #667

merged 1 commit into from
Sep 9, 2024

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kroening
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@kroening kroening commented Sep 5, 2024

Relations are special-cased in 1800-2017 11.8.2.

If both operands are signed, both are sign-extended to the max width.

Otherwise, both are zero-extended to the max width. In particular, signed operands are then not sign extended, which a typecast would do.

@kroening kroening force-pushed the typecheck_relation branch 3 times, most recently from 039ecf4 to 2575d4f Compare September 6, 2024 21:08
Relations are special-cased in 1800-2017 11.8.2.

If both operands are signed, both are sign-extended to the max width.

Otherwise, both are zero-extended to the max width.  In particular, signed
operands are then _not_ sign extended, which a typecast would do.
@kroening kroening marked this pull request as ready for review September 6, 2024 21:11
@tautschnig tautschnig merged commit 2e283cc into main Sep 9, 2024
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@tautschnig tautschnig deleted the typecheck_relation branch September 9, 2024 21:03
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