Verilog: fix for signed constants #660
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kroening
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tautschnig
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Sep 6, 2024
| bool bits_given=false; | ||
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| if(pos!=std::string::npos) // size given? | ||
| { | ||
| if(rest[0]!='\'') | ||
| { | ||
| bits=atoi(rest.c_str()); | ||
| bits = atol(rest.c_str()); |
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This is probably safe because of the lexer rules, but I would feel better if this used one of the safe_string2... functions instead of atol.
Verilog allows constants to be marked as signed (e.g., 'sb1). When using base 2, 8 and 16, these need to be sign extended to 32 bits unless the number of bits is given.
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Verilog allows constants to be marked as signed (e.g., 'sb1). When using base 2, 8 and 16, these need to be sign extended to 32 bits unless the number of bits is given.