Skip to content

ebmc: KNOWNBUG test for a bounded sequence expression #433

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Apr 3, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions regression/verilog/SVA/sequence1.desc
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
KNOWNBUG
sequence1.sv
--bound 20 --numbered-trace
^EXIT=10$
^SIGNAL=0$
--
^warning: ignoring
--
The trace shown only has one state, but 10 are expected.
14 changes: 14 additions & 0 deletions regression/verilog/SVA/sequence1.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
module main;

reg [31:0] x;
wire clk;

initial x=0;

always @(posedge clk)
x<=x+1;

// fails, and we want to see a trace 0...9
initial p0: assert property (##[0:9] x==100);

endmodule