SystemVerilog: distinguish assertions #422
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kroening
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tautschnig
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Mar 21, 2024
src/trans-word-level/property.cpp
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| for(std::size_t t = 0; t < no_timeframes; t++) | ||
| { | ||
| exprt prop_handle; | ||
| if(t == 0) | ||
| { | ||
| exprt tmp = instantiate(property_expr, t, no_timeframes, ns); | ||
| prop_handle = solver.handle(tmp); | ||
| } | ||
| else | ||
| prop_handle = true_exprt(); | ||
|
|
||
| prop_handles.push_back(std::move(prop_handle)); | ||
| } |
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How about:
std::size_t before = prop_handles.size();
if(no_timeframes > 0)
{
exprt tmp = instantiate(property_expr, 0, no_timeframes, ns);
prop_handles.push_back(solver.handle(tmp));
}
prop_handles.resize(before + no_timeframes, true_exprt{});
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This changes the front-end to distinguish three kinds of assertions/assumptions:
1) concurrent assertions/assumptions ("assert property"), which can be
module items or statements,
2) immediate assertion/assumption statements, and
3) SMV-style assertions/assumptions.
Front-end and BMC back-end support for initial concurrent assertion
statements is added.
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This changes the front-end to distinguish three kinds of assertions/assumptions:
concurrent assertions/assumptions ("assert property"), which can be module items or statements,
immediate assertion/assumption statements, and
SMV-style assertions/assumptions.
Front-end and BMC back-end support for initial concurrent assertion statements is added.