Verilog: introduce the Verilog indexer #397
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tautschnig
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Approving subject to making CI pass plus a few comments below. Tests would really be appreciated.
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| module main(input x, input y); | ||
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| reg result; | ||
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| always @(x, y) | ||
| case(x) | ||
| 0: result = 0; | ||
| 1: | ||
| case(y) | ||
| 1: result = 1; | ||
| 0: result = 0; | ||
| endcase | ||
| endcase | ||
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| always assert p1: result == (x && y); | ||
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| endmodule |
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In what way is this test exercising the new indexer?
src/vlindex/vlindex_parse_options.h
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| virtual int doit(); | ||
| virtual void help(); |
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| // possibly a macro that wasn't found | ||
| std::cout << "LPAREN: " << verilog_parser.get_file() << ':' | ||
| << verilog_parser.get_line_no() << ' ' << token.text << "\n"; | ||
| rParenExpression(); | ||
| } | ||
| else | ||
| { | ||
| // something else | ||
| std::cout << "ELSE: " << verilog_parser.get_file() << ':' | ||
| << verilog_parser.get_line_no() << ' ' << token.text << "\n"; | ||
| next_token(); |
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Now with tests in CI. |
This adds a recusive decent parser for quicky indexing large quantities of Verilog, tolerating parsing errors, for the purpose of creating overview data very quickly. A new executable, vlindex, is added to output it.
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Aug 19, 2025
Verilog: introduce the Verilog indexer
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This adds a recusive decent parser for quicky indexing large quantities of Verilog, tolerating parsing errors, for the purpose of creating overview data very quickly. A new executable,
vlindex, is added to output it.