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Merge pull request #1252 from diffblue/index-constant
Verilog: Tests for constant folding of index expressions
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CORE
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index-constant1.sv
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^\[.*\] .* PROVED .*$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main;
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// index expressions yield constants
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parameter p = 'b1010;
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parameter q = p[3];
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parameter r = p[0];
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assert final (q == 1);
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assert final (r == 0);
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endmodule
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KNOWNBUG
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index-constant2.sv
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^\[.*\] .* PROVED .*$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main;
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// index expressions yield constants
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parameter p = (1>0); // boolean
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parameter q = p[0];
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assert final (q == 1);
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endmodule

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