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Merge pull request #680 from diffblue/sva_and1
SVA Boolean connectives
2 parents 03d9ee4 + 282fde5 commit e546de9

16 files changed

+182
-5
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regression/verilog/SVA/eventually1.desc

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CORE
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eventually1.sv
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--bound 20
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^\[main\.property\.p0\] always \(main\.counter == 1 |-> eventually \[1:2\] main\.counter == 3\): PROVED up to bound 20$
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^\[main\.p0\] always main\.counter == 1 implies \(eventually \[1:2\] main\.counter == 3\): PROVED up to bound 20$
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^EXIT=0$
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^SIGNAL=0$
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--

regression/verilog/SVA/sva_and1.desc

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CORE
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sva_and1.sv
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--bound 0
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^\[main\.p0\] always 1 and 1: PROVED up to bound 0$
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^\[main\.p1\] always 1 and 0: REFUTED$
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^\[main\.p2\] always 1 and 32'b0000000000000000000000000000000x: PROVED up to bound 0$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

regression/verilog/SVA/sva_and1.sv

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module main;
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// should pass
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p0: assert property (10 and 20);
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// should fail
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p1: assert property (10 and 0);
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// should fail
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p2: assert property (10 and 'bx);
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endmodule

regression/verilog/SVA/sva_iff1.desc

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CORE
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sva_iff1.sv
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--bound 0
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^\[main\.p0\] always 1 iff 1: PROVED up to bound 0$
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^\[main\.p1\] always 1 iff 0: REFUTED$
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^\[main\.p2\] always 1 iff 32'b0000000000000000000000000000000x: PROVED up to bound 0$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

regression/verilog/SVA/sva_iff1.sv

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module main;
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// should pass
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p0: assert property (10 iff 20);
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// should fail
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p1: assert property (10 iff 0);
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// should fail
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p2: assert property (10 iff 'bx);
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endmodule
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CORE
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sva_implies1.sv
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--bound 0
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^\[main\.p0\] always 1 implies 1: PROVED up to bound 0$
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^\[main\.p1\] always 1 implies 0: REFUTED$
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^\[main\.p2\] always 1 implies 32'b0000000000000000000000000000000x: PROVED up to bound 0$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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module main;
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// should pass
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p0: assert property (10 implies 20);
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// should fail
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p1: assert property (10 implies 0);
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// should fail
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p2: assert property (10 implies 'bx);
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endmodule

regression/verilog/SVA/sva_not1.desc

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CORE
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sva_not1.sv
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--k-induction
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^\[main\.p0] always not 0: PROVED$
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^\[main\.p1] always not 1: REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring

regression/verilog/SVA/sva_not1.sv

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module main;
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// should pass
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p0: assert property (not 0);
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// should fail
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p1: assert property (not 1);
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endmodule

src/hw_cbmc_irep_ids.h

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IREP_ID_ONE(sva_overlapped_implication)
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IREP_ID_ONE(sva_non_overlapped_implication)
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IREP_ID_ONE(sva_and)
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IREP_ID_ONE(sva_iff)
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IREP_ID_ONE(sva_implies)
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IREP_ID_ONE(sva_not)
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IREP_ID_ONE(sva_or)
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IREP_ID_ONE(module_instance)

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