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Merge pull request #357 from diffblue/verilog-type-reference
Verilog: type references
2 parents 80245d3 + 4fb6793 commit 86bf873

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CORE
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type_operator.sv
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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module main;
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wire [31:0] some_wire;
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wire type(some_wire) other_wire;
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typedef bit [31:0] some_type;
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wire some_type next_wire;
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p0: assert property ($bits(other_wire) == 32);
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p1: assert property ($bits(next_wire) == 32);
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endmodule

src/hw_cbmc_irep_ids.h

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@@ -106,6 +106,7 @@ IREP_ID_ONE(uwire)
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IREP_ID_ONE(wand)
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IREP_ID_ONE(automatic)
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IREP_ID_ONE(verilog_enum)
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IREP_ID_ONE(verilog_type_reference)
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IREP_ID_ONE(enum_names)
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IREP_ID_ONE(var)
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IREP_ID_ONE(trireg)

src/verilog/expr2verilog.cpp

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@@ -1180,6 +1180,14 @@ std::string expr2verilogt::convert(const typet &type)
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{
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return "enum";
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}
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else if(type.id() == ID_verilog_type_reference)
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{
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auto &type_reference = to_verilog_type_reference(type);
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if(type_reference.expression_op().is_not_nil())
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return "type(" + convert(type_reference.expression_op()) + ")";
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else
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return "type(" + convert(type_reference.type_op()) + ")";
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}
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return "IREP("+type.pretty()+")";
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}

src/verilog/parser.y

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@@ -1255,6 +1255,7 @@ data_type:
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/*
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| ps_covergroup_identifier
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*/
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| type_reference
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;
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enum_name_value_opt:
@@ -1388,6 +1389,13 @@ simple_type:
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data_type_or_void: data_type | TOK_VOID
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;
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type_reference:
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TOK_TYPE '(' expression ')'
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{ init($$, ID_verilog_type_reference); mto($$, $3); }
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| TOK_TYPE '(' data_type ')'
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{ init($$, ID_verilog_type_reference); addswap($$, ID_type_arg, $3); }
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;
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// System Verilog standard 1800-2017
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// A.2.2.2 Strengths
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src/verilog/verilog_typecheck_type.cpp

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@@ -164,6 +164,19 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
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return std::move(result);
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}
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}
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else if(src.id() == ID_verilog_type_reference)
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{
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auto &type_reference = to_verilog_type_reference(src);
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if(type_reference.expression_op().is_not_nil())
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{
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// the expression is not evaluated
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auto expr = type_reference.expression_op();
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convert_expr(expr);
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return expr.type();
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}
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else
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return convert_type(type_reference.type_op());
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}
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else
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{
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error().source_location = source_location;

src/verilog/verilog_types.h

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@@ -407,4 +407,49 @@ inline verilog_enum_typet &to_verilog_enum_type(typet &type)
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return static_cast<verilog_enum_typet &>(type);
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}
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class verilog_type_referencet : public typet
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{
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public:
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// This comes in two flavors: a reference to the type
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// of a given type, or of a given expression.
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const exprt &expression_op() const
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{
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if(get_sub().size() == 1)
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return static_cast<const exprt &>(get_sub().front());
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else
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return static_cast<const exprt &>(get_nil_irep());
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}
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const typet &type_op() const
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{
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return static_cast<const typet &>(find(ID_type_arg));
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}
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};
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/*! \brief Cast a generic typet to a \ref verilog_type_referencet
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*
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* This is an unchecked conversion. \a type must be known to be \ref
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* verilog_type_referencet.
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*
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* \param type Source type
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* \return Object of type \ref verilog_type_referencet
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*
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* \ingroup gr_std_types
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*/
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inline const verilog_type_referencet &
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to_verilog_type_reference(const typet &type)
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{
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PRECONDITION(type.id() == ID_verilog_type_reference);
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return static_cast<const verilog_type_referencet &>(type);
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}
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/*! \copydoc to_verilog_type_reference(const typet &)
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* \ingroup gr_std_types
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*/
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inline verilog_type_referencet &to_verilog_type_reference(typet &type)
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{
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PRECONDITION(type.id() == ID_verilog_type_reference);
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return static_cast<verilog_type_referencet &>(type);
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}
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#endif

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