Skip to content

Commit 7fb3600

Browse files
authored
Merge pull request #670 from diffblue/size-cast-on-bool
Verilog: size-cast expression with Boolean operand
2 parents a52c32b + 297c2ed commit 7fb3600

File tree

2 files changed

+2
-1
lines changed

2 files changed

+2
-1
lines changed

regression/verilog/expressions/size_cast1.sv

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,5 +5,6 @@ module main;
55
p0: assert final ($bits(10'(1)) == 10);
66
p1: assert final ($bits(P'(1)) == 20);
77
p2: assert final (10'(-1) == -1);
8+
p3: assert final (2'(1==1) == 1);
89

910
endmodule

src/verilog/verilog_typecheck_expr.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2730,7 +2730,7 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)
27302730
return typecast_exprt{expr.rhs(), signedbv_typet{new_size_int}}
27312731
.with_source_location(expr);
27322732
}
2733-
else if(op_type.id() == ID_unsignedbv)
2733+
else if(op_type.id() == ID_unsignedbv || op_type.id() == ID_bool)
27342734
{
27352735
return typecast_exprt{expr.rhs(), unsignedbv_typet{new_size_int}}
27362736
.with_source_location(expr);

0 commit comments

Comments
 (0)