KNOWNBUG test for four-valued << and >>

Author: kroening

regression/verilog/expressions/shl3.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+shl3.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+aval/bval encoding is missing.

regression/verilog/expressions/shl3.sv

@@ -0,0 +1,13 @@
+module main;
+
+  assert final (3'b101 << 1 === 3'b010);
+  assert final ('b101 << 1 === 'b1010);
+  assert final ('b10x << 1 === 'b10x0);
+  assert final (3'b101 << 'bx === 32'hxxxx_xxxx);
+
+  assert final (3'b101 <<< 1 === 3'b010);
+  assert final ('b101 <<< 1 === 'b1010);
+  assert final ('b10x <<< 1 === 'b10x0);
+  assert final (3'b101 <<< 'bx === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/shr3.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+shr3.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+aval/bval encoding is missing.

regression/verilog/expressions/shr3.sv

@@ -0,0 +1,13 @@
+module main;
+
+  assert final (3'b101 >> 1 === 3'b010);
+  assert final ('b101 >> 1 === 'b1010);
+  assert final ('b1x0 >> 1 === 'b101x);
+  assert final (3'b101 >> 'bx === 32'hxxxx_xxxx);
+
+  assert final (3'b101 >>> 1 === 3'b010);
+  assert final ('b101 >>> 1 === 'b1010);
+  assert final ('b1x0 >>> 1 === 'b101x);
+  assert final (3'b101 >>> 'bx === 32'hxxxx_xxxx);
+
+endmodule