Merge pull request #440 from diffblue/fixup-sva_ranged_always

tautschnig · web-flow · commit 3d28944c5e2d · 2024-04-15T22:24:18.000+02:00
fixup for #432
diff --git a/src/verilog/verilog_typecheck_expr.cpp b/src/verilog/verilog_typecheck_expr.cpp
@@ -1592,7 +1592,6 @@ void verilog_typecheck_exprt::implicit_typecast(
       return;
     }
   }
-#if 0
   else if(src_type.id() == ID_natural)
   {
     if(dest_type.id()==ID_integer)
@@ -1601,7 +1600,6 @@ void verilog_typecheck_exprt::implicit_typecast(
       return;
     }
   }
-#endif
   else if(
     src_type.id() == ID_bool || src_type.id() == ID_unsignedbv ||
     src_type.id() == ID_signedbv || src_type.id() == ID_verilog_unsignedbv ||

Original file line number	Diff line number	Diff line change
`@@ -1592,7 +1592,6 @@ void verilog_typecheck_exprt::implicit_typecast(`
`1592`	`1592`	`return;`
`1593`	`1593`	`}`
`1594`	`1594`	`}`
`1595`		`-#if 0`
`1596`	`1595`	`else if(src_type.id() == ID_natural)`
`1597`	`1596`	`{`
`1598`	`1597`	`if(dest_type.id()==ID_integer)`
`@@ -1601,7 +1600,6 @@ void verilog_typecheck_exprt::implicit_typecast(`
`1601`	`1600`	`return;`
`1602`	`1601`	`}`
`1603`	`1602`	`}`
`1604`		`-#endif`
`1605`	`1603`	`else if(`
`1606`	`1604`	`src_type.id() == ID_bool \|\| src_type.id() == ID_unsignedbv \|\|`
`1607`	`1605`	`src_type.id() == ID_signedbv \|\| src_type.id() == ID_verilog_unsignedbv \|\|`