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Merge pull request #441 from diffblue/covergroup1.sv
Verilog: parse covergroup declarations
2 parents 5e5e9a3 + 88715b0 commit 1abd38e

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8 files changed

+99
-1
lines changed

8 files changed

+99
-1
lines changed
Lines changed: 7 additions & 0 deletions
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@@ -0,0 +1,7 @@
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CORE
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covergroup1.sv
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^no properties$
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^EXIT=10$
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^SIGNAL=0$
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--
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@@ -0,0 +1,9 @@
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module main;
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wire clk, some_signal;
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covergroup cg @(posedge clk);
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coverpoint some_signal;
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endgroup
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endmodule

src/hw_cbmc_irep_ids.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ IREP_ID_ONE(verilog_smv_using)
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IREP_ID_ONE(verilog_assert_property)
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IREP_ID_ONE(verilog_assume_property)
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IREP_ID_ONE(verilog_cover_property)
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IREP_ID_ONE(verilog_covergroup)
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IREP_ID_ONE(verilog_smv_assert)
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IREP_ID_ONE(verilog_smv_assume)
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IREP_ID_ONE(verilog_always)

src/verilog/parser.y

Lines changed: 70 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -891,7 +891,7 @@ class_item:
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// | attribute_instance_brace class_method
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// | attribute_instance_brace class_constraint
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attribute_instance_brace class_declaration
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// | attribute_instance_brace covergroup_declaration
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| attribute_instance_brace covergroup_declaration
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| local_parameter_declaration ';'
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| parameter_declaration ';'
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| ';'
@@ -1027,6 +1027,7 @@ package_or_generate_item_declaration:
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that let constructs may be declared in a
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module/interface/program/checker etc. */
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| let_declaration
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| covergroup_declaration
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| ';'
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{ init($$, ID_verilog_empty_item); }
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;
@@ -1285,6 +1286,9 @@ enum_name_declaration_list:
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{ $$=$1; mts($$, $3); }
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;
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class_scope: class_type TOK_COLONCOLON
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;
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integer_type:
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integer_vector_type
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| integer_atom_type
@@ -1864,6 +1868,13 @@ task_declaration:
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task_prototype: TOK_TASK task_identifier
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;
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tf_port_list_paren_opt:
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/* Optional */
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{ init($$); }
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| '(' tf_port_list_opt ')'
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{ $$ = $2; }
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;
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tf_port_list_opt:
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/* Optional */
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{ init($$); }
@@ -2067,6 +2078,55 @@ expression_or_dist:
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expression
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;
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// System Verilog standard 1800-2017
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// A.2.11 Covergroup declarations
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covergroup_declaration:
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TOK_COVERGROUP new_identifier tf_port_list_paren_opt coverage_event_opt ';'
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coverage_spec_or_option_brace TOK_ENDGROUP
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{ init($$, ID_verilog_covergroup); }
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;
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coverage_spec_or_option_brace:
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/* Optional */
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| coverage_spec_or_option_brace coverage_spec_or_option
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;
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coverage_spec_or_option:
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attribute_instance_brace coverage_spec
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;
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coverage_spec:
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cover_point
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;
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coverage_event_opt:
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/* Optional */
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| coverage_event
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;
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coverage_event:
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clocking_event
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;
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block_event_expression:
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block_event_expression TOK_OR block_event_expression
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| TOK_BEGIN hierarchical_btf_identifier
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| TOK_END hierarchical_btf_identifier
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;
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hierarchical_btf_identifier:
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hierarchical_tf_identifier
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| hierarchical_block_identifier
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| method_identifier
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| hierarchical_identifier '.' method_identifier
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| class_scope method_identifier
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;
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cover_point:
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TOK_COVERPOINT expression ';'
2128+
;
2129+
20702130
// System Verilog standard 1800-2017
20712131
// A.2.12 Let declarations
20722132

@@ -2910,6 +2970,11 @@ procedural_timing_control:
29102970
// System Verilog standard 1800-2017
29112971
// A.6.11 Clocking block
29122972

2973+
clocking_event:
2974+
'@' identifier
2975+
| '@' '(' event_expression ')'
2976+
;
2977+
29132978
cycle_delay:
29142979
"##" number
29152980
{ init($$, ID_verilog_cycle_delay); mto($$, $2); }
@@ -3396,6 +3461,8 @@ ps_covergroup_identifier:
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33973462
memory_identifier: identifier;
33983463
3464+
method_identifier: identifier;
3465+
33993466
type_identifier: TOK_TYPE_IDENTIFIER
34003467
{
34013468
init($$, ID_typedef_type);
@@ -3429,6 +3496,8 @@ function_identifier: hierarchical_identifier
34293496
34303497
hierarchical_event_identifier: event_identifier;
34313498
3499+
hierarchical_block_identifier: hierarchical_identifier;
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hierarchical_identifier:
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identifier
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| hierarchical_identifier '.' identifier

src/verilog/verilog_elaborate.cpp

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Original file line numberDiff line numberDiff line change
@@ -773,6 +773,9 @@ void verilog_typecheckt::collect_symbols(
773773
else if(module_item.id() == ID_verilog_package_import)
774774
{
775775
}
776+
else if(module_item.id() == ID_verilog_covergroup)
777+
{
778+
}
776779
else
777780
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
778781
}

src/verilog/verilog_interfaces.cpp

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Original file line numberDiff line numberDiff line change
@@ -296,6 +296,9 @@ void verilog_typecheckt::interface_module_item(
296296
else if(module_item.id() == ID_verilog_package_import)
297297
{
298298
}
299+
else if(module_item.id() == ID_verilog_covergroup)
300+
{
301+
}
299302
else
300303
{
301304
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());

src/verilog/verilog_synthesis.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2744,6 +2744,9 @@ void verilog_synthesist::synth_module_item(
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{
27452745
// done already
27462746
}
2747+
else if(module_item.id() == ID_verilog_covergroup)
2748+
{
2749+
}
27472750
else
27482751
{
27492752
throw errort().with_location(module_item.source_location())

src/verilog/verilog_typecheck.cpp

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@@ -1587,6 +1587,9 @@ void verilog_typecheckt::convert_module_item(
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else if(module_item.id() == ID_verilog_package_import)
15881588
{
15891589
}
1590+
else if(module_item.id() == ID_verilog_covergroup)
1591+
{
1592+
}
15901593
else
15911594
{
15921595
throw errort().with_location(module_item.source_location())

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