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Statement List: Jump instructions #5054
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Merged
tautschnig
merged 7 commits into
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MatWise:feature/statement-list-jumps
May 13, 2021
Merged
Statement List: Jump instructions #5054
tautschnig
merged 7 commits into
diffblue:develop
from
MatWise:feature/statement-list-jumps
May 13, 2021
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Travis build fails because of known doxygen issue, works locally. |
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tautschnig
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May 11, 2021
Codecov Report
@@ Coverage Diff @@
## develop #5054 +/- ##
===========================================
- Coverage 75.68% 75.33% -0.36%
===========================================
Files 1447 1447
Lines 157837 157988 +151
===========================================
- Hits 119465 119013 -452
- Misses 38372 38975 +603
Continue to review full report at Codecov.
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Changes the accepted format for labels and wraps instructions that have a label in a code label.
Includes parser support for: - JU (unconditional jump) - JC (conditional jump) - JCN (inverted conditional jump)
Just small formatting changes.
Adds support for the verification of jump instructions. Includes both conditional and unconditional jumps. Limitations: This implementation is only a rough concept and will likely be changed in the future. CFGs prove more useful for this task than the current concept, since they allow all parts of the PLC CPU to be modelled implicitly, without exceptions. Currently the state of the CPU needs to be saved as an intermediate result when encountering labels and jumps. This is only realised for logic sequences currently. Jump instructions in blocks that depend on the accumulator will yield to false results!
Sets the typecheck to the correct state for verifying new blocks or networks. Limitations: The accumulator is unaffected by this. It needs to be investigated whether the accumulator gets reset at all in TIA.
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Includes support for the following STL instructions:
Since not all label destinations in STL are valid (this can depend on several conditions), it is needed to introduce data structures which track the properties of label and jump locations to the typecheck. See the documentation for details about the whole strategy.
Limitations: This implementation is only a rough concept and will likely be changed in the future. CFGs prove more useful for this task than the current concept, since they allow all parts of the PLC CPU to be modelled implicitly, without exceptions. Currently the state of the CPU needs to be saved as an intermediate result when encountering labels and jumps. So far this has only been realised for logic sequences. Jump instructions in blocks that depend on the accumulator will yield to false results.