Use dependency style make

Change from calling the separate make targets inside a default
to instead using make dependency style.

Author: TGWDB

regression/cbmc/Makefile

@@ -1,5 +1,3 @@
-THIS_FILE := $(lastword $(MAKEFILE_LIST))
-
 default: test
 
 include ../../src/config.inc
@@ -11,10 +9,8 @@ else
 GCC_ONLY =
 endif
 
-test:
+test: test-cprover-smt2 test-paths-lifo
 	@../test.pl -e -p -c "../../../src/cbmc/cbmc --validate-goto-model --validate-ssa-equation" -X smt-backend $(GCC_ONLY)
-	@$(MAKE) -f $(THIS_FILE) test-paths-lifo
-	@$(MAKE) -f $(THIS_FILE) test-cprover-smt2
 
 test-cprover-smt2:
 	@../test.pl -e -p -c "../../../src/cbmc/cbmc --cprover-smt2" \