Skip to content

Commit e3cfc7e

Browse files
Moshe ShemeshSaeed Mahameed
authored andcommitted
net/mlx5e: TX, Add geneve tunnel stateless offload support
Currently support only default geneve udp port (6081). For the tx side, the HW is assisted by SW parsing, which sets the headers offset to offload tunneled LSO and csum. Note that for udp tunnels, we don't use special rx offloads, as rss on the outer headers is enough, we support checksum complete and GRO takes care of aggregation. Geneve TSO BW and CPU load results (tested using iperf single tcp stream). In this patch we add TSO support over Geneve, so the "before" result doesn't actually get to using the TSO HW offload even when turned on. Tested on ConnectX-5, Intel(R) Xeon(R) CPU E5-2660 v2 @2.20GHz. __________________________________ | Before | After | |________________|_________________| | 12.6 Gbits/sec | 21.7 Gbits/sec | | 100% CPU load | 61.5% CPU load | |________________|_________________| Signed-off-by: Moshe Shemesh <[email protected]> Acked-by: Or Gerlitz <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]>
1 parent cac018b commit e3cfc7e

File tree

4 files changed

+77
-3
lines changed

4 files changed

+77
-3
lines changed

drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -884,6 +884,12 @@ static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
884884
MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
885885
}
886886

887+
static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
888+
{
889+
return MLX5_CAP_ETH(mdev, swp) &&
890+
MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
891+
}
892+
887893
struct mlx5e_swp_spec {
888894
__be16 l3_proto;
889895
u8 l4_proto;

drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,57 @@
4040
#include "en_accel/tls_rxtx.h"
4141
#include "en.h"
4242

43+
#if IS_ENABLED(CONFIG_GENEVE)
44+
static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
45+
{
46+
return mlx5_tx_swp_supported(mdev);
47+
}
48+
49+
static inline void
50+
mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
51+
{
52+
struct mlx5e_swp_spec swp_spec = {};
53+
unsigned int offset = 0;
54+
__be16 l3_proto;
55+
u8 l4_proto;
56+
57+
l3_proto = vlan_get_protocol(skb);
58+
switch (l3_proto) {
59+
case htons(ETH_P_IP):
60+
l4_proto = ip_hdr(skb)->protocol;
61+
break;
62+
case htons(ETH_P_IPV6):
63+
l4_proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
64+
break;
65+
default:
66+
return;
67+
}
68+
69+
if (l4_proto != IPPROTO_UDP ||
70+
udp_hdr(skb)->dest != cpu_to_be16(GENEVE_UDP_PORT))
71+
return;
72+
swp_spec.l3_proto = l3_proto;
73+
swp_spec.l4_proto = l4_proto;
74+
swp_spec.is_tun = true;
75+
if (inner_ip_hdr(skb)->version == 6) {
76+
swp_spec.tun_l3_proto = htons(ETH_P_IPV6);
77+
swp_spec.tun_l4_proto = inner_ipv6_hdr(skb)->nexthdr;
78+
} else {
79+
swp_spec.tun_l3_proto = htons(ETH_P_IP);
80+
swp_spec.tun_l4_proto = inner_ip_hdr(skb)->protocol;
81+
}
82+
83+
mlx5e_set_eseg_swp(skb, eseg, &swp_spec);
84+
}
85+
86+
#else
87+
static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
88+
{
89+
return false;
90+
}
91+
92+
#endif /* CONFIG_GENEVE */
93+
4394
static inline void
4495
mlx5e_udp_gso_handle_tx_skb(struct sk_buff *skb)
4596
{

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
#include <net/pkt_cls.h>
3535
#include <linux/mlx5/fs.h>
3636
#include <net/vxlan.h>
37+
#include <net/geneve.h>
3738
#include <linux/bpf.h>
3839
#include <linux/if_bridge.h>
3940
#include <net/page_pool.h>
@@ -43,6 +44,7 @@
4344
#include "en_rep.h"
4445
#include "en_accel/ipsec.h"
4546
#include "en_accel/ipsec_rxtx.h"
47+
#include "en_accel/en_accel.h"
4648
#include "en_accel/tls.h"
4749
#include "accel/ipsec.h"
4850
#include "accel/tls.h"
@@ -2173,10 +2175,13 @@ static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
21732175
{
21742176
void *sqc = param->sqc;
21752177
void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2178+
bool allow_swp;
21762179

2180+
allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2181+
!!MLX5_IPSEC_DEV(priv->mdev);
21772182
mlx5e_build_sq_param_common(priv, param);
21782183
MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2179-
MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2184+
MLX5_SET(sqc, sqc, allow_swp, allow_swp);
21802185
}
21812186

21822187
static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
@@ -4103,6 +4108,12 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
41034108
/* Verify if UDP port is being offloaded by HW */
41044109
if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
41054110
return features;
4111+
4112+
#if IS_ENABLED(CONFIG_GENEVE)
4113+
/* Support Geneve offload for default UDP port */
4114+
if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4115+
return features;
4116+
#endif
41064117
}
41074118

41084119
out:
@@ -4674,15 +4685,16 @@ static void mlx5e_build_nic_netdev(struct net_device *netdev)
46744685
netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
46754686
netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
46764687

4677-
if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4688+
if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4689+
MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
46784690
netdev->hw_enc_features |= NETIF_F_IP_CSUM;
46794691
netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
46804692
netdev->hw_enc_features |= NETIF_F_TSO;
46814693
netdev->hw_enc_features |= NETIF_F_TSO6;
46824694
netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
46834695
}
46844696

4685-
if (mlx5_vxlan_allowed(mdev->vxlan)) {
4697+
if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
46864698
netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
46874699
NETIF_F_GSO_UDP_TUNNEL_CSUM;
46884700
netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232

3333
#include <linux/tcp.h>
3434
#include <linux/if_vlan.h>
35+
#include <net/geneve.h>
3536
#include <net/dsfield.h>
3637
#include "en.h"
3738
#include "ipoib/ipoib.h"
@@ -391,6 +392,10 @@ netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
391392
eseg = &wqe->eth;
392393
dseg = wqe->data;
393394

395+
#if IS_ENABLED(CONFIG_GENEVE)
396+
if (skb->encapsulation)
397+
mlx5e_tx_tunnel_accel(skb, eseg);
398+
#endif
394399
mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
395400

396401
eseg->mss = mss;

0 commit comments

Comments
 (0)