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aarch64: Don't emit invalid zero/sign-extend syntax
Given the following C function: double *f(double *p, unsigned x) { return p + x; } prior to this patch, GCC at -O2 would generate: f: add x0, x0, x1, uxtw 3 ret but this add instruction uses architecturally-invalid syntax: the width of the third operand conflicts with the width of the extension specifier. The third operand is only permitted to be an x register when the extension specifier is (u|s)xtx. This instruction, and analogous insns for adds, sub, subs, and cmp, are rejected by clang, but accepted by binutils. Assembling and disassembling such an insn with binutils gives the architecturally-valid version in the disassembly: 0: 8b214c00 add x0, x0, w1, uxtw gcc-mirror#3 This patch fixes several patterns in the AArch64 backend to use the standard syntax as specified in the Arm ARM such that GCC's output can be assembled by assemblers other than GAS. --- gcc/ChangeLog: * config/aarch64/aarch64.md (*adds_<optab><ALLX:mode>_<GPI:mode>): Ensure extended operand agrees with width of extension specifier. (*subs_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*adds_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise. (*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise. (*add_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*add_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise. (*add_uxt<mode>_shift2): Likewise. (*sub_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*sub_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise. (*sub_uxt<mode>_shift2): Likewise. (*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>): Likewise. (*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/adds3.c: Fix test w.r.t. new syntax. * gcc.target/aarch64/cmp.c: Likewise. * gcc.target/aarch64/subs3.c: Likewise. * gcc.target/aarch64/subsp.c: Likewise. * gcc.target/aarch64/extend-syntax.c: New test. (cherry picked from commit d4febc7)
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‎gcc/config/aarch64/aarch64.md‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2365,7 +2365,7 @@
23652365
(set (match_operand:GPI 0 "register_operand" "=r")
23662366
(plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))]
23672367
""
2368-
"adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
2368+
"adds\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:size>"
23692369
[(set_attr "type" "alus_ext")]
23702370
)
23712371

@@ -2379,7 +2379,7 @@
23792379
(set (match_operand:GPI 0 "register_operand" "=r")
23802380
(minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))]
23812381
""
2382-
"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
2382+
"subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size>"
23832383
[(set_attr "type" "alus_ext")]
23842384
)
23852385

@@ -2397,7 +2397,7 @@
23972397
(match_dup 2))
23982398
(match_dup 3)))]
23992399
""
2400-
"adds\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
2400+
"adds\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2"
24012401
[(set_attr "type" "alus_ext")]
24022402
)
24032403

@@ -2415,7 +2415,7 @@
24152415
(ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
24162416
(match_dup 3))))]
24172417
""
2418-
"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
2418+
"subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3"
24192419
[(set_attr "type" "alus_ext")]
24202420
)
24212421

@@ -2481,7 +2481,7 @@
24812481
(plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r"))
24822482
(match_operand:GPI 2 "register_operand" "r")))]
24832483
""
2484-
"add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
2484+
"add\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:size>"
24852485
[(set_attr "type" "alu_ext")]
24862486
)
24872487

@@ -2503,7 +2503,7 @@
25032503
(match_operand 2 "aarch64_imm3" "Ui3"))
25042504
(match_operand:GPI 3 "register_operand" "r")))]
25052505
""
2506-
"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
2506+
"add\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2"
25072507
[(set_attr "type" "alu_ext")]
25082508
)
25092509

@@ -2700,7 +2700,7 @@
27002700
"*
27012701
operands[3] = GEN_INT (aarch64_uxt_size (INTVAL(operands[2]),
27022702
INTVAL (operands[3])));
2703-
return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
2703+
return \"add\t%<w>0, %<w>4, %w1, uxt%e3 %2\";"
27042704
[(set_attr "type" "alu_ext")]
27052705
)
27062706

@@ -3130,7 +3130,7 @@
31303130
(ANY_EXTEND:GPI
31313131
(match_operand:ALLX 2 "register_operand" "r"))))]
31323132
""
3133-
"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
3133+
"sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size>"
31343134
[(set_attr "type" "alu_ext")]
31353135
)
31363136

@@ -3153,7 +3153,7 @@
31533153
(match_operand:ALLX 2 "register_operand" "r"))
31543154
(match_operand 3 "aarch64_imm3" "Ui3"))))]
31553155
""
3156-
"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
3156+
"sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3"
31573157
[(set_attr "type" "alu_ext")]
31583158
)
31593159

@@ -3404,7 +3404,7 @@
34043404
"*
34053405
operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]),
34063406
INTVAL (operands[3])));
3407-
return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
3407+
return \"sub\t%<w>0, %<w>4, %w1, uxt%e3 %2\";"
34083408
[(set_attr "type" "alu_ext")]
34093409
)
34103410

@@ -3797,7 +3797,7 @@
37973797
(match_operand:ALLX 0 "register_operand" "r"))
37983798
(match_operand:GPI 1 "register_operand" "r")))]
37993799
""
3800-
"cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>"
3800+
"cmp\\t%<GPI:w>1, %w0, <su>xt<ALLX:size>"
38013801
[(set_attr "type" "alus_ext")]
38023802
)
38033803

@@ -3809,7 +3809,7 @@
38093809
(match_operand 1 "aarch64_imm3" "Ui3"))
38103810
(match_operand:GPI 2 "register_operand" "r")))]
38113811
""
3812-
"cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
3812+
"cmp\\t%<GPI:w>2, %w0, <su>xt<ALLX:size> %1"
38133813
[(set_attr "type" "alus_ext")]
38143814
)
38153815

‎gcc/testsuite/gcc.target/aarch64/adds3.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,4 +58,4 @@ int main ()
5858
return 0;
5959
}
6060

61-
/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
61+
/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw" 2 } } */

‎gcc/testsuite/gcc.target/aarch64/cmp.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,4 +58,5 @@ cmp_di_test4 (int a, s64 b, s64 c)
5858
}
5959

6060
/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
61-
/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
61+
/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 2 } } */
62+
/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, sxtw" 2 } } */

‎gcc/testsuite/gcc.target/aarch64/extend-syntax.c‎

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
/* { dg-do compile } */
2+
/* { dg-options "-O2" } */
3+
4+
// Hits *add_uxtdi_shift2 (*add_uxt<mode>_shift2).
5+
/*
6+
** add1:
7+
** add x0, x0, w1, uxtw 3
8+
** ret
9+
*/
10+
unsigned long long *add1(unsigned long long *p, unsigned x)
11+
{
12+
return p + x;
13+
}
14+
15+
// Hits *add_zero_extendsi_di (*add_<optab><ALLX:mode>_<GPI:mode>).
16+
/*
17+
** add2:
18+
** add x0, x0, w1, uxtw
19+
** ret
20+
*/
21+
unsigned long long add2(unsigned long long x, unsigned y)
22+
{
23+
return x + y;
24+
}
25+
26+
// Hits *add_extendsi_shft_di (*add_<optab><ALLX:mode>_shft_<GPI:mode>).
27+
/*
28+
** add3:
29+
** add x0, x0, w1, sxtw 3
30+
** ret
31+
*/
32+
double *add3(double *p, int x)
33+
{
34+
return p + x;
35+
}
36+
37+
// Hits *sub_zero_extendsi_di (*sub_<optab><ALLX:mode>_<GPI:mode>).
38+
/*
39+
** sub1:
40+
** sub x0, x0, w1, uxtw
41+
** ret
42+
*/
43+
unsigned long long sub1(unsigned long long x, unsigned n)
44+
{
45+
return x - n;
46+
}
47+
48+
// Hits *sub_uxtdi_shift2 (*sub_uxt<mode>_shift2).
49+
/*
50+
** sub2:
51+
** sub x0, x0, w1, uxtw 3
52+
** ret
53+
*/
54+
double *sub2(double *x, unsigned n)
55+
{
56+
return x - n;
57+
}
58+
59+
// Hits *sub_extendsi_shft_di (*sub_<optab><ALLX:mode>_shft_<GPI:mode>).
60+
/*
61+
** sub3:
62+
** sub x0, x0, w1, sxtw 3
63+
** ret
64+
*/
65+
double *sub3(double *p, int n)
66+
{
67+
return p - n;
68+
}
69+
70+
// Hits *adds_zero_extendsi_di (*adds_<optab><ALLX:mode>_<GPI:mode>).
71+
int adds1(unsigned long long x, unsigned y)
72+
{
73+
/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */
74+
unsigned long long l = x + y;
75+
return !!l;
76+
}
77+
78+
// Hits *adds_extendsi_shift_di (*adds_<optab><ALLX:mode>_shift_<GPI:mode>).
79+
int adds2(long long x, int y)
80+
{
81+
/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
82+
long long t = x + ((long long)y << 3);
83+
return !!t;
84+
}
85+
86+
// Hits *subs_zero_extendsi_di (*subs_<optab><ALLX:mode>_<GPI:mode>).
87+
unsigned long long z;
88+
int subs1(unsigned long long x, unsigned y)
89+
{
90+
/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */
91+
unsigned long long t = x - y;
92+
z = t;
93+
return !!t;
94+
}
95+
96+
// Hits *subs_extendsi_shift_di (*subs_<optab><ALLX:mode>_shift_<GPI:mode>).
97+
unsigned long long *w;
98+
int subs2(unsigned long long *x, int y)
99+
{
100+
/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
101+
unsigned long long *t = x - y;
102+
w = t;
103+
return !!t;
104+
}
105+
106+
// Hits *cmp_swp_zero_extendsi_regdi (*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>).
107+
int cmp(unsigned long long x, unsigned y)
108+
{
109+
/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */
110+
return !!(x - y);
111+
}
112+
113+
// Hits *cmp_swp_extendsi_shft_di (*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>).
114+
int cmp2(unsigned long long x, int y)
115+
{
116+
/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
117+
return x == ((unsigned long long)y << 3);
118+
}
119+
120+
/* { dg-final { check-function-bodies "**" "" "" } } */

‎gcc/testsuite/gcc.target/aarch64/subs3.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,4 +58,4 @@ int main ()
5858
return 0;
5959
}
6060

61-
/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
61+
/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw" 2 } } */

‎gcc/testsuite/gcc.target/aarch64/subsp.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,4 +16,4 @@ f2 (int *x, int y)
1616
}
1717

1818
/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*\n" } } */
19-
/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*, sxtw 4\n" } } */
19+
/* { dg-final { scan-assembler "sub\tsp, sp, w\[0-9\]*, sxtw 4\n" } } */

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