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failures decreased to 2
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6 files changed

+152
-134
lines changed

6 files changed

+152
-134
lines changed

‎arch/RISCV/RISCVGenCSMappingInsnOp.inc‎

Lines changed: 57 additions & 57 deletions
Large diffs are not rendered by default.

‎arch/RISCV/RISCVInstPrinter.c‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ bool haveRequiredFeatures(const RISCV_SysReg *Reg, MCInst *MI) {
8383
// Not in 32-bit mode.
8484
if (Reg->isRV32Only && RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit))
8585
return false;
86-
86+
8787
return true;
8888
}
8989

@@ -383,13 +383,15 @@ void RISCV_LLVM_printInstruction(MCInst *MI, SStream *O, void * /* MCRegisterInf
383383
Uncompressed.csh = MI->csh;
384384
Uncompressed.flat_insn = MI->flat_insn;
385385
}
386-
386+
387387
if (printAliasInstr(McInstr, MI->address, O))
388388
MI->isAliasInstr = true;
389389
else
390390
printInstruction(McInstr, MI->address, O);
391391
}
392+
printf("\n\n ADDING MISSING ACCESS \n\n");
392393
RISCV_add_groups(MI);
394+
RISCV_add_missing_write_access(MI);
393395
RISCV_compact_operands(MI);
394396
}
395397

@@ -400,4 +402,10 @@ const char *getSysRegName(unsigned reg) {
400402

401403
const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx) {
402404
return getRegisterName(RegNo, AltIdx);
403-
}
405+
}
406+
407+
bool isCompressed(MCInst *MI) {
408+
MCInst unused;
409+
MCInst_Init(&unused, MI->csh->arch);
410+
return uncompressInst(&unused, MI);
411+
}

‎arch/RISCV/RISCVInstPrinter.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,8 @@ const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
5959

6060
const char *getSysRegName(unsigned reg);
6161

62+
bool isCompressed(MCInst *MI);
63+
6264
typedef enum {
6365
#define GET_ENUM_VALUES_SysReg
6466
#include "RISCVGenCSSystemOperandsEnum.inc"

‎arch/RISCV/RISCVMapping.c‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -46,24 +46,6 @@ static const map_insn_ops insn_operands[] = {
4646

4747
void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum)
4848
{
49-
// printf("========== OP: %d, (CODE: %d)", OpNum, MI->Opcode);
50-
// switch (opgroup) {
51-
52-
// case RISCV_OP_GROUP_Operand: printf("\n RISCV_OP_GROUP_Operand"); break;
53-
// case RISCV_OP_GROUP_BranchOperand:printf("\n RISCV_OP_GROUP_BranchOperand"); break;
54-
// case RISCV_OP_GROUP_VMaskReg:printf("\n RISCV_OP_GROUP_VMaskReg"); break;
55-
// case RISCV_OP_GROUP_VTypeI:printf("\n RISCV_OP_GROUP_VTypeI "); break;
56-
// case RISCV_OP_GROUP_ZeroOffsetMemOp:printf("\nRISCV_OP_GROUP_ZeroOffsetMemOp"); break;
57-
// case RISCV_OP_GROUP_Rlist:printf("\nRISCV_OP_GROUP_Rlist"); break;
58-
// case RISCV_OP_GROUP_Spimm:printf("\nRISCV_OP_GROUP_Spimm"); break;
59-
// case RISCV_OP_GROUP_CSRSystemRegister:printf("\n RISCV_OP_GROUP_CSRSystemRegister (%lu)", MCInst_getOperand(MI, OpNum)->ImmVal); break;
60-
// case RISCV_OP_GROUP_RegReg:printf("\nRISCV_OP_GROUP_RegReg"); break;
61-
// case RISCV_OP_GROUP_FRMArg:printf("\nRISCV_OP_GROUP_FRMArg"); break;
62-
// case RISCV_OP_GROUP_FRMArgLegacy:printf("\nRISCV_OP_GROUP_FRMArgLegacy"); break;
63-
// case RISCV_OP_GROUP_FenceArg:printf("\nRISCV_OP_GROUP_FenceArg"); break;
64-
// case RISCV_OP_GROUP_FPImmOperand:printf("\nRISCV_OP_GROUP_FPImmOperand"); break;
65-
// }
66-
// printf("\n================================================================== %d\n", insn_operands[0].ops[0].type);
6749
if (!detail_is_set(MI))
6850
return;
6951
// are not "true" arguments and has no Capstone equivalent
@@ -75,16 +57,13 @@ void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum)
7557
cs_riscv_op *op = &(riscv_details->operands[OpNum]);
7658
op->type = (riscv_op_type) map_get_op_type(MI, OpNum);
7759
op->access = (cs_ac_type) map_get_op_access(MI, OpNum);
78-
//printf("\n&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& OPINDEX: %d, OP: %d", OpNum, op->type);
7960
switch (map_get_op_type(MI, OpNum)) {
8061
case CS_OP_REG:
8162
op->reg = MCInst_getOperand(MI, OpNum)->RegVal;
82-
printf("\n ******************* REG %d: %d\n", OpNum, op->reg);
8363
break;
8464
case CS_OP_MEM:
8565
op->mem.base = 0;
8666
op->mem.disp = MCInst_getOperand(MI, OpNum)->ImmVal;
87-
printf("\n ******************* MEM %d: %d\n", OpNum, op->reg);
8867
break;
8968
case CS_OP_IMM: {
9069
uint64_t val = MCInst_getOperand(MI, OpNum)->ImmVal;
@@ -96,21 +75,18 @@ void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum)
9675
// CSR instruction always read-writes the system operand
9776
op->access = CS_AC_READ_WRITE;
9877
}
99-
printf("\n ******************* IMM %d: %lu\n", OpNum, op->imm);
10078
break;
10179
}
10280
case CS_OP_MEM_REG:
10381
op->type = (riscv_op_type) CS_OP_MEM;
10482
op->mem.base = MCInst_getOperand(MI, OpNum)->RegVal;
105-
printf("\n ******************* REG MEM %d: %d\n", OpNum, op->mem.base);
10683
break;
10784
case CS_OP_MEM_IMM:
10885
// fill in the disp in the last operand
10986
op = &(riscv_details->operands[OpNum - 1]);
11087
op->type = (riscv_op_type) CS_OP_MEM;
11188
op->mem.disp = MCInst_getOperand(MI, OpNum)->ImmVal;
11289
riscv_details->op_count--; // don't increase the count, cancel the coming increment
113-
printf("\n ******************* MEM %d: %lu\n", OpNum, op->mem.disp);
11490
break;
11591
case CS_OP_INVALID:
11692
break;
@@ -158,6 +134,31 @@ void RISCV_compact_operands(MCInst *MI) {
158134
memset((void *)(&ops[i]), CS_OP_INVALID, sizeof(cs_riscv_op));
159135
}
160136
}
137+
138+
// some C instructions have only 2 apparent operands, one of them is read-write
139+
// the operand information for those instruction has 3 operands, the first and second are the same,
140+
// but once with read and once write access
141+
// when those instructions are disassembled only the operand entry with the read access is used,
142+
// and therefore the read-write operand is wrongly classified as only-read
143+
// this logic tries to correct that
144+
void RISCV_add_missing_write_access(MCInst* MI) {
145+
printf("REACHABLE %d\n\n", !isCompressed(MI));
146+
if (!isCompressed(MI))
147+
return;
148+
149+
cs_riscv *riscv_details = &(MI->flat_insn->detail->riscv);
150+
cs_riscv_op* ops = riscv_details->operands;
151+
// make the detection condition as specific as possible
152+
// so it doesn't accidentally trigger for other cases
153+
printf("\n---------------- %d @ %d @ %d @ %d", riscv_details->op_count, ops[0].type,ops[1].type,ops[1].access);
154+
if (riscv_details->op_count == 2
155+
&& ops[0].type == RISCV_OP_INVALID && ops[1].type == RISCV_OP_REG
156+
&& ops[1].access == CS_AC_READ) {
157+
printf("\n\n&&&&&&&&&&&&& MISSING WRITE ACCESS DETECTED FOR OPCODE %d !!!!!!!!!!!!!!!!!!!!!!! \n\n", MI->Opcode);
158+
ops[1].access |= CS_AC_WRITE;
159+
}
160+
}
161+
161162
// given internal insn id, return public instruction info
162163
void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id)
163164
{
@@ -230,7 +231,6 @@ const char *RISCV_group_name(csh handle, unsigned int id)
230231
{
231232
#ifndef CAPSTONE_DIET
232233
// verify group id
233-
printf("GROUP ID: %d\n", id);
234234
// if past the end
235235
if (id >= RISCV_GRP_ENDING ||
236236
// or in the encoding gap between generic groups and arch-specific groups

‎arch/RISCV/RISCVMapping.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,9 @@ void RISCV_add_groups(MCInst *MI);
2424

2525
void RISCV_compact_operands(MCInst *MI);
2626

27+
void RISCV_add_missing_write_access(MCInst* MI);
28+
29+
2730
// map instruction name to instruction ID
2831
riscv_insn RISCV_map_insn(const char *name);
2932

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