Update python bindings with changes to PPC and cs_insn structs.

Author: Rot127

bindings/python/capstone/__init__.py

@@ -334,6 +334,7 @@
 CS_AC_INVALID  = 0        # Invalid/unitialized access type.
 CS_AC_READ     = (1 << 0) # Operand that is read from.
 CS_AC_WRITE    = (1 << 1) # Operand that is written to.
+CS_AC_READ_WRITE = (2)
 
 # Capstone syntax value
 CS_OPT_SYNTAX_DEFAULT = 1 << 1  # Default assembly syntax of all platforms (CS_OPT_SYNTAX)
@@ -479,11 +480,14 @@ class _cs_detail(ctypes.Structure):
 class _cs_insn(ctypes.Structure):
     _fields_ = (
         ('id', ctypes.c_uint),
+        ('alias_id', ctypes.c_uint64),
         ('address', ctypes.c_uint64),
         ('size', ctypes.c_uint16),
         ('bytes', ctypes.c_ubyte * 24),
         ('mnemonic', ctypes.c_char * 32),
         ('op_str', ctypes.c_char * 160),
+        ('is_alias', ctypes.c_bool),
+        ('usesAliasDetails', ctypes.c_bool),
         ('detail', ctypes.POINTER(_cs_detail)),
     )
 
@@ -783,7 +787,7 @@ def __gen_detail(self):
         elif arch == CS_ARCH_MIPS:
                 self.operands = mips.get_arch_info(self._raw.detail.contents.arch.mips)
         elif arch == CS_ARCH_PPC:
-            (self.bc, self.bh, self.update_cr0, self.operands) = \
+            (self.bc, self.update_cr0, self.operands) = \
                 ppc.get_arch_info(self._raw.detail.contents.arch.ppc)
         elif arch == CS_ARCH_SPARC:
             (self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)

bindings/python/capstone/ppc.py

@@ -9,27 +9,33 @@ class PpcOpMem(ctypes.Structure):
     _fields_ = (
         ('base', ctypes.c_uint),
         ('disp', ctypes.c_int32),
-    )
-
-class PpcOpCrx(ctypes.Structure):
-    _fields_ = (
-        ('scale', ctypes.c_uint),
-        ('reg', ctypes.c_uint),
-        ('cond', ctypes.c_uint),
+        ('offset', ctypes.c_uint),
     )
 
 class PpcOpValue(ctypes.Union):
     _fields_ = (
         ('reg', ctypes.c_uint),
         ('imm', ctypes.c_int64),
         ('mem', PpcOpMem),
-        ('crx', PpcOpCrx),
     )
 
 class PpcOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', PpcOpValue),
+        ('access', ctypes.c_uint),
+    )
+
+class PpcBC(ctypes.Structure):
+    _fields_ = (
+        ('bo', ctypes.c_uint8),
+        ('bi', ctypes.c_uint8),
+        ('crX_bit', ctypes.c_uint),
+        ('crX', ctypes.c_uint),
+        ('hint', ctypes.c_uint),
+        ('pred_cr', ctypes.c_uint),
+        ('pred_ctr', ctypes.c_uint),
+        ('bh', ctypes.c_uint),
     )
 
     @property
@@ -44,20 +50,14 @@ def reg(self):
     def mem(self):
         return self.value.mem
 
-    @property
-    def crx(self):
-        return self.value.crx
-
-
 class CsPpc(ctypes.Structure):
     _fields_ = (
-        ('bc', ctypes.c_uint),
-        ('bh', ctypes.c_uint),
+        ('bc', PpcBC),
         ('update_cr0', ctypes.c_bool),
         ('op_count', ctypes.c_uint8),
         ('operands', PpcOp * 8),
     )
 
 def get_arch_info(a):
-    return (a.bc, a.bh, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))
+    return (a.bc, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))
 

bindings/python/pyx/ccapstone.pxd

@@ -18,11 +18,14 @@ cdef extern from "<capstone/capstone.h>":
 
     ctypedef struct cs_insn:
         unsigned int id
+        uint64_t alias_id;
         uint64_t address
         uint16_t size
         uint8_t bytes[24]
         char mnemonic[32]
         char op_str[160]
+        bool is_alias;
+        bool usesAliasDetails;
         cs_detail *detail
 
     ctypedef enum cs_err:

bindings/python/test_ppc.py

@@ -30,33 +30,42 @@ def print_insn_detail(insn):
         c = 0
         for i in insn.operands:
             if i.type == PPC_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.value.reg)))
             if i.type == PPC_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.value.imm)))
             if i.type == PPC_OP_MEM:
                 print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
+                if i.value.mem.base != 0:
                     print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.disp != 0:
+                        % (c, insn.reg_name(i.value.mem.base)))
+                if i.value.mem.offset != 0:
+                    print("\t\t\toperands[%u].mem.offset: REG = %s\n" \
+                        % (c, insn.reg_name(i.value.mem.offset)))
+                if i.value.mem.disp != 0:
                     print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x_32(i.mem.disp)))
-            if i.type == PPC_OP_CRX:
-                print("\t\toperands[%u].type: CRX" % c)
-                print("\t\t\toperands[%u].crx.scale: = %u" \
-                        % (c, i.crx.scale))
-                if i.crx.reg != 0:
-                    print("\t\t\toperands[%u].crx.reg: REG = %s" \
-                        % (c, insn.reg_name(i.crx.reg)))
-                if i.crx.cond != 0:
-                    print("\t\t\toperands[%u].crx.cond: 0x%x" \
-                        % (c, i.crx.cond))
+                        % (c, to_x_32(i.value.mem.disp)))
+            if i.access == CS_AC_READ:
+                print("\t\toperands[%u].access: READ\n" % (c))
+            elif i.access == CS_AC_WRITE:
+                print("\t\toperands[%u].access: WRITE\n" % (c))
+            elif i.access == CS_AC_READ | CS_AC_WRITE:
+                print("\t\toperands[%u].access: READ | WRITE\n" % (c))
             c += 1
+        if insn.bc.pred_cr != PPC_PRED_INVALID or \
+            insn.bc.pred_ctr != PPC_PRED_INVALID:
+            print("\tBranch:\n")
+            print("\t\tbi: %u\n" % insn.bc.bi)
+            print("\t\tbo: %u\n" % insn.bc.bo)
+            if insn.bc.bh != PPC_BH_INVALID:
+                print("\t\tbh: %u\n" %insn.bc.bh)
+            if insn.bc.pred_cr != PPC_PRED_INVALID:
+                print("\t\tcrX: %s\n" % insn.reg_name(insn.bc.crX))
+                print("\t\tpred CR-bit: %u\n" % insn.bc.pred_cr)
+            if insn.bc.pred_ctr != PPC_PRED_INVALID:
+                print("\t\tpred CTR: %u\n" % insn.bc.pred_ctr)
+            if insn.bc.hint != PPC_BH_INVALID:
+                print("\t\thint: %u\n" % insn.bc.hint)
 
-    if insn.bc:
-        print("\tBranch code: %u" % insn.bc)
-    if insn.bh:
-        print("\tBranch hint: %u" % insn.bh)
     if insn.update_cr0:
         print("\tUpdate-CR0: True")