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[X86] Avoid introducing extra shuffles when lowering packed vector shifts.
When lowering a vector shift node, the backend checks if the shift count is a shuffle with a splat mask. If so, then it introduces an extra dag node to extract the splat value from the shuffle. The splat value is then used to generate a shift count of a target specific shift. However, if we know that the shift count is a splat shuffle, we can use the splat index 'I' to extract the I-th element from the first shuffle operand. The advantage is that the splat shuffle may become dead since we no longer use it. Example: ;; define <4 x i32> @example(<4 x i32> %a, <4 x i32> %b) { %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer %shl = shl <4 x i32> %a, %c ret <4 x i32> %shl } ;; Before this patch, llc generated the following code (-mattr=+avx): vpshufd $0, %xmm1, %xmm1 # xmm1 = xmm1[0,0,0,0] vpxor %xmm2, %xmm2 vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] vpslld %xmm1, %xmm0, %xmm0 retq With this patch, the redundant splat operation is removed from the code. vpxor %xmm2, %xmm2 vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] vpslld %xmm1, %xmm0, %xmm0 retq git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223461 91177308-0d34-0410-b5e6-96231b3b80d8
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-16
lines changed

3 files changed

+173
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‎lib/Target/X86/X86ISelLowering.cpp

+12-15
Original file line numberDiff line numberDiff line change
@@ -18444,30 +18444,27 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
1844418444
} else {
1844518445
if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
1844618446
Amt = Amt.getOperand(0);
18447-
if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18448-
cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18447+
18448+
ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18449+
if (SVN && SVN->isSplat()) {
18450+
unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
1844918451
SDValue InVec = Amt.getOperand(0);
1845018452
if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18451-
unsigned NumElts = InVec.getValueType().getVectorNumElements();
18452-
unsigned i = 0;
18453-
for (; i != NumElts; ++i) {
18454-
SDValue Arg = InVec.getOperand(i);
18455-
if (Arg.getOpcode() == ISD::UNDEF) continue;
18456-
BaseShAmt = Arg;
18457-
break;
18458-
}
18453+
assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18454+
"Unexpected shuffle index found!");
18455+
BaseShAmt = InVec.getOperand(SplatIdx);
1845918456
} else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
1846018457
if (ConstantSDNode *C =
1846118458
dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18462-
unsigned SplatIdx =
18463-
cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
1846418459
if (C->getZExtValue() == SplatIdx)
1846518460
BaseShAmt = InVec.getOperand(1);
1846618461
}
1846718462
}
18468-
if (!BaseShAmt.getNode())
18469-
BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18470-
DAG.getIntPtrConstant(0));
18463+
18464+
if (!BaseShAmt)
18465+
// Avoid introducing an extract element from a shuffle.
18466+
BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18467+
DAG.getIntPtrConstant(SplatIdx));
1847118468
}
1847218469
}
1847318470

‎test/CodeGen/X86/lower-vec-shift-2.ll

+160
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,160 @@
1+
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s -check-prefix=SSE2
2+
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s -check-prefix=AVX
3+
4+
define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
5+
; SSE2-LABEL: test1:
6+
; SSE2: # BB#0
7+
; SSE2-NEXT: movd %xmm1, %eax
8+
; SSE2-NEXT: movzwl %ax, %eax
9+
; SSE2-NEXT: movd %eax, %xmm1
10+
; SSE2-NEXT: psllw %xmm1, %xmm0
11+
; SSE2-NEXT: retq
12+
; AVX-LABEL: test1:
13+
; AVX: # BB#0
14+
; AVX-NEXT: vmovd %xmm1, %eax
15+
; AVX-NEXT: movzwl %ax, %eax
16+
; AVX-NEXT: vmovd %eax, %xmm1
17+
; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
18+
; AVX-NEXT: retq
19+
entry:
20+
%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
21+
%shl = shl <8 x i16> %A, %vecinit14
22+
ret <8 x i16> %shl
23+
}
24+
25+
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
26+
; SSE2-LABEL: test2:
27+
; SSE2: # BB#0
28+
; SSE2-NEXT: xorps %xmm2, %xmm2
29+
; SSE2-NEXT: movss %xmm1, %xmm2
30+
; SSE2-NEXT: pslld %xmm2, %xmm0
31+
; SSE2-NEXT: retq
32+
; AVX-LABEL: test2:
33+
; AVX: # BB#0
34+
; AVX-NEXT: vpxor %xmm2, %xmm2
35+
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
36+
; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
37+
; AVX-NEXT: retq
38+
entry:
39+
%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
40+
%shl = shl <4 x i32> %A, %vecinit6
41+
ret <4 x i32> %shl
42+
}
43+
44+
define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {
45+
; SSE2-LABEL: test3:
46+
; SSE2: # BB#0
47+
; SSE2-NEXT: movd %xmm1, %rax
48+
; SSE2-NEXT: movd %eax, %xmm1
49+
; SSE2-NEXT: psllq %xmm1, %xmm0
50+
; SSE2-NEXT: retq
51+
; AVX-LABEL: test3:
52+
; AVX: # BB#0
53+
; AVX-NEXT: vmovq %xmm1, %rax
54+
; AVX-NEXT: vmovd %eax, %xmm1
55+
; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
56+
; AVX-NEXT: retq
57+
entry:
58+
%vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
59+
%shl = shl <2 x i64> %A, %vecinit2
60+
ret <2 x i64> %shl
61+
}
62+
63+
define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {
64+
; SSE2-LABEL: test4:
65+
; SSE2: # BB#0
66+
; SSE2-NEXT: movd %xmm1, %eax
67+
; SSE2-NEXT: movzwl %ax, %eax
68+
; SSE2-NEXT: movd %eax, %xmm1
69+
; SSE2-NEXT: psrlw %xmm1, %xmm0
70+
; SSE2-NEXT: retq
71+
; AVX-LABEL: test4:
72+
; AVX: # BB#0
73+
; AVX-NEXT: vmovd %xmm1, %eax
74+
; AVX-NEXT: movzwl %ax, %eax
75+
; AVX-NEXT: vmovd %eax, %xmm1
76+
; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
77+
; AVX-NEXT: retq
78+
entry:
79+
%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
80+
%shr = lshr <8 x i16> %A, %vecinit14
81+
ret <8 x i16> %shr
82+
}
83+
84+
define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
85+
; SSE2-LABEL: test5:
86+
; SSE2: # BB#0
87+
; SSE2-NEXT: xorps %xmm2, %xmm2
88+
; SSE2-NEXT: movss %xmm1, %xmm2
89+
; SSE2-NEXT: psrld %xmm2, %xmm0
90+
; SSE2-NEXT: retq
91+
; AVX-LABEL: test5:
92+
; AVX: # BB#0
93+
; AVX-NEXT: vpxor %xmm2, %xmm2
94+
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
95+
; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
96+
; AVX-NEXT: retq
97+
entry:
98+
%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
99+
%shr = lshr <4 x i32> %A, %vecinit6
100+
ret <4 x i32> %shr
101+
}
102+
103+
define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {
104+
; SSE2-LABEL: test6:
105+
; SSE2: # BB#0
106+
; SSE2-NEXT: movd %xmm1, %rax
107+
; SSE2-NEXT: movd %eax, %xmm1
108+
; SSE2-NEXT: psrlq %xmm1, %xmm0
109+
; SSE2-NEXT: retq
110+
; AVX-LABEL: test6:
111+
; AVX: # BB#0
112+
; AVX-NEXT: vmovq %xmm1, %rax
113+
; AVX-NEXT: vmovd %eax, %xmm1
114+
; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
115+
; AVX-NEXT: retq
116+
entry:
117+
%vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
118+
%shr = lshr <2 x i64> %A, %vecinit2
119+
ret <2 x i64> %shr
120+
}
121+
122+
define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {
123+
; SSE2-LABEL: test7:
124+
; SSE2: # BB#0
125+
; SSE2-NEXT: movd %xmm1, %eax
126+
; SSE2-NEXT: movzwl %ax, %eax
127+
; SSE2-NEXT: movd %eax, %xmm1
128+
; SSE2-NEXT: psraw %xmm1, %xmm0
129+
; SSE2-NEXT: retq
130+
; AVX-LABEL: test7:
131+
; AVX: # BB#0
132+
; AVX-NEXT: vmovd %xmm1, %eax
133+
; AVX-NEXT: movzwl %ax, %eax
134+
; AVX-NEXT: vmovd %eax, %xmm1
135+
; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
136+
; AVX-NEXT: retq
137+
entry:
138+
%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
139+
%shr = ashr <8 x i16> %A, %vecinit14
140+
ret <8 x i16> %shr
141+
}
142+
143+
define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
144+
; SSE2-LABEL: test8:
145+
; SSE2: # BB#0
146+
; SSE2-NEXT: xorps %xmm2, %xmm2
147+
; SSE2-NEXT: movss %xmm1, %xmm2
148+
; SSE2-NEXT: psrad %xmm2, %xmm0
149+
; SSE2-NEXT: retq
150+
; AVX-LABEL: test8:
151+
; AVX: # BB#0
152+
; AVX-NEXT: vpxor %xmm2, %xmm2
153+
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
154+
; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
155+
; AVX-NEXT: retq
156+
entry:
157+
%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
158+
%shr = ashr <4 x i32> %A, %vecinit6
159+
ret <4 x i32> %shr
160+
}

‎test/CodeGen/X86/vshift-4.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ entry:
5757
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
5858
entry:
5959
; CHECK-LABEL: shift3a:
60-
; CHECK: movzwl
60+
; CHECK: pextrw $6
6161
; CHECK: psllw
6262
%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
6363
%shl = shl <8 x i16> %val, %shamt

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