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Ethernet: fixed CH_BASE for W5200
1 parent d02e908 commit c60d939

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2 files changed

+6
-2
lines changed

2 files changed

+6
-2
lines changed

libraries/Ethernet/src/utility/w5100.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ W5x00Class W5100;
1717

1818
uint8_t W5x00Class::chipset = W5x00Chipset::W5100;
1919
uint8_t W5x00Class::sockets = 4;
20+
uint16_t W5x00Class::CH_BASE = 0;
2021

2122
#define TX_RX_MAX_BUF_SIZE 2048
2223
#define TX_BUF 0x1100
@@ -79,6 +80,7 @@ void W5x00Class::init(void)
7980
// The default size for the RX and TX buffers is 2 kB
8081
if (chipset == W5x00Chipset::W5100) {
8182
sockets = 4;
83+
CH_BASE = 0x0400;
8284
SPI.beginTransaction(SPI_ETHERNET_SETTINGS);
8385
writeMR(1<<RST);
8486
SPI.endTransaction();
@@ -91,6 +93,7 @@ void W5x00Class::init(void)
9193
}
9294
} else if (chipset == W5x00Chipset::W5200) {
9395
sockets = 8;
96+
CH_BASE = 0x4000;
9497
SPI.beginTransaction(SPI_ETHERNET_SETTINGS);
9598
writeMR(1<<RST);
9699
SPI.endTransaction();
@@ -101,8 +104,9 @@ void W5x00Class::init(void)
101104
SBASE[i] = TXBUF_BASE + SSIZE * i;
102105
RBASE[i] = RXBUF_BASE + RSIZE * i;
103106
}
104-
} else {
107+
} else { // W5500
105108
sockets = 8;
109+
CH_BASE = 0x0400;
106110
SPI.beginTransaction(SPI_ETHERNET_SETTINGS);
107111
writeMR(1<<RST);
108112
SPI.endTransaction();

libraries/Ethernet/src/utility/w5100.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,7 @@ class W5x00Class {
276276
static inline uint16_t readSn(SOCKET _s, uint16_t _addr, uint8_t *_buf, uint16_t len);
277277
static inline uint16_t writeSn(SOCKET _s, uint16_t _addr, uint8_t *_buf, uint16_t len);
278278

279-
static const uint16_t CH_BASE = 0x0400;
279+
static uint16_t CH_BASE;
280280
static const uint16_t CH_SIZE = 0x0100;
281281

282282
#define __SOCKET_REGISTER8(name, address) \

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