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[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b). For example: add z0.s, z1.s, z2.b -> invalid element width ^_____^ mismatch For the vector-with-shift/extend (e.g. z0.s, uxtw brson#2) this patch takes a slightly different approach and instead returns a 'invalid operand' if the element size is not as expected. This is because the diagnostics are more specificied to suggest using the right shift/extend suffix. This is a trade-off not to introduce more operand classes and still provide useful diagnostics for LD1 and PRF instructions. For example: ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand ^________________^ mismatch For gather prefetches, both 'z0.s' and 'z0.d' would be allowed: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) brson#2' prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) brson#2' Without this change, the diagnostic would unnecessarily suggest a different element size: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) brson#2' Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46688 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332483 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64RegisterInfo.td‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -792,7 +792,7 @@ def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
792792

793793
class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
794794
let Name = "SVE" # name # "Reg";
795-
let PredicateMethod = "isSVEVectorRegOfWidth<"
795+
let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"
796796
# Width # ", " # "AArch64::" # RegClass # "RegClassID>";
797797
let DiagnosticType = "InvalidSVE" # name # "Reg";
798798
let RenderMethod = "addRegOperands";
@@ -837,9 +837,10 @@ def ZPR : RegisterClass<"AArch64",
837837

838838
class ZPRAsmOperand <string name, int Width>: AsmOperandClass {
839839
let Name = "SVE" # name # "Reg";
840-
let PredicateMethod = "isSVEVectorRegOfWidth<"
840+
let PredicateMethod = "isSVEDataVectorRegOfWidth<"
841841
# Width # ", AArch64::ZPRRegClassID>";
842842
let RenderMethod = "addRegOperands";
843+
let DiagnosticType = "InvalidZPR" # Width;
843844
let ParserMethod = "tryParseSVEDataVector<false, "
844845
# !if(!eq(Width, 0), "false", "true") # ">";
845846
}
@@ -958,7 +959,7 @@ class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
958959
let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
959960
# !if(ScaleAlwaysSame, "Only", "");
960961

961-
let PredicateMethod = "isSVEVectorRegWithShiftExtend<"
962+
let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"
962963
# RegWidth # ", AArch64::ZPRRegClassID, "
963964
# "AArch64_AM::" # ShiftExtend # ", "
964965
# Scale # ", "

‎lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 38 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -872,21 +872,37 @@ class AArch64Operand : public MCParsedAsmOperand {
872872
}
873873

874874
template <int ElementWidth, unsigned Class>
875-
bool isSVEVectorRegOfWidth() const {
876-
return isSVEVectorReg<Class>() &&
877-
(ElementWidth == 0 || Reg.ElementWidth == ElementWidth);
875+
DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
876+
if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
877+
return DiagnosticPredicateTy::NoMatch;
878+
879+
if (isSVEVectorReg<Class>() &&
880+
(ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
881+
return DiagnosticPredicateTy::Match;
882+
883+
return DiagnosticPredicateTy::NearMatch;
884+
}
885+
886+
template <int ElementWidth, unsigned Class>
887+
DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
888+
if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
889+
return DiagnosticPredicateTy::NoMatch;
890+
891+
if (isSVEVectorReg<Class>() &&
892+
(ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
893+
return DiagnosticPredicateTy::Match;
894+
895+
return DiagnosticPredicateTy::NearMatch;
878896
}
879897

880898
template <int ElementWidth, unsigned Class,
881899
AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
882900
bool ShiftWidthAlwaysSame>
883-
DiagnosticPredicate isSVEVectorRegWithShiftExtend() const {
884-
if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
901+
DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
902+
auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
903+
if (!VectorMatch.isMatch())
885904
return DiagnosticPredicateTy::NoMatch;
886905

887-
if (!isSVEVectorRegOfWidth<ElementWidth, Class>())
888-
return DiagnosticPredicateTy::NearMatch;
889-
890906
// Give a more specific diagnostic when the user has explicitly typed in
891907
// a shift-amount that does not match what is expected, but for which
892908
// there is also an unscaled addressing mode (e.g. sxtw/uxtw).
@@ -3817,6 +3833,14 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
38173833
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #2'");
38183834
case Match_InvalidZPR64LSL64:
38193835
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'");
3836+
case Match_InvalidZPR0:
3837+
return Error(Loc, "expected register without element width sufix");
3838+
case Match_InvalidZPR8:
3839+
case Match_InvalidZPR16:
3840+
case Match_InvalidZPR32:
3841+
case Match_InvalidZPR64:
3842+
case Match_InvalidZPR128:
3843+
return Error(Loc, "invalid element width");
38203844
case Match_InvalidSVEPattern:
38213845
return Error(Loc, "invalid predicate pattern");
38223846
case Match_InvalidSVEPredicateAnyReg:
@@ -4299,6 +4323,12 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
42994323
case Match_InvalidZPR64LSL16:
43004324
case Match_InvalidZPR64LSL32:
43014325
case Match_InvalidZPR64LSL64:
4326+
case Match_InvalidZPR0:
4327+
case Match_InvalidZPR8:
4328+
case Match_InvalidZPR16:
4329+
case Match_InvalidZPR32:
4330+
case Match_InvalidZPR64:
4331+
case Match_InvalidZPR128:
43024332
case Match_InvalidSVEPredicateAnyReg:
43034333
case Match_InvalidSVEPattern:
43044334
case Match_InvalidSVEPredicateBReg:

‎test/MC/AArch64/SVE/add-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ add z20.h, z2.h, z31.x
1414

1515
// Element size specifiers should match.
1616
add z27.h, z11.h, z27.b
17-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
1818
// CHECK-NEXT: add z27.h, z11.h, z27.b
1919
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2020

‎test/MC/AArch64/SVE/ld1b-diagnostics.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -115,17 +115,17 @@ ld1b z0.b, p0/z, [x0, w0, uxtw]
115115
// Invalid scalar + vector addressing modes
116116

117117
ld1b z0.d, p0/z, [x0, z0.b]
118-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
118+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
119119
// CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.b]
120120
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
121121

122122
ld1b z0.d, p0/z, [x0, z0.h]
123-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
123+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
124124
// CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.h]
125125
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
126126

127127
ld1b z0.d, p0/z, [x0, z0.s]
128-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
128+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
129129
// CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.s]
130130
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
131131

‎test/MC/AArch64/SVE/ld1d-diagnostics.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ ld1d z0.d, p0/z, [x0, w0, uxtw]
7575
// Invalid scalar + vector addressing modes
7676

7777
ld1d z0.d, p0/z, [x0, z0.s]
78-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
78+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
7979
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s]
8080
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8181

@@ -99,12 +99,12 @@ ld1d z0.d, p0/z, [x0, z0.d, lsl]
9999
// Invalid vector + immediate addressing modes
100100

101101
ld1d z0.s, p0/z, [z0.s]
102-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
102+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
103103
// CHECK-NEXT: ld1d z0.s, p0/z, [z0.s]
104104
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
105105

106106
ld1d z0.s, p0/z, [z0.s, #8]
107-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
107+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
108108
// CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8]
109109
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
110110

‎test/MC/AArch64/SVE/ld1h-diagnostics.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,12 @@ ld1h z0.h, p0/z, [x0, w0, uxtw]
105105
// Invalid scalar + vector addressing modes
106106

107107
ld1h z0.d, p0/z, [x0, z0.h]
108-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
108+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
109109
// CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h]
110110
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
111111

112112
ld1h z0.d, p0/z, [x0, z0.s]
113-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
113+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
114114
// CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s]
115115
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
116116

‎test/MC/AArch64/SVE/ld1rd-diagnostics.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,17 +33,17 @@ ld1rd z0.d, p1/z, [x0, #3]
3333
// Invalid result vector element size
3434

3535
ld1rd z0.b, p1/z, [x0]
36-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
36+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
3737
// CHECK-NEXT: ld1rd z0.b, p1/z, [x0]
3838
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3939

4040
ld1rd z0.h, p1/z, [x0]
41-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
4242
// CHECK-NEXT: ld1rd z0.h, p1/z, [x0]
4343
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4444

4545
ld1rd z0.s, p1/z, [x0]
46-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
46+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
4747
// CHECK-NEXT: ld1rd z0.s, p1/z, [x0]
4848
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4949

‎test/MC/AArch64/SVE/ld1rh-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ ld1rh z0.h, p1/z, [x0, #3]
3333
// Invalid result vector element size
3434

3535
ld1rh z0.b, p1/z, [x0]
36-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
36+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
3737
// CHECK-NEXT: ld1rh z0.b, p1/z, [x0]
3838
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3939

‎test/MC/AArch64/SVE/ld1rqb-diagnostics.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,17 +42,17 @@ ld1rqb z0.b, p0/z, [x0, #16, MUL VL]
4242
// Invalid destination register width.
4343

4444
ld1rqb z0.h, p0/z, [x0]
45-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
4646
// CHECK-NEXT: ld1rqb z0.h, p0/z, [x0]
4747
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4848

4949
ld1rqb z0.s, p0/z, [x0]
50-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5151
// CHECK-NEXT: ld1rqb z0.s, p0/z, [x0]
5252
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
5353

5454
ld1rqb z0.d, p0/z, [x0]
55-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
55+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5656
// CHECK-NEXT: ld1rqb z0.d, p0/z, [x0]
5757
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
5858

‎test/MC/AArch64/SVE/ld1rqd-diagnostics.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,17 +42,17 @@ ld1rqd z0.d, p0/z, [x0, #16, MUL VL]
4242
// Invalid destination register width.
4343

4444
ld1rqd z0.b, p0/z, [x0, x1, lsl #3]
45-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
4646
// CHECK-NEXT: ld1rqd z0.b, p0/z, [x0, x1, lsl #3]
4747
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4848

4949
ld1rqd z0.h, p0/z, [x0, x1, lsl #3]
50-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5151
// CHECK-NEXT: ld1rqd z0.h, p0/z, [x0, x1, lsl #3]
5252
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
5353

5454
ld1rqd z0.s, p0/z, [x0, x1, lsl #3]
55-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
55+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5656
// CHECK-NEXT: ld1rqd z0.s, p0/z, [x0, x1, lsl #3]
5757
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
5858

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