Skip to content

Commit 15f591e

Browse files
sdesmalen-armsdesmalen-arm
committed
[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to improve diagnostics for SVE's gather load (scalar + vector) addressing modes. Instead of always suggesting the 'unscaled' addressing mode, the use of DiagnosticPredicate enables a more specific error message in the context where the scaling is incorrect. For example: ld1h z0.d, p0/z, [x0, z0.d, lsl brson#2] ^ shift amount should be '1' Instead of suggesting the packed, unscaled addressing mode: expected 'z[0..31].d, (uxtw|sxtw)' the assembler now suggests using the proper scaling: expected 'z[0..31].d, (lsl|uxtw|sxtw) brson#1' Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46124 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331162 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 1fe6017 commit 15f591e

13 files changed

+74
-55
lines changed

‎lib/Target/AArch64/AArch64RegisterInfo.td‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -934,22 +934,27 @@ def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
934934
let ParserMatchClass = ZPRVectorList<64, 4>;
935935
}
936936

937-
class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale>
938-
: AsmOperandClass {
939-
let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale;
937+
class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
938+
bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
939+
let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
940+
# !if(ScaleAlwaysSame, "Only", "");
941+
940942
let PredicateMethod = "isSVEVectorRegWithShiftExtend<"
941943
# RegWidth # ", AArch64::ZPRRegClassID, "
942944
# "AArch64_AM::" # ShiftExtend # ", "
943-
# Scale # ">";
945+
# Scale # ", "
946+
# !if(ScaleAlwaysSame, "true", "false")
947+
# ">";
944948
let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
945949
let RenderMethod = "addRegOperands";
946950
let ParserMethod = "tryParseSVEDataVector<true, true>";
947951
}
948952

949953
class ZPRExtendRegisterOperand<bit SignExtend, bit IsLSL, string Repr,
950-
int RegWidth, int Scale> : RegisterOperand<ZPR> {
954+
int RegWidth, int Scale, string Suffix = "">
955+
: RegisterOperand<ZPR> {
951956
let ParserMatchClass =
952-
!cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale);
957+
!cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
953958
let PrintMethod = "printRegWithShiftExtend<"
954959
# !if(SignExtend, "true", "false") # ", "
955960
# Scale # ", "
@@ -959,22 +964,26 @@ class ZPRExtendRegisterOperand<bit SignExtend, bit IsLSL, string Repr,
959964

960965
foreach RegWidth = [32, 64] in {
961966
// UXTW(8|16|32|64)
967+
def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
962968
def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
963969
def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
964970
def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
965971
def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
966972

973+
def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "Only">;
967974
def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
968975
def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
969976
def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
970977
def ZPR#RegWidth#ExtUXTW64 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>;
971978

972979
// SXTW(8|16|32|64)
980+
def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>;
973981
def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
974982
def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
975983
def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
976984
def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;
977985

986+
def ZPR#RegWidth#ExtSXTW8Only : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "Only">;
978987
def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;
979988
def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
980989
def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
@@ -986,7 +995,6 @@ def ZPR64AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", 64, 8>;
986995
def ZPR64AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", 64, 16>;
987996
def ZPR64AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", 64, 32>;
988997
def ZPR64AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", 64, 64>;
989-
990998
def ZPR64ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 8>;
991999
def ZPR64ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 16>;
9921000
def ZPR64ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 32>;

‎lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -108,10 +108,10 @@ let Predicates = [HasSVE] in {
108108

109109
// Gathers using unscaled 32-bit offsets, e.g.
110110
// ld1h z0.s, p0/z, [x0, z0.s, uxtw]
111-
defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
112-
defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
113-
defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
114-
defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
111+
defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
112+
defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
113+
defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
114+
defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
115115
defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
116116
defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
117117
defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
@@ -190,10 +190,10 @@ let Predicates = [HasSVE] in {
190190

191191
// Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g.
192192
// ld1h z0.d, p0/z, [x0, z0.d, uxtw]
193-
defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
194-
defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
195-
defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
196-
defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
193+
defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
194+
defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
195+
defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
196+
defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
197197
defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
198198
defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
199199
defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;

‎lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -877,14 +877,25 @@ class AArch64Operand : public MCParsedAsmOperand {
877877
}
878878

879879
template <int ElementWidth, unsigned Class,
880-
AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth>
880+
AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
881+
bool ShiftWidthAlwaysSame>
881882
DiagnosticPredicate isSVEVectorRegWithShiftExtend() const {
882883
if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
883884
return DiagnosticPredicateTy::NoMatch;
884885

885-
if (isSVEVectorRegOfWidth<ElementWidth, Class>() &&
886-
ShiftExtendTy == getShiftExtendType() &&
887-
getShiftExtendAmount() == Log2_32(ShiftWidth / 8))
886+
if (!isSVEVectorRegOfWidth<ElementWidth, Class>())
887+
return DiagnosticPredicateTy::NearMatch;
888+
889+
// Give a more specific diagnostic when the user has explicitly typed in
890+
// a shift-amount that does not match what is expected, but for which
891+
// there is also an unscaled addressing mode (e.g. sxtw/uxtw).
892+
bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
893+
if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW ||
894+
ShiftExtendTy == AArch64_AM::SXTW) &&
895+
!ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8)
896+
return DiagnosticPredicateTy::NoMatch;
897+
898+
if (MatchShift && ShiftExtendTy == getShiftExtendType())
888899
return DiagnosticPredicateTy::Match;
889900

890901
return DiagnosticPredicateTy::NearMatch;

‎test/MC/AArch64/SVE/ld1d-diagnostics.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,12 @@ ld1d z0.d, p0/z, [x0, z0.s]
8080
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8181

8282
ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
83-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
83+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
8484
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
8585
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8686

8787
ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
88-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
88+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
8989
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
9090
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9191

‎test/MC/AArch64/SVE/ld1h-diagnostics.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -120,22 +120,22 @@ ld1h z0.s, p0/z, [x0, z0.s]
120120
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
121121

122122
ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
123-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
123+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
124124
// CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
125125
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
126126

127127
ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
128-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
128+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
129129
// CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
130130
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
131131

132132
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
133-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
133+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
134134
// CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
135135
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
136136

137137
ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
138-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
138+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
139139
// CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
140140
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
141141

‎test/MC/AArch64/SVE/ld1sh-diagnostics.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -119,22 +119,22 @@ ld1sh z0.s, p0/z, [x0, z0.s]
119119
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
120120

121121
ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
122-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
122+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
123123
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
124124
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
125125

126126
ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
127-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
127+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
128128
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
129129
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
130130

131131
ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
132-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
132+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
133133
// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
134134
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
135135

136136
ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
137-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
137+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
138138
// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
139139
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
140140

‎test/MC/AArch64/SVE/ld1sw-diagnostics.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -104,12 +104,12 @@ ld1sw z0.d, p0/z, [x0, z0.s]
104104
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
105105

106106
ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
107-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
107+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
108108
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
109109
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
110110

111111
ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
112-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
112+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
113113
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
114114
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
115115

@@ -119,12 +119,12 @@ ld1sw z0.d, p0/z, [x0, z0.d, lsl]
119119
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
120120

121121
ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
122-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
122+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
123123
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
124124
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
125125

126126
ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
127-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
127+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
128128
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
129129
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
130130

‎test/MC/AArch64/SVE/ld1w-diagnostics.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -105,22 +105,22 @@ ld1w z0.s, p0/z, [x0, z0.s]
105105
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
106106

107107
ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
108-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
108+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
109109
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
110110
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
111111

112112
ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
113-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
113+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
114114
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
115115
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
116116

117117
ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
118-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
118+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
119119
// CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
120120
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
121121

122122
ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
123-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
123+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
124124
// CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
125125
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
126126

‎test/MC/AArch64/SVE/ldff1d-diagnostics.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,12 +59,12 @@ ldff1d z0.d, p0/z, [x0, z0.s]
5959
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
6060

6161
ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
62-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
62+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
6363
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
6464
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
6565

6666
ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
67-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
67+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
6868
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
6969
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
7070

‎test/MC/AArch64/SVE/ldff1h-diagnostics.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,22 +69,22 @@ ldff1h z0.s, p0/z, [x0, z0.s]
6969
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
7070

7171
ldff1h z0.s, p0/z, [x0, z0.s, uxtw #2]
72-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
72+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
7373
// CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s, uxtw #2]
7474
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
7575

7676
ldff1h z0.s, p0/z, [x0, z0.s, lsl #1]
77-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
77+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
7878
// CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s, lsl #1]
7979
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8080

8181
ldff1h z0.d, p0/z, [x0, z0.d, lsl #2]
82-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
82+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
8383
// CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, lsl #2]
8484
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8585

8686
ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
87-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
87+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
8888
// CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
8989
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9090

0 commit comments

Comments
 (0)