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Fix spi gaps #4487
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Fix spi gaps #4487
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One question. Good otherwise! Nice bug hunting!
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Nice work! Thank you!
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definietely faster - esp32spi not working now but probably because some edge case in timing is being hit in the nina-fw.
.. so that it is more conveniently like the metro m7 for my testing
.. and set the "MasterPcsContinuous" flag, which removes some of the gap between bytes of a single SPI transaction
Set the betweenTransferDelay to the SCK low-time, to avoid long pauses between bytes (transfers) while preventing the last SCK cycle in a byte from being a runt pulse. Compared to an earlier revision of this change, which just set the delays all to zero, this doesn't break using an AirLift, which was sensitive to the runt pulses (the simple loopback-wire test didn't detect the problem)
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yay this now works for ESP32SPI!
It's possible to configure very large gaps between transfers (bytes), and indeed this is what we ended up with by using LPSPI_MasterGetDefaultConfig.
Set all the delays to zero, enable a bit for "continuous transfers", and cap the speed at 30MHz per the datasheet's restrictions.
After this change, here is a view of a transfer at 30MHz:

I tested on the MIMXRT1010-EVK both with a logic analyzer on the SCK and MOSI pins, and with a loopback wire from MOSI to MISO. (comment out the equality-assertion when scoping, put it back when looping back)
Closes: #3062