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jeplerjepler
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atmel-samd: Add SDIO SD card interface
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13 files changed

+782
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‎ports/atmel-samd/Makefile

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -246,6 +246,14 @@ SRC_ASF += \
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endif
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ifeq ($(CIRCUITPY_SDCARDIO_SDIO),1)
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SRC_ASF += \
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hal/src/hal_mci_sync.c \
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hpl/sdhc/hpl_sdhc.c \
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$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align
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endif
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SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF))
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SRC_C = \
@@ -290,6 +298,9 @@ SRC_C = \
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supervisor/shared/memory.c \
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timer_handler.c \
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ifeq ($(CIRCUITPY_SDCARDIO_SDIO),1)
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SRC_C += ports/atmel-samd/sd_mmc/sd_mmc.c
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endif
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ifeq ($(CIRCUITPY_NETWORK),1)
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CFLAGS += -DMICROPY_PY_NETWORK=1
@@ -346,6 +357,10 @@ endif
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OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
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SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
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$(HEADER_BUILD)/sdiodata.h: $(TOP)/tools/mksdiodata.py | $(HEADER_BUILD)
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$(Q)$(PYTHON3) $< > $@
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SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
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# Sources that only hold QSTRs after pre-processing.
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SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c

‎ports/atmel-samd/asf4_conf/samd51/hpl_sdhc_config.h

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@@ -0,0 +1,24 @@
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/* Auto-generated config file hpl_sdhc_config.h */
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#ifndef HPL_SDHC_CONFIG_H
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#define HPL_SDHC_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include "peripheral_clk_config.h"
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#ifndef CONF_BASE_FREQUENCY
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#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
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#endif
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// <o> Clock Generator Select
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// <0=> Divided Clock mode
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// <1=> Programmable Clock mode
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// <i> This defines the clock generator mode in the SDCLK Frequency Select field
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// <id> sdhc_clk_gsel
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#ifndef CONF_SDHC0_CLK_GEN_SEL
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#define CONF_SDHC0_CLK_GEN_SEL 0
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_SDHC_CONFIG_H

‎ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h

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Original file line numberDiff line numberDiff line change
@@ -1001,6 +1001,170 @@
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#define CONF_GCLK_USB_FREQUENCY 48000000
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#endif
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// <h> SDHC Clock Settings
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// <y> SDHC Clock source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for SDHC.
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// <id> sdhc_gclk_selection
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#ifndef CONF_GCLK_SDHC0_SRC
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#define CONF_GCLK_SDHC0_SRC GCLK_GENCTRL_SRC_DFLL_Val
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#endif
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// <y> SDHC clock slow source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for SDHC.
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// <id> sdhc_slow_gclk_selection
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#ifndef CONF_GCLK_SDHC0_SLOW_SRC
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#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
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#endif
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// </h>
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/**
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* \def SDHC FREQUENCY
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* \brief SDHC's Clock frequency
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*/
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#ifndef CONF_SDHC0_FREQUENCY
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#define CONF_SDHC0_FREQUENCY 12000000
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#endif
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/**
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* \def SDHC FREQUENCY
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* \brief SDHC's Clock slow frequency
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*/
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#ifndef CONF_SDHC0_SLOW_FREQUENCY
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#define CONF_SDHC0_SLOW_FREQUENCY 12000000
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#endif
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// <h> SDHC Clock Settings
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// <y> SDHC Clock source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for SDHC.
1114+
// <id> sdhc_gclk_selection
1115+
#ifndef CONF_GCLK_SDHC1_SRC
1116+
#define CONF_GCLK_SDHC1_SRC GCLK_GENCTRL_SRC_DFLL_Val
1117+
#endif
1118+
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// <y> SDHC clock slow source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for SDHC.
1146+
// <id> sdhc_slow_gclk_selection
1147+
#ifndef CONF_GCLK_SDHC1_SLOW_SRC
1148+
#define CONF_GCLK_SDHC1_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
1149+
#endif
1150+
// </h>
1151+
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/**
1153+
* \def SDHC FREQUENCY
1154+
* \brief SDHC's Clock frequency
1155+
*/
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#ifndef CONF_SDHC1_FREQUENCY
1157+
#define CONF_SDHC1_FREQUENCY 12000000
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#endif
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/**
1161+
* \def SDHC FREQUENCY
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* \brief SDHC's Clock slow frequency
1163+
*/
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#ifndef CONF_SDHC1_SLOW_FREQUENCY
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#define CONF_SDHC1_SLOW_FREQUENCY 12000000
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H

‎ports/atmel-samd/asf4_conf/same54/hpl_sdhc_config.h

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
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/* Auto-generated config file hpl_sdhc_config.h */
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#ifndef HPL_SDHC_CONFIG_H
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#define HPL_SDHC_CONFIG_H
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5+
// <<< Use Configuration Wizard in Context Menu >>>
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7+
#include "peripheral_clk_config.h"
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9+
#ifndef CONF_BASE_FREQUENCY
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#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
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#endif
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// <o> Clock Generator Select
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// <0=> Divided Clock mode
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// <1=> Programmable Clock mode
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// <i> This defines the clock generator mode in the SDCLK Frequency Select field
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// <id> sdhc_clk_gsel
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#ifndef CONF_SDHC0_CLK_GEN_SEL
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#define CONF_SDHC0_CLK_GEN_SEL 0
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_SDHC_CONFIG_H

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