[BUG] No warning reported when using a record element accessed via record's type name as type

[nselvara]

Bug description:

Hi there,
Related to the MRE in this issue: #386

When declaring a signal or variable using a record element accessed via the record type name, VHDL LS currently does not issue any warning - even though such usage is invalid in standard VHDL and rejected by synthesis/simulation tools.

This may lead to situations where the LSP assumes the accessed type element is valid, but downstream tools later reject the design - defeating the purpose of early validation and feedback.

---

Expected behaviour:
The analyser should issue a warning something like this:

The record element cannot be used directly as a type vhdl_ls(illegal_type_reference)

---

Minimal reproducible example (MRE):

architecture beh of data_acquisition_wrapper is
    type test_t is record
        slv: std_ulogic_vector(2 downto 0);
        sl: std_ulogic;
        bool: boolean;
    end record;

    -- These don't emit a warning
    signal slv_test: test_t.slv;
    signal sl_test: test_t.sl;
    signal bool_test: test_t.bool;
begin
end architecture;

Thanks again for your awesome work!

[nselvara]

Hi there, I checked again with Aldec Riviera Pro.
It actually throws the following error:

COMP96 ERROR COMP96_0381: "Bad type name.

So this seems to confirm - or at least strongly suggest - that using a record element accessed via the type name as a signal type is invalid, which aligns with what standard VHDL expects. 😅
(Of course, there’s always a chance the simulator could be misbehaving, but this adds some weight to the interpretation.)