Ignore any references to vunit_lib (do not report errors)

[obruendl]

I asked below question on gitter but I did not get a reply by now - so I try it again though a GitHub issue:

Initial Question

I am just starting to use VHDL-LS. Is there any documentation of the options I can set in the TOML?

Specifically I have the following question:

I use VUnit (and it is installed locally - so in a machine dependent location - through PIP). I would want to avoid VHDL-LS reporting errors on use-clauses like the one below. Can I somehow configure VHDL-LS to not report that it does not find the sources for anything in vunit_lib?
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.comcontext;
context vunitlib.vc_context;

I already tried "vunit_lib.is_third_party = true" but this line alone didn't do the job.

Can I somehow (e.g. by a comment in my VHDL) ignore a line? Sometimes I have unused generics for certain reasons (e.g. to not break reverse compatibility) and I'd like to avoid VHDL-LS reporting them as problems constantly.

First Reply (not resolving the issue)

Please look at the example in the Configurations section of the README.
https://github.com/VHDL-LS/rust_hdl?tab=readme-ov-file#configuration
It has an example of adding the Unisim library in the TOML file.

Follow-up from my side (no answer received)

I looked at this example. That's how arrived to the "vunit_lib.is_third__party = true" idea, which did not work.

The point is that I cannot implement the line below, because the install location of vunit_lib is machine dependent (because the vunit_lib is installed through PIP):

UNISIM.files = [
'C:\Xilinx\Vivado\2023.1\data\vhdl\src\unisims\unisim_VCOMP.vhd',
]

If you want to reproduce: The code (with my current TOML) is here:
https://github.com/open-logic/open-logic/tree/feature/VHDL-LS

[F2g-attocube]

It is much more sensible to solve this problem from the vunit side. In fact vunit has knowledge of all files in your project, including itself, an thus can give you all the necessary information.

I created this function and added in my run.py for vunit:

def generate_project_toml(vunit_object):
    libs = {}
    for lib in vunit_object.get_libraries():
        libs[lib.name] = []
        for file in lib.get_source_files(allow_empty=True):
            libs[lib.name].append(file.name)

    project_toml = [
        f'standard = "{vunit_object.vhdl_standard}"',
        "[libraries]",
    ]
    for lib in libs.keys():
        project_toml.append(f"{lib}.files = [")
        for file in libs[lib]:
            project_toml.append(f'  "{file}",')
        project_toml.append("]")
    project_toml.append("[lint]")
    project_toml.append("unused = 'error'")
    project_toml.append("unnecessary_work_library = false")

    with open("vhdl_ls.toml", "w") as f:
        f.write("\n".join(project_toml))

Call it right before running the vu.main() function and it will generate a suitable project toml file containing everything known to vunit.

It requires running vunit before having a language server config, but its does the job.

[obruendl]

To be honest, I would prefer just ignoring anything in vunit_lib over generating the TOML from VUnit.

Technically the solution makes sense. But the more dependencies between different tools (editor, simulator, etc.) is added, the more complex the project gets - which can be daunting to potential contributors and finally lead to them not contributing. So I try to keep things as simple as possible.

Bottomline: Is there a way to ignore any errors towards vunit_lib (e.g. through the TOML or through some VHDL comments instructing VHDL-LS to ignore certain lines in the file)?

If not - I might use the "generate TOML from VUnit" option as workaround. But for me it would clearly be preferrable to have a standalone TOML that does not require VUnit execution.

[LukasVik]

Even if the unresolved library/use statements could be ignored, all VUnit types/functions/entities used in your testbench will also generate errors. There is no way for the language server to know if these missing things are from VUnit (which should be ignored), or if they are missing due to a typo/error/mistake (which should be reported). I don't know how it would be theoretically possible to ignore all errors that stem from VUnit usage.

I don't think there is an equivalent function in any other language server. When using Python/C++/Rust in VSCode I have to add my libraries manually, or there will be warnings. I think that's just how it is.

In the case of vhdl_ls I think generating the configuration file is the best approach: https://github.com/tsfpga/tsfpga/blob/main/tsfpga/create_vhdl_ls_config.py
I call this function from my simulation script, which is called regularly when doing development, so that my config is always up to date.

[obruendl]

@LukasVik

OK, works perfectly fine for me now.

I now have a licensing question - Would you be okay if I copy this SINGLE FILE to open-logic and I publish it under PSI HDL License? The file is under BSD-3 and I'd like to not overcomplicate the licensing of Open Logic by having to state that there are certain files under other although permissive licenses.

Similar question, may I set the copyright to myself for the edited version? For new content in open-logic I have the policy to not have other copyright holders so I potentially could change the license in future.

It's really only about this single create_vhdl_ls_config.py file only.

[LukasVik]

@obruendl Oh yeah, of course man, it’s just a few lines of code. You can do whatever you want with it!

…

On Sat, 24 May 2025 at 10:07, Oliver Bründler ***@***.***> wrote: *obruendl* left a comment (VHDL-LS/rust_hdl#369) <#369 (comment)> @LukasVik <https://github.com/LukasVik> OK, works perfectly fine for me now. I now have a licensing question - Would you be okay if I copy this SINGLE FILE to open-logic and I publish it under PSI HDL License? The file is under BSD-3 and I'd like to not overcomplicate the licensing of Open Logic by having to state that there are certain files under other although permissive licenses. Similar question, may I set the copyright to myself for the edited version? For new content in open-logic I have the policy to not have other copyright holders so I potentially could change the license in future. It's really only about this single create_vhdl_ls_config.py file only. — Reply to this email directly, view it on GitHub <#369 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACOEO664YFCWHMSU7TIQ4J33AASDZAVCNFSM6AAAAABYYF4WN2VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDSMBWGYYTENBWHA> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[obruendl]

@LukasVik

That's what I assumed ;-) But I tend to stay clean on copyrights and the like. Thanks for the quick OK - that allows me to proceed with the next release (which is a nice one, you'll see).