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[AMDGPU][True16] Support disassembling .h registers.
Differential Revision: https://reviews.llvm.org/D156939
1 parent 27546a6 commit 637dfc5

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3 files changed

+116
-23
lines changed

3 files changed

+116
-23
lines changed

‎llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,8 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
505505

506506
RegInterval Result;
507507

508-
unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST));
508+
unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST)) &
509+
AMDGPU::EncValues::REG_IDX_MASK;
509510

510511
if (TRI->isVectorRegister(*MRI, Op.getReg())) {
511512
assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL);
@@ -1837,9 +1838,11 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
18371838
assert(NumSGPRsMax <= SQ_MAX_PGM_SGPRS);
18381839

18391840
RegisterEncoding Encoding = {};
1840-
Encoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0);
1841+
Encoding.VGPR0 =
1842+
TRI->getEncodingValue(AMDGPU::VGPR0) & AMDGPU::EncValues::REG_IDX_MASK;
18411843
Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1;
1842-
Encoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0);
1844+
Encoding.SGPR0 =
1845+
TRI->getEncodingValue(AMDGPU::SGPR0) & AMDGPU::EncValues::REG_IDX_MASK;
18431846
Encoding.SGPRL = Encoding.SGPR0 + NumSGPRsMax - 1;
18441847

18451848
TrackedWaitcntSet.clear();

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -122,10 +122,12 @@ class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
122122
//===----------------------------------------------------------------------===//
123123
// Declarations that describe the SI registers
124124
//===----------------------------------------------------------------------===//
125-
class SIReg <string n, bits<16> regIdx = 0> :
126-
Register<n> {
125+
class SIReg <string n, bits<8> regIdx = 0, bit isAGPROrVGPR = 0,
126+
bit isHi = 0> : Register<n> {
127127
let Namespace = "AMDGPU";
128-
let HWEncoding = regIdx;
128+
let HWEncoding{7-0} = regIdx;
129+
let HWEncoding{8} = isAGPROrVGPR;
130+
let HWEncoding{9} = isHi;
129131
}
130132

131133
// For register classes that use TSFlags.
@@ -148,28 +150,20 @@ class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
148150
let TSFlags{4} = HasSGPR;
149151
}
150152

151-
multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
152-
bit HWEncodingHigh = 0> {
153-
// There is no special encoding for 16 bit subregs, these are not real
154-
// registers but rather operands for instructions preserving other 16 bits
155-
// of the result or reading just 16 bits of a 32 bit VGPR.
156-
// It is encoded as a corresponding 32 bit register.
157-
// Non-VGPR register classes use it as we need to have matching subregisters
158-
// to move instructions and data between ALUs.
159-
def _LO16 : SIReg<n#".l", regIdx> {
160-
let HWEncoding{8} = HWEncodingHigh;
161-
}
162-
def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> {
153+
multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1,
154+
bit isAGPROrVGPR = 0> {
155+
def _LO16 : SIReg<n#".l", regIdx, isAGPROrVGPR>;
156+
def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isAGPROrVGPR,
157+
/* isHi */ 1> {
163158
let isArtificial = ArtificialHigh;
164-
let HWEncoding{8} = HWEncodingHigh;
165159
}
166160
def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
167161
!cast<Register>(NAME#"_HI16")]> {
168162
let Namespace = "AMDGPU";
169163
let SubRegIndices = [lo16, hi16];
170164
let CoveredBySubRegs = !not(ArtificialHigh);
171-
let HWEncoding = regIdx;
172-
let HWEncoding{8} = HWEncodingHigh;
165+
let HWEncoding{7-0} = regIdx;
166+
let HWEncoding{8} = isAGPROrVGPR;
173167
}
174168
}
175169

@@ -247,7 +241,7 @@ def SGPR_NULL64 :
247241
// the high 32 bits. The lower 32 bits are always zero (for base) or
248242
// -1 (for limit). Since we cannot access the high 32 bits, when we
249243
// need them, we need to do a 64 bit load and extract the bits manually.
250-
multiclass ApertureRegister<string name, bits<16> regIdx> {
244+
multiclass ApertureRegister<string name, bits<8> regIdx> {
251245
let isConstant = true in {
252246
// FIXME: We shouldn't need to define subregisters for these (nor add them to any 16 bit
253247
// register classes), but if we don't it seems to confuse the TableGen
@@ -315,7 +309,7 @@ foreach Index = 0...15 in {
315309
defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>;
316310
}
317311

318-
multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
312+
multiclass FLAT_SCR_LOHI_m <string n, bits<8> ci_e, bits<8> vi_e> {
319313
defm _ci : SIRegLoHi16<n, ci_e>;
320314
defm _vi : SIRegLoHi16<n, vi_e>;
321315
defm "" : SIRegLoHi16<n, 0>;

‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,10 +66,18 @@
6666
# GFX11-FAKE16: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x64]
6767
0x01,0x05,0x0a,0x64
6868

69+
# GFX11-REAL16: v_add_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x64]
70+
# GFX11-FAKE16: v_add_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x64]
71+
0x81,0x05,0x0a,0x64
72+
6973
# GFX11-REAL16: v_add_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x64]
7074
# GFX11-FAKE16: v_add_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x64]
7175
0x7f,0x05,0x0a,0x64
7276

77+
# GFX11-REAL16: v_add_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x64]
78+
# GFX11-FAKE16: v_add_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x64]
79+
0xff,0x05,0x0a,0x64
80+
7381
# GFX11-REAL16: v_add_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x64]
7482
# GFX11-FAKE16: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x64]
7583
0x01,0x04,0x0a,0x64
@@ -118,10 +126,18 @@
118126
# GFX11-FAKE16: v_add_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x64]
119127
0xfd,0x04,0x0a,0x64
120128

129+
# GFX11-REAL16: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65]
130+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x65
131+
0xfd,0x04,0x0b,0x65
132+
121133
# GFX11-REAL16: v_add_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
122134
# GFX11-FAKE16: v_add_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
123135
0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00
124136

137+
# GFX11-REAL16: v_add_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00]
138+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00
139+
0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00
140+
125141
# GFX11: v_add_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x06]
126142
0x01,0x05,0x0a,0x06
127143

@@ -906,10 +922,18 @@
906922
# GFX11-FAKE16: v_max_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x72]
907923
0x01,0x05,0x0a,0x72
908924

925+
# GFX11-REAL16: v_max_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x72]
926+
# GFX11-FAKE16: v_max_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x72]
927+
0x81,0x05,0x0a,0x72
928+
909929
# GFX11-REAL16: v_max_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x72]
910930
# GFX11-FAKE16: v_max_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x72]
911931
0x7f,0x05,0x0a,0x72
912932

933+
# GFX11-REAL16: v_max_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x72]
934+
# GFX11-FAKE16: v_max_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x72]
935+
0xff,0x05,0x0a,0x72
936+
913937
# GFX11-REAL16: v_max_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x72]
914938
# GFX11-FAKE16: v_max_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x72]
915939
0x01,0x04,0x0a,0x72
@@ -958,10 +982,18 @@
958982
# GFX11-FAKE16: v_max_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x72]
959983
0xfd,0x04,0x0a,0x72
960984

985+
# GFX11-REAL16: v_max_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x73]
986+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x73
987+
0xfd,0x04,0x0b,0x73
988+
961989
# GFX11-REAL16: v_max_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00]
962990
# GFX11-FAKE16: v_max_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00]
963991
0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00
964992

993+
# GFX11-REAL16: v_max_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00]
994+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00
995+
0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00
996+
965997
# GFX11: v_max_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x20]
966998
0x01,0x05,0x0a,0x20
967999

@@ -1101,10 +1133,18 @@
11011133
# GFX11-FAKE16: v_min_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x74]
11021134
0x01,0x05,0x0a,0x74
11031135

1136+
# GFX11-REAL16: v_min_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x74]
1137+
# GFX11-FAKE16: v_min_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x74]
1138+
0x81,0x05,0x0a,0x74
1139+
11041140
# GFX11-REAL16: v_min_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x74]
11051141
# GFX11-FAKE16: v_min_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x74]
11061142
0x7f,0x05,0x0a,0x74
11071143

1144+
# GFX11-REAL16: v_min_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x74]
1145+
# GFX11-FAKE16: v_min_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x74]
1146+
0xff,0x05,0x0a,0x74
1147+
11081148
# GFX11-REAL16: v_min_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x74]
11091149
# GFX11-FAKE16: v_min_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x74]
11101150
0x01,0x04,0x0a,0x74
@@ -1153,10 +1193,18 @@
11531193
# GFX11-FAKE16: v_min_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x74]
11541194
0xfd,0x04,0x0a,0x74
11551195

1196+
# GFX11-REAL16: v_min_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x75]
1197+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x75
1198+
0xfd,0x04,0x0b,0x75
1199+
11561200
# GFX11-REAL16: v_min_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00]
11571201
# GFX11-FAKE16: v_min_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00]
11581202
0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00
11591203

1204+
# GFX11-REAL16: v_min_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00]
1205+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00
1206+
0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00
1207+
11601208
# GFX11: v_min_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x1e]
11611209
0x01,0x05,0x0a,0x1e
11621210

@@ -1341,10 +1389,18 @@
13411389
# GFX11-FAKE16: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a]
13421390
0x01,0x05,0x0a,0x6a
13431391

1392+
# GFX11-REAL16: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a]
1393+
# GFX11-FAKE16: v_mul_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x6a
1394+
0x81,0x05,0x0a,0x6a
1395+
13441396
# GFX11-REAL16: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a]
13451397
# GFX11-FAKE16: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a]
13461398
0x7f,0x05,0x0a,0x6a
13471399

1400+
# GFX11-REAL16: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a]
1401+
# GFX11-FAKE16: v_mul_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x6a]
1402+
0xff,0x05,0x0a,0x6a
1403+
13481404
# GFX11-REAL16: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a]
13491405
# GFX11-FAKE16: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a]
13501406
0x01,0x04,0x0a,0x6a
@@ -1393,10 +1449,18 @@
13931449
# GFX11-FAKE16: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a]
13941450
0xfd,0x04,0x0a,0x6a
13951451

1452+
# GFX11-REAL16: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b]
1453+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x6b
1454+
0xfd,0x04,0x0b,0x6b
1455+
13961456
# GFX11-REAL16: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
13971457
# GFX11-FAKE16: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
13981458
0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00
13991459

1460+
# GFX11-REAL16: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00]
1461+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00
1462+
0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00
1463+
14001464
# GFX11: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10]
14011465
0x01,0x05,0x0a,0x10
14021466

@@ -1776,10 +1840,18 @@
17761840
# GFX11-FAKE16: v_sub_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x66]
17771841
0x01,0x05,0x0a,0x66
17781842

1843+
# GFX11-REAL16: v_sub_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x66]
1844+
# GFX11-FAKE16: v_sub_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x66]
1845+
0x81,0x05,0x0a,0x66
1846+
17791847
# GFX11-REAL16: v_sub_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x66]
17801848
# GFX11-FAKE16: v_sub_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x66]
17811849
0x7f,0x05,0x0a,0x66
17821850

1851+
# GFX11-REAL16: v_sub_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x66]
1852+
# GFX11-FAKE16: v_sub_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x66]
1853+
0xff,0x05,0x0a,0x66
1854+
17831855
# GFX11-REAL16: v_sub_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x66]
17841856
# GFX11-FAKE16: v_sub_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x66]
17851857
0x01,0x04,0x0a,0x66
@@ -1828,10 +1900,18 @@
18281900
# GFX11-FAKE16: v_sub_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x66]
18291901
0xfd,0x04,0x0a,0x66
18301902

1903+
# GFX11-REAL16: v_sub_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x67]
1904+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x67
1905+
0xfd,0x04,0x0b,0x67
1906+
18311907
# GFX11-REAL16: v_sub_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
18321908
# GFX11-FAKE16: v_sub_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
18331909
0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00
18341910

1911+
# GFX11-REAL16: v_sub_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00]
1912+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00
1913+
0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00
1914+
18351915
# GFX11: v_sub_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x08]
18361916
0x01,0x05,0x0a,0x08
18371917

@@ -1986,10 +2066,18 @@
19862066
# GFX11-FAKE16: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68]
19872067
0x01,0x05,0x0a,0x68
19882068

2069+
# GFX11-REAL16: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
2070+
# GFX11-FAKE16: v_subrev_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x68]
2071+
0x81,0x05,0x0a,0x68
2072+
19892073
# GFX11-REAL16: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68]
19902074
# GFX11-FAKE16: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68]
19912075
0x7f,0x05,0x0a,0x68
19922076

2077+
# GFX11-REAL16: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
2078+
# GFX11-FAKE16: v_subrev_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x68]
2079+
0xff,0x05,0x0a,0x68
2080+
19932081
# GFX11-REAL16: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68]
19942082
# GFX11-FAKE16: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68]
19952083
0x01,0x04,0x0a,0x68
@@ -2038,10 +2126,18 @@
20382126
# GFX11-FAKE16: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68]
20392127
0xfd,0x04,0x0a,0x68
20402128

2129+
# GFX11-REAL16: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
2130+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x69
2131+
0xfd,0x04,0x0b,0x69
2132+
20412133
# GFX11-REAL16: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
20422134
# GFX11-FAKE16: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
20432135
0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00
20442136

2137+
# GFX11-REAL16: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
2138+
# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00
2139+
0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00
2140+
20452141
# GFX11: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a]
20462142
0x01,0x05,0x0a,0x0a
20472143

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