17
17
#include <gtimer.h>
18
18
#include <cpuport.h>
19
19
#include <interrupt.h>
20
+ #include <ioremap.h>
21
+ #include <psci_api.h>
20
22
21
23
#include <board.h>
22
24
#include <drv_uart.h>
23
25
26
+ #include "mm_page.h"
27
+
28
+ #define PLATFORM_MEM_TALBE (va , size ) va, ((unsigned long)va + size - 1)
29
+
24
30
struct mem_desc platform_mem_desc [] =
25
31
{
26
- {0x200000 , 0x80000000 , 0x200000 , NORMAL_MEM },
27
- {UART0_MMIO_BASE , UART0_MMIO_BASE + 0x10000 , UART0_MMIO_BASE , DEVICE_MEM },
28
- {UART1_MMIO_BASE , UART1_MMIO_BASE + 0x90000 , UART1_MMIO_BASE , DEVICE_MEM },
29
- {GIC_PL600_DISTRIBUTOR_PPTR , GIC_PL600_DISTRIBUTOR_PPTR + 0x10000 , GIC_PL600_DISTRIBUTOR_PPTR , DEVICE_MEM },
30
- {GIC_PL600_REDISTRIBUTOR_PPTR , GIC_PL600_REDISTRIBUTOR_PPTR + 0xc0000 , GIC_PL600_REDISTRIBUTOR_PPTR , DEVICE_MEM },
32
+ {PLATFORM_MEM_TALBE (0x20000000 , 0x10000000 ), 0x20000000 , NORMAL_MEM },
33
+ {PLATFORM_MEM_TALBE (GRF_PMU_BASE , 0x10000 ), GRF_PMU_BASE , DEVICE_MEM },
34
+ {PLATFORM_MEM_TALBE (GRF_SYS_BASE , 0x10000 ), GRF_SYS_BASE , DEVICE_MEM },
35
+ {PLATFORM_MEM_TALBE (CRU_BASE , 0x10000 ), CRU_BASE , DEVICE_MEM },
36
+ {PLATFORM_MEM_TALBE (UART0_MMIO_BASE , 0x10000 ), UART0_MMIO_BASE , DEVICE_MEM },
37
+ {PLATFORM_MEM_TALBE (UART1_MMIO_BASE , 0x90000 ), UART1_MMIO_BASE , DEVICE_MEM },
38
+ {PLATFORM_MEM_TALBE (GIC_PL600_DISTRIBUTOR_PPTR , 0x10000 ), GIC_PL600_DISTRIBUTOR_PPTR , DEVICE_MEM },
39
+ {PLATFORM_MEM_TALBE (GIC_PL600_REDISTRIBUTOR_PPTR , 0xc0000 ), GIC_PL600_REDISTRIBUTOR_PPTR , DEVICE_MEM },
40
+ #ifdef PKG_USING_RT_OPENAMP
41
+ {PLATFORM_MEM_TALBE (AMP_SHARE_MEMORY_ADDRESS , AMP_SHARE_MEMORY_SIZE ), AMP_SHARE_MEMORY_ADDRESS , NORMAL_MEM },
42
+ #endif /* PKG_USING_RT_OPENAMP */
31
43
};
32
44
33
45
const rt_uint32_t platform_mem_desc_size = sizeof (platform_mem_desc ) / sizeof (platform_mem_desc [0 ]);
@@ -39,20 +51,30 @@ void idle_wfi(void)
39
51
40
52
void rt_hw_board_init (void )
41
53
{
42
- extern void * MMUTable ;
43
- rt_hw_mmu_map_init (& rt_kernel_space , (void * )0x80000000 , 0x10000000 , MMUTable , 0 );
54
+ extern unsigned long MMUTable [512 ];
55
+ rt_region_t init_page_region ;
56
+
57
+ rt_hw_mmu_map_init (& rt_kernel_space , (void * ) 0x20000000 , 0xE0000000 - 1 , MMUTable , 0 );
58
+
59
+ init_page_region .start = RT_HW_PAGE_START ;
60
+ init_page_region .end = RT_HW_PAGE_END ;
61
+ rt_page_init (init_page_region );
62
+
44
63
rt_hw_mmu_setup (& rt_kernel_space , platform_mem_desc , platform_mem_desc_size );
45
64
46
65
/* initialize hardware interrupt */
47
66
rt_hw_interrupt_init ();
67
+
48
68
/* initialize uart */
49
69
rt_hw_uart_init ();
70
+
50
71
/* initialize timer for os tick */
51
72
rt_hw_gtimer_init ();
52
73
53
74
rt_thread_idle_sethook (idle_wfi );
54
75
55
76
// TODO porting to FDT-driven PSCI: arm_psci_init(PSCI_METHOD_SMC, RT_NULL, RT_NULL);
77
+ psci_init ();
56
78
57
79
#if defined(RT_USING_CONSOLE ) && defined(RT_USING_DEVICE )
58
80
/* set console device */
@@ -79,26 +101,68 @@ void rt_hw_board_init(void)
79
101
void reboot (void )
80
102
{
81
103
// TODO poring to FDT to use new PSCI: arm_psci_system_reboot();
104
+ if (psci_ops .system_reset )
105
+ {
106
+ psci_ops .system_reset ();
107
+ }
108
+ else
109
+ {
110
+ void * cur_base = rt_ioremap ((void * ) CRU_BASE , 0x100 );
111
+ HWREG32 (cur_base + 0x00D4 ) = 0xfdb9 ;
112
+ HWREG32 (cur_base + 0x00D8 ) = 0xeca8 ;
113
+ }
82
114
}
83
115
MSH_CMD_EXPORT (reboot , reboot ...);
84
116
85
- #ifdef RT_USING_SMP
117
+ static void print_cpu_id (int argc , char * argv [])
118
+ {
119
+ rt_kprintf ("rt_hw_cpu_id:%d\n" , rt_hw_cpu_id ());
120
+ }
121
+ MSH_CMD_EXPORT_ALIAS (print_cpu_id , cpuid , print_cpu_id );
122
+
123
+ #ifdef RT_USING_AMP
124
+ void start_cpu (int argc , char * argv [])
125
+ {
126
+ rt_uint32_t status ;
127
+ if (psci_ops .cpu_on )
128
+ {
129
+ status = psci_ops .cpu_on (0x3 , (rt_uint64_t ) 0x7A000000 );
130
+ rt_kprintf ("arm_psci_cpu_on 0x%X\n" , status );
131
+ }
132
+ }
133
+ MSH_CMD_EXPORT (start_cpu , start_cpu );
134
+
135
+ #ifdef RT_AMP_SLAVE
136
+ void rt_hw_cpu_shutdown ()
137
+ {
138
+ if (psci_ops .cpu_off )
139
+ {
140
+ psci_ops .cpu_off (0 );
141
+ }
142
+ }
143
+ #endif /* RT_AMP_SLAVE */
144
+ #endif /* RT_USING_AMP */
145
+
146
+ #if defined(RT_USING_SMP ) || defined(RT_USING_AMP )
86
147
rt_uint64_t rt_cpu_mpidr_early [] =
87
148
{
88
- [0 ] = 0x81000000 ,
89
- [1 ] = 0x81000100 ,
90
- [2 ] = 0x81000200 ,
91
- [3 ] = 0x81000300 ,
149
+ [0 ] = 0x80000000 ,
150
+ [1 ] = 0x80000100 ,
151
+ [2 ] = 0x80000200 ,
152
+ [3 ] = 0x80000300 ,
153
+ [RT_CPUS_NR ] = 0
92
154
};
155
+ #endif
93
156
157
+ #ifdef RT_USING_SMP
94
158
void rt_hw_secondary_cpu_up (void )
95
159
{
96
160
int i ;
97
161
extern void secondary_cpu_start (void );
98
162
99
163
for (i = 1 ; i < RT_CPUS_NR ; ++ i )
100
164
{
101
- arm_psci_cpu_on (rt_cpu_mpidr_early [i ], (rt_uint64_t )secondary_cpu_start );
165
+ arm_psci_cpu_on (rt_cpu_mpidr_early [i ], (rt_uint64_t ) secondary_cpu_start );
102
166
}
103
167
}
104
168
0 commit comments