[libcpu-riscv]: [common64 virt64]: Add the dual-core feature under the SMP architecture.

Currently, it does not support operation with two or more cores.

Solution: Since the system runs in S-mode and does not support access to the
mhartid register, the hartid is currently stored in the satp register (this
register is not used when the bsp qemu-virt64-riscv runs RT-Thread). Additionally,
logic for storing boot_hartid and multi-core initialization logic for the sp
pointer have been added in startup_gcc.S. Logic for secondary core wake-up and
entry has been added in cpuport.c.

Signed-off-by: Mengchen Teng <[email protected]>

Author: Tm-C-mT

bsp/qemu-virt64-riscv/run.sh

@@ -24,7 +24,7 @@ if [ ! -f $path_image ]; then
 	exit
 fi
 
-qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin \
+qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin -smp 2 \
 -drive if=none,file=$path_image,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \
 -netdev user,id=tap0 -device virtio-net-device,netdev=tap0,bus=virtio-mmio-bus.1 \
 -device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0

libcpu/risc-v/common64/cpuport.c

@@ -64,7 +64,14 @@ void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus)
 
 int rt_hw_cpu_id(void)
 {
+#ifndef RT_USING_SMP
     return 0;
+#else
+    /* Currently, the hartid is stored in the satp register. */
+    uint32_t hart_id;
+    asm volatile ("csrr %0, satp" : "=r"(hart_id));
+    return hart_id;
+#endif /* RT_USING_SMP */
 }
 
 /**
@@ -151,13 +158,39 @@ void rt_hw_set_process_id(int pid)
 }
 
 #ifdef RT_USING_SMP
+extern void _start(void);
+extern int boot_hartid;
+/* Boot secondary harts using the SBI HSM hart_start call. */
 void rt_hw_secondary_cpu_up(void)
 {
-    
+    rt_uint64_t entry_pa;
+    int hart, ret;
+
+    /* translate kernel virtual _start to physical address */
+    entry_pa = (rt_uint64_t)&_start;//(rt_uint64_t)rt_kmem_v2p((void *)&_start);
+
+    for (hart = 0; hart < RT_CPUS_NR; hart++)
+    {
+        if (hart == boot_hartid) continue;
+
+        ret = sbi_hsm_hart_start((unsigned long)hart,
+                                 (unsigned long)entry_pa,
+                                 0UL);
+        if (ret)
+        {
+            rt_kprintf("sbi_hsm_hart_start failed for hart %d: %d\n", hart, ret);
+        }
+    }
 }
 
 void secondary_cpu_entry(void)
 {
-
+    /* The PLIC peripheral interrupts are currently handled by the boot_hart. */
+    /* Enable the Supervisor-Timer bit in SIE */
+    rt_hw_tick_init();
+  
+    rt_hw_spin_lock(&_cpus_lock);
+    /* invoke system scheduler start for secondary CPU */
+    rt_system_scheduler_start();
 }
 #endif /* RT_USING_SMP */

libcpu/risc-v/common64/startup_gcc.S

@@ -32,9 +32,19 @@ _start:
 1:
     /* save hartid */
     la t0, boot_hartid                /* global varible rt_boot_hartid */
+#ifdef RT_USING_SMP
+    lw   t2, (t0)
+    li   t3, 0xdeadbeef
+    li   t4, 0xffffffff
+    and  t2, t2, t4                   /* Extract the lower 32 bits. */
+    bne  t2, t3, system_init          /* If the current value is 0xdeadbeef, skip the boot_hartid assignment operation. */
+#endif
     mv t1, a0                         /* get hartid in S-mode frome a0 register */
     sw t1, (t0)                       /* store t1 register low 4 bits in memory address which is stored in t0 */
 
+#ifdef RT_USING_SMP
+system_init:
+#endif
     /* clear Interrupt Registers */
     csrw sie, 0
     csrw sip, 0
@@ -51,7 +61,10 @@ _start:
     li x7, 0
     li x8, 0
     li x9, 0
+#ifndef RT_USING_SMP
+    /* In the SMP architecture, a0 will be used again later */
     li x10,0
+#endif
     li x11,0
     li x12,0
     li x13,0
@@ -85,10 +98,29 @@ _start:
     la gp, __global_pointer$
 .option pop
 
+#ifndef RT_USING_SMP
     /* removed SMP support here */
     la   sp, __stack_start__
     li   t0, __STACKSIZE__
     add  sp, sp, t0
+#else
+    csrw   satp, a0        /* Currently, the hartid is stored in the satp register. */
+    /* Initialize the sp pointer according to different hartids. */
+    mv   t0, a0
+    /* calculate stack offset: hartid * __STACKSIZE__ */
+    li   t1, __STACKSIZE__
+    mul  t0, t0, t1        /* t0 = hartid * __STACKSIZE__ */
+
+    /* set stack pointer */
+    la   sp, __stack_start__
+    add  sp, sp, t0        /* sp = __stack_start__ + hartid * __STACKSIZE__ */
+    add  sp, sp, t1        /* sp += __STACKSIZE__ (point to stack top) */
+
+    mv   t0, a0
+    lw   t1, boot_hartid
+    bne  t0, t1, secondary_cpu_entry
+    li x10,0               /* Clear the a0 register. */
+#endif /* RT_USING_SMP */
 
     /**
      * sscratch is always zero on kernel mode