Alignment fix take 2

Author: sstefan1

llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp

@@ -112,6 +112,10 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
   StackSize += (16 - StackSize) & 0xf;
 
   if (STI.isWinABI()) {
+    uint64_t MaxAlignment = MFI.getMaxAlign().value();
+    if(MaxAlignment > 32)
+      StackSize += MaxAlignment;
+
     StackSize += 32;
 
     if (StackSize <= 32760) {
@@ -134,6 +138,28 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
       BuildMI(MBB, MBBI, dl, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg);
     }
 
+    // Calculate how much is needed to have the correct alignment.
+    // Change offset to: alignment + difference.
+    // For example, in case of alignment of 128:
+    // diff_to_128_aligned_address = (128 - (SP & 127))
+    // new_offset = 128 + diff_to_128_aligned_address
+    // This is safe to do because we increased the stack size by MaxAlignment.
+    unsigned Reg, RegMisAlign;
+    if (MaxAlignment > 32){
+      TII.loadImmediate(MBB, MBBI, &RegMisAlign, MaxAlignment - 1);
+      TII.loadImmediate(MBB, MBBI, &Reg, MaxAlignment);
+      BuildMI(MBB, MBBI, dl, TII.get(Xtensa::AND))
+          .addReg(RegMisAlign, RegState::Define)
+          .addReg(FP)
+          .addReg(RegMisAlign);
+      BuildMI(MBB, MBBI, dl, TII.get(Xtensa::SUB), RegMisAlign)
+          .addReg(Reg)
+          .addReg(RegMisAlign);
+      BuildMI(MBB, MBBI, dl, TII.get(Xtensa::ADD), SP)
+          .addReg(SP)
+          .addReg(RegMisAlign, RegState::Kill);
+    }
+
     // Store FP register in A8, because FP may be used to pass function
     // arguments
     if (XtensaFI->isSaveFrameRegister()) {

llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp

@@ -135,7 +135,6 @@ static bool isValidAddrOffset(MachineInstr &MI, int64_t Offset) {
 bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
                                      unsigned OpNo, int FrameIndex,
                                      uint64_t StackSize, int64_t SPOffset,
-                                     uint64_t Alignment,
                                      RegScavenger *RS) const {
   MachineInstr &MI = *II;
   MachineFunction &MF = *MI.getParent()->getParent();
@@ -184,9 +183,8 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
   LLVM_DEBUG(errs() << "Offset     : " << Offset << "\n"
                     << "<--------->\n");
 
-  bool Valid = (Alignment <= 32) ? isValidAddrOffset(MI, Offset) : false;
+  bool Valid = isValidAddrOffset(MI, Offset);
 
-
   // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
   // field.
   if (!MI.isDebugValue() && !Valid) {
@@ -197,27 +195,7 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
     const XtensaInstrInfo &TII = *static_cast<const XtensaInstrInfo *>(
         MBB.getParent()->getSubtarget().getInstrInfo());
 
-    // Calculate how much is needed to have the correct alignment.
-    // Change offset to: alignment + difference.
-    // For example, in case of alignment of 128:
-    // diff_to_128_aligned_address = (128 - (SP & 127))
-    // new_offset = 128 + diff_to_128_aligned_address
-    if (Alignment > 32) {
-      TII.loadImmediate(MBB, II, &RegMisAlign, Alignment - 1);
-      TII.loadImmediate(MBB, II, &Reg, Alignment);
-      BuildMI(MBB, II, DL, TII.get(Xtensa::AND))
-          .addReg(RegMisAlign, RegState::Define)
-          .addReg(FrameReg)
-          .addReg(RegMisAlign);
-      BuildMI(MBB, II, DL, TII.get(Xtensa::SUB), RegMisAlign)
-          .addReg(Reg)
-          .addReg(RegMisAlign);
-      BuildMI(MBB, II, DL, TII.get(Xtensa::ADD), Reg)
-          .addReg(Reg)
-          .addReg(RegMisAlign, RegState::Kill);
-    } else {
-      TII.loadImmediate(MBB, II, &Reg, Offset);
-    }
+    TII.loadImmediate(MBB, II, &Reg, Offset);
     BuildMI(MBB, II, DL, TII.get(ADD), Reg)
         .addReg(FrameReg)
         .addReg(Reg, RegState::Kill);
@@ -327,14 +305,12 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
   uint64_t stackSize = MF.getFrameInfo().getStackSize();
   int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
-  uint64_t Alignment = MF.getFrameInfo().getObjectAlign(FrameIndex).value();
 
   LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
                     << "spOffset   : " << spOffset << "\n"
                     << "stackSize  : " << stackSize << "\n");
 
-  return eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset,
-                     Alignment, RS);
+  return eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset, RS);
 }
 
 Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {

llvm/lib/Target/Xtensa/XtensaRegisterInfo.h

@@ -57,7 +57,7 @@ struct XtensaRegisterInfo : public XtensaGenRegisterInfo {
 private:
   bool eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
                    int FrameIndex, uint64_t StackSize, int64_t SPOffset,
-                   uint64_t Alignment, RegScavenger *RS) const;
+                   RegScavenger *RS) const;
 
   bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override;
 };

llvm/test/CodeGen/Xtensa/aligned_alloc.ll

@@ -4,25 +4,20 @@
 
 define i8 @loadi8_128(i8 %a) {
 ; XTENSA-LABEL: loadi8_128:
-; XTENSA:         entry a1, 288
-; XTENSA-NEXT:    movi a9, 127
+; XTENSA:         entry a1, 416
+; XTENSA-NEXT:    movi a8, 127
+; XTENSA-NEXT:    movi a9, 128
+; XTENSA-NEXT:    and a8, a1, a8
+; XTENSA-NEXT:    sub a8, a9, a8
+; XTENSA-NEXT:    add.n a1, a1, a8
 ; XTENSA-NEXT:    movi a8, 128
-; XTENSA-NEXT:    and a9, a1, a9
-; XTENSA-NEXT:    sub a9, a8, a9
-; XTENSA-NEXT:    add.n a8, a8, a9
 ; XTENSA-NEXT:    add.n a8, a1, a8
 ; XTENSA-NEXT:    addi a10, a8, 0
 ; XTENSA-NEXT:    movi.n a11, 0
 ; XTENSA-NEXT:    movi.n a12, 64
 ; XTENSA-NEXT:    l32r a8, .LCPI0_0
 ; XTENSA-NEXT:    callx8 a8
-; XTENSA-NEXT:    movi a9, 127
-; XTENSA-NEXT:    movi a8, 128
-; XTENSA-NEXT:    and a9, a1, a9
-; XTENSA-NEXT:    sub a9, a8, a9
-; XTENSA-NEXT:    add.n a8, a8, a9
-; XTENSA-NEXT:    add.n a8, a1, a8
-; XTENSA-NEXT:    l8ui a2, a8, 0
+; XTENSA-NEXT:    l8ui a2, a1, 128
 ; XTENSA-NEXT:    retw.n
     %aligned = alloca i8, align 128
     call void @llvm.memset.p0.i64(ptr noundef nonnull align 64 dereferenceable(64) %aligned, i8 0, i64 64, i1 false)