Merged main:5bd1b93cb220 into amd-gfx:18b1fa897044

Local branch amd-gfx 18b1fa8 Merged main:455bf3d1ccd6 into amd-gfx:c7691189ce5b
Remote branch main 5bd1b93 Move CallInst::CreateFree to IRBuilderBase

Author: SC llvm team

.github/CODEOWNERS

@@ -0,0 +1,4 @@
+/libcxx/ @llvm/reviewers-libcxx
+/libcxxabi/ @llvm/reviewers-libcxxabi
+/libunwind/ @llvm/reviewers-libunwind
+/runtimes/ @llvm/reviewers-libcxx

.github/new-issues-labeler.yml

@@ -1,6 +1,3 @@
-'new issue':
-  - '/.*/'
-
 'clang':
   - '/\bclang(?!\-)\b/i'
 

.github/new-prs-labeler.yml

@@ -110,16 +110,26 @@ mlir:
   - mlir/**
 
 mlir:core:
-  - mlir/**/Support/**
-  - mlir/**/Parser/**
-  - mlir/**/IR/**
-  - mlir/**/Bytecode/**
-  - mlir/**/AsmParser/**
-  - mlir/**/Pass/**
-  - mlir/**/tools/**
-  - mlir/**/Reducer/**
-  - mlir/**/Transforms/**
-  - mlir/**/Debug/**
+  - mlir/include/mlir/Support/**
+  - mlir/lib/Support/**
+  - mlir/include/mlir/Parser/**
+  - mlir/lib/Parser/**
+  - mlir/include/mlir/IR/**
+  - mlir/lib/IR/**
+  - mlir/include/mlir/Bytecode/**
+  - mlir/lib/Bytecode/**
+  - mlir/include/mlir/AsmParser/**
+  - mlir/lib/AsmParser/**
+  - mlir/include/mlir/Pass/**
+  - mlir/lib/Pass/**
+  - mlir/include/mlir/Tools/**
+  - mlir/lib/Tools/**
+  - mlir/include/mlir/Reducer/**
+  - mlir/lib/Reducer/**
+  - mlir/include/mlir/Transforms/**
+  - mlir/lib/Transforms/**
+  - mlir/include/mlir/Debug/**
+  - mlir/lib/Debug/**
   - mlir/tools/**
 
 mlir:ods:
@@ -300,7 +310,10 @@ vectorizers:
   - llvm/include/llvm/Transforms/Vectorize/**
 
 clang:
-  - clang/**
+  - any:
+    - clang/**
+    - '!clang/**/Format/**'
+    - '!clang/tools/clang-format/**'
 
 testing-tools:
   - llvm/include/llvm/FileCheck/**
@@ -510,6 +523,12 @@ llvm:analysis:
   - llvm/test/Analysis/**
   - llvm/unittests/Analysis/**
 
+llvm:adt:
+  - llvm/**/ADT/*
+
+llvm:support:
+  - llvm/**/Support/**
+
 llvm:transforms:
   - llvm/lib/Transforms/**
   - llvm/include/llvm/Transforms/**
@@ -554,6 +573,13 @@ backend:DirectX:
   - '**/*DXIL*/**'
   - '**/*dxil*/**'
 
+backend:SPIR-V:
+  - clang/lib/Driver/ToolChains/SPIRV.*
+  - llvm/lib/Target/SPIRV/**
+  - llvm/test/CodeGen/SPIRV/**
+  - llvm/test/Frontend/HLSL/**
+  - llvm/docs/SPIRVUsage.rst
+
 mlgo:
   - llvm/lib/Analysis/ML*
   - llvm/include/llvm/Analysis/ML*

.github/workflows/new-issues.yml

@@ -13,7 +13,7 @@ jobs:
     runs-on: ubuntu-latest
     if: github.repository == 'llvm/llvm-project'
     steps:
-      - uses: github/issue-labeler@v3.2
+      - uses: llvm/actions/issue-labeler@main
         with:
           repo-token: ${{ secrets.GITHUB_TOKEN }}
           configuration-path: .github/new-issues-labeler.yml

.github/workflows/pr-receive.yml

@@ -10,7 +10,12 @@ permissions:
 jobs:
   pr-target:
     runs-on: ubuntu-latest
-    if: github.repository == 'llvm/llvm-project'
+    # Ignore PRs with more than 10 commits.  Pull requests with a lot of
+    # commits tend to be accidents usually when someone made a mistake while trying
+    # to rebase.  We want to ignore these pull requests to avoid excessive
+    # notifications.
+    if: github.repository == 'llvm/llvm-project' &&
+        github.event.pull_request.commits < 10
     steps:
       - name: Store PR Information
         run: |

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -437,7 +437,7 @@ class MCPlusBuilder {
   virtual bool isUnsupportedBranch(const MCInst &Inst) const { return false; }
 
   /// Return true of the instruction is of pseudo kind.
-  bool isPseudo(const MCInst &Inst) const {
+  virtual bool isPseudo(const MCInst &Inst) const {
     return Info->get(Inst.getOpcode()).isPseudo();
   }
 

bolt/include/bolt/Passes/FixRISCVCallsPass.h

@@ -6,9 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the FixRISCVCallsPass class, which sets the JALR immediate
-// to 0 for AUIPC/JALR pairs with a R_RISCV_CALL(_PLT) relocation. This is
-// necessary since MC expects it to be zero in order to or-in fixups.
+// This file declares the FixRISCVCallsPass class, which replaces all types of
+// calls with PseudoCALL pseudo instructions. This ensures that relaxed calls
+// get expanded to auipc/jalr pairs so that BOLT can freely reassign function
+// addresses without having to worry about the limited range of relaxed calls.
+// Using PseudoCALL also ensures that the RISC-V backend inserts the necessary
+// relaxation-related relocations to allow JITLink to relax instruction back to
+// shorter versions where possible.
 //===----------------------------------------------------------------------===//
 
 #ifndef BOLT_PASSES_FIXRISCVCALLSPASS_H

bolt/lib/Core/BinaryContext.cpp

@@ -131,7 +131,7 @@ BinaryContext::createBinaryContext(const ObjectFile *File, bool IsPIC,
   case llvm::Triple::riscv64:
     ArchName = "riscv64";
     // RV64GC
-    FeaturesStr = "+m,+a,+f,+d,+zicsr,+zifencei,+c";
+    FeaturesStr = "+m,+a,+f,+d,+zicsr,+zifencei,+c,+relax";
     break;
   default:
     return createStringError(std::errc::not_supported,

bolt/lib/Core/BinaryFunction.cpp

@@ -3156,6 +3156,10 @@ void BinaryFunction::dumpGraphToFile(std::string Filename) const {
 }
 
 bool BinaryFunction::validateCFG() const {
+  // Skip the validation of CFG after it is finalized
+  if (CurrentState == State::CFG_Finalized)
+    return true;
+
   bool Valid = true;
   for (BinaryBasicBlock *BB : BasicBlocks)
     Valid &= BB->validateSuccessorInvariants();

bolt/lib/Core/Relocation.cpp

@@ -352,7 +352,7 @@ static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) {
     assert(isInt<28>(Value) && "only PC +/- 128MB is allowed for direct call");
     // Immediate goes in bits 25:0 of BL.
     // OP 1001_01 goes in bits 31:26 of BL.
-    Value = (Value >> 2) | 0x94000000ULL;
+    Value = ((Value >> 2) & 0x3ffffff) | 0x94000000ULL;
     break;
   }
   return Value;