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FailFishFailFish
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fix: use emitRRRI for ADDXr(x|s)
1 parent b6566f3 commit 3b992b2

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+21
-21
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+21
-21
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‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -508,11 +508,11 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
508508
SafeRd = AArch64::X22;
509509
emitRRRI0(Opcode, SafeRd, AArch64::X21, Rt, AArch64_AM::getMemExtendImm(AArch64_AM::UXTW, 0), STI);
510510
if (Rd == AArch64::LR)
511-
emitRRRI0(AArch64::ADDXrx, Rd, AArch64::X21, SafeRd, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
511+
emitRRRI(AArch64::ADDXrx, Rd, AArch64::X21, SafeRd, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
512512
}
513513

514514
void emitAddMask(MCRegister AddrReg, const MCSubtargetInfo &STI) {
515-
emitRRRI0(AArch64::ADDXrx, AArch64::X18, AArch64::X21, AddrReg, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
515+
emitRRRI(AArch64::ADDXrx, AArch64::X18, AArch64::X21, AddrReg, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
516516
}
517517

518518
void emitSafeMemDemoted(unsigned N, const MCInst &Inst, const MCSubtargetInfo &STI) {
@@ -546,7 +546,7 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
546546
SafeInst.addOperand(Inst.getOperand(I));
547547
AArch64ELFStreamer::emitInstruction(SafeInst, STI);
548548
if (PostGuard)
549-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
549+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
550550
}
551551

552552
void emitSafeMem1(const MCInst &Inst, const MCSubtargetInfo &STI) {
@@ -589,7 +589,7 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
589589
}
590590
emitRRI(AArch64::LDRXui, AArch64::LR, AArch64::X21, Offset, STI);
591591
emitR(AArch64::BLR, AArch64::LR, STI);
592-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
592+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
593593
}
594594

595595
void emitSyscall(const MCSubtargetInfo &STI) {
@@ -657,10 +657,10 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
657657
if (Reg != AArch64::SP)
658658
break;
659659
if (Inst.getOperand(2).getImm() == 0) {
660-
emitRRRI0(AArch64::ADDXrx, AArch64::SP, AArch64::X21, Inst.getOperand(1).getReg(), AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
660+
emitRRRI(AArch64::ADDXrx, AArch64::SP, AArch64::X21, Inst.getOperand(1).getReg(), AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
661661
} else {
662662
emitRRII(Inst.getOpcode(), AArch64::X22, AArch64::SP, Inst.getOperand(2).getImm(), Inst.getOperand(3).getImm(), STI);
663-
emitRRRI0(AArch64::ADDXrx, AArch64::SP, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
663+
emitRRRI(AArch64::ADDXrx, AArch64::SP, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
664664
}
665665
return;
666666
case AArch64::ADDXrr:
@@ -675,33 +675,33 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
675675
if (Reg != AArch64::SP)
676676
break;
677677
emitRRRI(Inst.getOpcode(), AArch64::X22, AArch64::SP, Inst.getOperand(2).getReg(), Inst.getOperand(3).getImm(), STI);
678-
emitRRRI0(AArch64::ADDXrx, AArch64::SP, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
678+
emitRRRI(AArch64::ADDXrx, AArch64::SP, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
679679
return;
680680
case AArch64::ORRXrs:
681681
Reg = Inst.getOperand(0).getReg();
682682
if ((Reg == AArch64::SP) || (Reg == AArch64::LR)) {
683-
emitRRRI0(AArch64::ADDXrx, Reg, AArch64::X21, Inst.getOperand(2).getReg(), AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
683+
emitRRRI(AArch64::ADDXrx, Reg, AArch64::X21, Inst.getOperand(2).getReg(), AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
684684
return;
685685
}
686686
break;
687687
case AArch64::LDRXui:
688688
if (isAddrReg(Inst.getOperand(1).getReg()) && Inst.getOperand(0).getReg() == AArch64::LR) {
689689
emitRRI(AArch64::LDRXui, AArch64::X22, Inst.getOperand(1).getReg(), Inst.getOperand(2).getImm(), STI);
690-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
690+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
691691
return;
692692
}
693693
break;
694694
case AArch64::LDRXpre:
695695
if (isAddrReg(Inst.getOperand(2).getReg()) && Inst.getOperand(1).getReg() == AArch64::LR) {
696696
emitRRRI(AArch64::LDRXpre, Inst.getOperand(0).getReg(), AArch64::X22, Inst.getOperand(2).getReg(), Inst.getOperand(3).getImm(), STI);
697-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
697+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
698698
return;
699699
}
700700
break;
701701
case AArch64::LDRXpost:
702702
if (isAddrReg(Inst.getOperand(2).getReg()) && Inst.getOperand(1).getReg() == AArch64::LR) {
703703
emitRRRI(AArch64::LDRXpost, Inst.getOperand(0).getReg(), AArch64::X22, Inst.getOperand(2).getReg(), Inst.getOperand(3).getImm(), STI);
704-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
704+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
705705
return;
706706
}
707707
break;
@@ -714,7 +714,7 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
714714
}
715715
if (Inst.getOperand(1).getReg() == AArch64::LR) {
716716
emitRRRI0(AArch64::LDPXi, Inst.getOperand(0).getReg(), AArch64::X22, Inst.getOperand(2).getReg(), Inst.getOperand(3).getImm(), STI);
717-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
717+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
718718
return;
719719
}
720720
}
@@ -723,12 +723,12 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
723723
if (isAddrReg(Inst.getOperand(3).getReg())) {
724724
if (Inst.getOperand(1).getReg() == AArch64::LR) {
725725
emitRRRRI(AArch64::LDPXpre, Inst.getOperand(0).getReg(), AArch64::X22, Inst.getOperand(2).getReg(), Inst.getOperand(3).getReg(), Inst.getOperand(4).getImm(), STI);
726-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
726+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
727727
return;
728728
}
729729
if (Inst.getOperand(2).getReg() == AArch64::LR) {
730730
emitRRRRI(AArch64::LDPXpre, Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(), AArch64::X22, Inst.getOperand(3).getReg(), Inst.getOperand(4).getImm(), STI);
731-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
731+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
732732
return;
733733
}
734734
}
@@ -737,12 +737,12 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
737737
if (isAddrReg(Inst.getOperand(3).getReg())) {
738738
if (Inst.getOperand(1).getReg() == AArch64::LR) {
739739
emitRRRRI(AArch64::LDPXpost, Inst.getOperand(0).getReg(), AArch64::X22, Inst.getOperand(2).getReg(), Inst.getOperand(3).getReg(), Inst.getOperand(4).getImm(), STI);
740-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
740+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
741741
return;
742742
}
743743
if (Inst.getOperand(2).getReg() == AArch64::LR) {
744744
emitRRRRI(AArch64::LDPXpost, Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(), AArch64::X22, Inst.getOperand(3).getReg(), Inst.getOperand(4).getImm(), STI);
745-
emitRRRI0(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
745+
emitRRRI(AArch64::ADDXrx, AArch64::LR, AArch64::X21, AArch64::X22, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, 0), STI);
746746
return;
747747
}
748748
}
@@ -769,7 +769,7 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
769769
emitSafeMemDemoted(BaseRegIdx, Inst, STI);
770770
MCRegister Base = Inst.getOperand(BaseRegIdx).getReg();
771771
if (Inst.getOperand(OffsetIdx).isReg())
772-
emitRRRI0(AArch64::ADDXrs, Base, Base, Inst.getOperand(OffsetIdx).getReg(), 0, STI);
772+
emitRRRI(AArch64::ADDXrs, Base, Base, Inst.getOperand(OffsetIdx).getReg(), 0, STI); // TODO: bug?
773773
else
774774
emitRRI0(AArch64::ADDXri, Base, Base, Inst.getOperand(OffsetIdx).getImm() * getPrePostScale(Inst.getOpcode()), STI);
775775
} else {
@@ -829,9 +829,9 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
829829
if (!IsShift)
830830
Shift = 0;
831831
if (Extend)
832-
emitRRRI0(AArch64::ADDXrx, AArch64::X22, Reg1, Reg2, AArch64_AM::getArithExtendImm(AArch64_AM::SXTX, Shift), STI);
832+
emitRRRI(AArch64::ADDXrx, AArch64::X22, Reg1, Reg2, AArch64_AM::getArithExtendImm(AArch64_AM::SXTX, Shift), STI);
833833
else
834-
emitRRRI0(AArch64::ADDXrs, AArch64::X22, Reg1, Reg2, AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift), STI);
834+
emitRRRI(AArch64::ADDXrs, AArch64::X22, Reg1, Reg2, AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift), STI);
835835
emitMemMask(MemOp, Inst.getOperand(0).getReg(), AArch64::X22, STI);
836836
return;
837837
}
@@ -843,9 +843,9 @@ class AArch64LFIELFStreamer : public AArch64ELFStreamer {
843843
if (!IsShift)
844844
Shift = 0;
845845
if (S)
846-
emitRRRI0(AArch64::ADDXrx, AArch64::X22, Reg1, Reg2, AArch64_AM::getArithExtendImm(AArch64_AM::SXTW, Shift), STI);
846+
emitRRRI(AArch64::ADDXrx, AArch64::X22, Reg1, Reg2, AArch64_AM::getArithExtendImm(AArch64_AM::SXTW, Shift), STI);
847847
else
848-
emitRRRI0(AArch64::ADDXrx, AArch64::X22, Reg1, Reg2, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, Shift), STI);
848+
emitRRRI(AArch64::ADDXrx, AArch64::X22, Reg1, Reg2, AArch64_AM::getArithExtendImm(AArch64_AM::UXTW, Shift), STI);
849849
emitMemMask(MemOp, Inst.getOperand(0).getReg(), AArch64::X22, STI);
850850
return;
851851
}

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