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Merged
merged 26 commits into from
Nov 5, 2023
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This patch adds new intrinsics and types for supporting SME2.


name: Pull request
about: Feature proposal.


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This patch adds new intrinsics and types for supporting SME2.
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Looks great. I haven't looked in detail at each individual intrinsic — the actual implementation seems like the best way of doing that — but I've added some comments based on a comparison with SVE.

* Addressed suggestions in descriptions
* Removed unnecessary newlines
* Merged optional suffixes e.g. `[_single][_u16][_x2]` -> `[_single_u16_x2]`
* Renamed svuqrshr -> svqrshr (the signedness can be deduced form the
  operands and there wasn't a svsqrshr either for SQRSHR)
* Replaced `enum sv_vgkind` by `uint64_t` immediate.
* Generalised `imm_1_8` into `imm` since this immediate wasn't correct for all types.
sdesmalen-arm added a commit to llvm/llvm-project that referenced this pull request Mar 1, 2023
The C and C++ Language Extensions for AArch64 SME2 [1] adds a new type called
`svcount_t` which describes a predicate. This is not a predicate vector
mask, but rather a description of a predicate vector mask that can be
expanded into a mask using explicit instructions. The type is a scalable
opaque type.

To implement `svcount_t` type this patch uses the existing Target Extension Type
mechanism, but adds further support so that this type can be a scalable type.

AArch64 CodeGen support will follow in a separate patch.

[1] ARM-software/acle#217

Reviewed By: jcranmer-intel, nikic

Differential Revision: https://reviews.llvm.org/D136861
The 'l' is redundant because of the `_za32` or `_za64` suffixes
already present in the function prototype, from which the 'long'
or 'long long' can be deduced.
This avoids a name clash with SVE intrinsics for svmlslb_f32/svmlslt_f32,
and also aligns with what was done with bfmlalb/bfmlalt for SVE.
For _za8, the tile can only be '0', hence the reason why the tile wasn't explicitly passed in.
But there are overloaded forms for _za16, _za32, _za64 and _za128 that do require a tile,
so this change adds the tile operand to all intrinsics. For _za8, it is up to the compiler
to ensure that no value other than '0' can be passed.
The return type cannot be deduced from one of the operands, so must be
explicitly specified in the name of the intrinsic.
The following SME2 intrinsic:

  svint32_t svdot[_s32](svint32_t, svint8_t, svint8_t);

clashes with the one we defined for SME2:

  svint32_t svdot[_s32](svint32_t, svint16_t, svint16_t);

This patch renames these to:

  svint32_t svdot[_s32_s16_s16]((svint32_t, svint16_t, svint16_t);

which is unambiguous and allows for the possibility of retroactively
updating the SVE intrinsics to have a similar name (svdot[_s32_s8_s8]).
The PSEL and PFALSE instructions have aliases to accept a predicate-as-counter
register. It makes sense to add corresponding ACLE intrinsics for user convenience.
Also fixed a use of `svread_hor_za8` in the description of _vg2/_vg4
where it was missing the newly added tile operand.
kmclaughlin-arm added a commit to kmclaughlin-arm/llvm-project that referenced this pull request Nov 24, 2023
Adds the following SME2 builtins:
 - svmop(a|s)_za32,
 - svbmop(a|s)_za32

See ARM-software/acle#217
kmclaughlin-arm added a commit to llvm/llvm-project that referenced this pull request Nov 27, 2023
)

Adds the following SME2 builtins:
 - svmop(a|s)_za32,
 - svbmop(a|s)_za32

See ARM-software/acle#217
MDevereau added a commit to llvm/llvm-project that referenced this pull request Dec 1, 2023
MDevereau added a commit to MDevereau/llvm-project that referenced this pull request Dec 4, 2023
MDevereau added a commit to MDevereau/llvm-project that referenced this pull request Dec 5, 2023
Adds builtins for:
- FCVT
- BFCVT
- FCVTZS
- FCVTZU
- SCVTF
- UCVTF
- BFCVTN
- FCVTN
- SQCVT
- SQCVTU
- UQCVT
- SQCVTN
- SQCVTUN
- UQCVTN

See ARM-software/acle#217
kmclaughlin-arm added a commit to kmclaughlin-arm/llvm-project that referenced this pull request Dec 5, 2023
Adds the following SME2 builtins:
 - svread_hor/ver,
 - svwrite_hor/ver,
 - svread_za64,
 - svwrite_za64

See ARM-software/acle#217
MDevereau added a commit to llvm/llvm-project that referenced this pull request Dec 6, 2023
CarolineConcatto pushed a commit to CarolineConcatto/acle that referenced this pull request Dec 6, 2023
This patch adds new intrinsics and types for supporting SME2.
MDevereau added a commit to MDevereau/llvm-project that referenced this pull request Dec 6, 2023
MDevereau added a commit to MDevereau/llvm-project that referenced this pull request Dec 6, 2023
MDevereau added a commit to llvm/llvm-project that referenced this pull request Dec 6, 2023
MDevereau added a commit to llvm/llvm-project that referenced this pull request Dec 6, 2023
Adds builtins for:
- FCVT
- BFCVT
- FCVTZS
- FCVTZU
- SCVTF
- UCVTF
- BFCVTN
- FCVTN
- SQCVT
- SQCVTU
- UQCVT
- SQCVTN
- SQCVTUN
- UQCVTN

See ARM-software/acle#217
MDevereau added a commit to llvm/llvm-project that referenced this pull request Dec 6, 2023
MDevereau added a commit to llvm/llvm-project that referenced this pull request Dec 6, 2023
Extend pfalse and ptrue builtins with svcount_t return types to be
enabled for sve2p1 and sme2

See ARM-software/acle#217
kmclaughlin-arm added a commit to llvm/llvm-project that referenced this pull request Dec 19, 2023
Adds the following SME2 builtins:
 - svread_hor/ver,
 - svwrite_hor/ver,
 - svread_za64,
 - svwrite_za64

See ARM-software/acle#217
ZA array vectors. The intrinsics model this in the following way:

* Multi-vector operands are groups of SVE data vectors, that use the same
tuple types as defined in the [SVE ACLE](#sve-vector-types), e.g.
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Avoid Latin contractions.
e.g. -> for example.

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@sallyarmneale sallyarmneale left a comment

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Avoid all latin contractions:
e.g. -> For example
i.e. -> that is
etc. -> and so on

qihangkong pushed a commit to rvgpu/rvgpu-llvm that referenced this pull request Apr 23, 2024
Adds the following SME2 builtins:
 - svread_hor/ver,
 - svwrite_hor/ver,
 - svread_za64,
 - svwrite_za64

See ARM-software/acle#217
veselypeta pushed a commit to veselypeta/cherillvm that referenced this pull request Aug 23, 2024
These intrinsics are used to implement the sel intrinsics that selects
a tuple of 2 or 4 values based on a predicate-as-counter operand, e.g.

  __attribute__((arm_streaming))
  svuint8x2_t svsel[_u8_x2](svcount_t png, svuint8x2_t zn, svuint8x2_t zm);

  __attribute__((arm_streaming))
  svuint8x4_t svsel[_u8_x4](svcount_t png, svuint8x4_t zn, svuint8x4_t zm);

As described in ARM-software/acle#217

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D150951
veselypeta pushed a commit to veselypeta/cherillvm that referenced this pull request Aug 23, 2024
…nt1/st1/stnt1

These intrinsics are used to implement multi-vector load/store intrinsics that loads
or stores a tuple of 2 or 4 values, based on a predicate-as-counter operand, e.g.

  __attribute__((arm_streaming))
  svuint8x2_t svld1[_u8]_x2(svcount_t png, const uint8_t *rn);

  __attribute__((arm_streaming))
  void svst1[_u8_x2](svcount_t png, uint8_t *rn, svuint8x2_t zt);

As described in ARM-software/acle#217

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D150956
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