@@ -708,6 +708,13 @@ RVOP(mulhu, {
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})
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/* DIV: Divide Signed */
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+ /* +------------------------+-----------+----------+-----------+
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+ * | Condition | Dividend | Divisor | DIV[W] |
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+ * +------------------------+-----------+----------+-----------+
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+ * | Division by zero | x | 0 | −1 |
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+ * | Overflow (signed only) | −2^{L−1} | −1 | −2^{L−1} |
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+ * +------------------------+-----------+----------+-----------+
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+ */
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RVOP (div , {
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const int32_t dividend = (int32_t ) rv -> X [ir -> rs1 ];
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const int32_t divisor = (int32_t ) rv -> X [ir -> rs2 ];
@@ -718,13 +725,26 @@ RVOP(div, {
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})
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/* DIVU: Divide Unsigned */
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+ /* +------------------------+-----------+----------+----------+
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+ * | Condition | Dividend | Divisor | DIVU[W] |
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+ * +------------------------+-----------+----------+----------+
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+ * | Division by zero | x | 0 | 2^L − 1 |
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+ * +------------------------+-----------+----------+----------+
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+ */
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RVOP (divu , {
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const uint32_t dividend = rv -> X [ir -> rs1 ];
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const uint32_t divisor = rv -> X [ir -> rs2 ];
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rv -> X [ir -> rd ] = !divisor ? ~0U : dividend / divisor ;
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})
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/* REM: Remainder Signed */
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+ /* +------------------------+-----------+----------+---------+
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+ * | Condition | Dividend | Divisor | REM[W] |
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+ * +------------------------+-----------+----------+---------+
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+ * | Division by zero | x | 0 | x |
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+ * | Overflow (signed only) | −2^{L−1} | −1 | 0 |
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+ * +------------------------+-----------+----------+---------+
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+ */
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RVOP (rem , {
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const int32_t dividend = rv -> X [ir -> rs1 ];
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const int32_t divisor = rv -> X [ir -> rs2 ];
@@ -735,6 +755,12 @@ RVOP(rem, {
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})
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/* REMU: Remainder Unsigned */
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+ /* +------------------------+-----------+----------+----------+
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+ * | Condition | Dividend | Divisor | REMU[W] |
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+ * +------------------------+-----------+----------+----------+
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+ * | Division by zero | x | 0 | x |
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+ * +------------------------+-----------+----------+----------+
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+ */
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RVOP (remu , {
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const uint32_t dividend = rv -> X [ir -> rs1 ];
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const uint32_t divisor = rv -> X [ir -> rs2 ];
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