Forcefully mark all of SRAM uncachable

Author: salkinium

examples/nucleo_h723zg/vl53/vl53l8_spi/main.cpp

@@ -43,6 +43,26 @@ modm::Vl53SpiTransport<SpiMaster, Cs, LPn> transport;
 int
 main()
 {
+	// This is a workaround for Erratum 1259864 on Cortex-M7 r1p1 CPUs. The data
+	// cache may return garbage data when reading from the SRAM after a write operation.
+	// https://www.st.com/resource/en/errata_sheet/es0392-stm32h742xig-stm32h743xig-stm32h750xb-stm32h753xi-device-errata-stmicroelectronics.pdf
+	MPU->CTRL = 0; __DSB();
+	// Set region 0 to SRAM base address [0x20000000, 0x40000000[ = 29-bits size
+	MPU->RBAR = 0x20000010;
+	// Permission register
+	MPU->RASR = (   28 << MPU_RASR_SIZE_Pos) | // 2^(28+1) = 0x20000000
+				(0b001 << MPU_RASR_TEX_Pos)  | // Normal memory type, outer and inner non-cachable
+				(  0b0 << MPU_RASR_S_Pos)    | // We only have one CPU, so not necessary to share
+				(  0b0 << MPU_RASR_C_Pos)    | // Non-Cacheable
+				(  0b0 << MPU_RASR_B_Pos)    | // Non-Bufferable
+				(0b011 << MPU_RASR_AP_Pos)   | // Read/Write full access
+				(  0b0 << MPU_RASR_XN_Pos)   | // Allow execution of .fastcode
+				MPU_RASR_ENABLE_Msk;           // Enable region
+	// Use default memory map, handlers use MPU too
+	MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_ENABLE_Msk;
+	// Flush entire memory system
+	__DSB(); __ISB();
+
 	Board::initialize();
 
 	Dma1::enable();