Commit 929bb2b
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OmpSs-2-at-FPGA release 3.0.0-rc1
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- README.md+3-4
- ait/backend/xilinx/IPs/bsc_ompss_picosompssmanager_7.2.zip-3
- ait/backend/xilinx/IPs/bsc_ompss_picosompssmanager_7.3.zip+3
- ait/backend/xilinx/board/alveo_u200/basic_info.json+1-1
- ait/backend/xilinx/board/alveo_u250/basic_info.json+1-1
- ait/backend/xilinx/board/alveo_u280/basic_info.json+1-1
- ait/backend/xilinx/board/alveo_u280_hbm/basic_info.json+1-1
- ait/backend/xilinx/board/alveo_u55c/basic_info.json+1-1
- ait/backend/xilinx/board/axiom/IPs/.gitattributes-1
- ait/backend/xilinx/board/axiom/IPs/user.org_user_led_common_1.0.zip-3
- ait/backend/xilinx/board/axiom/IPs/user.org_user_parallel_trace_adapter_1.0.zip-3
- ait/backend/xilinx/board/axiom/axiom_boot.dtsi-7
- ait/backend/xilinx/board/axiom/baseDesign.tcl-1.6k
- ait/backend/xilinx/board/axiom/constraints/SECO_Axiom_XCZU9EG_ES2.xdc-77
- ait/backend/xilinx/board/axiom/constraints/basic_constraints.xdc-1
- ait/backend/xilinx/board/axiom/procs.tcl-33
- ait/backend/xilinx/board/com_express/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/com_express/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/common/boot/overlay_ompss_at_fpga.dtsi+11
- ait/backend/xilinx/board/common/boot/pl_ompss_at_fpga.dtsi+6
- ait/backend/xilinx/board/euroexa_maxilink/IPs/manchester.ac.uk_maxilink_maxilink_xilinx_axi_hsl_with_phy_crdb_tb2_vu9_100MHz_1.0.zip-3
- ait/backend/xilinx/board/euroexa_maxilink/baseDesign.tcl-1.3k
- ait/backend/xilinx/board/euroexa_maxilink/basic_info.json-31
- ait/backend/xilinx/board/euroexa_maxilink/constraints/acc_common_floorplan.xdc-1
- ait/backend/xilinx/board/euroexa_maxilink/constraints/basic_constraints.xdc-1
- ait/backend/xilinx/board/euroexa_maxilink/constraints/constraints.xdc-160
- ait/backend/xilinx/board/euroexa_maxilink/constraints/create_pblocks.xdc-14
- ait/backend/xilinx/board/euroexa_maxilink/constraints/ddr_clocking.xdc-16
- ait/backend/xilinx/board/euroexa_maxilink/constraints/io_ddr4_c1.xdc-132
- ait/backend/xilinx/board/euroexa_maxilink/constraints/io_ddr4_c2.xdc-132
- ait/backend/xilinx/board/euroexa_maxilink/constraints/io_ddr4_c3.xdc-132
- ait/backend/xilinx/board/euroexa_maxilink/constraints/static_board_floorplan.xdc-54
- ait/backend/xilinx/board/euroexa_maxilink/constraints/static_common_floorplan.xdc-1
- ait/backend/xilinx/board/euroexa_maxilink/procs.tcl-48
- ait/backend/xilinx/board/euroexa_maxilink_quad/IPs/manchester.ac.uk_maxilink_maxilink_xilinx_axi_hsl_with_phy_crdb_tb2_vu9_100MHz_1.0.zip-3
- ait/backend/xilinx/board/euroexa_maxilink_quad/baseDesign.tcl-1.3k
- ait/backend/xilinx/board/euroexa_maxilink_quad/basic_info.json-31
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/acc_common_floorplan.xdc-1
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/basic_constraints.xdc-1
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/constraints.xdc-160
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/create_pblocks.xdc-14
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/ddr_clocking.xdc-16
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/io_ddr4_c1.xdc-132
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/io_ddr4_c2.xdc-132
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/io_ddr4_c3.xdc-132
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/static_board_floorplan.xdc-54
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/static_common_floorplan.xdc-1
- ait/backend/xilinx/board/euroexa_maxilink_quad/procs.tcl-48
- ait/backend/xilinx/board/kv260/baseDesign.tcl+1.1k
- ait/backend/xilinx/board/kv260/basic_info.json+6-6
- ait/backend/xilinx/board/kv260/boot/kv260_boot.dtsi
- ait/backend/xilinx/board/kv260/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/kv260/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/kv260/constraints/basic_constraints.xdc+11
- ait/backend/xilinx/board/zcu102/baseDesign.tcl+151-57
- ait/backend/xilinx/board/zcu102/basic_info.json+3-3
- ait/backend/xilinx/board/zcu102/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zcu102/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zcu102/boot/zcu102_boot.dtsi+20
- ait/backend/xilinx/board/zedboard/basic_info.json+1-1
- ait/backend/xilinx/board/zedboard/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zedboard/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zybo/basic_info.json+1-1
- ait/backend/xilinx/board/zybo/board_files/zybo/B.4/board.xml-921
- ait/backend/xilinx/board/zybo/board_files/zybo/B.4/part0_pins.xml-70
- ait/backend/xilinx/board/zybo/board_files/zybo/B.4/preset.xml-837
- ait/backend/xilinx/board/zybo/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zybo/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zynq702/basic_info.json+1-1
- ait/backend/xilinx/board/zynq702/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zynq702/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zynq706/basic_info.json+1-1
- ait/backend/xilinx/board/zynq706/boot/overlay_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/board/zynq706/boot/pl_ompss_at_fpga.dtsi+1
- ait/backend/xilinx/info.py+3-3
- ait/backend/xilinx/steps/HLS.py+34-47
- ait/backend/xilinx/steps/bitstream.py+18-38
- ait/backend/xilinx/steps/boot.py+39-79
- ait/backend/xilinx/steps/design.py+23-27
- ait/backend/xilinx/steps/implementation.py+3-13
- ait/backend/xilinx/steps/synthesis.py+7-14
- ait/backend/xilinx/tcl/scripts/generate_bitstream.tcl+11-18
- ait/backend/xilinx/tcl/scripts/generate_design.tcl+13-15
- ait/backend/xilinx/tcl/scripts/implement_design.tcl+5-3
- ait/backend/xilinx/tcl/scripts/synthesize_design.tcl+9-7
- ait/backend/xilinx/utils/checkers.py+20-45
- ait/backend/xilinx/utils/parser.py+3-3
- ait/frontend/config.py+3-3
- ait/frontend/parser.py+5-13
- ait/frontend/utils.py+8
Submodule nanos6-fpga updated 208 files
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