From 7c30dbb435836004095c2e495907c70a72298d27 Mon Sep 17 00:00:00 2001 From: Jayashree Srinivasan Date: Fri, 8 Nov 2024 16:18:15 -0500 Subject: [PATCH 001/133] [zep fromtree] platform: ext: adi: max32657: Add platform and fetch hal_adi Add support for Analog Devices MAX32657 platform and fetch ADI HAL library. Co-authored-by: Hao Zhang Co-authored-by: Sadik Ozer Change-Id: If884aa9a35664f6117574b0d4cde363a19e4eca5 Signed-off-by: Jayashree Srinivasan (cherry picked from commit 54a8a58c7bd79ca97bf2bdbae5b5a822d38be1d9) --- .../ext/target/adi/max32657/CMakeLists.txt | 34 +++++++++++++++++++ platform/ext/target/adi/max32657/config.cmake | 9 +++++ .../ext/target/adi/max32657/cpuarch.cmake | 15 ++++++++ 3 files changed, 58 insertions(+) create mode 100644 platform/ext/target/adi/max32657/CMakeLists.txt create mode 100644 platform/ext/target/adi/max32657/config.cmake create mode 100644 platform/ext/target/adi/max32657/cpuarch.cmake diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt new file mode 100644 index 0000000000..eb076d2e47 --- /dev/null +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -0,0 +1,34 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2024 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +################################################################################ + +# Fetch hal_adi repository +fetch_remote_library( + LIB_NAME hal_adi + LIB_SOURCE_PATH_VAR HAL_ADI_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/hal_adi + GIT_TAG ${HAL_ADI_VERSION} + GIT_PROGRESS TRUE +) + +set(TARGET_LC "max32657") +string(TOUPPER ${TARGET_LC} TARGET_UC) + +set(HAL_ADI_LIBRARY_DIR ${HAL_ADI_PATH}/MAX/Libraries) + +set(HAL_ADI_CMSIS_DIR ${HAL_ADI_LIBRARY_DIR}/CMSIS/Device/Maxim/${TARGET_UC}) +set(HAL_ADI_CMSIS_INC_DIR ${HAL_ADI_CMSIS_DIR}/Include) +set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source) + +set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers) +set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC}) +set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake new file mode 100644 index 0000000000..f2b4c5a8bd --- /dev/null +++ b/platform/ext/target/adi/max32657/config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2024 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") +set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") diff --git a/platform/ext/target/adi/max32657/cpuarch.cmake b/platform/ext/target/adi/max32657/cpuarch.cmake new file mode 100644 index 0000000000..8d4c7422cd --- /dev/null +++ b/platform/ext/target/adi/max32657/cpuarch.cmake @@ -0,0 +1,15 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# In the new split build this file defines a platform specific parameters +# like mcpu core, arch etc and to be included by toolchain files. + +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") +set(CONFIG_TFM_ENABLE_FP OFF) From e46a8d1e2efe47f1bcaa9116311a1b623e9d141b Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Wed, 20 Nov 2024 22:40:10 +0300 Subject: [PATCH 002/133] [zep fromtree] platform: ext: adi: Enable BL2 for MAX32657 To enable BL2 for MAX32657, this commit - Enables BL2 - Updates CMakeFile - Adds gcc linker file, common/gcc/tfm_bl2_common.ld copied as max32657_sla.ld - Adds system file Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: Ifd0379aadd74df8006fad062397c093cab27c560 Signed-off-by: Sadik Ozer (cherry picked from commit d3036b5b3e122eaf218dbeeeffa701e5014f6504) --- .../ext/target/adi/max32657/CMakeLists.txt | 61 ++++- platform/ext/target/adi/max32657/config.cmake | 2 + .../adi/max32657/device/gcc/max32657_sla.ld | 203 ++++++++++++++ .../max32657/device/src/startup_max32657.c | 248 ++++++++++++++++++ .../adi/max32657/device/src/system_max32657.c | 122 +++++++++ 5 files changed, 635 insertions(+), 1 deletion(-) create mode 100644 platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld create mode 100644 platform/ext/target/adi/max32657/device/src/startup_max32657.c create mode 100644 platform/ext/target/adi/max32657/device/src/system_max32657.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index eb076d2e47..613857637a 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -1,5 +1,5 @@ #------------------------------------------------------------------------------- -# Portions Copyright (C) 2024 Analog Devices, Inc. +# Portions Copyright (C) 2024-2025 Analog Devices, Inc. # # SPDX-License-Identifier: BSD-3-Clause # @@ -32,3 +32,62 @@ set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source) set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers) set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC}) set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) + +###### BL2 Related Cmake Configurations ######################################## +if(BL2) + # Add scatter files for BL2 + target_add_scatter_file(bl2 + $<$:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/gcc/${TARGET_LC}_sla.ld> + ) + + # Add startup file for BL2 + target_sources(bl2 + PRIVATE + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/startup_${TARGET_LC}.c + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c + ) + + # Add includes for BL2 + target_include_directories(platform_bl2 + PUBLIC + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} + PRIVATE + . + ${PLATFORM_DIR}/.. + ) + + target_compile_options(platform_bl2 + PUBLIC + -mno-unaligned-access # Added to mitigate the unaligned access problem + ) + + target_sources(platform_bl2 + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + ) + + target_compile_definitions(platform_bl2 + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CMSIS_device_header="${TARGET_LC}.h" + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 + ) + +endif() diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index f2b4c5a8bd..a0cb7f2841 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -5,5 +5,7 @@ # #------------------------------------------------------------------------------- +set(BL2 ON CACHE BOOL "Whether to build BL2") + set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") diff --git a/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld b/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld new file mode 100644 index 0000000000..de6049c5da --- /dev/null +++ b/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld @@ -0,0 +1,203 @@ +;/* +; * Copyright (c) 2022-2024 Arm Limited. All rights reserved. +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * +; * This file is derivative of CMSIS V5.00 gcc_arm.ld +; */ + +/* Linker script to configure memory regions. */ +/* This file will be run trough the pre-processor. */ + +#include "region_defs.h" + +MEMORY +{ + FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE + RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE +} + +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text (READONLY) : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .copy.table */ + . = ALIGN(4); + __copy_table_start__ = .; +#ifdef CODE_SHARING + LONG (LOADADDR(.tfm_shared_symbols)) + LONG (ADDR(.tfm_shared_symbols)) + LONG (SIZEOF(.tfm_shared_symbols) / 4) +#endif + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + __copy_table_end__ = .; + + /* .zero.table */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) + __zero_table_end__ = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + +#ifdef CODE_SHARING + /* The code sharing between bootloader and runtime firmware requires to + * share the global variables. Section size must be equal with + * SHARED_SYMBOL_AREA_SIZE defined in region_defs.h + */ + .tfm_shared_symbols : ALIGN(4) + { + *(.data.mbedtls_calloc_func) + *(.data.mbedtls_free_func) + *(.data.mbedtls_exit) + *(.data.memset_func) + . = ALIGN(SHARED_SYMBOL_AREA_SIZE); + } > RAM AT > FLASH + + ASSERT(SHARED_SYMBOL_AREA_SIZE % 4 == 0, "SHARED_SYMBOL_AREA_SIZE must be divisible by 4") +#endif + + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + + .data : ALIGN(4) + { + *(vtable) + *(.data*) + + KEEP(*(.jcr*)) + . = ALIGN(4); + + } > RAM AT > FLASH + Image$$ER_DATA$$Base = ADDR(.data); + + .bss : ALIGN(4) + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .msp_stack (NOLOAD) : ALIGN(32) + { + . += __msp_stack_size__ - 0x8; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .msp_stack_seal_res : + { + . += 0x8; + } > RAM + __StackSeal = ADDR(.msp_stack_seal_res); + +#else + .msp_stack (NOLOAD) : ALIGN(32) + { + . += __msp_stack_size__; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + .heap (NOLOAD): ALIGN(8) + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += __heap_size__; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); + + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); +} diff --git a/platform/ext/target/adi/max32657/device/src/startup_max32657.c b/platform/ext/target/adi/max32657/device/src/startup_max32657.c new file mode 100644 index 0000000000..f95240c820 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/startup_max32657.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ +//FIXME: check if following includes are needed +#include "tfm_hal_device_header.h" +#if defined(TEST_NS_FPU) || defined(TEST_S_FPU) +#include "test_interrupt.h" +#endif + +#include "system_max32657.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ + __NO_RETURN void __WEAK handler_name(void); \ + void handler_name(void) \ + { \ + while (1) \ + ; \ + } + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) +DEFAULT_IRQ_HANDLER(Default_Handler) + +/* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + +DEFAULT_IRQ_HANDLER(ICE_IRQHandler) /* 0x10 0x0040 16: ICE Unlock */ +DEFAULT_IRQ_HANDLER(WDT_IRQHandler) /* 0x11 0x0044 17: Watchdog Timer */ +DEFAULT_IRQ_HANDLER(RTC_IRQHandler) /* 0x12 0x0048 18: RTC */ +DEFAULT_IRQ_HANDLER(TRNG_IRQHandler) /* 0x13 0x004C 19: True Random Number Generator */ +DEFAULT_IRQ_HANDLER(TMR0_IRQHandler) /* 0x14 0x0050 20: Timer 0 */ +DEFAULT_IRQ_HANDLER(TMR1_IRQHandler) /* 0x15 0x0054 21: Timer 1 */ +DEFAULT_IRQ_HANDLER(TMR2_IRQHandler) /* 0x16 0x0058 22: Timer 2 */ +DEFAULT_IRQ_HANDLER(TMR3_IRQHandler) /* 0x17 0x005C 23: Timer 3 */ +DEFAULT_IRQ_HANDLER(TMR4_IRQHandler) /* 0x18 0x0060 24: Timer 4 */ +DEFAULT_IRQ_HANDLER(TMR5_IRQHandler) /* 0x19 0x0064 25: Timer 5 */ +DEFAULT_IRQ_HANDLER(I3C_IRQHandler) /* 0x1A 0x0068 26: I3C */ +DEFAULT_IRQ_HANDLER(UART_IRQHandler) /* 0x1B 0x006C 27: UART */ +DEFAULT_IRQ_HANDLER(SPI_IRQHandler) /* 0x1C 0x0070 28: SPI */ +DEFAULT_IRQ_HANDLER(FLC_IRQHandler) /* 0x1D 0x0074 29: FLC */ +DEFAULT_IRQ_HANDLER(GPIO0_IRQHandler) /* 0x1E 0x0078 30: GPIO0 */ +DEFAULT_IRQ_HANDLER(RSV15_IRQHandler) /* 0x1F 0x007C 31: Reserved */ +DEFAULT_IRQ_HANDLER(DMA0_CH0_IRQHandler) /* 0x20 0x0080 32: DMA0 Channel 0 */ +DEFAULT_IRQ_HANDLER(DMA0_CH1_IRQHandler) /* 0x21 0x0084 33: DMA0 Channel 1 */ +DEFAULT_IRQ_HANDLER(DMA0_CH2_IRQHandler) /* 0x22 0x0088 34: DMA0 Channel 2 */ +DEFAULT_IRQ_HANDLER(DMA0_CH3_IRQHandler) /* 0x23 0x008C 35: DMA0 Channel 3 */ +DEFAULT_IRQ_HANDLER(DMA1_CH0_IRQHandler) /* 0x24 0x0090 36: DMA1 Channel 0 */ +DEFAULT_IRQ_HANDLER(DMA1_CH1_IRQHandler) /* 0x25 0x0094 37: DMA1 Channel 1 */ +DEFAULT_IRQ_HANDLER(DMA1_CH2_IRQHandler) /* 0x26 0x0098 38: DMA1 Channel 2 */ +DEFAULT_IRQ_HANDLER(DMA1_CH3_IRQHandler) /* 0x27 0x009C 39: DMA1 Channel 3 */ +DEFAULT_IRQ_HANDLER(WUT0_IRQHandler) /* 0x28 0x00A0 40: Wakeup Timer 0 */ +DEFAULT_IRQ_HANDLER(WUT1_IRQHandler) /* 0x29 0x00A4 41: Wakeup Timer 1 */ +DEFAULT_IRQ_HANDLER(GPIOWAKE_IRQHandler) /* 0x2A 0x00A8 42: GPIO Wakeup */ +DEFAULT_IRQ_HANDLER(CRC_IRQHandler) /* 0x2B 0x00AC 43: CRC */ +DEFAULT_IRQ_HANDLER(AES_IRQHandler) /* 0x2C 0x00B0 44: AES */ +DEFAULT_IRQ_HANDLER(ERFO_IRQHandler) /* 0x2D 0x00B4 45: ERFO Ready */ +DEFAULT_IRQ_HANDLER(BOOST_IRQHandler) /* 0x2E 0x00B8 46: Boost Controller */ +DEFAULT_IRQ_HANDLER(ECC_IRQHandler) /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX0_IRQHandler) /* 0x30 0x00C0 48: BTLE XXXX0 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX1_IRQHandler) /* 0x31 0x00C4 49: BTLE XXXX1 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX2_IRQHandler) /* 0x32 0x00C8 50: BTLE XXXX2 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX3_IRQHandler) /* 0x33 0x00CC 51: BTLE XXXX3 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX4_IRQHandler) /* 0x34 0x00D0 52: BTLE XXXX4 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX5_IRQHandler) /* 0x35 0x00D4 53: BTLE XXXX5 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX6_IRQHandler) /* 0x36 0x00D8 54: BTLE XXXX6 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX7_IRQHandler) /* 0x37 0x00DC 55: BTLE XXXX7 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX8_IRQHandler) /* 0x38 0x00E0 56: BTLE XXXX8 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX9_IRQHandler) /* 0x39 0x00E4 57: BTLE XXXX9 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXA_IRQHandler) /* 0x3A 0x00E8 58: BTLE XXXXA */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXB_IRQHandler) /* 0x3B 0x00EC 59: BTLE XXXXB */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXC_IRQHandler) /* 0x3C 0x00F0 60: BTLE XXXXC */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXD_IRQHandler) /* 0x3D 0x00F4 61: BTLE XXXXD */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXE_IRQHandler) /* 0x3E 0x00F8 62: BTLE XXXXE */ +DEFAULT_IRQ_HANDLER(RSV47_IRQHandler) /* 0x3F 0x00FC 63: Reserved */ +DEFAULT_IRQ_HANDLER(MPC_IRQHandler) /* 0x40 0x0100 64: MPC Combined (Secure) */ +DEFAULT_IRQ_HANDLER(PPC_IRQHandler) /* 0x44 0x0104 65: PPC Combined (Secure) */ +DEFAULT_IRQ_HANDLER(RSV50_IRQHandler) /* 0x48 0x0108 66: Reserved */ +DEFAULT_IRQ_HANDLER(RSV51_IRQHandler) /* 0x49 0x010C 67: Reserved */ +DEFAULT_IRQ_HANDLER(RSV52_IRQHandler) /* 0x4A 0x0110 68: Reserved */ +DEFAULT_IRQ_HANDLER(RSV53_IRQHandler) /* 0x4B 0x0114 69: Reserved */ + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void (*VECTOR_TABLE_Type)(void); + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + SecureFault_Handler, /* Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + ICE_IRQHandler, /* 0x10 0x0040 16: ICE Unlock */ + WDT_IRQHandler, /* 0x11 0x0044 17: Watchdog Timer */ + RTC_IRQHandler, /* 0x12 0x0048 18: RTC */ + TRNG_IRQHandler, /* 0x13 0x004C 19: True Random Number Generator */ + TMR0_IRQHandler, /* 0x14 0x0050 20: Timer 0 */ + TMR1_IRQHandler, /* 0x15 0x0054 21: Timer 1 */ + TMR2_IRQHandler, /* 0x16 0x0058 22: Timer 2 */ + TMR3_IRQHandler, /* 0x17 0x005C 23: Timer 3 */ + TMR4_IRQHandler, /* 0x18 0x0060 24: Timer 4 */ + TMR5_IRQHandler, /* 0x19 0x0064 25: Timer 5 */ + I3C_IRQHandler, /* 0x1A 0x0068 26: I3C */ + UART_IRQHandler, /* 0x1B 0x006C 27: UART */ + SPI_IRQHandler, /* 0x1C 0x0070 28: SPI */ + FLC_IRQHandler, /* 0x1D 0x0074 29: FLC */ + GPIO0_IRQHandler, /* 0x1E 0x0078 30: GPIO0 */ + RSV15_IRQHandler, /* 0x1F 0x007C 31: Reserved */ + DMA0_CH0_IRQHandler, /* 0x20 0x0080 32: DMA0 Channel 0 */ + DMA0_CH1_IRQHandler, /* 0x21 0x0084 33: DMA0 Channel 1 */ + DMA0_CH2_IRQHandler, /* 0x22 0x0088 34: DMA0 Channel 2 */ + DMA0_CH3_IRQHandler, /* 0x23 0x008C 35: DMA0 Channel 3 */ + DMA1_CH0_IRQHandler, /* 0x24 0x0090 36: DMA1 Channel 0 */ + DMA1_CH1_IRQHandler, /* 0x25 0x0094 37: DMA1 Channel 1 */ + DMA1_CH2_IRQHandler, /* 0x26 0x0098 38: DMA1 Channel 2 */ + DMA1_CH3_IRQHandler, /* 0x27 0x009C 39: DMA1 Channel 3 */ + WUT0_IRQHandler, /* 0x28 0x00A0 40: Wakeup Timer 0 */ + WUT1_IRQHandler, /* 0x29 0x00A4 41: Wakeup Timer 1 */ + GPIOWAKE_IRQHandler, /* 0x2A 0x00A8 42: GPIO Wakeup */ + CRC_IRQHandler, /* 0x2B 0x00AC 43: CRC */ + AES_IRQHandler, /* 0x2C 0x00B0 44: AES */ + ERFO_IRQHandler, /* 0x2D 0x00B4 45: ERFO Ready */ + BOOST_IRQHandler, /* 0x2E 0x00B8 46: Boost Controller */ + ECC_IRQHandler, /* 0x2F 0x00BC 47: ECC */ + /* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + BTLE_XXXX0_IRQHandler, /* 0x30 0x00C0 48: BTLE XXXX0 */ + BTLE_XXXX1_IRQHandler, /* 0x31 0x00C4 49: BTLE XXXX1 */ + BTLE_XXXX2_IRQHandler, /* 0x32 0x00C8 50: BTLE XXXX2 */ + BTLE_XXXX3_IRQHandler, /* 0x33 0x00CC 51: BTLE XXXX3 */ + BTLE_XXXX4_IRQHandler, /* 0x34 0x00D0 52: BTLE XXXX4 */ + BTLE_XXXX5_IRQHandler, /* 0x35 0x00D4 53: BTLE XXXX5 */ + BTLE_XXXX6_IRQHandler, /* 0x36 0x00D8 54: BTLE XXXX6 */ + BTLE_XXXX7_IRQHandler, /* 0x37 0x00DC 55: BTLE XXXX7 */ + BTLE_XXXX8_IRQHandler, /* 0x38 0x00E0 56: BTLE XXXX8 */ + BTLE_XXXX9_IRQHandler, /* 0x39 0x00E4 57: BTLE XXXX9 */ + BTLE_XXXXA_IRQHandler, /* 0x3A 0x00E8 58: BTLE XXXXA */ + BTLE_XXXXB_IRQHandler, /* 0x3B 0x00EC 59: BTLE XXXXB */ + BTLE_XXXXC_IRQHandler, /* 0x3C 0x00F0 60: BTLE XXXXC */ + BTLE_XXXXD_IRQHandler, /* 0x3D 0x00F4 61: BTLE XXXXD */ + BTLE_XXXXE_IRQHandler, /* 0x3E 0x00F8 62: BTLE XXXXE */ + RSV47_IRQHandler, /* 0x3F 0x00FC 63: Reserved */ + MPC_IRQHandler, /* 0x40 0x0100 64: MPC Combined (Secure) */ + PPC_IRQHandler, /* 0x44 0x0104 65: PPC Combined (Secure) */ + RSV50_IRQHandler, /* 0x48 0x0108 66: Reserved */ + RSV51_IRQHandler, /* 0x49 0x010C 67: Reserved */ + RSV52_IRQHandler, /* 0x4A 0x0110 68: Reserved */ + RSV53_IRQHandler, /* 0x4B 0x0114 69: Reserved */ +}; + +// FIXME: if we want to have __isr_vector in system_max32657.c, uncomment below line +// extern const VECTOR_TABLE_Type __VECTOR_TABLE __attribute__((alias("__isr_vector"))); + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __disable_irq(); +#endif + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/platform/ext/target/adi/max32657/device/src/system_max32657.c b/platform/ext/target/adi/max32657/device/src/system_max32657.c new file mode 100644 index 0000000000..b79ddfdec8 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/system_max32657.c @@ -0,0 +1,122 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include +#include "mxc_sys.h" +#include "mxc_errors.h" +#include "max32657.h" +#include "system_max32657.h" +#include "gcr_regs.h" +#include "mpc.h" + + +uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup + +/* + The libc implementation from GCC 11+ depends on _getpid and _kill in some places. + There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore + we implement stub functions that return an error code to resolve linker warnings. +*/ +__weak int _getpid(void) +{ + return E_NOT_SUPPORTED; +} + +__weak int _kill(void) +{ + return E_NOT_SUPPORTED; +} + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); + switch (clk_src) { + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: + base_freq = IPO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: + base_freq = ERFO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: + base_freq = INRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: + base_freq = IBRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + default: + // Codes 001 and 111 are reserved. + // This code should never execute, however, initialize to safe value. + base_freq = HIRC_FREQ; + break; + } + + // Get the clock divider + div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; + + SystemCoreClock = base_freq >> div; +} + +/** + * This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +void SystemInit(void) +{ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern void *__VECTOR_TABLE[]; + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif /* __VTOR_PRESENT check */ + +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ + + /** + * Enable Unaligned Access Trapping to throw an exception when there is an + * unaligned memory access while unaligned access support is disabled. + * + * Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ +#if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + __DSB(); + __ISB(); + + /* Enable interrupts */ + __enable_irq(); + + /* Change system clock source to the main high-speed clock */ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); + MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); + SystemCoreClockUpdate(); +} From 76eb795cda8bfd4203cefd9e63ecc70f1b33069b Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 21 Nov 2024 18:38:16 +0300 Subject: [PATCH 003/133] [zep fromtree] platform: ext: adi: Enable TF-M for MAX32657 Update CMakeFile for tf-m integration Enable tf-m flags in config file Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I67484cdd9c4b8d3c94873a2d1fc8e69ef7eb1d08 Signed-off-by: Sadik Ozer (cherry picked from commit aa15c18907b29ae37c48bf69cf6e3eaa210fe4da) --- .../ext/target/adi/max32657/CMakeLists.txt | 82 +++++++++++++++++++ platform/ext/target/adi/max32657/config.cmake | 10 ++- 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 613857637a..34c7812edc 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -33,6 +33,12 @@ set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers) set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC}) set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) +########################## Platform region defs ################################ +target_include_directories(platform_region_defs + INTERFACE + partition +) + ###### BL2 Related Cmake Configurations ######################################## if(BL2) # Add scatter files for BL2 @@ -91,3 +97,79 @@ if(BL2) ) endif() + +###### TF-M Related Cmake Configurations ####################################### + +target_compile_definitions(tfm_s + PRIVATE + IS_SECURE_ENVIRONMENT + TFM_DATA_INITIALIZE # Enables copying of TF-M specific Data sections from Flash to RAM during startup +) + +target_add_scatter_file(tfm_s + $<$:${PLATFORM_DIR}/ext/common/gcc/tfm_common_s.ld> +) + +target_sources(tfm_s + PRIVATE + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/startup_${TARGET_LC}.c + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c +) + +target_compile_definitions(tfm_s + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CMSIS_device_header="${TARGET_LC}.h" + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 +) + +target_compile_definitions(platform_s + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CMSIS_device_header="${TARGET_LC}.h" + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 +) + +target_compile_options(platform_s + PUBLIC + ${COMPILER_CMSE_FLAG} + -mno-unaligned-access # Added to mitigate the unaligned access problem +) + +target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/TZ/spc_me30.c + + $<$:${CMAKE_CURRENT_SOURCE_DIR}/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} + ${PLATFORM_DIR}/.. +) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index a0cb7f2841..750c3cd474 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -1,11 +1,19 @@ #------------------------------------------------------------------------------- -# Portions Copyright (C) 2024 Analog Devices, Inc. +# Portions Copyright (C) 2024-2025 Analog Devices, Inc. # # SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- set(BL2 ON CACHE BOOL "Whether to build BL2") +set(CONFIG_TFM_USE_TRUSTZONE ON) +set(TFM_PARTITION_PLATFORM OFF CACHE BOOL "Enable Platform partition") +set(TFM_PARTITION_CRYPTO ON CACHE BOOL "Enable Crypto partition") +set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE ON CACHE BOOL "Enable Internal Trusted Storage partition") +set(TFM_PARTITION_NS_AGENT_TZ ON CACHE BOOL "Enable Non-Secure Agent in Secure partition") +set(CONFIG_TFM_BOOT_STORE_MEASUREMENTS OFF CACHE BOOL "Store measurement values from all the boot stages. Used for initial attestation token.") +set(CONFIG_TFM_BOOT_STORE_ENCODED_MEASUREMENTS OFF CACHE BOOL "Enable storing of encoded measurements in boot.") +set(CONFIG_TFM_HALT_ON_CORE_PANIC ON CACHE BOOL "On fatal errors in the secure firmware, halt instead of rebooting.") set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") From 839cbba4b94a76d8be3835425ee97ff152b553a9 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Fri, 22 Nov 2024 15:02:58 +0300 Subject: [PATCH 004/133] [zep fromtree] platform: ext: adi: Add PPC driver Add PPC driver for MAX32657, it is a shim driver that filled with hal_adi call functions Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I1f16c64263846321f1f156b744af5ac25d0e6d12 Signed-off-by: Sadik Ozer (cherry picked from commit 3599278a4d2078a4803a43e53956628d68f47a21) --- .../ext/target/adi/max32657/CMakeLists.txt | 2 + platform/ext/target/adi/max32657/RTE_Device.h | 28 ++++ .../adi/max32657/cmsis_drivers/Driver_PPC.c | 123 ++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 platform/ext/target/adi/max32657/RTE_Device.h create mode 100644 platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 34c7812edc..35093138b3 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -148,6 +148,8 @@ target_compile_options(platform_s target_sources(platform_s PRIVATE + cmsis_drivers/Driver_PPC.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c diff --git a/platform/ext/target/adi/max32657/RTE_Device.h b/platform/ext/target/adi/max32657/RTE_Device.h new file mode 100644 index 0000000000..81eab3c9c1 --- /dev/null +++ b/platform/ext/target/adi/max32657/RTE_Device.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016-2018 ARM Limited + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// PPC (Peripheral Protection Controller) [Driver_PPC] +// Configuration settings for Driver_PPC in component ::Drivers:PPC +#define RTE_PPC 1 +// PPC (Peripheral Protection Controller) [Driver_PPC] + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c new file mode 100644 index 0000000000..eb34325817 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "Driver_PPC.h" + +#include "mxc_device.h" +#include "RTE_Device.h" +#include "spc.h" + +/* Driver version */ +#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) + +#ifdef RTE_PPC + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_PPC_API_VERSION, + ARM_PPC_DRV_VERSION +}; + +static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void) +{ + return DriverVersion; +} + +static int32_t PPC_Initialize(void) +{ + return ARM_DRIVER_OK; +} + +static int32_t PPC_Uninitialize(void) +{ + return ARM_DRIVER_OK; +} + +static int32_t PPC_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + mxc_spc_periph_t mxc_periph = (1U << periph); + mxc_spc_priv_t mxc_priv; + + if (priv_attr == ARM_PPC_PRIV_ONLY) { + mxc_priv = MXC_SPC_PRIVILEGED; + } else { + mxc_priv = MXC_SPC_UNPRIVILEGED; + } + + if(sec_attr == ARM_PPC_SECURE_ONLY) { + MXC_SPC_SetSecure(mxc_periph); + } else { + MXC_SPC_SetNonSecure(mxc_periph); + } + MXC_SPC_SetPrivAccess(mxc_periph, mxc_priv); + + return ARM_DRIVER_OK; +} + +static uint32_t PPC_IsPeriphSecure(uint8_t periph) +{ + mxc_spc_periph_t mxc_periph = (1U << periph); + + if (MXC_SPC->apbsec & mxc_periph) { + return 0; // Non-Secure + } else { + return 1; // Secure + } +} + +static uint32_t PPC_IsPeriphPrivOnly(uint8_t periph) +{ + mxc_spc_periph_t mxc_periph = (1U << periph); + + if (MXC_SPC->apbpriv & mxc_periph) { + return 0; // unprivileged + } else { + return 1; // privileged + } +} + +static int32_t PPC_EnableInterrupt(void) +{ + MXC_SPC_PPC_EnableInt(MXC_F_SPC_PPC_INTEN_APBPPC); + + return ARM_DRIVER_OK; +} + +static void PPC_DisableInterrupt(void) +{ + MXC_SPC_PPC_DisableInt(MXC_F_SPC_PPC_INTEN_APBPPC); +} + +static void PPC_ClearInterrupt(void) +{ + MXC_SPC_PPC_ClearFlags(MXC_F_SPC_PPC_INTCLR_APBPPC); +} + +static uint32_t PPC_InterruptState(void) +{ + if (MXC_SPC_PPC_GetFlags() & MXC_F_SPC_PPC_STATUS_APBPPC) { + return 1; // pending interrupt + } else { + return 0; // no interrupt + } +} + +ARM_DRIVER_PPC Driver_PPC = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = PPC_Initialize, + .Uninitialize = PPC_Uninitialize, + .ConfigPeriph = PPC_ConfigPeriph, + .IsPeriphSecure = PPC_IsPeriphSecure, + .IsPeriphPrivOnly = PPC_IsPeriphPrivOnly, + .EnableInterrupt = PPC_EnableInterrupt, + .DisableInterrupt = PPC_DisableInterrupt, + .ClearInterrupt = PPC_ClearInterrupt, + .InterruptState = PPC_InterruptState +}; +#endif /* RTE_PPC */ From dd776d3cf56678257f281fe5843d25d4852dc7a0 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 26 Nov 2024 12:42:02 +0300 Subject: [PATCH 005/133] [zep fromtree] platform: ext: adi: Define S and NS address Define secure, non-secure memory and required peripheral address Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I5b6c0335d6e34c55a7a671008848e94cb851b6fb Signed-off-by: Sadik Ozer (cherry picked from commit 609ef3f4be013b2f382399230830ceaf54008b80) --- .../target/adi/max32657/platform_retarget.h | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 platform/ext/target/adi/max32657/platform_retarget.h diff --git a/platform/ext/target/adi/max32657/platform_retarget.h b/platform/ext/target/adi/max32657/platform_retarget.h new file mode 100644 index 0000000000..16fee969d8 --- /dev/null +++ b/platform/ext/target/adi/max32657/platform_retarget.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __ADI_MAX32657_RETARGET_H__ +#define __ADI_MAX32657_RETARGET_H__ + +#include "max32657.h" + +/* ======= Defines peripherals memory map addresses ======= */ +/* Define Peripherals NS address range for the platform */ +#define PERIPHERALS_BASE_NS_START (0x40000000) +#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF) + +/* Non-secure memory map addresses */ +#define UART0_BASE_NS MXC_BASE_UART_NS +#define TRNG_BASE_NS MXC_BASE_TRNG_NS + +/* Secure memory map addresses */ +#define UART0_BASE_S MXC_BASE_UART_S +#define TRNG_BASE_S MXC_BASE_TRNG_S +#define MPC_SRAM0_BASE_S MXC_BASE_MPC_SRAM0_S +#define MPC_SRAM1_BASE_S MXC_BASE_MPC_SRAM1_S +#define MPC_SRAM2_BASE_S MXC_BASE_MPC_SRAM2_S +#define MPC_SRAM3_BASE_S MXC_BASE_MPC_SRAM3_S +#define MPC_SRAM4_BASE_S MXC_BASE_MPC_SRAM4_S +#define MPC_FLASH_BASE_S MXC_BASE_MPC_FLASH_S + + +/* SRAM MPC ranges and limits */ +/* Internal memory */ +#define MPC_SRAM0_RANGE_BASE_NS 0x20000000 +#define MPC_SRAM0_RANGE_LIMIT_NS 0x20007FFF +#define MPC_SRAM0_RANGE_BASE_S 0x30000000 +#define MPC_SRAM0_RANGE_LIMIT_S 0x30007FFF + +#define MPC_SRAM1_RANGE_BASE_NS 0x20008000 +#define MPC_SRAM1_RANGE_LIMIT_NS 0x2000FFFF +#define MPC_SRAM1_RANGE_BASE_S 0x30008000 +#define MPC_SRAM1_RANGE_LIMIT_S 0x3000FFFF + +#define MPC_SRAM2_RANGE_BASE_NS 0x20010000 +#define MPC_SRAM2_RANGE_LIMIT_NS 0x2001FFFF +#define MPC_SRAM2_RANGE_BASE_S 0x30010000 +#define MPC_SRAM2_RANGE_LIMIT_S 0x3001FFFF + +#define MPC_SRAM3_RANGE_BASE_NS 0x20020000 +#define MPC_SRAM3_RANGE_LIMIT_NS 0x2002FFFF +#define MPC_SRAM3_RANGE_BASE_S 0x30020000 +#define MPC_SRAM3_RANGE_LIMIT_S 0x3002FFFF + +#define MPC_SRAM4_RANGE_BASE_NS 0x20030000 +#define MPC_SRAM4_RANGE_LIMIT_NS 0x2003FFFF +#define MPC_SRAM4_RANGE_BASE_S 0x30030000 +#define MPC_SRAM4_RANGE_LIMIT_S 0x3003FFFF + +/* Flash memory */ +#define FLASH0_BASE_S 0x11000000 +#define FLASH0_BASE_NS MXC_PHY_FLASH_MEM_BASE +#define FLASH0_SIZE MXC_PHY_FLASH_MEM_SIZE /* 1 MB */ +#define FLASH0_SECTOR_SIZE MXC_PHY_FLASH_PAGE_SIZE /* 8 kB */ +#define FLASH0_PAGE_SIZE MXC_PHY_FLASH_PAGE_SIZE /* 8 kB */ +#define FLASH0_PROGRAM_UNIT 0x10 /* Minimum write size */ + +/* Flash memory Info Block */ +#define FLASH_INFO_BASE MXC_INFO_MEM_BASE +#define FLASH_INFO_SIZE MXC_INFO_MEM_SIZE /* 16 KB */ +#define FLASH_INFO_SECTOR_SIZE 0x00002000 /* 8 kB */ +#define FLASH_INFO_PAGE_SIZE 0x00002000 /* 8 kB */ +#define FLASH_INFO_PROGRAM_UNIT 0x10 /* Minimum write size */ + +#endif /* __ADI_MAX32657_RETARGET_H__ */ From fd0484fa2e333432f9a922f104f45f42fce6657d Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 26 Nov 2024 12:53:09 +0300 Subject: [PATCH 006/133] [zep fromtree] platform: ext: adi: Define flash regions Set image region for fw and other section, flash devided as below /* Flash layout on MAX32657 with BL2 (multiple image boot): * * Secure flash address which 28th bit 1 is logical address * * 0X0100_0000 BL2 - MCUBoot (64KB) * 0x0101_0000 Secure image primary slot (320KB) * 0x0106_0000 Non-secure image primary slot (576KB) * 0x010F_0000 Secure image secondary slot (0KB) * 0x010F_0000 Non-secure image secondary slot (0KB) * 0x010F_0000 Scratch area (0) * 0x010F_0000 Protected Storage Area (0) * 0x010F_0000 Internal Trusted Storage Area (16 KB) * 0x010F_4000 OTP / NV counters area (16 KB) * 0x010F_8000 Unused (32KB) * * Flash layout on MAX32657 with BL2 (single image boot): * * 0X0100_0000 BL2 - MCUBoot (64KB) * 0x0101_0000 Primary image area (896KB): * 0x0101_0000 Secure image primary * 0x0106_0000 Non-secure image primary * 0x010F_0000 Secondary image area (0KB): * 0x010F_0000 Secure image secondary * 0x010F_0000 Non-secure image secondary * 0x010F_0000 Scratch area (0) * 0x010F_0000 Protected Storage Area (0) * 0x010F_0000 Internal Trusted Storage Area (16 KB) * 0x010F_4000 OTP / NV counters area (16 KB) * 0x010F_8000 Unused * * Flash layout on MAX32657, if BL2 not defined: * * 0X0100_0000 Secure image (512KB) * 0X0108_0000 Non-secure image (512KB) */ Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I0f7021ed6f06e56b5549bf5edfefc86adb12b604 Signed-off-by: Sadik Ozer (cherry picked from commit 098c6bd4f26217333df8e09ed996a6987596e2d8) --- .../ext/target/adi/max32657/CMakeLists.txt | 2 + .../adi/max32657/partition/flash_layout.h | 212 ++++++++++++++++++ 2 files changed, 214 insertions(+) create mode 100644 platform/ext/target/adi/max32657/partition/flash_layout.h diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 35093138b3..b395e8fb6e 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -56,6 +56,7 @@ if(BL2) # Add includes for BL2 target_include_directories(platform_bl2 PUBLIC + partition ${HAL_ADI_PERIPH_INC_DIR} ${HAL_ADI_CMSIS_INC_DIR} PRIVATE @@ -171,6 +172,7 @@ target_include_directories(platform_s PUBLIC . ../common + partition ${HAL_ADI_PERIPH_INC_DIR} ${HAL_ADI_CMSIS_INC_DIR} ${PLATFORM_DIR}/.. diff --git a/platform/ext/target/adi/max32657/partition/flash_layout.h b/platform/ext/target/adi/max32657/partition/flash_layout.h new file mode 100644 index 0000000000..ef89879e71 --- /dev/null +++ b/platform/ext/target/adi/max32657/partition/flash_layout.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * Copyright 2019-2023 NXP. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +/* Flash layout on MAX32657 with BL2 (multiple image boot): + * + * Secure flash address which 28th bit 1 is logical address + * + * 0X0100_0000 BL2 - MCUBoot (64KB) + * 0x0101_0000 Secure image primary slot (320KB) + * 0x0106_0000 Non-secure image primary slot (576KB) + * 0x010F_0000 Secure image secondary slot (0KB) + * 0x010F_0000 Non-secure image secondary slot (0KB) + * 0x010F_0000 Scratch area (0) + * 0x010F_0000 Protected Storage Area (0) + * 0x010F_0000 Internal Trusted Storage Area (16 KB) + * 0x010F_4000 OTP / NV counters area (16 KB) + * 0x010F_8000 Unused (32KB) + * + * Flash layout on MAX32657 with BL2 (single image boot): + * + * 0X0100_0000 BL2 - MCUBoot (64KB) + * 0x0101_0000 Primary image area (896KB): + * 0x0101_0000 Secure image primary + * 0x0106_0000 Non-secure image primary + * 0x010F_0000 Secondary image area (0KB): + * 0x010F_0000 Secure image secondary + * 0x010F_0000 Non-secure image secondary + * 0x010F_0000 Scratch area (0) + * 0x010F_0000 Protected Storage Area (0) + * 0x010F_0000 Internal Trusted Storage Area (16 KB) + * 0x010F_4000 OTP / NV counters area (16 KB) + * 0x010F_8000 Unused + * + * Flash layout on MAX32657, if BL2 not defined: + * + * 0X0100_0000 Secure image (512KB) + * 0X0108_0000 Non-secure image (512KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +#ifndef KB +#define KB(x) ((x) * 1024) +#endif + +/* Size of a Secure and of a Non-secure image */ +#define FLASH_S_PARTITION_SIZE (0x50000) /* S partition: 320 KB */ +#define FLASH_NS_PARTITION_SIZE (0x90000) /* NS partition: 576 KB */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif +/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE KB(8) +/* Same as FLASH0_SIZE */ +#define FLASH_TOTAL_SIZE KB(1024) + +/* Flash layout info for BL2 bootloader */ +/* Same as FLASH0_BASE_S */ +#define FLASH_BASE_ADDRESS (0x11000000) + +/* Offset and size definitions of the flash partitions that are handled by the + * bootloader. The image swapping is done between IMAGE_PRIMARY and + * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image + * swapping. + */ +#define FLASH_AREA_BL2_OFFSET (0) +#define FLASH_AREA_BL2_SIZE KB(64) + +#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) +/* Secure + Non-secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE) +/* Secure + Non-secure secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_2_SIZE (0) +/* Not used (scratch area), the 'Swap' firmware upgrade operation is not + * supported on MAX32657 */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#elif (MCUBOOT_IMAGE_NUMBER == 2) +/* Secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image primary slot */ +#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) +/* Secure image secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) +#define FLASH_AREA_2_SIZE (0) +/* Non-secure image secondary slot */ +#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_3_SIZE (0) +/* Scratch area */ +/* FIXME: remove scartch area. Currently removing them yields BL2 error*/ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) +#else /* MCUBOOT_IMAGE_NUMBER > 2 */ +#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" +#endif /* MCUBOOT_IMAGE_NUMBER */ + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + FLASH_AREA_SCRATCH_SIZE) +#define FLASH_PS_AREA_SIZE KB(0) /* 0 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE KB(16) + +/* Placing OTP backup area in Flash because of limited availability of Secure Flash Info area */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE*2) +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_OFFSET (0) +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE + +#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + SECURE_IMAGE_MAX_SIZE) +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +/* Smallest flash programmable unit in bytes - MAX32657: 128 bits */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x00000010) + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x00000010) + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x00000010) // Supports 128 bit writes + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + TFM_OTP_NV_COUNTERS_AREA_SIZE) + +/* Flash and RAM configurations for secure and non-secure image partitions*/ + +#define S_ROM_ALIAS_BASE (0x11000000) +#define NS_ROM_ALIAS_BASE (0X01000000) + +#define S_RAM_ALIAS_BASE (0x30000000) +#define NS_RAM_ALIAS_BASE (0x20000000) + +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE +#define TOTAL_RAM_SIZE KB(256) + +#endif /* __FLASH_LAYOUT_H__ */ From d790934f02510add779ac3ebfbbe96a9a27dfac7 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 26 Nov 2024 12:57:39 +0300 Subject: [PATCH 007/133] [zep fromtree] platform: ext: adi: Set TF-M flash related macros Set the flag that required by the tf-m project - BL2 - RAM and Code size - Shared section size Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: Ia3b343d3a3e363dd7b259580d7f1ad284ff29f1d Signed-off-by: Sadik Ozer (cherry picked from commit 8e0d63a256c2aab0cd8794d08e4a20d8ce5fddb5) --- .../adi/max32657/partition/region_defs.h | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 platform/ext/target/adi/max32657/partition/region_defs.h diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h new file mode 100644 index 0000000000..1ee6aaf491 --- /dev/null +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * Copyright 2019-2023 NXP. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#define BL2_HEAP_SIZE KB(4) +#define BL2_MSP_STACK_SIZE KB(6) + +#ifdef ENABLE_HEAP +#define S_HEAP_SIZE (512) +#endif + +#ifdef TFM_FIH_PROFILE_ON +#define S_MSP_STACK_SIZE (0x00000A40) +#else +#define S_MSP_STACK_SIZE KB(4) +#endif +#define S_PSP_STACK_SIZE KB(2) + +#define NS_HEAP_SIZE KB(4) +#define NS_STACK_SIZE (0x000001E0) + + +#ifdef BL2 +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0) +#endif /* BL2 */ + +#ifndef LINK_TO_SECONDARY_PARTITION + +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET + FLASH_S_PARTITION_SIZE) +#else +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET + FLASH_S_PARTITION_SIZE) +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ +#if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET) +/* If secure image and nonsecure image are concatenated, and nonsecure image + * locates at the higher memory range, then the secure image does not need + * the trailer area. + */ +#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE) +#else +#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#endif + +#define IMAGE_NS_CODE_SIZE FLASH_NS_PARTITION_SIZE + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +/* Size of vector table: 69 interrupt handlers + 16 bytes of reserved space */ +#define S_CODE_VECTOR_TABLE_SIZE (0x00000124) + +#define S_DATA_START (S_RAM_ALIAS(0x00000000)) +#define S_DATA_SIZE KB(64) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Non-secure regions + * MPC block aligned 32KB, NS binary need to aling that + */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS( S_DATA_SIZE )) +#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC) +#define DEV_APIS_TEST_NVMEM_REGION_SIZE KB(1) +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - DEV_APIS_TEST_NVMEM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for MPC and SAU configuration */ + +#define MPC_CONFIG_BLOCK_SIZE KB(32) //Configurable block size by MPC is 32kb + +#define NS_PARTITION_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_PARTITION_END (NS_PARTITION_START + NS_PARTITION_SIZE - 1) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE) + +#ifdef BL2 +/* Bootloader regions */ +#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +#define BL2_DATA_START (S_RAM_ALIAS(0x0)) +#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared symbol area between bootloader and runtime firmware. Global variables + * in the shared code can be placed here. + */ +#ifdef CODE_SHARING +#define SHARED_SYMBOL_AREA_BASE (S_RAM_ALIAS_BASE) +#define SHARED_SYMBOL_AREA_SIZE (0x00000020) +#else +#define SHARED_SYMBOL_AREA_BASE (S_RAM_ALIAS_BASE) +#define SHARED_SYMBOL_AREA_SIZE (0x00000000) +#endif /* CODE_SHARING */ + +/* Shared data area between bootloader and runtime firmware. + * These areas are allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE (SHARED_SYMBOL_AREA_BASE + SHARED_SYMBOL_AREA_SIZE) +#define BOOT_TFM_SHARED_DATA_SIZE KB(1) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) + +#endif /* __REGION_DEFS_H__ */ From 19f223ab641c0d5b55cf677c54b2505659ea7c13 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Wed, 11 Dec 2024 20:12:39 +0300 Subject: [PATCH 008/133] [zep fromtree] platform: ext: adi: Add Flash driver Add flash driver for MAX32657, it is a shim driver that filled with hal_adi call functions Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I2a3691e2bb0946df8bf1f4fa57bb25a3dad4b5f4 Signed-off-by: Sadik Ozer (cherry picked from commit dd40134ec72b8e50fa8b0377daa717a102bdda0f) --- .../ext/target/adi/max32657/CMakeLists.txt | 3 + platform/ext/target/adi/max32657/RTE_Device.h | 5 + .../adi/max32657/cmsis_drivers/Driver_Flash.c | 228 ++++++++++++++++++ .../adi/max32657/partition/flash_layout.h | 16 ++ 4 files changed, 252 insertions(+) create mode 100644 platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index b395e8fb6e..743d3db473 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -71,6 +71,8 @@ if(BL2) target_sources(platform_bl2 PRIVATE + cmsis_drivers/Driver_Flash.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c @@ -149,6 +151,7 @@ target_compile_options(platform_s target_sources(platform_s PRIVATE + cmsis_drivers/Driver_Flash.c cmsis_drivers/Driver_PPC.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c diff --git a/platform/ext/target/adi/max32657/RTE_Device.h b/platform/ext/target/adi/max32657/RTE_Device.h index 81eab3c9c1..cc5aedc89a 100644 --- a/platform/ext/target/adi/max32657/RTE_Device.h +++ b/platform/ext/target/adi/max32657/RTE_Device.h @@ -25,4 +25,9 @@ #define RTE_PPC 1 // PPC (Peripheral Protection Controller) [Driver_PPC] +// FLASH (Flash Memory) [Driver_FLASH0] +// Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH +#define RTE_FLASH0 1 +// FLASH (Flash Memory) [Driver_FLASH0] + #endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c new file mode 100644 index 0000000000..4fd67258e7 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "Driver_Flash.h" +#include "platform_retarget.h" +#include "RTE_Device.h" +#include "mxc_errors.h" +#include "flc.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) ((void)arg) +#endif + +/* Driver version */ +#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 1) + +/** + * Data width values for ARM_FLASH_CAPABILITIES::data_width + * \ref ARM_FLASH_CAPABILITIES + */ + enum { + DATA_WIDTH_8BIT = 0u, + DATA_WIDTH_16BIT, + DATA_WIDTH_32BIT, + DATA_WIDTH_ENUM_SIZE +}; + +static const uint32_t data_width_byte[DATA_WIDTH_ENUM_SIZE] = { + sizeof(uint8_t), + sizeof(uint16_t), + sizeof(uint32_t), +}; + +struct arm_flash_dev_t { + const uint32_t memory_base; /*!< FLASH memory base address */ + ARM_FLASH_INFO *data; /*!< FLASH data */ +}; + +/* Flash Status */ +static ARM_FLASH_STATUS FlashStatus = {0, 0, 0}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_FLASH_API_VERSION, + ARM_FLASH_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES DriverCapabilities = { + 0, /* event_ready */ + 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ + 1 /* erase_chip */ +}; + +#if (RTE_FLASH0) +static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE, + .sector_size = FLASH0_SECTOR_SIZE, + .page_size = FLASH0_PAGE_SIZE, + .program_unit = FLASH0_PROGRAM_UNIT, + .erased_value = 0xFF +}; + +static struct arm_flash_dev_t ARM_FLASH0_DEV = { +#if (__DOMAIN_NS == 1) + .memory_base = FLASH0_BASE_NS, +#else + .memory_base = FLASH0_BASE_S, +#endif /* __DOMAIN_NS == 1 */ + .data = &(ARM_FLASH0_DEV_DATA)}; + +struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV; + +/* + * Functions + */ + +static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) +{ + ARG_UNUSED(cb_event); + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + + case ARM_POWER_OFF: + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +static int32_t ARM_Flash_ReadData(uint32_t offset, void *data, uint32_t cnt) +{ + /* Check flash memory boundaries */ + if ((offset + cnt) >= FLASH0_SIZE) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* CMSIS ARM_FLASH_ReadData API requires the offset data type size aligned. + * Data type size is specified by the data_width in ARM_FLASH_CAPABILITIES. + */ + if (offset % data_width_byte[DriverCapabilities.data_width] != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Conversion between data items and bytes */ + uint32_t addr = FLASH0_DEV->memory_base + offset; + int num_of_bytes = cnt * data_width_byte[DriverCapabilities.data_width]; + + MXC_FLC_Read(addr, data, num_of_bytes); + + return cnt; +} + +static int32_t ARM_Flash_ProgramData(uint32_t offset, const void *data, uint32_t cnt) +{ + /* Check flash memory boundaries */ + if ((offset + cnt) >= FLASH0_SIZE) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + uint32_t addr = FLASH0_DEV->memory_base + offset; + + if(MXC_FLC_Write(addr, cnt, (uint32_t *)data) != E_NO_ERROR) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + return cnt; +} + +static int32_t ARM_Flash_EraseSector(uint32_t offset) +{ + /* Check flash memory boundaries */ + if (offset >= FLASH0_SIZE) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Sector shall be aligned, check it */ + if ((offset % FLASH0_DEV->data->sector_size) != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + uint32_t addr = FLASH0_DEV->memory_base + offset; + + if (MXC_FLC_PageErase(addr) != E_NO_ERROR) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_EraseChip(void) +{ + if (DriverCapabilities.erase_chip == 1) { + if(MXC_FLC_MassErase() != E_NO_ERROR) { + return ARM_DRIVER_ERROR_PARAMETER; + } + } else { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static ARM_FLASH_STATUS ARM_Flash_GetStatus(void) +{ + return FlashStatus; +} + +static ARM_FLASH_INFO* ARM_Flash_GetInfo(void) +{ + return FLASH0_DEV->data; +} + +ARM_DRIVER_FLASH Driver_FLASH0 = { + ARM_Flash_GetVersion, + ARM_Flash_GetCapabilities, + ARM_Flash_Initialize, + ARM_Flash_Uninitialize, + ARM_Flash_PowerControl, + ARM_Flash_ReadData, + ARM_Flash_ProgramData, + ARM_Flash_EraseSector, + ARM_Flash_EraseChip, + ARM_Flash_GetStatus, + ARM_Flash_GetInfo +}; +#endif /* RTE_FLASH0 */ diff --git a/platform/ext/target/adi/max32657/partition/flash_layout.h b/platform/ext/target/adi/max32657/partition/flash_layout.h index ef89879e71..86b6bcba0e 100644 --- a/platform/ext/target/adi/max32657/partition/flash_layout.h +++ b/platform/ext/target/adi/max32657/partition/flash_layout.h @@ -163,9 +163,17 @@ #define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + SECURE_IMAGE_MAX_SIZE) #define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE +/* Flash device name used by BL2 */ +#define FLASH_DEV_NAME Driver_FLASH0 /* Smallest flash programmable unit in bytes - MAX32657: 128 bits */ #define TFM_HAL_FLASH_PROGRAM_UNIT (0x00000010) +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + /* In this target the CMSIS driver requires only the offset from the base * address instead of the full memory address. */ @@ -179,6 +187,14 @@ /* Smallest flash programmable unit in bytes */ #define TFM_HAL_PS_PROGRAM_UNIT (0x00000010) +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + /* In this target the CMSIS driver requires only the offset from the base * address instead of the full memory address. */ From 47de9d691697ecd7b82431e0b40614555dde808a Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 9 Dec 2024 09:20:54 +0300 Subject: [PATCH 009/133] [zep fromtree] platform: ext: adi: Add MAX32657 custom OTP file - Disable PLATFORM_DEFAULT_OTP to implement MAX32657 OTP - Add read, write, get size functions - Before writing and after reading OTP cell bits are reverted due to default values not match with tfm expectation. On default tfm expect otp cell be 0x00 and bit can be transceived from 0 to 1 but MAX32657 OTP default value is 0xff and bits can be converted from 1 to 0. So that before write and after read bits are reverted. - Set bl2_rotpk_X size as 100 (max value) to get fix otp layout Change-Id: I325f2934a78633d6add6592dc9fdf1c3dcd852ba Signed-off-by: Sadik Ozer (cherry picked from commit 258b8fd3cde0830b9848c38302e8bd3311eb2a50) --- .../ext/target/adi/max32657/CMakeLists.txt | 3 + platform/ext/target/adi/max32657/config.cmake | 1 + .../ext/target/adi/max32657/otp_max32657.c | 216 ++++++++++++++++++ .../target/adi/max32657/platform_otp_ids.h | 56 +++++ 4 files changed, 276 insertions(+) create mode 100644 platform/ext/target/adi/max32657/otp_max32657.c create mode 100644 platform/ext/target/adi/max32657/platform_otp_ids.h diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 743d3db473..624326e32c 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -36,6 +36,7 @@ set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) ########################## Platform region defs ################################ target_include_directories(platform_region_defs INTERFACE + ./ partition ) @@ -72,6 +73,7 @@ if(BL2) target_sources(platform_bl2 PRIVATE cmsis_drivers/Driver_Flash.c + $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c @@ -153,6 +155,7 @@ target_sources(platform_s PRIVATE cmsis_drivers/Driver_Flash.c cmsis_drivers/Driver_PPC.c + $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 750c3cd474..c32dbcbee4 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -14,6 +14,7 @@ set(TFM_PARTITION_NS_AGENT_TZ ON CACHE BOOL "Enable Non-S set(CONFIG_TFM_BOOT_STORE_MEASUREMENTS OFF CACHE BOOL "Store measurement values from all the boot stages. Used for initial attestation token.") set(CONFIG_TFM_BOOT_STORE_ENCODED_MEASUREMENTS OFF CACHE BOOL "Enable storing of encoded measurements in boot.") set(CONFIG_TFM_HALT_ON_CORE_PANIC ON CACHE BOOL "On fatal errors in the secure firmware, halt instead of rebooting.") +set(PLATFORM_DEFAULT_OTP OFF CACHE BOOL "Use trusted on-chip flash to implement OTP memory") set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") diff --git a/platform/ext/target/adi/max32657/otp_max32657.c b/platform/ext/target/adi/max32657/otp_max32657.c new file mode 100644 index 0000000000..756f551648 --- /dev/null +++ b/platform/ext/target/adi/max32657/otp_max32657.c @@ -0,0 +1,216 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#include "config_tfm.h" +#include "tfm_plat_otp.h" + +#include "region_defs.h" +#include "tfm_hal_device_header.h" +#include "platform_retarget.h" +#include "flc.h" + +#include "cmsis_compiler.h" + +#define INFOBLOCK_LINE_SIZE 8 +#define OTP_KEY_OFFSET (FLASH_INFO_BASE + 0x3000) + + +#ifdef BL2 +#if defined(MCUBOOT_SIGN_EC384) +#define BL2_ROTPK_HASH_SIZE (48) +#define BL2_ROTPK_KEY_SIZE (100) /* Aligned to 4 bytes */ +#else +#define BL2_ROTPK_HASH_SIZE (32) +#endif /* MCUBOOT_SIGN_EC384 */ +#if defined(MCUBOOT_SIGN_EC256) +#define BL2_ROTPK_KEY_SIZE (68) /* Aligned to 4 bytes */ +#endif /* MCUBOOT_SIGN_EC256 */ + +#ifdef MCUBOOT_BUILTIN_KEY +#define BL2_ROTPK_SIZE BL2_ROTPK_KEY_SIZE +#else +#define BL2_ROTPK_SIZE BL2_ROTPK_HASH_SIZE +#endif /* MCUBOOT_BUILTIN_KEY */ +#endif /* BL2 */ + + +__PACKED_STRUCT max32657_otp_nv_counters_region_t { + uint8_t huk[32]; + uint8_t iak[32]; + uint8_t iak_len[4]; + uint8_t iak_type[4]; + uint8_t iak_id[32]; + + uint8_t boot_seed[32]; + uint8_t lcs[4]; + uint8_t implementation_id[32]; + uint8_t cert_ref[32]; + uint8_t verification_service_url[32]; + uint8_t profile_definition[32]; + + uint8_t bl2_rotpk_0[100]; + uint8_t bl2_rotpk_1[100]; + uint8_t bl2_rotpk_2[100]; + uint8_t bl2_rotpk_3[100]; + + uint8_t bl2_nv_counter_0[64]; + uint8_t bl2_nv_counter_1[64]; + uint8_t bl2_nv_counter_2[64]; + uint8_t bl2_nv_counter_3[64]; + + uint8_t ns_nv_counter_0[64]; + uint8_t ns_nv_counter_1[64]; + uint8_t ns_nv_counter_2[64]; + + uint8_t entropy_seed[64]; + uint8_t secure_debug_pk[32]; +}; + +#define GET_OFFSET(item) (OTP_KEY_OFFSET + offsetof(struct max32657_otp_nv_counters_region_t, item)) +#define GET_SIZE(item) sizeof(((struct max32657_otp_nv_counters_region_t*)0)->item) + +struct max32657_otp_element_t { + uint32_t offset; + uint8_t len; +}; + +static const struct max32657_otp_element_t otp_map[] = { + [PLAT_OTP_ID_HUK] = {.offset = GET_OFFSET(huk) , .len = GET_SIZE(huk) }, + [PLAT_OTP_ID_IAK] = {.offset = GET_OFFSET(iak) , .len = GET_SIZE(iak) }, + [PLAT_OTP_ID_IAK_LEN] = {.offset = GET_OFFSET(iak_len) , .len = GET_SIZE(iak_len) }, + [PLAT_OTP_ID_IAK_TYPE] = {.offset = GET_OFFSET(iak_type) , .len = GET_SIZE(iak_type) }, + [PLAT_OTP_ID_IAK_ID] = {.offset = GET_OFFSET(iak_id) , .len = GET_SIZE(iak_id) }, + [PLAT_OTP_ID_BOOT_SEED] = {.offset = GET_OFFSET(boot_seed) , .len = GET_SIZE(boot_seed) }, + [PLAT_OTP_ID_LCS] = {.offset = GET_OFFSET(lcs) , .len = GET_SIZE(lcs) }, + [PLAT_OTP_ID_IMPLEMENTATION_ID] = {.offset = GET_OFFSET(implementation_id) , .len = GET_SIZE(implementation_id) }, + [PLAT_OTP_ID_CERT_REF] = {.offset = GET_OFFSET(cert_ref) , .len = GET_SIZE(cert_ref) }, + [PLAT_OTP_ID_VERIFICATION_SERVICE_URL] = {.offset = GET_OFFSET(verification_service_url) , .len = GET_SIZE(verification_service_url) }, + [PLAT_OTP_ID_PROFILE_DEFINITION] = {.offset = GET_OFFSET(profile_definition) , .len = GET_SIZE(profile_definition) }, + [PLAT_OTP_ID_BL2_ROTPK_0] = {.offset = GET_OFFSET(bl2_rotpk_0) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_BL2_ROTPK_1] = {.offset = GET_OFFSET(bl2_rotpk_1) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_BL2_ROTPK_2] = {.offset = GET_OFFSET(bl2_rotpk_2) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_BL2_ROTPK_3] = {.offset = GET_OFFSET(bl2_rotpk_3) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_NV_COUNTER_BL2_0] = {.offset = GET_OFFSET(bl2_nv_counter_0) , .len = GET_SIZE(bl2_nv_counter_0) }, + [PLAT_OTP_ID_NV_COUNTER_BL2_1] = {.offset = GET_OFFSET(bl2_nv_counter_1) , .len = GET_SIZE(bl2_nv_counter_1) }, + [PLAT_OTP_ID_NV_COUNTER_BL2_2] = {.offset = GET_OFFSET(bl2_nv_counter_2) , .len = GET_SIZE(bl2_nv_counter_2) }, + [PLAT_OTP_ID_NV_COUNTER_BL2_3] = {.offset = GET_OFFSET(bl2_nv_counter_3) , .len = GET_SIZE(bl2_nv_counter_3) }, + + [PLAT_OTP_ID_NV_COUNTER_NS_0] = {.offset = GET_OFFSET(ns_nv_counter_0) , .len = GET_SIZE(ns_nv_counter_0) }, + [PLAT_OTP_ID_NV_COUNTER_NS_1] = {.offset = GET_OFFSET(ns_nv_counter_1) , .len = GET_SIZE(ns_nv_counter_1) }, + [PLAT_OTP_ID_NV_COUNTER_NS_2] = {.offset = GET_OFFSET(ns_nv_counter_2) , .len = GET_SIZE(ns_nv_counter_2) }, + + [PLAT_OTP_ID_ENTROPY_SEED] = {.offset = GET_OFFSET(entropy_seed) , .len = GET_SIZE(entropy_seed) }, + [PLAT_OTP_ID_SECURE_DEBUG_PK] = {.offset = GET_OFFSET(secure_debug_pk) , .len = GET_SIZE(secure_debug_pk) }, +}; + + +enum tfm_plat_err_t tfm_plat_otp_init(void) +{ + /* Do nothing */ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_read(enum tfm_otp_element_id_t id, + size_t out_len, uint8_t *out) +{ + int i; + size_t copy_len; + + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + copy_len = (out_len < otp_map[id].len) ? out_len : otp_map[id].len; + + MXC_FLC_Read(otp_map[id].offset, out, copy_len); + /* + * TF-M project expect default OTP value be 0x00 and + * OTP bits able to be transceive from 0 to 1. + * But MAX32657 OTP default value is 0xff and it transceive from 1 to 0. + * So that after reading OTP, the bits are reversed. + */ + for(i = 0; i < copy_len; i++) { + /* Reverse bits, 1 to 0, 0 to 1 */ + out[i] ^= 0xff; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_write(enum tfm_otp_element_id_t id, + size_t in_len, const uint8_t *in) +{ + enum tfm_plat_err_t ret = TFM_PLAT_ERR_SUCCESS; + unsigned char buf[INFOBLOCK_LINE_SIZE]; + size_t copy_len; + int addr; + int i; + + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + if (in_len > otp_map[id].len) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + MXC_FLC_UnlockInfoBlock(MXC_INFO_MEM_BASE); + + addr = otp_map[id].offset; + while( in_len ) { + copy_len = (in_len < INFOBLOCK_LINE_SIZE) ? in_len: INFOBLOCK_LINE_SIZE; + + /* + * TF-M project expect default OTP value be 0x00 and + * OTP bits able to be transceive from 0 to 1. + * But MAX32657 OTP default value is 0xff and it transceive from 1 to 0. + * So that Before writing bits are reversed. + */ + for (i = 0; i < copy_len; i++) { + /* Reverse bits, 1 to 0, 0 to 1 */ + buf[i] = *in ^ 0xff; + in++; + } + + if (MXC_FLC_Write(addr, copy_len, (uint32_t *)buf) != E_NO_ERROR) { + ret = TFM_PLAT_ERR_SYSTEM_ERR; + break; + } + + in_len -= copy_len; + addr += copy_len; + } + + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); + + return ret; +} + +enum tfm_plat_err_t tfm_plat_otp_get_size(enum tfm_otp_element_id_t id, + size_t *size) +{ + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + *size = otp_map[id].len; + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_secure_provisioning_start(void) +{ + /* Do nothing */ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_secure_provisioning_finish(void) +{ + /* Do nothing */ + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/adi/max32657/platform_otp_ids.h b/platform/ext/target/adi/max32657/platform_otp_ids.h new file mode 100644 index 0000000000..6524ba8de6 --- /dev/null +++ b/platform/ext/target/adi/max32657/platform_otp_ids.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __PLATFORM_OTP_IDS_H__ +#define __PLATFORM_OTP_IDS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum tfm_otp_element_id_t { + PLAT_OTP_ID_HUK = 0, + PLAT_OTP_ID_IAK, + PLAT_OTP_ID_IAK_LEN, + PLAT_OTP_ID_IAK_TYPE, + PLAT_OTP_ID_IAK_ID, + + PLAT_OTP_ID_BOOT_SEED, + PLAT_OTP_ID_LCS, + PLAT_OTP_ID_IMPLEMENTATION_ID, + PLAT_OTP_ID_CERT_REF, + PLAT_OTP_ID_VERIFICATION_SERVICE_URL, + PLAT_OTP_ID_PROFILE_DEFINITION, + + /* BL2 ROTPK must be contiguous */ + PLAT_OTP_ID_BL2_ROTPK_0, + PLAT_OTP_ID_BL2_ROTPK_1, + PLAT_OTP_ID_BL2_ROTPK_2, + PLAT_OTP_ID_BL2_ROTPK_3, + + /* BL2 NV counters must be contiguous */ + PLAT_OTP_ID_NV_COUNTER_BL2_0, + PLAT_OTP_ID_NV_COUNTER_BL2_1, + PLAT_OTP_ID_NV_COUNTER_BL2_2, + PLAT_OTP_ID_NV_COUNTER_BL2_3, + + PLAT_OTP_ID_NV_COUNTER_NS_0, + PLAT_OTP_ID_NV_COUNTER_NS_1, + PLAT_OTP_ID_NV_COUNTER_NS_2, + + PLAT_OTP_ID_ENTROPY_SEED, + PLAT_OTP_ID_SECURE_DEBUG_PK, + + PLAT_OTP_ID_MAX, +}; + +#ifdef __cplusplus +} +#endif +#endif /* __PLATFORM_OTP_IDS_H__ */ From ad2b99707f0f1917bfeafa00c825d28e2dee7e9c Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 27 Nov 2024 11:39:53 -0500 Subject: [PATCH 010/133] [zep fromtree] platform: ext: adi: Allow to NS app read OTP Enable ioctl service to NS app (Zephyr) able to read - USN - LDO_TRIM_BB/RF - DBB_SETTINGS Co-authored-by: Sadik Ozer Change-Id: Ie3f5bf60cba2b68e255dc602b3c5dc55d570c4df Signed-off-by: Hao Zhang (cherry picked from commit 9509e1b1ce916c22bec62118310c5d916f70d262) --- .../ext/target/adi/max32657/CMakeLists.txt | 4 +- .../services/include/tfm_ioctl_core_api.h | 33 ++++++++ .../services/src/tfm_platform_hal_ioctl.c | 77 +++++++++++++++++++ .../services/src/tfm_platform_system.c | 29 +++++++ 4 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h create mode 100644 platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c create mode 100644 platform/ext/target/adi/max32657/services/src/tfm_platform_system.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 624326e32c..6b3f52d9a6 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -171,7 +171,8 @@ target_sources(platform_s ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/TZ/spc_me30.c - $<$:${CMAKE_CURRENT_SOURCE_DIR}/tfm_platform_system.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_hal_ioctl.c> ) target_include_directories(platform_s @@ -179,6 +180,7 @@ target_include_directories(platform_s . ../common partition + services/include ${HAL_ADI_PERIPH_INC_DIR} ${HAL_ADI_CMSIS_INC_DIR} ${PLATFORM_DIR}/.. diff --git a/platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h b/platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h new file mode 100644 index 0000000000..ccd0a036f8 --- /dev/null +++ b/platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#ifndef TFM_IOCTL_CORE_API_H__ +#define TFM_IOCTL_CORE_API_H__ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @brief Supported request types. + */ +enum tfm_platform_ioctl_core_reqest_types_t { + TFM_PLATFORM_ADI_IOCTL_READ_OTP_SERVICE = 0, +}; + +enum tfm_platform_err_t +tfm_platform_adi_hal_otp_service(const psa_invec *in_vec, + const psa_outvec *out_vec); + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_IOCTL_CORE_API_H__ */ diff --git a/platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c b/platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c new file mode 100644 index 0000000000..c0cb1f1a1c --- /dev/null +++ b/platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c @@ -0,0 +1,77 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#include "tfm_platform_api.h" +#include "psa/client.h" +#include "tfm_plat_defs.h" +#include "platform_retarget.h" +#include "flc.h" + +#define IOCTL_OTP_INVEC_LEN 1 + +#define MXC_INFO_MEM_USN_ADDR FLASH_INFO_BASE +#define MXC_INFO_MEM_USN_PKG_CODE_ADDR (FLASH_INFO_BASE + 0x14) +#define MXC_INFO_MEM_LDO_TRIM_BB_ADDR (FLASH_INFO_BASE + 0x19C) +#define MXC_INFO_MEM_LDO_TRIM_RF_ADDR (FLASH_INFO_BASE + 0x1AC) +#define MXC_INFO_MEM_DBB_SETTINGS_ADDR0 (FLASH_INFO_BASE + 0x400) +#define MXC_INFO_MEM_DBB_SETTINGS_ADDR1 (FLASH_INFO_BASE + 0x440) + +enum adi_otp_types_t { + ADI_OTP_ID_USN = 0, + ADI_OTP_ID_BLE_LDO_TRIM_BB, + ADI_OTP_ID_BLE_LDO_TRIM_RF, + ADI_OTP_ID_DBB_SETTINGS0, + ADI_OTP_ID_DBB_SETTINGS1, +}; + + +enum tfm_platform_err_t +tfm_platform_adi_hal_otp_service(const psa_invec *in_vec, + const psa_outvec *out_vec) +{ + if ( (in_vec == NULL) || + (out_vec == NULL) || + (in_vec->len != IOCTL_OTP_INVEC_LEN) ) { + + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + enum adi_otp_types_t arg = *(enum adi_otp_types_t *)in_vec->base; + int src; + int len; + switch (arg) { + case ADI_OTP_ID_USN: + len = 24; + src = MXC_INFO_MEM_USN_ADDR; + break; + case ADI_OTP_ID_BLE_LDO_TRIM_BB: + len = 4; + src = MXC_INFO_MEM_LDO_TRIM_BB_ADDR; + break; + case ADI_OTP_ID_BLE_LDO_TRIM_RF: + len = 4; + src = MXC_INFO_MEM_LDO_TRIM_RF_ADDR; + break; + case ADI_OTP_ID_DBB_SETTINGS0: + len = 64; + src = MXC_INFO_MEM_DBB_SETTINGS_ADDR0; + break; + case ADI_OTP_ID_DBB_SETTINGS1: + len = 64; + src = MXC_INFO_MEM_DBB_SETTINGS_ADDR1; + break; + default: + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + MXC_FLC_UnlockInfoBlock(FLASH_INFO_BASE); + MXC_FLC_Read(src, out_vec->base, len); + MXC_FLC_LockInfoBlock(FLASH_INFO_BASE); + + return TFM_PLATFORM_ERR_SUCCESS; +} diff --git a/platform/ext/target/adi/max32657/services/src/tfm_platform_system.c b/platform/ext/target/adi/max32657/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..8e4283d353 --- /dev/null +++ b/platform/ext/target/adi/max32657/services/src/tfm_platform_system.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + switch (request) { + case TFM_PLATFORM_ADI_IOCTL_READ_OTP_SERVICE: + return tfm_platform_adi_hal_otp_service(in_vec, out_vec); + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } +} From 5d1d464f32b211bafb5a3107aff8b9d02d6bdd57 Mon Sep 17 00:00:00 2001 From: Gowri Ramshankar Date: Fri, 15 Nov 2024 16:37:28 -0500 Subject: [PATCH 011/133] [zep fromtree] platform: ext: adi: Enable crypto configs for MAX32657 Use PSA crpyto for MCUBoot, this commit enable this feture Change-Id: I289f03ac88fea4ca4fbafe8607d4dc5c6e8fe1fb Signed-off-by: Gowri Ramshankar (cherry picked from commit 6afbbd862a9cff2a822e6996af0d02cb5ad82762) --- platform/ext/target/adi/max32657/config.cmake | 3 +++ 1 file changed, 3 insertions(+) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index c32dbcbee4..261608bb8b 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -18,3 +18,6 @@ set(PLATFORM_DEFAULT_OTP OFF CACHE BOOL "Use truste set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") + +set(MCUBOOT_USE_PSA_CRYPTO ON CACHE BOOL "Use PSA Crypto for MCUBOOT") +set(CRYPTO_HW_ACCELERATOR OFF) From 16791d3ba492bed4a8138ecdf8ab9d8363b674b1 Mon Sep 17 00:00:00 2001 From: Jayashree Srinivasan Date: Fri, 1 Nov 2024 12:48:34 -0400 Subject: [PATCH 012/133] [zep fromtree] platform: ext: adi: Enable Attestation Partition Enable the initial attestation partition in the configuration file for the ADI MAX32657 target. Boot measurements are needed for initial attestation. Measurements are part of the shared data between boot and runtime. The static buffer size used by mbedtls for its allocations has been increased - to resolve the attestation testcase failure due to insufficient memory. Note: This configuration could not be changed from zephyr or within the TF-M platform configurations. The size might be an issue upstream. The issue has been notified to the TF-M community. Increase MBEDTLS static buffer size within platform directory The static buffer size used by MBEDTLS is increased from within the platform directory instead of altering the small profile configuration. Co-authored-by: Sadik Ozer Change-Id: I3ed73ca6df52bd8d4655b1ca2e5ee09ba223c6e0 Signed-off-by: Jayashree Srinivasan (cherry picked from commit 9089b67cb2130deec5f9f01676cb76e999859b8d) --- platform/ext/target/adi/max32657/config.cmake | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 261608bb8b..4df9e5f669 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -11,8 +11,9 @@ set(TFM_PARTITION_PLATFORM OFF CACHE BOOL "Enable Pla set(TFM_PARTITION_CRYPTO ON CACHE BOOL "Enable Crypto partition") set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE ON CACHE BOOL "Enable Internal Trusted Storage partition") set(TFM_PARTITION_NS_AGENT_TZ ON CACHE BOOL "Enable Non-Secure Agent in Secure partition") -set(CONFIG_TFM_BOOT_STORE_MEASUREMENTS OFF CACHE BOOL "Store measurement values from all the boot stages. Used for initial attestation token.") -set(CONFIG_TFM_BOOT_STORE_ENCODED_MEASUREMENTS OFF CACHE BOOL "Enable storing of encoded measurements in boot.") +set(CONFIG_TFM_BOOT_STORE_MEASUREMENTS ON CACHE BOOL "Store measurement values from all the boot stages. Used for initial attestation token.") +set(CONFIG_TFM_BOOT_STORE_ENCODED_MEASUREMENTS ON CACHE BOOL "Enable storing of encoded measurements in boot.") +set(TFM_PARTITION_INITIAL_ATTESTATION ON CACHE BOOL "Enable Initial Attestation partition") set(CONFIG_TFM_HALT_ON_CORE_PANIC ON CACHE BOOL "On fatal errors in the secure firmware, halt instead of rebooting.") set(PLATFORM_DEFAULT_OTP OFF CACHE BOOL "Use trusted on-chip flash to implement OTP memory") @@ -21,3 +22,9 @@ set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version set(MCUBOOT_USE_PSA_CRYPTO ON CACHE BOOL "Use PSA Crypto for MCUBOOT") set(CRYPTO_HW_ACCELERATOR OFF) + +if (CONFIG_TFM_PROFILE_SMALL) + # Static Buffer size for MBEDTLS allocations - Has been increased from the default value of small profile + # to ensure that initial attestation testcases in regression build passes + add_compile_definitions(CRYPTO_ENGINE_BUF_SIZE=0x500) +endif() From cc85802b0efc77dfb8ac73736c7d3ff53ccd3f52 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 12 Dec 2024 11:18:47 +0300 Subject: [PATCH 013/133] [zep fromtree] platform: ext: adi: Add UART driver Add UART driver for MAX32657, it is a shim driver that filled with hal_adi call functions Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I651058f11288efdcabbb7a7ae46ea0530dd47ed5 Signed-off-by: Sadik Ozer (cherry picked from commit d0145300bd2850e71184453530ad3d401288ae57) --- .../ext/target/adi/max32657/CMakeLists.txt | 2 + platform/ext/target/adi/max32657/RTE_Device.h | 5 + .../adi/max32657/cmsis_drivers/Driver_USART.c | 326 ++++++++++++++++++ platform/ext/target/adi/max32657/device_cfg.h | 25 ++ 4 files changed, 358 insertions(+) create mode 100644 platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c create mode 100644 platform/ext/target/adi/max32657/device_cfg.h diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 6b3f52d9a6..b37cdb77e3 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -73,6 +73,7 @@ if(BL2) target_sources(platform_bl2 PRIVATE cmsis_drivers/Driver_Flash.c + cmsis_drivers/Driver_USART.c $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c @@ -154,6 +155,7 @@ target_compile_options(platform_s target_sources(platform_s PRIVATE cmsis_drivers/Driver_Flash.c + cmsis_drivers/Driver_USART.c cmsis_drivers/Driver_PPC.c $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> diff --git a/platform/ext/target/adi/max32657/RTE_Device.h b/platform/ext/target/adi/max32657/RTE_Device.h index cc5aedc89a..abb22b3eed 100644 --- a/platform/ext/target/adi/max32657/RTE_Device.h +++ b/platform/ext/target/adi/max32657/RTE_Device.h @@ -20,6 +20,11 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] + // PPC (Peripheral Protection Controller) [Driver_PPC] // Configuration settings for Driver_PPC in component ::Drivers:PPC #define RTE_PPC 1 diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c new file mode 100644 index 0000000000..225ee56adb --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_USART.h" + +#include "mxc_device.h" +#include "uart.h" +#include "RTE_Device.h" +#include "device_cfg.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +/* Driver version */ +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_USART_CAPABILITIES DriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */ + 0 /* Reserved */ +}; + +static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) +{ + return DriverCapabilities; +} + +typedef struct { + mxc_uart_regs_t* dev; /* UART regs */ + uint32_t tx_nbr_bytes; /* Number of bytes transfered */ + uint32_t rx_nbr_bytes; /* Number of bytes recevied */ + ARM_USART_SignalEvent_t cb_event; /* Callback function for events */ +} UARTx_Resources; + +static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev) +{ + /* Initializes generic UART driver */ + MXC_UART_Init(uart_dev->dev, DEFAULT_UART_BAUDRATE, MXC_UART_APB_CLK); + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *src, uint32_t len) +{ + if (src == NULL) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + int retVal; + uint8_t *data = (uint8_t *)src; + uint32_t i = 0; + + while (i < len) { + retVal = MXC_UART_WriteCharacter(uart_dev->dev, data[i]); + if (retVal == E_NO_ERROR) { + i++; + } + } + uart_dev->tx_nbr_bytes = i; + + if (uart_dev->cb_event) { + uart_dev->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev, void *dst, uint32_t len) +{ + if (dst == NULL) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + int retVal; + uint8_t *data = (uint8_t *)dst; + uint32_t i = 0; + + while (i < len) { + retVal = MXC_UART_ReadCharacter(uart_dev->dev); + if (retVal >= 0) { + data[i] = retVal; + i++; + } + } + uart_dev->rx_nbr_bytes = i; + + if (uart_dev->cb_event) { + uart_dev->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + + return ARM_DRIVER_OK; +} + +static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev) +{ + return uart_dev->tx_nbr_bytes; +} + +static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev) +{ + return uart_dev->rx_nbr_bytes; +} + +static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control, + uint32_t arg) +{ + if ((control & ARM_USART_CONTROL_Msk) != ARM_USART_MODE_ASYNCHRONOUS) { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + if(MXC_UART_SetFrequency(uart_dev->dev, arg, MXC_UART_APB_CLK) < 0) { + return ARM_USART_ERROR_BAUDRATE; + } + + /* UART Data bits */ + switch (control & ARM_USART_DATA_BITS_Msk) { + case ARM_USART_DATA_BITS_5: + MXC_UART_SetDataSize(uart_dev->dev, 5); + break; + case ARM_USART_DATA_BITS_6: + MXC_UART_SetDataSize(uart_dev->dev, 6); + break; + case ARM_USART_DATA_BITS_7: + MXC_UART_SetDataSize(uart_dev->dev, 7); + break; + case ARM_USART_DATA_BITS_8: + MXC_UART_SetDataSize(uart_dev->dev, 8); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* UART Parity */ + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: + MXC_UART_SetParity(uart_dev->dev, MXC_UART_PARITY_DISABLE); + break; + case ARM_USART_PARITY_EVEN: + MXC_UART_SetParity(uart_dev->dev, MXC_UART_PARITY_EVEN_1); + break; + case ARM_USART_PARITY_ODD: + MXC_UART_SetParity(uart_dev->dev, MXC_UART_PARITY_ODD_1); + break; + } + + /* USART Stop bits */ + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: + MXC_UART_SetStopBits(uart_dev->dev, MXC_UART_STOP_1); + break; + case ARM_USART_STOP_BITS_2: + MXC_UART_SetStopBits(uart_dev->dev, MXC_UART_STOP_2); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev, + ARM_POWER_STATE state) +{ + ARG_UNUSED(uart_dev); + + switch (state) { + case ARM_POWER_OFF: + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + default: + return ARM_DRIVER_ERROR_PARAMETER; + } +} + +#if (RTE_USART0) + +/* USART0 Driver wrapper functions */ +static UARTx_Resources USART0_DEV = { + .dev = MXC_UART, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART0_DEV); +} + +static int32_t ARM_USART0_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART0_DEV, state); +} + +static int32_t ARM_USART0_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART0_DEV, data, num); +} + +static int32_t ARM_USART0_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART0_DEV, data, num); +} + +static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART0_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART0_DEV); +} + +static uint32_t ARM_USART0_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART0_DEV); +} + +static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART0_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART0_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART0; +ARM_DRIVER_USART Driver_USART0 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART0_Initialize, + ARM_USART0_Uninitialize, + ARM_USART0_PowerControl, + ARM_USART0_Send, + ARM_USART0_Receive, + ARM_USART0_Transfer, + ARM_USART0_GetTxCount, + ARM_USART0_GetRxCount, + ARM_USART0_Control, + ARM_USART0_GetStatus, + ARM_USART0_SetModemControl, + ARM_USART0_GetModemStatus +}; +#endif /* RTE_USART0 */ diff --git a/platform/ext/target/adi/max32657/device_cfg.h b/platform/ext/target/adi/max32657/device_cfg.h new file mode 100644 index 0000000000..b1f77deff7 --- /dev/null +++ b/platform/ext/target/adi/max32657/device_cfg.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/* ARM UART */ +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ From 25c13307b6a44b3c0a1ca2fdc9b2c15700ad3ed1 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Mon, 16 Dec 2024 16:51:33 -0500 Subject: [PATCH 014/133] [zep fromtree] platform: ext: adi: Add MPC driver Add MPC driver for MAX32657, it is referred to arm mpc sie200 driver Co-authored-by: Jayashree Srinivasan Co-authored-by: Tanmaya Mishra Co-authored-by: Sadik Ozer Change-Id: I5834c0414bbcc1eff5c7d249b2d412fc3f8c85bc Signed-off-by: Hao Zhang (cherry picked from commit eb55261f3ff173714a8f77f3d8181221765113c0) --- .../ext/target/adi/max32657/CMakeLists.txt | 3 + platform/ext/target/adi/max32657/RTE_Device.h | 30 + .../adi/max32657/cmsis_drivers/Driver_MPC.c | 944 ++++++++++++++++++ .../adi/max32657/device/inc/mpc_sie200_drv.h | 277 +++++ .../adi/max32657/device/src/mpc_sie200_drv.c | 657 ++++++++++++ 5 files changed, 1911 insertions(+) create mode 100644 platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c create mode 100644 platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h create mode 100644 platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index b37cdb77e3..7a589f231d 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -157,6 +157,8 @@ target_sources(platform_s cmsis_drivers/Driver_Flash.c cmsis_drivers/Driver_USART.c cmsis_drivers/Driver_PPC.c + cmsis_drivers/Driver_MPC.c + device/src/mpc_sie200_drv.c $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c @@ -182,6 +184,7 @@ target_include_directories(platform_s . ../common partition + device/inc services/include ${HAL_ADI_PERIPH_INC_DIR} ${HAL_ADI_CMSIS_INC_DIR} diff --git a/platform/ext/target/adi/max32657/RTE_Device.h b/platform/ext/target/adi/max32657/RTE_Device.h index abb22b3eed..cc84193fa3 100644 --- a/platform/ext/target/adi/max32657/RTE_Device.h +++ b/platform/ext/target/adi/max32657/RTE_Device.h @@ -35,4 +35,34 @@ #define RTE_FLASH0 1 // FLASH (Flash Memory) [Driver_FLASH0] +// MPC (Memory Protection Controller) [Driver_SRAM0_MPC] +// Configuration settings for Driver_SRAM0_MPC in component ::Drivers:MPC +#define RTE_SRAM0_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM0_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM1_MPC] +// Configuration settings for Driver_SRAM1_MPC in component ::Drivers:MPC +#define RTE_SRAM1_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM1_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM2_MPC] +// Configuration settings for Driver_SRAM2_MPC in component ::Drivers:MPC +#define RTE_SRAM2_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM2_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM3_MPC] +// Configuration settings for Driver_SRAM3_MPC in component ::Drivers:MPC +#define RTE_SRAM3_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM3_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM4_MPC] +// Configuration settings for Driver_SRAM4_MPC in component ::Drivers:MPC +#define RTE_SRAM4_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM4_MPC] + +// MPC (Memory Protection Controller) [Driver_FLASH_MPC] +// Configuration settings for Driver_FLASH_MPC in component ::Drivers:MPC +#define RTE_FLASH_MPC 1 +// MPC (Memory Protection Controller) [Driver_FLASH_MPC] + #endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c new file mode 100644 index 0000000000..2f357fb688 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c @@ -0,0 +1,944 @@ +/* + * Copyright (c) 2016-2017 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Driver_MPC.h" + +#include "mxc_device.h" +#include "platform_retarget.h" +#include "RTE_Device.h" +#include "mpc_sie200_drv.h" + +/* ARM MPC SSE 200 driver structures */ +#ifdef RTE_SRAM0_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM0_DEV_CFG_S = { + .base = MPC_SRAM0_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM0_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM0_DEV_S = { + &(MPC_SRAM0_DEV_CFG_S), + &(MPC_SRAM0_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM1_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM1_DEV_CFG_S = { + .base = MPC_SRAM1_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM1_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM1_DEV_S = { + &(MPC_SRAM1_DEV_CFG_S), + &(MPC_SRAM1_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM2_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM2_DEV_CFG_S = { + .base = MPC_SRAM2_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM2_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM2_DEV_S = { + &(MPC_SRAM2_DEV_CFG_S), + &(MPC_SRAM2_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM3_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM3_DEV_CFG_S = { + .base = MPC_SRAM3_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM3_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM3_DEV_S = { + &(MPC_SRAM3_DEV_CFG_S), + &(MPC_SRAM3_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM4_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM4_DEV_CFG_S = { + .base = MPC_SRAM4_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM4_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM4_DEV_S = { + &(MPC_SRAM4_DEV_CFG_S), + &(MPC_SRAM4_DEV_DATA_S)}; +#endif + +#ifdef RTE_FLASH_MPC +static const struct mpc_sie200_dev_cfg_t MPC_FLASH_DEV_CFG_S = { + .base = MPC_FLASH_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_FLASH_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_FLASH_DEV_S = { + &(MPC_FLASH_DEV_CFG_S), + &(MPC_FLASH_DEV_DATA_S)}; +#endif + +/* driver version */ +#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_MPC_API_VERSION, + ARM_MPC_DRV_VERSION}; + +static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void) +{ + return DriverVersion; +} + +/* + * \brief Translates error codes from native API to CMSIS API. + * + * \param[in] err Error code to translate (\ref mpc_sie200_error_t). + * + * \return Returns CMSIS error code. + */ +static int32_t error_trans(enum mpc_sie200_error_t err) +{ + switch (err) + { + case MPC_SIE200_ERR_NONE: + return ARM_DRIVER_OK; + case MPC_SIE200_INVALID_ARG: + return ARM_DRIVER_ERROR_PARAMETER; + case MPC_SIE200_NOT_INIT: + return ARM_MPC_ERR_NOT_INIT; + case MPC_SIE200_ERR_NOT_IN_RANGE: + return ARM_MPC_ERR_NOT_IN_RANGE; + case MPC_SIE200_ERR_NOT_ALIGNED: + return ARM_MPC_ERR_NOT_ALIGNED; + case MPC_SIE200_ERR_INVALID_RANGE: + return ARM_MPC_ERR_INVALID_RANGE; + case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE: + return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; + /* default: The default is not defined intentionally to force the + * compiler to check that all the enumeration values are + * covered in the switch. + */ + } +} + +#if (RTE_SRAM0_MPC) +/* Ranges controlled by this SRAM0_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM0_RANGE_S = { + .base = MPC_SRAM0_RANGE_BASE_S, + .limit = MPC_SRAM0_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM0_RANGE_NS = { + .base = MPC_SRAM0_RANGE_BASE_NS, + .limit = MPC_SRAM0_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM0_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM0_RANGE_LIST[MPC_SRAM0_RANGE_LIST_LEN] = + {&MPC_SRAM0_RANGE_S, &MPC_SRAM0_RANGE_NS}; + +/* SRAM0_MPC Driver wrapper functions */ +static int32_t SRAM0_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM0_DEV_S, + MPC_SRAM0_RANGE_LIST, + MPC_SRAM0_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM0_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM0_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM0_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM0_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM0_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM0_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM0_DEV_S); + + return error_trans(ret); +} + +static void SRAM0_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM0_DEV_S); +} + +static void SRAM0_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM0_DEV_S); +} + +static uint32_t SRAM0_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM0_DEV_S); +} + +static int32_t SRAM0_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM0_DEV_S); +} + +/* SRAM0_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM0_MPC; +ARM_DRIVER_MPC Driver_SRAM0_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM0_MPC_Initialize, + .Uninitialize = SRAM0_MPC_Uninitialize, + .GetBlockSize = SRAM0_MPC_GetBlockSize, + .GetCtrlConfig = SRAM0_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM0_MPC_SetCtrlConfig, + .ConfigRegion = SRAM0_MPC_ConfigRegion, + .GetRegionConfig = SRAM0_MPC_GetRegionConfig, + .EnableInterrupt = SRAM0_MPC_EnableInterrupt, + .DisableInterrupt = SRAM0_MPC_DisableInterrupt, + .ClearInterrupt = SRAM0_MPC_ClearInterrupt, + .InterruptState = SRAM0_MPC_InterruptState, + .LockDown = SRAM0_MPC_LockDown, +}; +#endif /* RTE_SRAM0_MPC */ + +#if (RTE_SRAM1_MPC) +/* Ranges controlled by this SRAM1_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM1_RANGE_S = { + .base = MPC_SRAM1_RANGE_BASE_S, + .limit = MPC_SRAM1_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM1_RANGE_NS = { + .base = MPC_SRAM1_RANGE_BASE_NS, + .limit = MPC_SRAM1_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM1_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM1_RANGE_LIST[MPC_SRAM1_RANGE_LIST_LEN] = + {&MPC_SRAM1_RANGE_S, &MPC_SRAM1_RANGE_NS}; + +/* SRAM1_MPC Driver wrapper functions */ +static int32_t SRAM1_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM1_DEV_S, + MPC_SRAM1_RANGE_LIST, + MPC_SRAM1_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM1_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM1_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM1_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM1_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM1_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM1_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM1_DEV_S); + + return error_trans(ret); +} + +static void SRAM1_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM1_DEV_S); +} + +static void SRAM1_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM1_DEV_S); +} + +static uint32_t SRAM1_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM1_DEV_S); +} + +static int32_t SRAM1_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM1_DEV_S); +} + +/* SRAM1_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM1_MPC; +ARM_DRIVER_MPC Driver_SRAM1_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM1_MPC_Initialize, + .Uninitialize = SRAM1_MPC_Uninitialize, + .GetBlockSize = SRAM1_MPC_GetBlockSize, + .GetCtrlConfig = SRAM1_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM1_MPC_SetCtrlConfig, + .ConfigRegion = SRAM1_MPC_ConfigRegion, + .GetRegionConfig = SRAM1_MPC_GetRegionConfig, + .EnableInterrupt = SRAM1_MPC_EnableInterrupt, + .DisableInterrupt = SRAM1_MPC_DisableInterrupt, + .ClearInterrupt = SRAM1_MPC_ClearInterrupt, + .InterruptState = SRAM1_MPC_InterruptState, + .LockDown = SRAM1_MPC_LockDown, +}; +#endif /* RTE_SRAM1_MPC */ + +#if (RTE_SRAM2_MPC) +/* Ranges controlled by this SRAM2_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM2_RANGE_S = { + .base = MPC_SRAM2_RANGE_BASE_S, + .limit = MPC_SRAM2_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM2_RANGE_NS = { + .base = MPC_SRAM2_RANGE_BASE_NS, + .limit = MPC_SRAM2_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM2_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM2_RANGE_LIST[MPC_SRAM2_RANGE_LIST_LEN] = + {&MPC_SRAM2_RANGE_S, &MPC_SRAM2_RANGE_NS}; + +/* SRAM2_MPC Driver wrapper functions */ +static int32_t SRAM2_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM2_DEV_S, + MPC_SRAM2_RANGE_LIST, + MPC_SRAM2_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM2_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM2_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM2_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM2_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM2_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM2_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM2_DEV_S); + + return error_trans(ret); +} + +static void SRAM2_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM2_DEV_S); +} + +static void SRAM2_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM2_DEV_S); +} + +static uint32_t SRAM2_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM2_DEV_S); +} + +static int32_t SRAM2_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM2_DEV_S); +} + +/* SRAM2_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM2_MPC; +ARM_DRIVER_MPC Driver_SRAM2_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM2_MPC_Initialize, + .Uninitialize = SRAM2_MPC_Uninitialize, + .GetBlockSize = SRAM2_MPC_GetBlockSize, + .GetCtrlConfig = SRAM2_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM2_MPC_SetCtrlConfig, + .ConfigRegion = SRAM2_MPC_ConfigRegion, + .GetRegionConfig = SRAM2_MPC_GetRegionConfig, + .EnableInterrupt = SRAM2_MPC_EnableInterrupt, + .DisableInterrupt = SRAM2_MPC_DisableInterrupt, + .ClearInterrupt = SRAM2_MPC_ClearInterrupt, + .InterruptState = SRAM2_MPC_InterruptState, + .LockDown = SRAM2_MPC_LockDown, +}; +#endif /* RTE_SRAM2_MPC */ + +#if (RTE_SRAM3_MPC) +/* Ranges controlled by this SRAM3_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM3_RANGE_S = { + .base = MPC_SRAM3_RANGE_BASE_S, + .limit = MPC_SRAM3_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM3_RANGE_NS = { + .base = MPC_SRAM3_RANGE_BASE_NS, + .limit = MPC_SRAM3_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM3_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM3_RANGE_LIST[MPC_SRAM3_RANGE_LIST_LEN] = + {&MPC_SRAM3_RANGE_S, &MPC_SRAM3_RANGE_NS}; + +/* SRAM3_MPC Driver wrapper functions */ +static int32_t SRAM3_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM3_DEV_S, + MPC_SRAM3_RANGE_LIST, + MPC_SRAM3_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM3_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM3_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM3_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM3_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM3_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM3_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM3_DEV_S); + + return error_trans(ret); +} + +static void SRAM3_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM3_DEV_S); +} + +static void SRAM3_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM3_DEV_S); +} + +static uint32_t SRAM3_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM3_DEV_S); +} + +static int32_t SRAM3_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM3_DEV_S); +} + +/* SRAM3_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM3_MPC; +ARM_DRIVER_MPC Driver_SRAM3_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM3_MPC_Initialize, + .Uninitialize = SRAM3_MPC_Uninitialize, + .GetBlockSize = SRAM3_MPC_GetBlockSize, + .GetCtrlConfig = SRAM3_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM3_MPC_SetCtrlConfig, + .ConfigRegion = SRAM3_MPC_ConfigRegion, + .GetRegionConfig = SRAM3_MPC_GetRegionConfig, + .EnableInterrupt = SRAM3_MPC_EnableInterrupt, + .DisableInterrupt = SRAM3_MPC_DisableInterrupt, + .ClearInterrupt = SRAM3_MPC_ClearInterrupt, + .InterruptState = SRAM3_MPC_InterruptState, + .LockDown = SRAM3_MPC_LockDown, +}; +#endif /* RTE_SRAM3_MPC */ + +#if (RTE_SRAM4_MPC) +/* Ranges controlled by this SRAM4_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM4_RANGE_S = { + .base = MPC_SRAM4_RANGE_BASE_S, + .limit = MPC_SRAM4_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM4_RANGE_NS = { + .base = MPC_SRAM4_RANGE_BASE_NS, + .limit = MPC_SRAM4_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM4_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM4_RANGE_LIST[MPC_SRAM4_RANGE_LIST_LEN] = + {&MPC_SRAM4_RANGE_S, &MPC_SRAM4_RANGE_NS}; + +/* SRAM4_MPC Driver wrapper functions */ +static int32_t SRAM4_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM4_DEV_S, + MPC_SRAM4_RANGE_LIST, + MPC_SRAM4_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM4_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM4_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM4_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM4_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM4_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM4_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM4_DEV_S); + + return error_trans(ret); +} + +static void SRAM4_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM4_DEV_S); +} + +static void SRAM4_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM4_DEV_S); +} + +static uint32_t SRAM4_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM4_DEV_S); +} + +static int32_t SRAM4_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM4_DEV_S); +} + +/* SRAM4_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM4_MPC; +ARM_DRIVER_MPC Driver_SRAM4_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM4_MPC_Initialize, + .Uninitialize = SRAM4_MPC_Uninitialize, + .GetBlockSize = SRAM4_MPC_GetBlockSize, + .GetCtrlConfig = SRAM4_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM4_MPC_SetCtrlConfig, + .ConfigRegion = SRAM4_MPC_ConfigRegion, + .GetRegionConfig = SRAM4_MPC_GetRegionConfig, + .EnableInterrupt = SRAM4_MPC_EnableInterrupt, + .DisableInterrupt = SRAM4_MPC_DisableInterrupt, + .ClearInterrupt = SRAM4_MPC_ClearInterrupt, + .InterruptState = SRAM4_MPC_InterruptState, + .LockDown = SRAM4_MPC_LockDown, +}; +#endif /* RTE_SRAM4_MPC */ + +#if (RTE_FLASH_MPC) +/* Ranges controlled by this FLASH_MPC */ +static struct mpc_sie200_memory_range_t MPC_FLASH_RANGE_S = { + .base = FLASH0_BASE_S, + .limit = FLASH0_BASE_S + FLASH0_SIZE - 1, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_FLASH_RANGE_NS = { + .base = FLASH0_BASE_NS, + .limit = FLASH0_BASE_NS + FLASH0_SIZE - 1, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_FLASH_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_FLASH_RANGE_LIST[MPC_FLASH_RANGE_LIST_LEN] = + {&MPC_FLASH_RANGE_S, &MPC_FLASH_RANGE_NS}; + +/* FLASH_MPC Driver wrapper functions */ +static int32_t FLASH_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_FLASH_DEV_S, + MPC_FLASH_RANGE_LIST, + MPC_FLASH_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t FLASH_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_FLASH_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_FLASH_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_FLASH_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_FLASH_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_FLASH_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_FLASH_DEV_S); + + return error_trans(ret); +} + +static void FLASH_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_FLASH_DEV_S); +} + +static void FLASH_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_FLASH_DEV_S); +} + +static uint32_t FLASH_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_FLASH_DEV_S); +} + +static int32_t FLASH_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_FLASH_DEV_S); +} + +/* FLASH_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_FLASH_MPC; +ARM_DRIVER_MPC Driver_FLASH_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = FLASH_MPC_Initialize, + .Uninitialize = FLASH_MPC_Uninitialize, + .GetBlockSize = FLASH_MPC_GetBlockSize, + .GetCtrlConfig = FLASH_MPC_GetCtrlConfig, + .SetCtrlConfig = FLASH_MPC_SetCtrlConfig, + .ConfigRegion = FLASH_MPC_ConfigRegion, + .GetRegionConfig = FLASH_MPC_GetRegionConfig, + .EnableInterrupt = FLASH_MPC_EnableInterrupt, + .DisableInterrupt = FLASH_MPC_DisableInterrupt, + .ClearInterrupt = FLASH_MPC_ClearInterrupt, + .InterruptState = FLASH_MPC_InterruptState, + .LockDown = FLASH_MPC_LockDown, +}; +#endif /* RTE_FLASH_MPC */ diff --git a/platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h b/platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h new file mode 100644 index 0000000000..9f9bd95875 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2016-2017 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file mpc_sie200_drv.h + * \brief Generic driver for ARM SIE 200 Memory Protection + * Controllers (MPC). + */ + +#ifndef __MPC_SIE_200_DRV_H__ +#define __MPC_SIE_200_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error code returned by the driver functions */ +enum mpc_sie200_error_t { + MPC_SIE200_ERR_NONE, /*!< No error */ + MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */ + MPC_SIE200_NOT_INIT, /*!< MPC not initialized */ + MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range + * controlled by the MPC */ + MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size + * of this MPC */ + MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure + * is invalid. This could be because: + * - The base and limit swapped + * - The base and limit addresses + * are in different ranges */ + MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be + * accessed with the wanted + * security attributes */ +}; + +/* Security attribute used in various place of the API */ +enum mpc_sie200_sec_attr_t { + MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */ + MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */ + /*!< Used when getting the configuration of a memory range and some blocks + * are secure whereas some other are non secure */ + MPC_SIE200_SEC_ATTR_MIXED, +}; + +/* What can happen when trying to do an illegal memory access */ +enum mpc_sie200_sec_resp_t { + MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */ + MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */ +}; + +/* Description of a memory range controlled by the MPC */ +struct mpc_sie200_memory_range_t { + const uint32_t base; /*!< Base address (included in the range) */ + const uint32_t limit; /*!< Limit address (excluded in the range) */ + const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute + needed to be matched when + accessing this range. + For example, the non-secure + alias of a memory region can not + be accessed using secure access, + and configuring the MPC to + secure using that range will not + be permitted by the driver. */ +}; + +/* ARM MPC SIE 200 device configuration structure */ +struct mpc_sie200_dev_cfg_t { + const uint32_t base; /*!< MPC base address */ +}; + +/* ARM MPC SIE 200 device data structure */ +struct mpc_sie200_dev_data_t { + const struct mpc_sie200_memory_range_t** range_list; /*!< Array of pointers + to memory ranges + controlled by + the MPC */ + uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */ + uint8_t state; /*!< Indicates if the MPC driver + is initialized and enabled */ + uint16_t reserved; /*!< 32 bits alignment */ +}; + +/* ARM MPC SIE 200 device structure */ +struct mpc_sie200_dev_t { + const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */ + struct mpc_sie200_dev_data_t* const data; /*!< MPC data */ +}; + +/** + * \brief Initializes a MPC device. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] range_list List of memory ranges controller by the MPC + * (\ref mpc_sie200_memory_range_t). This list can not + * freed after the initializations. + * \param[in] nbr_of_ranges Number of memory ranges + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev, + const struct mpc_sie200_memory_range_t** range_list, + uint8_t nbr_of_ranges); + +/** + * \brief Gets MPC block size. All regions must be aligned on this block + * size (base address and limit+1 address). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] blk_size MPC block size + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev, + uint32_t* blk_size); + +/** + * \brief Configures a memory region (base and limit included). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] base Base address of the region to poll. This bound is + * included. It does not need to be aligned in any way. + * + * \param[in] limit Limit address of the region to poll. This bound is + * included. (limit+1) does not need to be aligned + * in any way. + * \param[in] attr Security attribute of the region. If the region has mixed + * secure/non-secure, a special value is returned + * (\ref mpc_sie200_sec_attr_t). + * + * In case base and limit+1 addresses are not aligned on + * the block size, the enclosing region with base and + * limit+1 aligned on block size will be queried. + * In case of early termination of the function (error), the + * security attribute will be set to MPC_SIE200_ATTR_MIXED. + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev, + const uint32_t base, + const uint32_t limit, + enum mpc_sie200_sec_attr_t attr); + +/** + * \brief Gets a memory region configuration(base and limit included). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] base Base address of the region to get the configuration. + * \param[in] limit Limit address of the region to get the configuration. + * \param[out] attr Security attribute of the region + * \ref mpc_sie200_sec_attr_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_region_config( + struct mpc_sie200_dev_t* dev, + uint32_t base, + uint32_t limit, + enum mpc_sie200_sec_attr_t* attr); + +/** + * \brief Gets the MPC control value. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] ctrl_val Current MPC control value. + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t* ctrl_val); + +/** + * \brief Sets the MPC control value. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] mpc_ctrl New MPC control value + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t mpc_ctrl); + +/** + * \brief Gets the configured secure response. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t). + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev, + enum mpc_sie200_sec_resp_t* sec_rep); + +/** + * \brief Enables MPC interrupt. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev); + +/** + * \brief Disables MPC interrupt + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev); + +/** + * \brief Clears MPC interrupt. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev); + +/** + * \brief Returns the MPC interrupt state. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns 1 if the interrupt is active, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev); + +/** + * \brief Locks down the MPC configuration. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev); + +#ifdef __cplusplus +} +#endif +#endif /* __MPC_SIE_200_DRV_H__ */ diff --git a/platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c b/platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c new file mode 100644 index 0000000000..31c5b84a93 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c @@ -0,0 +1,657 @@ +/* + * Copyright (c) 2016-2017 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mpc_sie200_drv.h" + +#include + +#include "mxc_device.h" + +#define MPC_SIE200_BLK_CFG_OFFSET 5U + +#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a + * bus error */ +#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */ +#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */ + +/* ARM MPC interrupt */ +#define MPC_SIE200_INT_EN 1UL +#define MPC_SIE200_INT_STAT 1UL + +/* ARM MPC state definitions */ +#define MPC_SIE200_INITIALIZED (1 << 0) + +/* Error code returned by the internal driver functions */ +enum mpc_sie200_intern_error_t{ + MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE, + MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE, + MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED, + MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE, + MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE = + MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, + /* Calculated block index + is higher than the maximum allowed by the MPC. It should never + happen unless the controlled ranges of the MPC are misconfigured + in the driver or if the IP has not enough LUTs to cover the + range, due to wrong reported block size for example. + */ + MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1, + +}; + +/* ARM MPC memory mapped register access structure */ +struct mpc_sie200_reg_map_t { + volatile uint32_t ctrl; /* (R/W) MPC Control */ + volatile uint32_t reserved[3];/* Reserved */ + volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */ + volatile uint32_t blk_cfg; /* (R/ ) Block configuration */ + volatile uint32_t blk_idx; /* (R/W) Index value for accessing block + * based look up table */ + volatile uint32_t blk_lutn; /* (R/W) Block based gating + * Look Up Table (LUT) */ + volatile uint32_t int_stat; /* (R/ ) Interrupt state */ + volatile uint32_t int_clear; /* ( /W) Interrupt clear */ + volatile uint32_t int_en; /* (R/W) Interrupt enable */ + volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */ + volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */ + volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */ + volatile uint32_t reserved2[997]; /* Reserved */ + volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ + volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */ + volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */ + volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */ + volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ + volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ + volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ + volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ + volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ + volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ + volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ + volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ +}; + +/* + * Checks if the address is controlled by the MPC and returns + * the range index in which it is contained. + * + * \param[in] dev MPC device to initalize \ref mpc_sie200_dev_t + * \param[in] addr Address to check if it is controlled by MPC. + * \param[out] addr_range Range index in which it is contained. + * + * \return True if the base is controller by the range list, false otherwise. + */ +static uint32_t is_ctrl_by_range_list(struct mpc_sie200_dev_t* dev, uint32_t addr, + const struct mpc_sie200_memory_range_t** addr_range) +{ + uint32_t i; + const struct mpc_sie200_memory_range_t* range; + + for(i = 0; i < dev->data->nbr_of_ranges; i++) { + range = dev->data->range_list[i]; + if(addr >= range->base && addr <= range->limit) { + *addr_range = range; + return 1; + } + } + return 0; +} + +/* + * Gets the masks selecting the bits in the LUT of the MPC corresponding + * to the base address (included) up to the limit address (included) + * + * \param[in] mpc_dev The MPC device. + * \param[in] base Address in a range controlled by this MPC + * (included), aligned on block size. + * \param[in] limit Address in a range controlled by this MPC + * (included), aligned on block size. + * \param[out] range Memory range in which the base address and + * limit are. + * \param[out] first_word_idx Index of the first touched word in the LUT. + * \param[out] nr_words Number of words used in the LUT. If 1, only + * first_word_mask is valid and limit_word_mask + * must not be used. + * \param[out] first_word_mask First word mask in the LUT will be stored here. + * \param[out] limit_word_mask Limit word mask in the LUT will be stored here. + * + * \return Returns error code as specified in \ref mpc_sie200_intern_error_t + */ +static enum mpc_sie200_intern_error_t get_lut_masks( + struct mpc_sie200_dev_t* dev, + const uint32_t base, const uint32_t limit, + const struct mpc_sie200_memory_range_t** range, + uint32_t *first_word_idx, + uint32_t *nr_words, + uint32_t *first_word_mask, + uint32_t *limit_word_mask) +{ + const struct mpc_sie200_memory_range_t* base_range; + uint32_t block_size; + uint32_t base_block_idx; + uint32_t base_word_idx; + uint32_t blk_max; + const struct mpc_sie200_memory_range_t* limit_range; + uint32_t limit_block_idx; + uint32_t limit_word_idx; + uint32_t mask; + uint32_t norm_base; + uint32_t norm_limit; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + /* + * Check that the addresses are within the controlled regions + * of this MPC + */ + if(!is_ctrl_by_range_list(dev, base, &base_range) || + !is_ctrl_by_range_list(dev, limit, &limit_range)) { + return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE; + } + + /* Base and limit should be part of the same range */ + if(base_range != limit_range) { + return MPC_SIE200_INTERN_ERR_INVALID_RANGE; + } + *range = base_range; + + block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + /* Base and limit+1 addresses must be aligned on the MPC block size */ + if(base % block_size || (limit+1) % block_size) { + return MPC_SIE200_INTERN_ERR_NOT_ALIGNED; + } + + /* + * Get a normalized address that is an offset from the beginning + * of the lowest range controlled by the MPC + */ + norm_base = (base - base_range->base); + norm_limit = (limit - base_range->base); + + /* + * Calculate block index and to which 32 bits word it belongs + */ + limit_block_idx = norm_limit/block_size; + limit_word_idx = limit_block_idx/32; + + base_block_idx = norm_base/block_size; + base_word_idx = base_block_idx/32; + + if(base_block_idx > limit_block_idx) { + return MPC_SIE200_INTERN_ERR_INVALID_RANGE; + } + + /* Transmit the information to the caller */ + *nr_words = limit_word_idx - base_word_idx + 1; + *first_word_idx = base_word_idx; + + /* Limit to the highest block that can be configured */ + blk_max = p_mpc->blk_max; + + if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) { + return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH; + } + + /* + * Create the mask for the first word to only select the limit N bits + */ + *first_word_mask = ~((1 << (base_block_idx % 32)) - 1); + + /* + * Create the mask for the limit word to select only the first M bits. + */ + *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1; + /* + * If limit_word_mask is 0, it means that the limit touched block index is + * the limit in its word, so the limit word mask has all its bits selected + */ + if(*limit_word_mask == 0) { + *limit_word_mask = 0xFFFFFFFF; + } + + /* + * If the blocks to configure are all packed in one word, only + * touch this word. + * Code using the computed masks should test if this mask + * is non-zero, and if so, only use this one instead of the limit_word_mask + * and first_word_mask. + * As the only bits that are the same in both masks are the 1 that we want + * to select, just use XOR to extract them. + */ + if(base_word_idx == limit_word_idx) { + mask = ~(*first_word_mask ^ *limit_word_mask); + *first_word_mask = mask; + *limit_word_mask = mask; + } + + return MPC_SIE200_INTERN_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev, + const struct mpc_sie200_memory_range_t** range_list, + uint8_t nbr_of_ranges) +{ + if((range_list == NULL) || (nbr_of_ranges == 0)) { + return MPC_SIE200_INVALID_ARG; + } + + dev->data->range_list = range_list; + dev->data->nbr_of_ranges = nbr_of_ranges; + dev->data->state = MPC_SIE200_INITIALIZED; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev, + uint32_t* blk_size) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(blk_size == 0) { + return MPC_SIE200_INVALID_ARG; + } + + /* Calculate the block size in byte according to the manual */ + *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev, + const uint32_t base, + const uint32_t limit, + enum mpc_sie200_sec_attr_t attr) +{ + enum mpc_sie200_intern_error_t error; + uint32_t first_word_idx; + uint32_t first_word_mask; + uint32_t i; + uint32_t limit_word_mask; + uint32_t limit_word_idx; + uint32_t nr_words; + const struct mpc_sie200_memory_range_t* range; + uint32_t word_value; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + /* Sanity check to make sure the given range is within this MPCs range */ + if ((dev->data->range_list[attr]->base > base) || + (dev->data->range_list[attr]->limit < limit) ) { + return MPC_SIE200_ERR_NOT_IN_RANGE; + } + + /* Get the bitmasks used to select the bits in the LUT */ + error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, + &first_word_mask, &limit_word_mask); + + limit_word_idx = first_word_idx + nr_words - 1; + + if(error != MPC_SIE200_INTERN_ERR_NONE) { + /* Map internal error code lower than 0 to a generic errpr */ + if(error < 0) { + return MPC_SIE200_ERR_INVALID_RANGE; + } + return (enum mpc_sie200_error_t)error; + } + + /* + * The memory range should allow accesses in with the wanted security + * attribute if it requires special attribute for successfull accesses + */ + if(range->attr != attr) { + return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; + } + + /* + * Starts changing actual configuration so issue DMB to ensure every + * transaction has completed by now + */ + __DMB(); + + /* Set the block index to the first word that will be updated */ + p_mpc->blk_idx = first_word_idx; + + /* If only one word needs to be touched in the LUT */ + if(nr_words == 1) { + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= first_word_mask; + } else { + word_value &= ~first_word_mask; + } + + /* + * Set the index again because full word read or write could have + * incremented it + */ + p_mpc->blk_idx = first_word_idx; + p_mpc->blk_lutn = word_value; + + /* Commit the configuration change */ + __DSB(); + __ISB(); + + return MPC_SIE200_ERR_NONE; + } + + /* First word */ + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= first_word_mask; + } else { + word_value &= ~first_word_mask; + } + /* + * Set the index again because full word read or write could have + * incremented it + */ + p_mpc->blk_idx = first_word_idx; + /* Partially configure the first word */ + p_mpc->blk_lutn = word_value; + + /* Fully configure the intermediate words if there are any */ + for(i=first_word_idx+1; iblk_idx = i; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + p_mpc->blk_lutn = 0xFFFFFFFF; + } else { + p_mpc->blk_lutn = 0x00000000; + } + } + + /* Partially configure the limit word */ + p_mpc->blk_idx = limit_word_idx; + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= limit_word_mask; + } else { + word_value &= ~limit_word_mask; + } + p_mpc->blk_idx = limit_word_idx; + p_mpc->blk_lutn = word_value; + + /* Commit the configuration change */ + __DSB(); + __ISB(); + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_region_config( + struct mpc_sie200_dev_t* dev, + uint32_t base, uint32_t limit, + enum mpc_sie200_sec_attr_t* attr) +{ + enum mpc_sie200_sec_attr_t attr_prev; + uint32_t block_size; + uint32_t block_size_mask; + enum mpc_sie200_intern_error_t error; + uint32_t first_word_idx; + uint32_t first_word_mask; + uint32_t i; + uint32_t limit_word_idx; + uint32_t limit_word_mask; + uint32_t nr_words; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + const struct mpc_sie200_memory_range_t* range; + uint32_t word_value; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(attr == 0) { + return MPC_SIE200_INVALID_ARG; + } + + /* + * Initialize the security attribute to mixed in case of early + * termination of this function. A caller that does not check the + * returned error will act as if it does not know anything about the + * region queried, which is the safest bet + */ + *attr = MPC_SIE200_SEC_ATTR_MIXED; + + /* + * If the base and limit are not aligned, align them and make sure + * that the resulting region fully includes the original region + */ + block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + block_size_mask = block_size - 1; + base &= ~(block_size_mask); + limit &= ~(block_size_mask); + limit += block_size - 1; /* Round to the upper block address, + * and then remove one to get the preceding + * address. + */ + + /* Get the bitmasks used to select the bits in the LUT */ + error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, + &first_word_mask, &limit_word_mask); + + limit_word_idx = first_word_idx+nr_words - 1; + + if(error != MPC_SIE200_INTERN_ERR_NONE) { + /* Map internal error code lower than 0 to generic error */ + if(error < 0) { + return MPC_SIE200_ERR_INVALID_RANGE; + } + return (enum mpc_sie200_error_t)error; + } + + /* Set the block index to the first word that will be updated */ + p_mpc->blk_idx = first_word_idx; + + /* If only one word needs to be touched in the LUT */ + if(nr_words == 1) { + word_value = p_mpc->blk_lutn; + word_value &= first_word_mask; + if(word_value == 0) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + /* + * If there are differences between the mask and the word value, + * it means that the security attributes of blocks are mixed + */ + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + return MPC_SIE200_ERR_NONE; + } + + /* Get the partial configuration of the first word */ + word_value = p_mpc->blk_lutn & first_word_mask; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + /* + * Bail out as the security attribute will be the same regardless + * of the configuration of other blocks + */ + return MPC_SIE200_ERR_NONE; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + /* + * Store the current found attribute, to check that all the blocks indeed + * have the same security attribute. + */ + attr_prev = *attr; + + /* Get the configuration of the intermediate words if there are any */ + for(i=first_word_idx+1; iblk_idx = i; + word_value = p_mpc->blk_lutn; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value == 0xFFFFFFFF) { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } else { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + + /* If the attribute is different than the one found before, bail out */ + if(*attr != attr_prev) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + attr_prev = *attr; + } + + /* Get the partial configuration of the limit word */ + p_mpc->blk_idx = limit_word_idx; + word_value = p_mpc->blk_lutn & limit_word_mask; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + + if(*attr != attr_prev) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t* ctrl_val) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(ctrl_val == 0) { + return MPC_SIE200_INVALID_ARG; + } + + *ctrl_val = p_mpc->ctrl; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t mpc_ctrl) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->ctrl = mpc_ctrl; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev, + enum mpc_sie200_sec_resp_t* sec_rep) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(sec_rep == 0) { + return MPC_SIE200_INVALID_ARG; + } + + if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) { + *sec_rep = MPC_SIE200_RESP_BUS_ERROR; + return MPC_SIE200_ERR_NONE; + } + + *sec_rep = MPC_SIE200_RESP_RAZ_WI; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->int_en |= MPC_SIE200_INT_EN; + + return MPC_SIE200_ERR_NONE; +} + +void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + p_mpc->int_en &= ~MPC_SIE200_INT_EN; +} + +void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + p_mpc->int_clear = MPC_SIE200_INT_EN; +} + +uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + return (p_mpc->int_stat & MPC_SIE200_INT_STAT); +} + +enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT + | MPC_SIE200_CTRL_SEC_LOCK_DOWN); + + return MPC_SIE200_ERR_NONE; +} From 868817edc5da64bdb122344b508e84003b0c6792 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Wed, 18 Dec 2024 18:44:17 +0300 Subject: [PATCH 015/133] [zep fromtree] platform: ext: adi: Configure peripheral and memory This commit defines secure non-secure peripheral & memory regions Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I26f9fc9d9e7ae4474c62f03ad5a0e40fd3bb0089 Signed-off-by: Sadik Ozer (cherry picked from commit 37abe21fa0cf7625fb497c4b94baeecf8fd3914f) --- .../ext/target/adi/max32657/CMakeLists.txt | 5 + platform/ext/target/adi/max32657/target_cfg.c | 562 ++++++++++++++++++ platform/ext/target/adi/max32657/target_cfg.h | 189 ++++++ .../target/adi/max32657/tfm_peripherals_def.h | 29 + 4 files changed, 785 insertions(+) create mode 100644 platform/ext/target/adi/max32657/target_cfg.c create mode 100644 platform/ext/target/adi/max32657/target_cfg.h create mode 100644 platform/ext/target/adi/max32657/tfm_peripherals_def.h diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 7a589f231d..ffe5ca1731 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -134,6 +134,11 @@ target_compile_definitions(tfm_s __MXC_FLASH_MEM_SIZE=0x00100000 ) +target_sources(tfm_spm + PRIVATE + target_cfg.c +) + target_compile_definitions(platform_s PUBLIC TARGET=${TARGET_UC} diff --git a/platform/ext/target/adi/max32657/target_cfg.c b/platform/ext/target/adi/max32657/target_cfg.c new file mode 100644 index 0000000000..5cbde2bf12 --- /dev/null +++ b/platform/ext/target/adi/max32657/target_cfg.c @@ -0,0 +1,562 @@ +/* + * Copyright (c) 2017-2024 Arm Limited + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mxc_device.h" +#include "fih.h" +#include "target_cfg.h" +#include "Driver_MPC.h" +#include "Driver_PPC.h" +#include "platform_retarget.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "region.h" +#include "spc.h" + +/* Ensure that the start and end of NS is MPC block aligned (32kb) */ +_Static_assert(NS_PARTITION_START % MPC_CONFIG_BLOCK_SIZE == 0, "Align NS Start to MPC Block size"); +_Static_assert((NS_PARTITION_END + 1) % MPC_CONFIG_BLOCK_SIZE == 0, "Align NS End to MPC Block size"); + +#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) + +#define NVIC_SECURE_CONFIG 0 +#define NVIC_NON_SECURE_CONFIG 1 + +/* The section names come from the scatter file */ +REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); +REGION_DECLARE(Image$$, ER_VENEER, $$Base); +REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit); + +#ifdef BL2 +REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); +#endif /* BL2 */ + +const struct memory_region_limits memory_regions = { + .non_secure_code_start = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + BL2_HEADER_SIZE, + + .non_secure_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), + + .non_secure_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + NS_PARTITION_SIZE - 1, + + .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base), + .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit), + +#ifdef BL2 + .secondary_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), + + .secondary_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + + SECONDARY_PARTITION_SIZE - 1, +#endif /* BL2 */ +}; + +/* Allows software, via SAU, to define the code region as a NSC */ +#define NSCCFG_CODENSC 1 + +struct platform_data_t tfm_peripheral_std_uart = { + UART0_BASE_NS, + UART0_BASE_NS + 0xFFF, + PPC_SP_DO_NOT_CONFIGURE, + SPC_UART +}; + +/* Import MPC driver */ +extern ARM_DRIVER_MPC Driver_SRAM0_MPC, Driver_SRAM1_MPC, + Driver_SRAM2_MPC, Driver_SRAM3_MPC, + Driver_FLASH_MPC, Driver_SRAM4_MPC; + +extern ARM_DRIVER_PPC Driver_PPC; + +/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, + * otherwise the processor ignores the write. + */ +#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) + +typedef struct { + ARM_DRIVER_MPC *Driver_MPC; + uint32_t base; + uint32_t limit; +} NS_MPC_Config; + +/** + * @brief Array of MPC ranges for NS access + * + */ +static NS_MPC_Config ns_mpc_config_arr[] = { + { + &Driver_SRAM2_MPC, + MPC_SRAM2_RANGE_BASE_NS, + MPC_SRAM2_RANGE_LIMIT_NS + }, + { + &Driver_SRAM3_MPC, + MPC_SRAM3_RANGE_BASE_NS, + MPC_SRAM3_RANGE_LIMIT_NS + }, + { + &Driver_SRAM4_MPC, + MPC_SRAM4_RANGE_BASE_NS, + MPC_SRAM4_RANGE_LIMIT_NS + }, + { + &Driver_FLASH_MPC, + memory_regions.non_secure_partition_base, + memory_regions.non_secure_partition_limit, + }, +}; + +/** + * @brief Array of peripherals partitioned to the NS domain + * + */ + +uint8_t ns_periph_arr[] = { + SPC_GCR, + SPC_SIR, + SPC_FCR, + SPC_WDT, + SPC_AES, + SPC_AESKEY, + SPC_CRC, + SPC_GPIO0, + SPC_TIMER0, + SPC_TIMER1, + SPC_TIMER2, + SPC_TIMER3, + SPC_TIMER4, + SPC_TIMER5, + SPC_I3C, + SPC_UART, + SPC_SPI, + SPC_TRNG, + SPC_BTLE_DBB, + SPC_BTLE_RFFE, + SPC_RSTZ, + SPC_BOOST, + SPC_BBSIR, + SPC_BBFCR, + SPC_RTC, + SPC_WUT0, + SPC_WUT1, + SPC_PWR, + SPC_MCR, +}; + +uint8_t nvic_set_ns[] = { + ICE_IRQn, + WDT_IRQn, + RTC_IRQn, + TRNG_IRQn, + TMR0_IRQn, + TMR1_IRQn, + TMR2_IRQn, + TMR3_IRQn, + TMR4_IRQn, + TMR5_IRQn, + I3C_IRQn, + UART_IRQn, + SPI_IRQn, + GPIO0_IRQn, + DMA0_CH0_IRQn, + DMA0_CH1_IRQn, + DMA0_CH2_IRQn, + DMA0_CH3_IRQn, + WUT0_IRQn, + WUT1_IRQn, + GPIOWAKE_IRQn, + CRC_IRQn, + AES_IRQn, + ERFO_IRQn, + BOOST_IRQn, + ECC_IRQn, + BTLE_TX_DONE_IRQn, + BTLE_RX_RCVD_IRQn, + BTLE_RX_ENG_DET_IRQn, + BTLE_SFD_DET_IRQn, + BTLE_SFD_TO_IRQn, + BTLE_GP_EVENT_IRQn, + BTLE_CFO_IRQn, + BTLE_SIG_DET_IRQn, + BTLE_AGC_EVENT_IRQn, + BTLE_RFFE_SPIM_IRQn, + BTLE_TX_AES_IRQn, + BTLE_RX_AES_IRQn, + BTLE_INV_APB_ADDR_IRQn, + BTLE_IQ_DATA_VALID_IRQn, + BTLE_RX_CRC_IRQn, +}; + +enum tfm_plat_err_t enable_fault_handlers(void) +{ + /* Explicitly set secure fault priority to the highest */ + NVIC_SetPriority(SecureFault_IRQn, 0); + + /* Enables BUS, MEM, USG and Secure faults */ + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk + | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_MEMFAULTENA_Msk + | SCB_SHCSR_SECUREFAULTENA_Msk; + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t system_reset_cfg(void) +{ + uint32_t reg_value = SCB->AIRCR; + + /* Clear SCB_AIRCR_VECTKEY value */ + reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); + + /* Enable system reset request only to the secure world */ + reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk); + + SCB->AIRCR = reg_value; + + return TFM_PLAT_ERR_SUCCESS; +} + +FIH_RET_TYPE(enum tfm_plat_err_t) init_debug(void) +{ +#if !defined(DAUTH_CHIP_DEFAULT) +#error "Debug features are set during provisioning." +#endif + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be WI */ + for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ITNS); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that MPC and PPC are targeted to S state */ + NVIC_ClearTargetState(MPC_IRQn); + NVIC_ClearTargetState(PPC_IRQn); + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + int32_t ret = ARM_DRIVER_OK; + + /* MPC interrupt enabling */ + ret = Driver_SRAM0_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM1_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM2_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM3_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM4_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + NVIC_EnableIRQ(MPC_IRQn); + + /* PPC interrupt enabling */ + Driver_PPC.Initialize(); + /* Clear pending PPC interrupts */ + Driver_PPC.ClearInterrupt(); + + /* Enable PPC interrupts */ + ret = Driver_PPC.EnableInterrupt(); + if(ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + NVIC_EnableIRQ(PPC_IRQn); + + return TFM_PLAT_ERR_SUCCESS; +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ +#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC) +#define DEV_APIS_TEST_NVMEM_REGION_START (NS_DATA_LIMIT + 1) +#define DEV_APIS_TEST_NVMEM_REGION_LIMIT \ + (DEV_APIS_TEST_NVMEM_REGION_START + DEV_APIS_TEST_NVMEM_REGION_SIZE - 1) +#endif + +struct sau_cfg_t { + uint32_t RBAR; + uint32_t RLAR; + bool nsc; +}; + +const struct sau_cfg_t sau_cfg[] = { + { + ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base)), + ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + NS_PARTITION_SIZE - 1), + false, + }, + { + NS_DATA_START, + NS_DATA_LIMIT, + false, + }, + { + (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base), + (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit) - 1, + true, + }, + { + PERIPHERALS_BASE_NS_START, + PERIPHERALS_BASE_NS_END, + false, + }, +}; + +FIH_RET_TYPE(int32_t) sau_and_idau_cfg(void) +{ + uint32_t i; + + /* Ensure all memory accesses are completed */ + __DMB(); + + /* Enables SAU */ + TZ_SAU_Enable(); + + for (i = 0; i < ARRAY_SIZE(sau_cfg); i++) { + SAU->RNR = i; + SAU->RBAR = sau_cfg[i].RBAR & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | + (sau_cfg[i].nsc ? SAU_RLAR_NSC_Msk : 0U) | + SAU_RLAR_ENABLE_Msk; + } + + /* Allows SAU to define the code region as a NSC */ + MXC_SPC_SetCode_NSC(true); + + /* Ensure the write is completed and flush pipeline */ + __DSB(); + __ISB(); + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int fih_verify_sau_and_idau_cfg(void) +{ + uint32_t i; + + /* Check SAU is enabled */ + if ((SAU->CTRL & (SAU_CTRL_ENABLE_Msk)) != (SAU_CTRL_ENABLE_Msk)) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + + for (i = 0; i < ARRAY_SIZE(sau_cfg); i++) { + SAU->RNR = i; + if (SAU->RBAR != (sau_cfg[i].RBAR & SAU_RBAR_BADDR_Msk)) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + if (SAU->RLAR != ((sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | + (sau_cfg[i].nsc ? SAU_RLAR_NSC_Msk : 0U) | + SAU_RLAR_ENABLE_Msk)) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + } + + if ((MXC_SPC->nscidau & MXC_F_SPC_NSCIDAU_CODE) != MXC_F_SPC_NSCIDAU_CODE) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} +#endif /* TFM_FIH_PROFILE_ON */ + +/*------------------- Memory configuration functions -------------------------*/ +FIH_RET_TYPE(int32_t) mpc_init_cfg(void) +{ + int32_t ret = ARM_DRIVER_OK; + + for(int i = 0; i < ARRAY_SIZE(ns_mpc_config_arr); i++) { + ARM_DRIVER_MPC Driver_MPC = *(ns_mpc_config_arr[i].Driver_MPC); + uint32_t base = ns_mpc_config_arr[i].base; + uint32_t limit = ns_mpc_config_arr[i].limit; + + ret = Driver_MPC.Initialize(); + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + ret = Driver_MPC.ConfigRegion(base, + limit, + ARM_MPC_ATTR_NONSECURE); + if(ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + ret = Driver_MPC.EnableInterrupt(); + if(ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + ret = Driver_MPC.LockDown(); + if(ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + /* Add barriers to assure the MPC configuration is done before continue + * the execution. + */ + __DSB(); + __ISB(); + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int fih_verify_mpc_cfg(void) +{ + ARM_MPC_SEC_ATTR attr; + + for(int i = 0; i < ARRAY_SIZE(ns_mpc_config_arr); i++) { + ARM_DRIVER_MPC Driver_MPC = *(ns_mpc_config_arr[i].Driver_MPC); + uint32_t base = ns_mpc_config_arr[i].base; + uint32_t limit = ns_mpc_config_arr[i].limit; + + Driver_MPC.GetRegionConfig(base, limit, &attr); + + if (attr != ARM_MPC_ATTR_NONSECURE) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + } + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} +#endif /* TFM_FIH_PROFILE_ON */ + +/*---------------------- PPC configuration functions -------------------------*/ +FIH_RET_TYPE(int32_t) ppc_init_cfg(void) +{ + int32_t ret = ARM_DRIVER_OK; + int i; + + ret = Driver_PPC.Initialize(); + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + for (i = 0; i < NUM_SPC_PERIPH; i++) { + ret = ppc_configure_to_secure(i); + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + ret = ppc_en_secure_unpriv(i); + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + + /* + * Selectively open up and allow interrupts to peripherals in the NS space + * All peripherals will be privileged unless NSPC is configured otherwise + */ + for (i = 0; i < sizeof(ns_periph_arr); i++) { + ppc_configure_to_non_secure(ns_periph_arr[i]); + } + + /* Depend on the configuration set the target state of the interrupts to non-secure */ + for (i = 0; i < sizeof(nvic_set_ns); i++) { + if (NVIC_SetTargetState(nvic_set_ns[i]) != NVIC_NON_SECURE_CONFIG) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + } + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int fih_verify_ppc_cfg(void) +{ + int32_t ret = ARM_DRIVER_OK; + + /* Check if non-secure peripherals are partitioned correctly */ + for (int i = 0; i < sizeof(ns_periph_arr); i++) { + if(!Driver_PPC.isPeriphSecure(i)) + ret = ARM_DRIVER_ERROR; + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + + /* Check if non-secure peripherals interrupts are partitioned correctly */ + for (int i = 0; i< sizeof(nvic_set_ns); i++) { + if(NVIC_GetTargetState(i) != NVIC_NON_SECURE_CONFIG) + ret = ARM_DRIVER_ERROR; + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} +#endif /* TFM_FIH_PROFILE_ON */ + +void ppc_configure_to_non_secure(uint16_t pos) +{ + /* Will default to privileged only once configured to non-secure */ + Driver_PPC.ConfigPeriph(pos, ARM_PPC_NONSECURE_ONLY, ARM_PPC_PRIV_ONLY); +} + +FIH_RET_TYPE(int32_t) ppc_configure_to_secure(uint16_t pos) +{ + /* Will default to privileged only once configured to secure */ + FIH_RET(fih_int_encode(Driver_PPC.ConfigPeriph(pos, + ARM_PPC_SECURE_ONLY, + ARM_PPC_PRIV_ONLY))); +} + +FIH_RET_TYPE(int32_t) ppc_en_secure_unpriv(uint16_t pos) +{ + FIH_RET(fih_int_encode(Driver_PPC.ConfigPeriph(pos, + ARM_PPC_SECURE_ONLY, + ARM_PPC_PRIV_AND_NONPRIV))); +} + +FIH_RET_TYPE(int32_t) ppc_clr_secure_unpriv(uint16_t pos) +{ + FIH_RET(fih_int_encode(Driver_PPC.ConfigPeriph(pos, + ARM_PPC_SECURE_ONLY, + ARM_PPC_PRIV_ONLY))); +} + +void ppc_clear_irq(void) +{ + Driver_PPC.ClearInterrupt(); +} diff --git a/platform/ext/target/adi/max32657/target_cfg.h b/platform/ext/target/adi/max32657/target_cfg.h new file mode 100644 index 0000000000..ed20a7c5e9 --- /dev/null +++ b/platform/ext/target/adi/max32657/target_cfg.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2017-2021 Arm Limited + * Portions Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TARGET_CFG_H__ +#define __TARGET_CFG_H__ + +#include "uart_stdout.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_defs.h" +#include "fih.h" + +#define TFM_DRIVER_STDIO Driver_USART0 +#define NS_DRIVER_STDIO Driver_USART0 + + +/** + * @brief Defines word offsets of the PPC + */ +enum ppc_bank_e { + PPC_SP_DO_NOT_CONFIGURE = -1, + PPC_SP_PPC0, +}; + +/** + * \brief Defines the bit offsets of within the SPC + */ +enum spc_periph_e { + SPC_GCR = 0, + SPC_SIR, + SPC_FCR, + SPC_WDT, + SPC_AES, + SPC_AESKEY, + SPC_CRC, + SPC_GPIO0, + SPC_TIMER0, + SPC_TIMER1, + SPC_TIMER2, + SPC_TIMER3, + SPC_TIMER4, + SPC_TIMER5, + SPC_I3C, + SPC_UART, + SPC_SPI, + SPC_TRNG, + SPC_BTLE_DBB, + SPC_BTLE_RFFE, + SPC_RSTZ, + SPC_BOOST, + SPC_BBSIR, + SPC_BBFCR, + SPC_RTC, + SPC_WUT0, + SPC_WUT1, + SPC_PWR, + SPC_MCR, + NUM_SPC_PERIPH +}; + +/** + * \brief Store the addresses of memory regions + */ +struct memory_region_limits { + uint32_t non_secure_code_start; + uint32_t non_secure_partition_base; + uint32_t non_secure_partition_limit; + uint32_t veneer_base; + uint32_t veneer_limit; +#ifdef BL2 + uint32_t secondary_partition_base; + uint32_t secondary_partition_limit; +#endif /* BL2 */ +}; + +/** + * \brief Holds the data necessary to do isolation for a specific peripheral. + */ +struct platform_data_t { + uint32_t periph_start; + uint32_t periph_limit; + enum ppc_bank_e periph_ppc_bank; + int16_t periph_ppc_loc; +}; + +/** + * \brief Configures the Memory Protection Controller. + * + * \return Returns error code. + */ +FIH_RET_TYPE(int32_t) mpc_init_cfg(void); + +/** + * \brief Configures the Peripheral Protection Controller. + */ +FIH_RET_TYPE(int32_t) ppc_init_cfg(void); + +/** + * \brief Restict access to peripheral to secure + */ +FIH_RET_TYPE(int32_t) ppc_configure_to_secure(uint16_t loc); + +/** + * \brief Allow non-secure access to peripheral + */ +void ppc_configure_to_non_secure(uint16_t loc); + +/** + * \brief Enable secure unprivileged access to peripheral + */ +FIH_RET_TYPE(int32_t) ppc_en_secure_unpriv(uint16_t pos); + +/** + * \brief Clear secure unprivileged access to peripheral + */ +FIH_RET_TYPE(int32_t) ppc_clr_secure_unpriv(uint16_t pos); + +/** + * \brief Clears PPC interrupt. + */ +void ppc_clear_irq(void); + +/** + * \brief Configures SAU and IDAU. + */ +FIH_RET_TYPE(int32_t) sau_and_idau_cfg(void); + +/** + * \brief Enables the fault handlers and sets priorities. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t enable_fault_handlers(void); + +/** + * \brief Configures the system reset request properties + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t system_reset_cfg(void); + +/** + * \brief Configures the system debug properties. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +FIH_RET_TYPE(enum tfm_plat_err_t) init_debug(void); + +/** + * \brief Configures all external interrupts to target the + * NS state, apart for the ones associated to secure + * peripherals (plus MPC and PPC) + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); + +/** + * \brief This function enable the interrupts associated + * to the secure peripherals (plus the isolation boundary violation + * interrupts) + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_enable(void); + +/* Function for FIH to verify that SAU & IDAU are correctly configured. */ +fih_int fih_verify_sau_and_idau_cfg(void); + +/* Function for FIH to verify that MPC is correctly configured. */ +fih_int fih_verify_mpc_cfg(void); + +/* Function for FIH to verify that PPC is correctly configured. */ +fih_int fih_verify_ppc_cfg(void); + +#endif /* __TARGET_CFG_H__ */ diff --git a/platform/ext/target/adi/max32657/tfm_peripherals_def.h b/platform/ext/target/adi/max32657/tfm_peripherals_def.h new file mode 100644 index 0000000000..91b323f5d8 --- /dev/null +++ b/platform/ext/target/adi/max32657/tfm_peripherals_def.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __TFM_PERIPHERALS_DEF_H__ +#define __TFM_PERIPHERALS_DEF_H__ + +#include "max32657.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * tfm_peripheral_std_uart is defined for regression test partition + */ + +struct platform_data_t; + +extern struct platform_data_t tfm_peripheral_std_uart; + +#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) + +#endif /* __TFM_PERIPHERALS_DEF_H__ */ From d44691734f8d1e065ca676fb052338f6e6457f1c Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Tue, 15 Oct 2024 13:05:40 -0400 Subject: [PATCH 016/133] [zep fromtree] platform: ext: adi Add NS support This commit added NS support to able to execute zephyr regression tests. MAX32657 supports small profile for now. CONFIG_TFM_PROFILE_TYPE_SMALL=y -- -------- NS TEST Configuration -------------------- -- TEST_NS_ATTESTATION OFF -- TEST_NS_CRYPTO ON -- TEST_NS_ITS ON -- TEST_NS_PS OFF -- TEST_NS_QCBOR OFF -- TEST_NS_T_COSE OFF -- TEST_NS_PLATFORM OFF -- TEST_NS_FWU OFF -- TEST_NS_IPC OFF -- TEST_NS_FLIH_IRQ OFF -- TEST_NS_MULTI_CORE OFF -- TEST_NS_MANAGE_NSID OFF -- TEST_NS_SFN_BACKEND ON -- TEST_NS_FPU OFF -- --------------------------------------------------- Added UART here to get test output. To build it, tf-m-tests shall be added in west file: west config manifest.project-filter -- +tf-m-tests west update Change-Id: Ie60b62e83c59cec00f1ad197b3249ee7c7d89205 Signed-off-by: Hao Zhang (cherry picked from commit 4ae67f6f36aa7e26b30abd158956449d9db38377) --- .../ext/target/adi/max32657/CMakeLists.txt | 52 +++++++++++ platform/ext/target/adi/max32657/cmsis.h | 13 +++ .../ext/target/adi/max32657/ns/CMakeLists.txt | 86 +++++++++++++++++++ .../tests/psa_arch_tests_config.cmake | 10 +++ .../adi/max32657/tests/tfm_tests_config.cmake | 12 +++ 5 files changed, 173 insertions(+) create mode 100644 platform/ext/target/adi/max32657/cmsis.h create mode 100644 platform/ext/target/adi/max32657/ns/CMakeLists.txt create mode 100644 platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index ffe5ca1731..70b8c46c04 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -195,3 +195,55 @@ target_include_directories(platform_s ${HAL_ADI_CMSIS_INC_DIR} ${PLATFORM_DIR}/.. ) + +#========================= Files for building NS platform =====================# + +install(FILES ${TARGET_PLATFORM_PATH}/cmsis_drivers/Driver_USART.c + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(FILES ${TARGET_PLATFORM_PATH}/partition/region_defs.h + ${TARGET_PLATFORM_PATH}/partition/flash_layout.h + ${TARGET_PLATFORM_PATH}/device/inc/mpc_sie200_drv.h + ${TARGET_PLATFORM_PATH}/platform_retarget.h + ${TARGET_PLATFORM_PATH}/target_cfg.h + ${TARGET_PLATFORM_PATH}/device_cfg.h + ${TARGET_PLATFORM_PATH}/tfm_peripherals_def.h + ${TARGET_PLATFORM_PATH}/RTE_Device.h + ${TARGET_PLATFORM_PATH}/cmsis.h + ${PLATFORM_DIR}/ext/common/test_interrupt.h + ${PLATFORM_DIR}/ext/driver/Driver_USART.h + ${PLATFORM_DIR}/ext/driver/Driver_Common.h + ${PLATFORM_DIR}/include/tfm_plat_defs.h + ${CMAKE_SOURCE_DIR}/lib/fih/inc/fih.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include) + +install(DIRECTORY ${HAL_ADI_PERIPH_INC_DIR} + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include) + +install(DIRECTORY ${HAL_ADI_CMSIS_INC_DIR} + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include/cmsis) + +install(FILES ${TARGET_PLATFORM_PATH}/device/src/startup_${TARGET_LC}.c + ${TARGET_PLATFORM_PATH}/device/src/system_${TARGET_LC}.c + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/device/src) + +install(FILES ${HAL_ADI_CMSIS_INC_DIR}/max32657.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/device/inc) + +install(FILES ${PLATFORM_DIR}/ext/common/gcc/tfm_common_ns.ld + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/linker_scripts) + +# copy all files from active platform directory +install(DIRECTORY ${TARGET_PLATFORM_PATH}/ns/ + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(FILES ${TARGET_PLATFORM_PATH}/cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Copy the platform specific config +install(FILES ${TARGET_PLATFORM_PATH}/config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Install test configs +install(DIRECTORY ${TARGET_PLATFORM_PATH}/tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) diff --git a/platform/ext/target/adi/max32657/cmsis.h b/platform/ext/target/adi/max32657/cmsis.h new file mode 100644 index 0000000000..1a7efc6901 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MAX32657_CMSIS_H__ +#define __MAX32657_CMSIS_H__ + +#include "max32657.h" + +#endif /* __MAX32657_CMSIS_H__ */ diff --git a/platform/ext/target/adi/max32657/ns/CMakeLists.txt b/platform/ext/target/adi/max32657/ns/CMakeLists.txt new file mode 100644 index 0000000000..8aa3f52bdb --- /dev/null +++ b/platform/ext/target/adi/max32657/ns/CMakeLists.txt @@ -0,0 +1,86 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# This file is exported to NS side during CMake installation phase and renamed +# to CMakeLists.txt. It instructs how to build a platform on non-secture side. +# The structure and sources list are fully platform specific. +list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/../../trusted-firmware-m/cmake) +include(remote_library) + +add_library(platform_ns) + +# Fetch hal_adi repository +fetch_remote_library( + LIB_NAME hal_adi + LIB_SOURCE_PATH_VAR HAL_ADI_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/hal_adi + GIT_TAG ${HAL_ADI_VERSION} + GIT_PROGRESS TRUE +) + +set(TARGET_LC "max32657") +string(TOUPPER ${TARGET_LC} TARGET_UC) + +set(HAL_ADI_LIBRARY_DIR ${HAL_ADI_PATH}/MAX/Libraries) + +set(HAL_ADI_CMSIS_DIR ${HAL_ADI_LIBRARY_DIR}/CMSIS/Device/Maxim/${TARGET_UC}) +set(HAL_ADI_CMSIS_INC_DIR ${HAL_ADI_CMSIS_DIR}/Include) +set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source) + +set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers) +set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC}) +set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) + +target_compile_definitions(platform_ns + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CMSIS_device_header="${TARGET_LC}.h" +) + +target_compile_options(platform_ns + PUBLIC + -mno-unaligned-access +) + +target_sources(platform_ns + PRIVATE + Driver_USART.c + device/src/startup_${TARGET_LC}.c + device/src/system_${TARGET_LC}.c + + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c +) + +target_include_directories(platform_ns + PRIVATE + retarget + PUBLIC + include + include/${TARGET_UC} + ${HAL_ADI_CMSIS_INC_DIR} + ${HAL_ADI_PERIPH_INC_DIR} + ext/cmsis/Include + ext/cmsis/Include/m-profile + device/inc + ext/common +) + +# Include region_defs.h and flash_layout.h +target_include_directories(platform_region_defs + INTERFACE + include +) diff --git a/platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake b/platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..40f15a3e09 --- /dev/null +++ b/platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Paramters for PSA API tests + +set(PSA_API_TEST_TARGET max32657 CACHE STRING "PSA_API_TARGET name") diff --git a/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake b/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..04dd1d7180 --- /dev/null +++ b/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake @@ -0,0 +1,12 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(TEST_NS_SLIH_IRQ OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests") +set(TEST_NS_PS OFF CACHE BOOL "Whether to build NS PS tests") +set(TEST_NS_PLATFORM OFF ) +set(TEST_NS_IPC OFF ) +set(TEST_NS_FLIH_IRQ OFF ) From bbd0ebfcef1a0210604154cdbb12d4ec2339d0bf Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 23 Dec 2024 15:39:49 +0300 Subject: [PATCH 017/133] [zep fromtree] platform: ext: adi: Add hal_paltform file Hal platform file requires to get ns entry point, vtor and code start address. This commit add these features. Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Change-Id: Ib45a0562c42730efb91a94b528b2e83bb8596dba Signed-off-by: Sadik Ozer (cherry picked from commit 88773292512382ef1f6c3dfa6c73b33ffdff3e06) --- .../ext/target/adi/max32657/CMakeLists.txt | 1 + .../target/adi/max32657/tfm_hal_platform.c | 42 +++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 platform/ext/target/adi/max32657/tfm_hal_platform.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 70b8c46c04..51bde00742 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -137,6 +137,7 @@ target_compile_definitions(tfm_s target_sources(tfm_spm PRIVATE target_cfg.c + tfm_hal_platform.c ) target_compile_definitions(platform_s diff --git a/platform/ext/target/adi/max32657/tfm_hal_platform.c b/platform/ext/target/adi/max32657/tfm_hal_platform.c new file mode 100644 index 0000000000..3934c1134f --- /dev/null +++ b/platform/ext/target/adi/max32657/tfm_hal_platform.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "target_cfg.h" +#include "tfm_hal_platform.h" +#include "tfm_plat_defs.h" + +extern const struct memory_region_limits memory_regions; + +FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) +{ + enum tfm_plat_err_t plat_err = TFM_PLAT_ERR_SYSTEM_ERR; + + __enable_irq(); + + plat_err = nvic_interrupt_target_state_cfg(); + if (plat_err != TFM_PLAT_ERR_SUCCESS) { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_GENERIC)); + } + + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); +} + +uint32_t tfm_hal_get_ns_VTOR(void) +{ + return memory_regions.non_secure_code_start; +} + +uint32_t tfm_hal_get_ns_MSP(void) +{ + return *((uint32_t *)memory_regions.non_secure_code_start); +} + +uint32_t tfm_hal_get_ns_entry_point(void) +{ + return *((uint32_t *)(memory_regions.non_secure_code_start + 4)); +} From e0e0d6b02a343c13b45acc9e1a14fc89a69de685 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 23 Dec 2024 16:02:51 +0300 Subject: [PATCH 018/133] [zep fromtree] platform: ext: adi: Enable ICC cache Enable ICC for MAX32657 ICC cache only accessibly by secure world. Change-Id: I11b2e25bec3a46bed68b96e1d9a5888fbaf869aa Signed-off-by: Sadik Ozer (cherry picked from commit cfdc11b486816ea6e6af89cd011cc22bdc43da1d) --- platform/ext/target/adi/max32657/CMakeLists.txt | 4 ++++ .../ext/target/adi/max32657/device/src/system_max32657.c | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 51bde00742..3288297a47 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -88,6 +88,8 @@ if(BL2) ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c ) target_compile_definitions(platform_bl2 @@ -180,6 +182,8 @@ target_sources(platform_s ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/TZ/spc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_hal_ioctl.c> diff --git a/platform/ext/target/adi/max32657/device/src/system_max32657.c b/platform/ext/target/adi/max32657/device/src/system_max32657.c index b79ddfdec8..97bf21078c 100644 --- a/platform/ext/target/adi/max32657/device/src/system_max32657.c +++ b/platform/ext/target/adi/max32657/device/src/system_max32657.c @@ -26,6 +26,7 @@ #include "system_max32657.h" #include "gcr_regs.h" #include "mpc.h" +#include "icc.h" uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup @@ -115,6 +116,10 @@ void SystemInit(void) /* Enable interrupts */ __enable_irq(); +#if CONFIG_TRUSTED_EXECUTION_SECURE + MXC_ICC_Enable(); +#endif + /* Change system clock source to the main high-speed clock */ MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); From dcffef0d5978cd155983de973b32c9f832ef7556 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 23 Dec 2024 15:46:43 +0300 Subject: [PATCH 019/133] [zep fromtree] platform: ext: adi: Add hal isolation layer Implement hal isolation layer as per of existing implementation and tfm requirement Co-authored-by: Jayashree Srinivasan Co-authored-by: Hao Zhang Co-authored-by: Tanmaya Mishra Change-Id: I8c8d5a6ecdfb8eeb1fb7dd21a830b46eea1dceb3 Signed-off-by: Sadik Ozer (cherry picked from commit 915c0c9f810da8d742f22cf13b6b38e6dc6ea665) --- .../ext/target/adi/max32657/CMakeLists.txt | 1 + platform/ext/target/adi/max32657/mmio_defs.h | 35 +++ .../target/adi/max32657/tfm_hal_isolation.c | 277 ++++++++++++++++++ 3 files changed, 313 insertions(+) create mode 100644 platform/ext/target/adi/max32657/mmio_defs.h create mode 100644 platform/ext/target/adi/max32657/tfm_hal_isolation.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 3288297a47..1dc47c85bb 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -139,6 +139,7 @@ target_compile_definitions(tfm_s target_sources(tfm_spm PRIVATE target_cfg.c + tfm_hal_isolation.c tfm_hal_platform.c ) diff --git a/platform/ext/target/adi/max32657/mmio_defs.h b/platform/ext/target/adi/max32657/mmio_defs.h new file mode 100644 index 0000000000..1033c4e8a3 --- /dev/null +++ b/platform/ext/target/adi/max32657/mmio_defs.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MMIO_DEFS_H__ +#define __MMIO_DEFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "tfm_peripherals_def.h" + +/* Boundary handle binding macros. */ +#define HANDLE_ATTR_PRIV_POS 1U +#define HANDLE_ATTR_PRIV_MASK (0x1UL << HANDLE_ATTR_PRIV_POS) +#define HANDLE_ATTR_NS_POS 0U +#define HANDLE_ATTR_NS_MASK (0x1UL << HANDLE_ATTR_NS_POS) + +/* Allowed named MMIO of this platform */ +const uintptr_t partition_named_mmio_list[] = { + (uintptr_t)TFM_PERIPHERAL_STD_UART, +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* __MMIO_DEFS_H__ */ diff --git a/platform/ext/target/adi/max32657/tfm_hal_isolation.c b/platform/ext/target/adi/max32657/tfm_hal_isolation.c new file mode 100644 index 0000000000..cb17df829b --- /dev/null +++ b/platform/ext/target/adi/max32657/tfm_hal_isolation.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024 Cypress Semiconductor Corporation (an Infineon + * company) or an affiliate of Cypress Semiconductor Corporation. All rights + * reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include +#include "array.h" +#include "tfm_hal_device_header.h" +#include "Driver_Common.h" +#include "mmio_defs.h" +#include "region.h" +#include "target_cfg.h" +#include "tfm_hal_defs.h" +#include "tfm_hal_isolation.h" +#include "tfm_plat_defs.h" +#include "region_defs.h" +#include "tfm_peripherals_def.h" +#include "load/partition_defs.h" +#include "load/asset_defs.h" +#include "load/spm_load_api.h" + +#define PROT_BOUNDARY_VAL \ + ((1U << HANDLE_ATTR_PRIV_POS) & HANDLE_ATTR_PRIV_MASK) + +enum tfm_hal_status_t tfm_hal_set_up_static_boundaries( + uintptr_t *p_spm_boundary) +{ + /* Set up isolation boundaries between SPE and NSPE */ + sau_and_idau_cfg(); + if (mpc_init_cfg() != ARM_DRIVER_OK) { + return TFM_HAL_ERROR_GENERIC; + } + + if (ppc_init_cfg() != ARM_DRIVER_OK) { + return TFM_HAL_ERROR_GENERIC; + } + + *p_spm_boundary = (uintptr_t)PROT_BOUNDARY_VAL; + + return TFM_HAL_SUCCESS; +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int tfm_hal_verify_static_boundaries(void) +{ + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); +} +#endif + +enum tfm_hal_status_t tfm_hal_bind_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t *p_boundary) +{ + uint32_t i, j; + bool privileged; + bool ns_agent; + uint32_t partition_attrs = 0; + const struct asset_desc_t *p_asset; + struct platform_data_t *plat_data_ptr; + + if (!p_ldinf || !p_boundary) { + return TFM_HAL_ERROR_GENERIC; + } + +#if TFM_ISOLATION_LEVEL == 1 + privileged = true; +#else + privileged = IS_PSA_ROT(p_ldinf); +#endif + + ns_agent = IS_NS_AGENT(p_ldinf); + p_asset = LOAD_INFO_ASSET(p_ldinf); + + /* + * Validate if the named MMIO of partition is allowed by the platform. + * Otherwise, skip validation. + * + * NOTE: Need to add validation of numbered MMIO if platform requires. + */ + for (i = 0; i < p_ldinf->nassets; i++) { + if (!(p_asset[i].attr & ASSET_ATTR_NAMED_MMIO)) { + continue; + } + for (j = 0; j < ARRAY_SIZE(partition_named_mmio_list); j++) { + if (p_asset[i].dev.dev_ref == partition_named_mmio_list[j]) { + break; + } + } + + if (j == ARRAY_SIZE(partition_named_mmio_list)) { + /* The MMIO asset is not in the allowed list of platform. */ + return TFM_HAL_ERROR_GENERIC; + } + /* Assume PPC & MPC settings are required even under level 1 */ + plat_data_ptr = REFERENCE_TO_PTR(p_asset[i].dev.dev_ref, + struct platform_data_t *); + + if (plat_data_ptr->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) { + ppc_configure_to_secure(plat_data_ptr->periph_ppc_loc); + if (privileged) { + ppc_clr_secure_unpriv(plat_data_ptr->periph_ppc_loc); + } else { + ppc_en_secure_unpriv(plat_data_ptr->periph_ppc_loc); + } + } + } + + partition_attrs = ((uint32_t)privileged << HANDLE_ATTR_PRIV_POS) & + HANDLE_ATTR_PRIV_MASK; + partition_attrs |= ((uint32_t)ns_agent << HANDLE_ATTR_NS_POS) & + HANDLE_ATTR_NS_MASK; + *p_boundary = (uintptr_t)partition_attrs; + + return TFM_HAL_SUCCESS; +} + +#ifdef TFM_FIH_PROFILE_ON +FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_activate_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t boundary) +{ + CONTROL_Type ctrl; + uint32_t local_handle = (uint32_t)boundary; + bool privileged = !!(local_handle & HANDLE_ATTR_PRIV_MASK); + + /* Privileged level is required to be set always */ + ctrl.w = __get_CONTROL(); + ctrl.b.nPRIV = privileged ? 0 : 1; + __set_CONTROL(ctrl.w); + + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); +} + +FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_memory_check(uintptr_t boundary, uintptr_t base, + size_t size, uint32_t access_type) +{ + int flags = 0; + + /* If size is zero, this indicates an empty buffer and base is ignored */ + if (size == 0) { + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); + } + + if (!base) { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_INVALID_INPUT)); + } + + if ((access_type & TFM_HAL_ACCESS_READWRITE) == TFM_HAL_ACCESS_READWRITE) { + flags |= CMSE_MPU_READWRITE; + } else if (access_type & TFM_HAL_ACCESS_READABLE) { + flags |= CMSE_MPU_READ; + } else { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_INVALID_INPUT)); + } + + if (!((uint32_t)boundary & HANDLE_ATTR_PRIV_MASK)) { + flags |= CMSE_MPU_UNPRIV; + } + + if ((uint32_t)boundary & HANDLE_ATTR_NS_MASK) { + CONTROL_Type ctrl; + ctrl.w = __TZ_get_CONTROL_NS(); + if (ctrl.b.nPRIV == 1) { + flags |= CMSE_MPU_UNPRIV; + } else { + flags &= ~CMSE_MPU_UNPRIV; + } + flags |= CMSE_NONSECURE; + } + + if (cmse_check_address_range((void *)base, size, flags) != NULL) { + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); + } else { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_MEM_FAULT)); + } +} + +FIH_RET_TYPE(bool) tfm_hal_boundary_need_switch(uintptr_t boundary_from, + uintptr_t boundary_to) +{ + if (boundary_from == boundary_to) { + FIH_RET(fih_int_encode(false)); + } + + if (((uint32_t)boundary_from & HANDLE_ATTR_PRIV_MASK) && + ((uint32_t)boundary_to & HANDLE_ATTR_PRIV_MASK)) { + FIH_RET(fih_int_encode(false)); + } + FIH_RET(fih_int_encode(true)); +} + +#else /* TFM_FIH_PROFILE_ON */ + +enum tfm_hal_status_t tfm_hal_memory_check(uintptr_t boundary, uintptr_t base, + size_t size, uint32_t access_type) +{ + int flags = 0; + + /* If size is zero, this indicates an empty buffer and base is ignored */ + if (size == 0) { + return TFM_HAL_SUCCESS; + } + + if (!base) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if ((access_type & TFM_HAL_ACCESS_READWRITE) == TFM_HAL_ACCESS_READWRITE) { + flags |= CMSE_MPU_READWRITE; + } else if (access_type & TFM_HAL_ACCESS_READABLE) { + flags |= CMSE_MPU_READ; + } else { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (!((uint32_t)boundary & HANDLE_ATTR_PRIV_MASK)) { + flags |= CMSE_MPU_UNPRIV; + } + + if ((uint32_t)boundary & HANDLE_ATTR_NS_MASK) { + CONTROL_Type ctrl; + ctrl.w = __TZ_get_CONTROL_NS(); + if (ctrl.b.nPRIV == 1) { + flags |= CMSE_MPU_UNPRIV; + } else { + flags &= ~CMSE_MPU_UNPRIV; + } + flags |= CMSE_NONSECURE; + } + + if (cmse_check_address_range((void *)base, size, flags) != NULL) { + return TFM_HAL_SUCCESS; + } else { + return TFM_HAL_ERROR_MEM_FAULT; + } +} + +enum tfm_hal_status_t tfm_hal_activate_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t boundary) +{ + CONTROL_Type ctrl; + uint32_t local_handle = (uint32_t)boundary; + bool privileged = !!(local_handle & HANDLE_ATTR_PRIV_MASK); + + /* Privileged level is required to be set always */ + ctrl.w = __get_CONTROL(); + ctrl.b.nPRIV = privileged ? 0 : 1; + __set_CONTROL(ctrl.w); + + return TFM_HAL_SUCCESS; +} + +bool tfm_hal_boundary_need_switch(uintptr_t boundary_from, + uintptr_t boundary_to) +{ + if (boundary_from == boundary_to) { + return false; + } + + if (((uint32_t)boundary_from & HANDLE_ATTR_PRIV_MASK) && + ((uint32_t)boundary_to & HANDLE_ATTR_PRIV_MASK)) { + return false; + } + return true; +} + +#endif /* TFM_FIH_PROFILE_ON */ From fafda5ef648e32acef3716021fce16513ec54d0d Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 6 Jan 2025 17:53:20 +0300 Subject: [PATCH 020/133] [zep fromtree] platform: ext: adi: Enable CP10CP11 for MAX32657 We intend to use FP in our own NSPE application but the TF-M SPE services that we enable do not require FP. CONFIG_TFM_ENABLE_CP10CP11 detail: Make FPU and MVE operational when SPE and/or NSPE require FPU or MVE usage. This alone only enables the coprocessors CP10-CP11, whereas CONFIG_TFM_FLOAT_ABI=hard along with CONFIG_TFM_ENABLE_FP, CONFIG_TFM_ENABLE_MVE or CONFIG_TFM_ENABLE_MVE_FP compiles the code with hardware FP or MVE instructions and ABI. Change-Id: Ifb8cdefcc05fb2a856593d2fb128a95f1c6f66ec Signed-off-by: Sadik Ozer (cherry picked from commit fab0109803e73cee7f2d8304335b36cd86fb94cf) --- platform/ext/target/adi/max32657/cpuarch.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/ext/target/adi/max32657/cpuarch.cmake b/platform/ext/target/adi/max32657/cpuarch.cmake index 8d4c7422cd..f693263b85 100644 --- a/platform/ext/target/adi/max32657/cpuarch.cmake +++ b/platform/ext/target/adi/max32657/cpuarch.cmake @@ -13,3 +13,4 @@ set(TFM_SYSTEM_PROCESSOR cortex-m33) set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") set(CONFIG_TFM_ENABLE_FP OFF) +set(CONFIG_TFM_ENABLE_CP10CP11 ON) From 3503c2a7c6416524a5a44b294be190e6ebdeb86b Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Fri, 3 Jan 2025 14:16:05 +0300 Subject: [PATCH 021/133] [zep fromtree] platform: ext: adi: Manage UART between NS and S domain There is one UART on MAX32657, it is need to be used by NS and S world depend on the test. This commit adds related flag to switch UART between S and NS world Change-Id: I990866c846ffa0aa7d2100dbb2f09172ff454dc4 Signed-off-by: Sadik Ozer (cherry picked from commit 881f7e3eaf219ecf0ec4dfd55d486c084c8c2dcd) --- platform/ext/target/adi/max32657/CMakeLists.txt | 3 +++ platform/ext/target/adi/max32657/target_cfg.c | 4 ++++ platform/ext/target/adi/max32657/tfm_hal_platform.c | 7 ++++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 1dc47c85bb..2f535c4dd1 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -153,6 +153,9 @@ target_compile_definitions(platform_s __MXC_FLASH_MEM_BASE=0x11000000 __MXC_FLASH_MEM_SIZE=0x00100000 + + $<$:TFM_S_REG_TEST> + $<$:TFM_NS_REG_TEST> ) target_compile_options(platform_s diff --git a/platform/ext/target/adi/max32657/target_cfg.c b/platform/ext/target/adi/max32657/target_cfg.c index 5cbde2bf12..cd77afd20c 100644 --- a/platform/ext/target/adi/max32657/target_cfg.c +++ b/platform/ext/target/adi/max32657/target_cfg.c @@ -145,7 +145,9 @@ uint8_t ns_periph_arr[] = { SPC_TIMER4, SPC_TIMER5, SPC_I3C, +#if !defined(TFM_S_REG_TEST) SPC_UART, +#endif SPC_SPI, SPC_TRNG, SPC_BTLE_DBB, @@ -173,7 +175,9 @@ uint8_t nvic_set_ns[] = { TMR4_IRQn, TMR5_IRQn, I3C_IRQn, +#if !defined(TFM_S_REG_TEST) UART_IRQn, +#endif SPI_IRQn, GPIO0_IRQn, DMA0_CH0_IRQn, diff --git a/platform/ext/target/adi/max32657/tfm_hal_platform.c b/platform/ext/target/adi/max32657/tfm_hal_platform.c index 3934c1134f..fdd0d7576f 100644 --- a/platform/ext/target/adi/max32657/tfm_hal_platform.c +++ b/platform/ext/target/adi/max32657/tfm_hal_platform.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2021-2024, Arm Limited. All rights reserved. - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2024-2025 Analog Devices, Inc. * * SPDX-License-Identifier: BSD-3-Clause * @@ -17,6 +17,11 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) enum tfm_plat_err_t plat_err = TFM_PLAT_ERR_SYSTEM_ERR; __enable_irq(); +#if defined(TFM_SPM_LOG_RAW_ENABLED) && \ + !defined(TFM_NS_REG_TEST) && \ + !defined(TFM_S_REG_TEST) + stdio_init(); +#endif plat_err = nvic_interrupt_target_state_cfg(); if (plat_err != TFM_PLAT_ERR_SUCCESS) { From 24d9635310917c8d4fa084b0cd6b3b0a941de981 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Fri, 3 Jan 2025 12:32:21 +0300 Subject: [PATCH 022/133] [zep fromtree] platform: ext: adi: Enable system reset for secure domain Enable system reset request only to the secure world that triggered via NVIC_SystemReset function. Change-Id: I53457fba66a7c3aaec7524bda58f588f2f68fad3 Signed-off-by: Sadik Ozer (cherry picked from commit 037bcfda03d2d61da45225ca02cb2074c5e421e6) --- platform/ext/target/adi/max32657/tfm_hal_platform.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/platform/ext/target/adi/max32657/tfm_hal_platform.c b/platform/ext/target/adi/max32657/tfm_hal_platform.c index fdd0d7576f..98fd0944f7 100644 --- a/platform/ext/target/adi/max32657/tfm_hal_platform.c +++ b/platform/ext/target/adi/max32657/tfm_hal_platform.c @@ -16,6 +16,11 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) { enum tfm_plat_err_t plat_err = TFM_PLAT_ERR_SYSTEM_ERR; + plat_err = system_reset_cfg(); + if (plat_err != TFM_PLAT_ERR_SUCCESS) { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_GENERIC)); + } + __enable_irq(); #if defined(TFM_SPM_LOG_RAW_ENABLED) && \ !defined(TFM_NS_REG_TEST) && \ From 0917199e2db9abe328f8dc18c4161e1fac3c424c Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 2 Jan 2025 13:38:42 +0300 Subject: [PATCH 023/133] [zep fromtree] platform: ext: adi: Define RAM function section To enable ER_CODE_SRAM section in linker file define SRAM_CODE_START and SIZE. Size set as 1KB, this allow to store ramfunctions in SRAM Flash driver function stored in .flashprog in hal layer so that S_RAM_CODE_EXTRA_SECTION_NAME defined. .map output .ER_CODE_SRAM 0x000000003000fc00 0x3b8 load address 0x0000000011012a20 *libflash_drivers*:(SORT_BY_ALIGNMENT(.text*)) *libflash_drivers*:(SORT_BY_ALIGNMENT(.rodata*)) *(.ramfunc) *(.flashprog) .flashprog 0x000000003000fc00 0x58 platform/libplatform_s.a(flc_me30.o) 0x000000003000fc00 MXC_FLC_Busy 0x000000003000fc04 MXC_FLC_PageErase 0x000000003000fc28 MXC_FLC_Write128 .flashprog 0x000000003000fc58 0x11c platform/libplatform_s.a(flc_common.o) 0x000000003000fc58 MXC_FLC_Com_VerifyData 0x000000003000fc7c MXC_FLC_Com_Write 0x000000003000fd6a MXC_FLC_Com_Read .flashprog 0x000000003000fd74 0x218 platform/libplatform_s.a(flc_reva.o) 0x000000003000fdb4 MXC_FLC_RevA_Busy 0x000000003000fdc4 MXC_FLC_RevA_MassErase 0x000000003000fe04 MXC_FLC_RevA_PageErase 0x000000003000fe46 MXC_FLC_RevA_Write32 0x000000003000fea4 MXC_FLC_RevA_Write32Using128 0x000000003000ff2c MXC_FLC_RevA_Write128 Change-Id: I9bc4b99602dc3b13c19faaec52c2e23211b8e959 Signed-off-by: Sadik Ozer (cherry picked from commit b21f20921ebe4a7888fd78cc89238f4d2243c30f) --- .../target/adi/max32657/partition/region_defs.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h index 1ee6aaf491..e5fb0bcc49 100644 --- a/platform/ext/target/adi/max32657/partition/region_defs.h +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -92,10 +92,16 @@ /* Size of vector table: 69 interrupt handlers + 16 bytes of reserved space */ #define S_CODE_VECTOR_TABLE_SIZE (0x00000124) +#define S_TOTAL_DATA_SIZE KB(64) +#define S_RAM_CODE_SIZE KB(1) /* ramfuncs section size*/ + #define S_DATA_START (S_RAM_ALIAS(0x00000000)) -#define S_DATA_SIZE KB(64) +#define S_DATA_SIZE (S_TOTAL_DATA_SIZE - S_RAM_CODE_SIZE) #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) +#define S_RAM_CODE_START (S_DATA_START + S_DATA_SIZE) /* ramfuncs section start */ +#define S_RAM_CODE_EXTRA_SECTION_NAME ".flashprog" /* ramfuncs section name */ + /* Non-secure regions * MPC block aligned 32KB, NS binary need to aling that */ @@ -104,12 +110,12 @@ #define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) -#define NS_DATA_START (NS_RAM_ALIAS( S_DATA_SIZE )) +#define NS_DATA_START (NS_RAM_ALIAS( S_TOTAL_DATA_SIZE )) #if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC) #define DEV_APIS_TEST_NVMEM_REGION_SIZE KB(1) -#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - DEV_APIS_TEST_NVMEM_REGION_SIZE) +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_TOTAL_DATA_SIZE - DEV_APIS_TEST_NVMEM_REGION_SIZE) #else -#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_TOTAL_DATA_SIZE) #endif #define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) From bd503b33da255045b385e2af58b2abd0dca7d3b0 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Tue, 7 Jan 2025 17:22:38 -0500 Subject: [PATCH 024/133] [zep fromtree] platform: ext: adi: clear FPCA bit of control register ADI BootRom secure mode currently uses floating point registers and set FPCA bit. ADI TF-M would ensure FPCA bit is cleared before jumping to NS Change-Id: Ibe3c2adfe54cb13353c77b4827b279816d9e19bc Signed-off-by: Hao Zhang (cherry picked from commit cc6354c7039ee528a3a2a897602e942cb2a25f70) --- .../target/adi/max32657/device/src/system_max32657.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/device/src/system_max32657.c b/platform/ext/target/adi/max32657/device/src/system_max32657.c index 97bf21078c..7fa6aa865d 100644 --- a/platform/ext/target/adi/max32657/device/src/system_max32657.c +++ b/platform/ext/target/adi/max32657/device/src/system_max32657.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2024-2025 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -124,4 +124,13 @@ void SystemInit(void) MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); + + /* + * FPCA bit of CONTROL register can be enabled while + * performing floating point operation in Secure domain. + * It will trigger fault if it is not cleared before + * switching to Non-secure domain. + * Hence, clearing FPCA bit during initialization firmware + */ + __set_CONTROL(__get_CONTROL() & ~0x4); } From b3be783086156d753822d3356ff9f19e1940821a Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Wed, 20 Nov 2024 22:56:29 +0300 Subject: [PATCH 025/133] [zep fromtree] platform: ext: adi: Add MAX32657 MCUBoot header MAX32657 firmware need to have a header and signature section to it be interpreted and validated by BootROM Change-Id: I1d96deda795048ec96b5028c352a6078afde5d79 Signed-off-by: Sadik Ozer (cherry picked from commit 574cf798f69cb2396f03aa60e72f272aae875e94) --- .../ext/target/adi/max32657/CMakeLists.txt | 1 + .../adi/max32657/device/gcc/max32657_sla.ld | 16 ++++++ .../max32657/device/src/sla_header_max32657.c | 50 +++++++++++++++++++ 3 files changed, 67 insertions(+) create mode 100644 platform/ext/target/adi/max32657/device/src/sla_header_max32657.c diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 2f535c4dd1..bbebe1ae6a 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -52,6 +52,7 @@ if(BL2) PRIVATE ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/startup_${TARGET_LC}.c ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/sla_header_${TARGET_LC}.c ) # Add includes for BL2 diff --git a/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld b/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld index de6049c5da..10a91a559f 100644 --- a/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld +++ b/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld @@ -1,5 +1,6 @@ ;/* ; * Copyright (c) 2022-2024 Arm Limited. All rights reserved. +; * Copyright (C) 2024-2025 Analog Devices, Inc. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -41,6 +42,8 @@ SECTIONS __Vectors_End = .; __Vectors_Size = __Vectors_End - __Vectors; __end__ = .; + . = ALIGN(1024); /* Authentication header is 1024 byte aligned. */ + KEEP(*(.sla_header)) /* authentication header */ *(.text*) @@ -200,4 +203,17 @@ SECTIONS Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + + /* End of flash image. */ + /* This segment is required during the signing operation to + * enforce any padding in previous FLASH segments. + */ + .end_of_flash_image : + { + FILL(0xFF) + KEEP(*(.end_of_flash_image)) + /* End marker. */ + LONG(0x55AA55AA); + _application_end = .; + } > FLASH } diff --git a/platform/ext/target/adi/max32657/device/src/sla_header_max32657.c b/platform/ext/target/adi/max32657/device/src/sla_header_max32657.c new file mode 100644 index 0000000000..a9a14b8a4d --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/sla_header_max32657.c @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/***** Includes *****/ +#include +#include + +extern uint32_t _application_end; + +#define SLA_HEADER_MAGIC0 0xBF1421E4 +#define SLA_HEADER_MAGIC1 0x461A8CF5 +#define SLA_HEADER_VERSION 0x00000001 +#define SLA_HEADER_ALGORITHM_ECDSA 0x516A0001 +#define SLA_HEADER_RESERVED 0x00000000 + +typedef struct { + uint32_t magic0; + uint32_t magic1; + uint32_t version; + uint32_t verifytype; + uint32_t sigaddress; + uint32_t reserved5; + uint32_t reserved6; + uint32_t reserved7; +} flash_app_header_t; + +__attribute__((section(".sla_header"))) __attribute__((__used__)) +const flash_app_header_t sla_header = { .magic0 = SLA_HEADER_MAGIC0, + .magic1 = SLA_HEADER_MAGIC1, + .version = SLA_HEADER_VERSION, + .verifytype = SLA_HEADER_ALGORITHM_ECDSA, + .sigaddress = (uint32_t)&_application_end, + .reserved5 = SLA_HEADER_RESERVED, + .reserved6 = SLA_HEADER_RESERVED, + .reserved7 = SLA_HEADER_RESERVED }; From 2dcb460fff6ec2cc7c855d4b85d71257975dbdd9 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 11 Feb 2025 13:20:46 +0300 Subject: [PATCH 026/133] [zep fromtree] platform: ext: adi: Enable provisioning_bundle for MAX32657 By using PLATFORM_DEFAULT_PROVISIONING user can provision device by its secret key If PLATFORM_DEFAULT_PROVISIONING flag been OFF platform/ext/common/provision_bundle will be build that include test key, user can set related item with their private values. This bundle can be loaded to SRAM and executed there. If -DPLATFORM_DEFAULT_PROVISIONING=OFF and -DTFM_DUMMY_PROVISIONING=ON then the keys in the tf-m/platform/ext/target/common/provisioning/provisioning_config.cmake and the default MCUBoot signing keys will be used for provisioning. If -DPLATFORM_DEFAULT_PROVISIONING=OFF and -DTFM_DUMMY_PROVISIONING=OFF are set then unique values can be used for provisioning. The keys and seeds can be changed by passing the new values to the build command, or by setting the -DPROVISIONING_KEYS_CONFIG flag to a .cmake file that contains the keys. An example config cmake file can be seen at tf-m/platform/ext/target/common/provisioning/provisioning_config.cmake. Otherwise new random values are going to be generated and used. For the image signing the ${MCUBOOT_KEY_S} and ${MCUBOOT_KEY_NS} will be used. These variables should point to .pem files that contain the code signing private keys. The public keys are going to be generated from these private keys and will be used for provisioning. The hash of the public key is going to be written into the provisioning_data.c automatically. Change-Id: I9d54c76ccc3e1adc20ecf4047351d9c19b3d256f Signed-off-by: Sadik Ozer (cherry picked from commit 5c0ffdb5f0a1efb2a0d6d5fad99fa698d8b10f60) --- platform/ext/target/adi/max32657/CMakeLists.txt | 12 ++++++++++++ platform/ext/target/adi/max32657/config.cmake | 6 ++++++ .../ext/target/adi/max32657/partition/region_defs.h | 10 ++++++++++ 3 files changed, 28 insertions(+) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index bbebe1ae6a..be86a4f7f0 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -173,6 +173,7 @@ target_sources(platform_s cmsis_drivers/Driver_MPC.c device/src/mpc_sie200_drv.c $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c @@ -206,6 +207,17 @@ target_include_directories(platform_s ${PLATFORM_DIR}/.. ) +if(NOT PLATFORM_DEFAULT_PROVISIONING) + add_subdirectory(${PLATFORM_DIR}/ext/common/provisioning_bundle provisioning) + + target_compile_definitions(platform_region_defs + INTERFACE + PROVISIONING_CODE_PADDED_SIZE=${PROVISIONING_CODE_PADDED_SIZE} + PROVISIONING_VALUES_PADDED_SIZE=${PROVISIONING_VALUES_PADDED_SIZE} + PROVISIONING_DATA_PADDED_SIZE=${PROVISIONING_DATA_PADDED_SIZE} + ) +endif() + #========================= Files for building NS platform =====================# install(FILES ${TARGET_PLATFORM_PATH}/cmsis_drivers/Driver_USART.c diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 4df9e5f669..0c6612d69f 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -17,6 +17,12 @@ set(TFM_PARTITION_INITIAL_ATTESTATION ON CACHE BOOL "Enable Ini set(CONFIG_TFM_HALT_ON_CORE_PANIC ON CACHE BOOL "On fatal errors in the secure firmware, halt instead of rebooting.") set(PLATFORM_DEFAULT_OTP OFF CACHE BOOL "Use trusted on-chip flash to implement OTP memory") +set(PLATFORM_DEFAULT_PROVISIONING ON CACHE BOOL "Use default provisioning implementation") +set(PROVISIONING_DATA_PADDED_SIZE "0x400" CACHE STRING "") +set(PROVISIONING_KEYS_CONFIG "" CACHE FILEPATH "The config file which has the keys and seeds for provisioning") +set(PROVISIONING_CODE_PADDED_SIZE "0x2000" CACHE STRING "") +set(PROVISIONING_VALUES_PADDED_SIZE "0x400" CACHE STRING "") + set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h index e5fb0bcc49..5de67cd5d0 100644 --- a/platform/ext/target/adi/max32657/partition/region_defs.h +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -161,4 +161,14 @@ #define BOOT_TFM_SHARED_DATA_SIZE KB(1) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) + +#define PROVISIONING_BUNDLE_CODE_START (BL2_DATA_START + BL2_DATA_SIZE - KB(32)) +#define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) +/* The max size of the values(keys, seeds) that are going to be provisioned into the OTP. */ +#define PROVISIONING_BUNDLE_VALUES_START (PROVISIONING_BUNDLE_CODE_START + PROVISIONING_BUNDLE_CODE_SIZE) +#define PROVISIONING_BUNDLE_VALUES_SIZE (PROVISIONING_VALUES_PADDED_SIZE) +#define PROVISIONING_BUNDLE_DATA_START (PROVISIONING_BUNDLE_VALUES_START + PROVISIONING_BUNDLE_VALUES_SIZE) +#define PROVISIONING_BUNDLE_DATA_SIZE (PROVISIONING_DATA_PADDED_SIZE) +#define PROVISIONING_BUNDLE_START (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) + #endif /* __REGION_DEFS_H__ */ From 3de734571909e7e5efbd2f7d884d6b4c7230d240 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 30 Jan 2025 09:10:16 +0300 Subject: [PATCH 027/133] [zep fromtree] doc: Add MAX32657 This commit adds/updates related file for MAX32657 documentations Change-Id: I5ff357ef35b0a3e7e31b0ae127f90803d3c6f397 Signed-off-by: Sadik Ozer (cherry picked from commit 89f8f9656a4152b58a220002f55516c57879e050) --- docs/platform/adi/index.rst | 13 ++ docs/platform/adi/max32657/README.rst | 180 ++++++++++++++++++++++++ docs/platform/index.rst | 1 + docs/platform/platform_introduction.rst | 2 + 4 files changed, 196 insertions(+) create mode 100644 docs/platform/adi/index.rst create mode 100644 docs/platform/adi/max32657/README.rst diff --git a/docs/platform/adi/index.rst b/docs/platform/adi/index.rst new file mode 100644 index 0000000000..3dad109b31 --- /dev/null +++ b/docs/platform/adi/index.rst @@ -0,0 +1,13 @@ +############################## +Analog Devices, Inc. Platforms +############################## + +.. toctree:: + :maxdepth: 1 + :titlesonly: + + MAX32657 + +-------------- + +*Copyright (c) 2025, Analog Devices, Inc. All rights reserved.* diff --git a/docs/platform/adi/max32657/README.rst b/docs/platform/adi/max32657/README.rst new file mode 100644 index 0000000000..7b1737f858 --- /dev/null +++ b/docs/platform/adi/max32657/README.rst @@ -0,0 +1,180 @@ +MAX32657 +======== + + +Introduction +------------ + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) +with digital signal processing (DSP) instructions, large flash and SRAM memories, +and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. +This device unites processing horsepower with the connectivity required for +continuous glucose monitoring (CGM), wearables, and other medical applications. +The nano-power modes increase battery life substantially. + +MAX32657 1MB flash and 256KB RAM split to define section for MCUBoot, +TF-M (S), Zephyr (NS) and storage that used for secure services and configurations. +Default layout of MAX32657 is listed in below table. + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x1000000[64K] | MCU Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x1010000[320k] | Secure image slot0 (TF-M) | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x1060000[576k] | Non-secure image slot0 | ++----------+------------------+---------------------------------+ +| slot1 | 0x10F0000[0k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x10F0000[0k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x30000000[64k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20010000[192k] | Non-Secure memory | ++----------------+------------------+-------------------+ + + +Secure Boot ROM +--------------- + +MAX32657 has Secure Boot ROM that used to authenticate user code via ECDSA 256 public key. +The Secure Boot ROM is disabled on default, to enable it user need to provision device first. + + +Building TF-M +------------- + +This platform port supports TF-M regression tests (Secure and Non-secure) +with Isolation Level 1. + +To build S and NS application, run the following commands: + +.. note:: + + Only GNU toolchain is supported. + +.. note:: + + Only "profile_small" predefined profile is supported. + +Prepare the tf-m-tests repository inside the TF-M base folder. + +.. code-block:: bash + + cd + git clone https://git.trustedfirmware.org/TF-M/tf-m-tests.git + +.. code:: bash + + cd /tf-m-test/tests_reg + + cmake -S -B build_spe \ + -G"Unix Makefiles" \ + -DTFM_PLATFORM=adi/max32657 \ + -DTFM_TOOLCHAIN_FILE=[tf-m path]/toolchain_GNUARM.cmake \ + -DTEST_S=OFF \ + -DTEST_NS=ON \ + -DTFM_NS_REG_TEST=ON \ + -DMCUBOOT_LOG_LEVEL="INFO" \ + -DTFM_ISOLATION_LEVEL=1 + cmake --build build_spe -- install + + cmake -S . -B build_test \ + -G"Unix Makefiles" \ + -DCONFIG_SPE_PATH=[tf-m-tests path]/tests_reg/build_spe/api_ns \ + -DTFM_TOOLCHAIN_FILE=cmake/toolchain_ns_GNUARM.cmake \ + -DTFM_NS_REG_TEST=ON + cmake --build build_test + + +Merge and Flash Images +---------------------- + +Follow the steps below to program the flash with a compiled TF-M image (i.e. S, NS or both). + + +Generate Intel hex files from the output binary (bin) files as follows: + +.. code-block:: console + + srec_cat build_test/bin/tfm_ns_signed.bin -binary --offset 0x01060000 -o build_test/bin/tfm_ns_signed.hex -intel + + +Merge hex files as follows: + +.. code-block:: console + + srec_cat.exe build_spe/bin/bl2.hex -Intel build_spe/bin/tfm_s_signed.hex -Intel build_test/bin/tfm_ns_signed.hex -Intel -o tfm_merged.hex -Intel + + +Flash them with JLink as follows: + +.. code-block:: console + + JLinkExe -device MAX32657 -if swd -speed 2000 -autoconnect 1 + J-Link>h + J-Link>r + J-Link>erase + J-Link>loadfile build_spe/bin/tfm_merged.hex + + +BL2 and TF-M Provisioning +------------------------- + +On default ``-DPLATFORM_DEFAULT_PROVISIONING=ON`` and ``-DTFM_DUMMY_PROVISIONING=ON`` +which will use default provisioning and dummpy keys, these configuration is fine +for development purpose but for production customer specific keys shall be used +Provisioning bundles can be generated with the ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` flag. +The provisioning bundle binary will be generated and it's going to contain +the provisioning code and provisioning values. + +If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` and ``-DTFM_DUMMY_PROVISIONING=ON`` then the keys in +the ``tf-m/platform/ext/target/common/provisioning/provisioning_config.cmake`` and the +default MCUBoot signing keys will be used for provisioning. + +If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` and ``-DTFM_DUMMY_PROVISIONING=OFF`` are set +then unique values can be used for provisioning. The keys and seeds can be changed by +passing the new values to the build command, or by setting the ``-DPROVISIONING_KEYS_CONFIG`` flag +to a .cmake file that contains the keys. An example config cmake file can be seen at +``tf-m/platform/ext/target/common/provisioning/provisioning_config.cmake``. +Otherwise new random values are going to be generated and used. For the image signing +the ${MCUBOOT_KEY_S} and ${MCUBOOT_KEY_NS} will be used. These variables should point to +.pem files that contain the code signing private keys. The public keys are going to be generated +from these private keys and will be used for provisioning. The hash of the public key is going to +be written into the ``provisioning_data.c`` automatically. + +If ``-DMCUBOOT_GENERATE_SIGNING_KEYPAIR=ON`` is set then a new mcuboot signing public and private +keypair is going to be generated and it's going to be used to sign the S and NS binaries. + +The new generated keypair can be found in the ``/bin`` folder or in the +``/image_signing/keys`` after installation. +The generated provisioning_data.c file can be found at +``/platform/target/provisioning/provisioning_data.c`` + +.. note:: + + The provisioning bundle generation depends on pyelftools that's have to be installed:: + + pip3 install pyelftools + +UART Console +************ + +MAX32657 has one UART (UART0) peripheral which is routed for Non-Secure console output by default. +S and NS firmware can not use UART at the same time. +If TFM_S_REG_TEST been defined the UART console will be routed to the Secure side otherwise it will +be on NS side. + +-------------- + +*Copyright 2025 Analog Devices, Inc. All rights reserved. +*SPDX-License-Identifier: BSD-3-Clause* diff --git a/docs/platform/index.rst b/docs/platform/index.rst index ada59219e8..1efdf56c6b 100644 --- a/docs/platform/index.rst +++ b/docs/platform/index.rst @@ -7,6 +7,7 @@ TF-M Platforms .. toctree:: :maxdepth: 2 + Analog Devices, Inc. Arm ArmChina Cypress diff --git a/docs/platform/platform_introduction.rst b/docs/platform/platform_introduction.rst index 0075e73bca..283b3f2e4c 100644 --- a/docs/platform/platform_introduction.rst +++ b/docs/platform/platform_introduction.rst @@ -47,6 +47,8 @@ Supported Platforms `_ - `BL5340 DVK (lairdconnectivity/bl5340_dvk_cpuapp). `_ + - `MAX32657 (adi/max32657). + `_ - Cortex-M23 system: From 27ac4e5875026e8ae2111ffc6295f8236ed1b69d Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 2 Dec 2024 09:16:15 +0300 Subject: [PATCH 028/133] [zep fromtree] platform: ext: adi: Enable ADI TESA extention TESA stands for Trusted Edge Security Architecture. This commit download ADI TESA-Toolkit repository which includes binaries (that used to sign image) provisioning scripts and keys. MAX32657 has Secure Boot ROM which used to authenticite user second layer firmware for TF-M case second layer is MCUBoot. If SecureBoot ROM been activated MCUBoot need to be signed to be validated by ADI Secure BootROM. Set BL1=ON if you would like to enable Secure Boot ROM on device The MCUBoot will be signed during build if BL1 be ON bin2hex.py scripts is used to convert bl2_signed.bin to bl2_signed.hex it comes from https://github.com/python-intelhex/intelhex Change-Id: Ibb858515397ffc1d649f1cdc2c4660eba597d702 Signed-off-by: Sadik Ozer (cherry picked from commit b6d24df0e4ea7ac6b1bd840a4eeb618f1304d038) --- docs/platform/adi/max32657/README.rst | 38 ++++++ .../ext/target/adi/max32657/CMakeLists.txt | 5 + platform/ext/target/adi/max32657/config.cmake | 4 + .../target/adi/max32657/tesa-toolkit.cmake | 50 ++++++++ tools/modules/bin2hex.py | 114 ++++++++++++++++++ 5 files changed, 211 insertions(+) create mode 100644 platform/ext/target/adi/max32657/tesa-toolkit.cmake create mode 100644 tools/modules/bin2hex.py diff --git a/docs/platform/adi/max32657/README.rst b/docs/platform/adi/max32657/README.rst index 7b1737f858..2e889c6465 100644 --- a/docs/platform/adi/max32657/README.rst +++ b/docs/platform/adi/max32657/README.rst @@ -49,6 +49,40 @@ Secure Boot ROM MAX32657 has Secure Boot ROM that used to authenticate user code via ECDSA 256 public key. The Secure Boot ROM is disabled on default, to enable it user need to provision device first. +ADI provides enable_secure_boot.py (under /lib/ext/tesa-toolkit-src/devices/max32657/scripts/bl1_provision) +script to simply provision the device. This script reads user certificate via command line parameter +then writes user key on the device and disables debug interface. + +To create pub & private key pair for MAX32657 run: + +.. code-block:: bash + + openssl ecparam -out -genkey -name prime256v1 + + +.. note:: + + Debug interface will be disabled after secure boot is enabled. + User must write final firmware before provisioning the device. It can + be written during device provision, Just add your final firmware hex file in + JLinkScript under /lib/ext/tesa-toolkit-src/devices/max32657/scripts/bl1_provision folder. + + +After secure boot has been enabled BL2 image must be signed with user certificate +otherwise Secure Boot ROM will not validate BL2 image and will not execute it. +The sign process will be done automatically if BL1 be ON ``-DBL1=ON`` +The sign key can be sepecified over command line option -DTFM_BL2_SIGNING_KEY_PATH= +or by setting the flag in /platform/ext/target/adi/max32657/config.cmake +Development purpose test certificate is here: +/lib/ext/tesa-toolkit-src/devices/max32657/keys/bl1_dummy.pem +It shall not been used for production purpose just for development purpose. + +.. note:: + + The signature generation depends on ecdsa that's have to be installed:: + + pip3 install ecdsa + Building TF-M ------------- @@ -115,6 +149,10 @@ Merge hex files as follows: srec_cat.exe build_spe/bin/bl2.hex -Intel build_spe/bin/tfm_s_signed.hex -Intel build_test/bin/tfm_ns_signed.hex -Intel -o tfm_merged.hex -Intel +.. note:: + + Use bl2_signed.hex instead bl2.hex if Secure Boot ROM is enabled. + Flash them with JLink as follows: diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index be86a4f7f0..2ad596e0c4 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -105,6 +105,11 @@ if(BL2) __MXC_FLASH_MEM_SIZE=0x00100000 ) + # + # Process Trusted Edge Security Arhictecture (TESA) extention + # + include(tesa-toolkit.cmake) + endif() ###### TF-M Related Cmake Configurations ####################################### diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 0c6612d69f..bae7ce1220 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -5,6 +5,10 @@ # #------------------------------------------------------------------------------- +set(BL1 OFF CACHE BOOL "Enable/disable ADI Secure Boot ROM, BL2 image will be signed") +set(PLATFORM_DEFAULT_BL1 OFF CACHE STRING "ADI provides Secure Boot ROM so that disable default BL1") +set(TFM_BL2_SIGNING_KEY_PATH "" CACHE FILEPATH "") + set(BL2 ON CACHE BOOL "Whether to build BL2") set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_PARTITION_PLATFORM OFF CACHE BOOL "Enable Platform partition") diff --git a/platform/ext/target/adi/max32657/tesa-toolkit.cmake b/platform/ext/target/adi/max32657/tesa-toolkit.cmake new file mode 100644 index 0000000000..306c1e93f1 --- /dev/null +++ b/platform/ext/target/adi/max32657/tesa-toolkit.cmake @@ -0,0 +1,50 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +if(BL1) + set(FETCHCONTENT_QUIET TRUE) + set(TESA_TOOLKIT_PATH "DOWNLOAD" CACHE PATH "Path to TESA-Toolkit (or DOWNLOAD to fetch automatically") + set(TESA_TOOLKIT_VERSION "v1.0.0" CACHE STRING "The version of TESA-Toolkit to use") + + # Fetch TESA-Toolkit repository to sign image and provision device + fetch_remote_library( + LIB_NAME tesa-toolkit + LIB_SOURCE_PATH_VAR TESA_TOOLKIT_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/tesa-toolkit + GIT_TAG ${TESA_TOOLKIT_VERSION} + GIT_PROGRESS TRUE + ) + + # Set TFM_BL2_SIGNING_KEY_PATH as test key if it is not set + if(NOT TFM_BL2_SIGNING_KEY_PATH) + set(TFM_BL2_SIGNING_KEY_PATH "${TESA_TOOLKIT_PATH}/devices/max32657/keys/bl1_dummy.pem") + endif() + + # + # If MAX32657 SecureBoot has been enabled MCUBoot need to be signed + # to it be validated and executed by BootROM. + # + add_custom_target(bl2_signed.bin + ALL + DEPENDS $/bl2.bin + DEPENDS ${TESA_TOOLKIT_PATH}/devices/max32657/scripts/sign/sign_app.py + COMMAND echo "----------------" + COMMAND ${Python3_EXECUTABLE} ${TESA_TOOLKIT_PATH}/devices/max32657/scripts/sign/sign_app.py + --input_file $/bl2.bin + --img_output_file $/bl2_signed.bin + --sign_key_file ${TFM_BL2_SIGNING_KEY_PATH} + COMMAND echo "----------------" + COMMAND echo "Converting bl2_signed.bin to bl2_signed.hex..." + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/../../../../../tools/modules/bin2hex.py + --offset=0x11000000 + $/bl2_signed.bin + $/bl2_signed.hex + COMMAND echo "Bin2Hex conversion done." + COMMAND echo "----------------" + ) +endif() diff --git a/tools/modules/bin2hex.py b/tools/modules/bin2hex.py new file mode 100644 index 0000000000..2098e33878 --- /dev/null +++ b/tools/modules/bin2hex.py @@ -0,0 +1,114 @@ +#!/usr/bin/python +# Copyright (c) 2008-2018 Alexander Belchenko +# All rights reserved. +# +# Redistribution and use in source and binary forms, +# with or without modification, are permitted provided +# that the following conditions are met: +# +# * Redistributions of source code must retain +# the above copyright notice, this list of conditions +# and the following disclaimer. +# * Redistributions in binary form must reproduce +# the above copyright notice, this list of conditions +# and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# * Neither the name of the author nor the names +# of its contributors may be used to endorse +# or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +# BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +'''Intel HEX file format bin2hex convertor utility.''' + +VERSION = '2.3.0' + +if __name__ == '__main__': + import getopt + import os + import sys + + usage = '''Bin2Hex convertor utility. +Usage: + python bin2hex.py [options] INFILE [OUTFILE] + +Arguments: + INFILE name of bin file for processing. + Use '-' for reading from stdin. + + OUTFILE name of output file. If omitted then output + will be writing to stdout. + +Options: + -h, --help this help message. + -v, --version version info. + --offset=N offset for loading bin file (default: 0). +''' + + offset = 0 + + try: + opts, args = getopt.getopt(sys.argv[1:], "hv", + ["help", "version", "offset="]) + + for o, a in opts: + if o in ("-h", "--help"): + print(usage) + sys.exit(0) + elif o in ("-v", "--version"): + print(VERSION) + sys.exit(0) + elif o in ("--offset"): + base = 10 + if a[:2].lower() == '0x': + base = 16 + try: + offset = int(a, base) + except: + raise getopt.GetoptError('Bad offset value') + + if not args: + raise getopt.GetoptError('Input file is not specified') + + if len(args) > 2: + raise getopt.GetoptError('Too many arguments') + + except getopt.GetoptError: + msg = sys.exc_info()[1] # current exception + txt = 'ERROR: '+str(msg) # that's required to get not-so-dumb result from 2to3 tool + print(txt) + print(usage) + sys.exit(2) + + from intelhex import compat + + fin = args[0] + if fin == '-': + # read from stdin + fin = compat.get_binary_stdin() + elif not os.path.isfile(fin): + txt = "ERROR: File not found: %s" % fin # that's required to get not-so-dumb result from 2to3 tool + print(txt) + sys.exit(1) + + if len(args) == 2: + fout = args[1] + else: + # write to stdout + fout = sys.stdout # compat.get_binary_stdout() + + from intelhex import bin2hex + sys.exit(bin2hex(fin, fout, offset)) From 4d02c76e9524f2dd9c5b8b7dd7abab12eb7a3c42 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 20 Mar 2025 11:28:46 +0300 Subject: [PATCH 029/133] [zep fromtree] platform: ext: adi: Refactor MAX32657 cmake Move HAL layer files under hal_adi.cmake to simplify maintanence Change-Id: I511549147cbb05f926073710466fc4f2ed8dd057 Signed-off-by: Sadik Ozer (cherry picked from commit b3025d0c1fe138b5793aa4d17fc068cfe7bcd9ec) --- .../ext/target/adi/max32657/CMakeLists.txt | 74 +---------- .../ext/target/adi/max32657/hal_adi.cmake | 121 ++++++++++++++++++ 2 files changed, 123 insertions(+), 72 deletions(-) create mode 100644 platform/ext/target/adi/max32657/hal_adi.cmake diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 2ad596e0c4..3ee0d8bc30 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -10,28 +10,8 @@ set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) ################################################################################ -# Fetch hal_adi repository -fetch_remote_library( - LIB_NAME hal_adi - LIB_SOURCE_PATH_VAR HAL_ADI_PATH - FETCH_CONTENT_ARGS - GIT_REPOSITORY https://github.com/analogdevicesinc/hal_adi - GIT_TAG ${HAL_ADI_VERSION} - GIT_PROGRESS TRUE -) - -set(TARGET_LC "max32657") -string(TOUPPER ${TARGET_LC} TARGET_UC) - -set(HAL_ADI_LIBRARY_DIR ${HAL_ADI_PATH}/MAX/Libraries) - -set(HAL_ADI_CMSIS_DIR ${HAL_ADI_LIBRARY_DIR}/CMSIS/Device/Maxim/${TARGET_UC}) -set(HAL_ADI_CMSIS_INC_DIR ${HAL_ADI_CMSIS_DIR}/Include) -set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source) - -set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers) -set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC}) -set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) +# Add hal_adi in build system +include(hal_adi.cmake) ########################## Platform region defs ################################ target_include_directories(platform_region_defs @@ -59,8 +39,6 @@ if(BL2) target_include_directories(platform_bl2 PUBLIC partition - ${HAL_ADI_PERIPH_INC_DIR} - ${HAL_ADI_CMSIS_INC_DIR} PRIVATE . ${PLATFORM_DIR}/.. @@ -76,33 +54,11 @@ if(BL2) cmsis_drivers/Driver_Flash.c cmsis_drivers/Driver_USART.c $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> - - ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c - ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c - ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c - ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c - ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c - ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c - ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c ) target_compile_definitions(platform_bl2 PUBLIC - TARGET=${TARGET_UC} - TARGET_REV=0x4131 CMSIS_device_header="${TARGET_LC}.h" - CONFIG_TRUSTED_EXECUTION_SECURE - IS_SECURE_ENVIRONMENT - - __MXC_FLASH_MEM_BASE=0x11000000 - __MXC_FLASH_MEM_SIZE=0x00100000 ) # @@ -151,14 +107,7 @@ target_sources(tfm_spm target_compile_definitions(platform_s PUBLIC - TARGET=${TARGET_UC} - TARGET_REV=0x4131 CMSIS_device_header="${TARGET_LC}.h" - CONFIG_TRUSTED_EXECUTION_SECURE - IS_SECURE_ENVIRONMENT - - __MXC_FLASH_MEM_BASE=0x11000000 - __MXC_FLASH_MEM_SIZE=0x00100000 $<$:TFM_S_REG_TEST> $<$:TFM_NS_REG_TEST> @@ -178,23 +127,6 @@ target_sources(platform_s cmsis_drivers/Driver_MPC.c device/src/mpc_sie200_drv.c $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> - ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c - - ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c - ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c - ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c - ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c - ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c - ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c - ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/TZ/spc_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c - ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_hal_ioctl.c> @@ -207,8 +139,6 @@ target_include_directories(platform_s partition device/inc services/include - ${HAL_ADI_PERIPH_INC_DIR} - ${HAL_ADI_CMSIS_INC_DIR} ${PLATFORM_DIR}/.. ) diff --git a/platform/ext/target/adi/max32657/hal_adi.cmake b/platform/ext/target/adi/max32657/hal_adi.cmake new file mode 100644 index 0000000000..a3a8bd76ca --- /dev/null +++ b/platform/ext/target/adi/max32657/hal_adi.cmake @@ -0,0 +1,121 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +################################################################################ +# Fetch hal_adi repository +set(FETCHCONTENT_QUIET TRUE) + +fetch_remote_library( + LIB_NAME hal_adi + LIB_SOURCE_PATH_VAR HAL_ADI_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/hal_adi + GIT_TAG ${HAL_ADI_VERSION} + GIT_PROGRESS TRUE +) + +set(TARGET_LC "max32657" CACHE STRING "") +string(TOUPPER ${TARGET_LC} TARGET_UC) + +set(HAL_ADI_PATH ${HAL_ADI_PATH} CACHE PATH "") +set(HAL_ADI_LIBRARY_DIR ${HAL_ADI_PATH}/MAX/Libraries CACHE PATH "") + +set(HAL_ADI_CMSIS_DIR ${HAL_ADI_LIBRARY_DIR}/CMSIS/Device/Maxim/${TARGET_UC} CACHE PATH "") +set(HAL_ADI_CMSIS_INC_DIR ${HAL_ADI_CMSIS_DIR}/Include CACHE PATH "") +set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source CACHE PATH "") + +set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers CACHE PATH "") +set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC} CACHE PATH "") +set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source CACHE PATH "") + + +###### BL2 Related Cmake Configurations ######################################## +if(BL2) + target_include_directories(platform_bl2 + PUBLIC + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} + ) + + target_sources(platform_bl2 + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c + ) + + target_compile_definitions(platform_bl2 + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 + ) +endif() # BL2 + + +###### TFM Related Cmake Configurations ######################################## +target_compile_definitions(platform_s + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 +) + +target_include_directories(platform_s + PUBLIC + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} +) + +target_sources(platform_s + PRIVATE + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c + + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + + ${HAL_ADI_PERIPH_SRC_DIR}/TZ/spc_me30.c + + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c +) From 9d7af0dae2f08de2e63dfb6578844cc6532f17c8 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 25 Feb 2025 14:27:53 +0300 Subject: [PATCH 030/133] [zep fromtree] platform: ext: adi: Configure S-NS peripherals ownership Add configuration flags to define peripherals ownerships either secure or non-secure Remove ICE_IRQn and ECC_IRQn fron NS due to this peripherals not accessible by NS world User can configure peripheral ownership over s_ns_access_overlay.cmake file. This file need to be defined in the project folder root folder. On default NS world control all peripheral. As an example to transfer gpio and timer0 on the secure world write below lines in the overlay file. ... set(ADI_NS_PRPH_GPIO0 OFF) set(ADI_NS_PRPH_TIMER0 OFF) ... s_ns_access_overlay.cmake file must be defined in the project workspace root folder. Change-Id: I37ab37ef600043707cc88aac046e4c3ce8ff903f Signed-off-by: Sadik Ozer (cherry picked from commit 1bd0c2d3a2dde1be3914e3784eadcbbdbcb6af92) --- .../ext/target/adi/max32657/CMakeLists.txt | 41 +++++ .../ext/target/adi/max32657/ns/CMakeLists.txt | 3 + .../ext/target/adi/max32657/s_ns_access.cmake | 43 +++++ platform/ext/target/adi/max32657/target_cfg.c | 156 ++++++++++++++---- 4 files changed, 209 insertions(+), 34 deletions(-) create mode 100644 platform/ext/target/adi/max32657/s_ns_access.cmake diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 3ee0d8bc30..1368217246 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -10,6 +10,9 @@ set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) ################################################################################ +# Get S - NS peripheral and memory access +include(s_ns_access.cmake) + # Add hal_adi in build system include(hal_adi.cmake) @@ -204,3 +207,41 @@ install(FILES ${TARGET_PLATFORM_PATH}/config.cmake # Install test configs install(DIRECTORY ${TARGET_PLATFORM_PATH}/tests DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Copy the S-NS peripheral & memory configuration +install(FILES ${TARGET_PLATFORM_PATH}/s_ns_access.cmake + DESTINATION ${CMAKE_BINARY_DIR}/../) + +# Export configuration flags +target_compile_definitions(tfm_spm + PUBLIC + $<$:ADI_NS_PRPH_GCR> + $<$:ADI_NS_PRPH_SIR> + $<$:ADI_NS_PRPH_FCR> + $<$:ADI_NS_PRPH_WDT> + $<$:ADI_NS_PRPH_AES> + $<$:ADI_NS_PRPH_AESKEY> + $<$:ADI_NS_PRPH_CRC> + $<$:ADI_NS_PRPH_GPIO0> + $<$:ADI_NS_PRPH_TIMER0> + $<$:ADI_NS_PRPH_TIMER1> + $<$:ADI_NS_PRPH_TIMER2> + $<$:ADI_NS_PRPH_TIMER3> + $<$:ADI_NS_PRPH_TIMER4> + $<$:ADI_NS_PRPH_TIMER5> + $<$:ADI_NS_PRPH_I3C> + $<$:ADI_NS_PRPH_UART> + $<$:ADI_NS_PRPH_SPI> + $<$:ADI_NS_PRPH_TRNG> + $<$:ADI_NS_PRPH_BTLE_DBB> + $<$:ADI_NS_PRPH_BTLE_RFFE> + $<$:ADI_NS_PRPH_RSTZ> + $<$:ADI_NS_PRPH_BOOST> + $<$:ADI_NS_PRPH_BBSIR> + $<$:ADI_NS_PRPH_BBFCR> + $<$:ADI_NS_PRPH_RTC> + $<$:ADI_NS_PRPH_WUT0> + $<$:ADI_NS_PRPH_WUT1> + $<$:ADI_NS_PRPH_PWR> + $<$:ADI_NS_PRPH_MCR> +) diff --git a/platform/ext/target/adi/max32657/ns/CMakeLists.txt b/platform/ext/target/adi/max32657/ns/CMakeLists.txt index 8aa3f52bdb..ed25b8df6d 100644 --- a/platform/ext/target/adi/max32657/ns/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/ns/CMakeLists.txt @@ -84,3 +84,6 @@ target_include_directories(platform_region_defs INTERFACE include ) + +# Get S - NS peripheral and memory access +include(${CMAKE_BINARY_DIR}/../s_ns_access.cmake) diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake new file mode 100644 index 0000000000..315d9fa64b --- /dev/null +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(ADI_NS_PRPH_GCR ON CACHE BOOL "") +set(ADI_NS_PRPH_SIR ON CACHE BOOL "") +set(ADI_NS_PRPH_FCR ON CACHE BOOL "") +set(ADI_NS_PRPH_WDT ON CACHE BOOL "") +set(ADI_NS_PRPH_AES ON CACHE BOOL "") +set(ADI_NS_PRPH_AESKEY ON CACHE BOOL "") +set(ADI_NS_PRPH_CRC ON CACHE BOOL "") +set(ADI_NS_PRPH_GPIO0 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER0 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER1 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER2 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER3 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER4 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") +set(ADI_NS_PRPH_I3C ON CACHE BOOL "") +set(ADI_NS_PRPH_UART ON CACHE BOOL "") +set(ADI_NS_PRPH_SPI ON CACHE BOOL "") +set(ADI_NS_PRPH_TRNG ON CACHE BOOL "") +set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") +set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") +set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") +set(ADI_NS_PRPH_BOOST ON CACHE BOOL "") +set(ADI_NS_PRPH_BBSIR ON CACHE BOOL "") +set(ADI_NS_PRPH_BBFCR ON CACHE BOOL "") +set(ADI_NS_PRPH_RTC ON CACHE BOOL "") +set(ADI_NS_PRPH_WUT0 ON CACHE BOOL "") +set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") +set(ADI_NS_PRPH_PWR ON CACHE BOOL "") +set(ADI_NS_PRPH_MCR ON CACHE BOOL "") + +# +# Allow user set S-NS resources ownership by overlay file +# +if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") + include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) +endif() diff --git a/platform/ext/target/adi/max32657/target_cfg.c b/platform/ext/target/adi/max32657/target_cfg.c index cd77afd20c..a68eab51e5 100644 --- a/platform/ext/target/adi/max32657/target_cfg.c +++ b/platform/ext/target/adi/max32657/target_cfg.c @@ -130,68 +130,156 @@ static NS_MPC_Config ns_mpc_config_arr[] = { */ uint8_t ns_periph_arr[] = { - SPC_GCR, - SPC_SIR, - SPC_FCR, - SPC_WDT, - SPC_AES, - SPC_AESKEY, - SPC_CRC, - SPC_GPIO0, - SPC_TIMER0, - SPC_TIMER1, - SPC_TIMER2, - SPC_TIMER3, - SPC_TIMER4, - SPC_TIMER5, - SPC_I3C, -#if !defined(TFM_S_REG_TEST) - SPC_UART, -#endif - SPC_SPI, - SPC_TRNG, - SPC_BTLE_DBB, - SPC_BTLE_RFFE, - SPC_RSTZ, - SPC_BOOST, - SPC_BBSIR, - SPC_BBFCR, - SPC_RTC, - SPC_WUT0, - SPC_WUT1, - SPC_PWR, - SPC_MCR, +#if defined(ADI_NS_PRPH_GCR) + SPC_GCR, +#endif +#if defined(ADI_NS_PRPH_SIR) + SPC_SIR, +#endif +#if defined(ADI_NS_PRPH_FCR) + SPC_FCR, +#endif +#if defined(ADI_NS_PRPH_WDT) + SPC_WDT, +#endif +#if defined(ADI_NS_PRPH_AES) + SPC_AES, +#endif +#if defined(ADI_NS_PRPH_AESKEY) + SPC_AESKEY, +#endif +#if defined(ADI_NS_PRPH_CRC) + SPC_CRC, +#endif +#if defined(ADI_NS_PRPH_GPIO0) + SPC_GPIO0, +#endif +#if defined(ADI_NS_PRPH_TIMER0) + SPC_TIMER0, +#endif +#if defined(ADI_NS_PRPH_TIMER1) + SPC_TIMER1, +#endif +#if defined(ADI_NS_PRPH_TIMER2) + SPC_TIMER2, +#endif +#if defined(ADI_NS_PRPH_TIMER3) + SPC_TIMER3, +#endif +#if defined(ADI_NS_PRPH_TIMER4) + SPC_TIMER4, +#endif +#if defined(ADI_NS_PRPH_TIMER5) + SPC_TIMER5, +#endif +#if defined(ADI_NS_PRPH_I3C) + SPC_I3C, +#endif +#if defined(ADI_NS_PRPH_UART) && !defined(TFM_S_REG_TEST) + SPC_UART, +#endif +#if defined(ADI_NS_PRPH_SPI) + SPC_SPI, +#endif +#if defined(ADI_NS_PRPH_TRNG) + SPC_TRNG, +#endif +#if defined(ADI_NS_PRPH_BTLE_DBB) + SPC_BTLE_DBB, +#endif +#if defined(ADI_NS_PRPH_BTLE_RFFE) + SPC_BTLE_RFFE, +#endif +#if defined(ADI_NS_PRPH_RSTZ) + SPC_RSTZ, +#endif +#if defined(ADI_NS_PRPH_BOOST) + SPC_BOOST, +#endif +#if defined(ADI_NS_PRPH_BBSIR) + SPC_BBSIR, +#endif +#if defined(ADI_NS_PRPH_BBFCR) + SPC_BBFCR, +#endif +#if defined(ADI_NS_PRPH_RTC) + SPC_RTC, +#endif +#if defined(ADI_NS_PRPH_WUT0) + SPC_WUT0, +#endif +#if defined(ADI_NS_PRPH_WUT1) + SPC_WUT1, +#endif +#if defined(ADI_NS_PRPH_PWR) + SPC_PWR, +#endif +#if defined(ADI_NS_PRPH_MCR) + SPC_MCR, +#endif }; uint8_t nvic_set_ns[] = { - ICE_IRQn, +#if defined(ADI_NS_PRPH_WDT) WDT_IRQn, +#endif +#if defined(ADI_NS_PRPH_RTC) RTC_IRQn, +#endif +#if defined(ADI_NS_PRPH_TRNG) TRNG_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER0) TMR0_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER1) TMR1_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER2) TMR2_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER3) TMR3_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER4) TMR4_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER5) TMR5_IRQn, +#endif +#if defined(ADI_NS_PRPH_I3C) I3C_IRQn, -#if !defined(TFM_S_REG_TEST) +#endif +#if defined(ADI_NS_PRPH_UART) && !defined(TFM_S_REG_TEST) UART_IRQn, #endif +#if defined(ADI_NS_PRPH_SPI) SPI_IRQn, +#endif +#if defined(ADI_NS_PRPH_GPIO0) GPIO0_IRQn, +#endif DMA0_CH0_IRQn, DMA0_CH1_IRQn, DMA0_CH2_IRQn, DMA0_CH3_IRQn, +#if defined(ADI_NS_PRPH_WUT0) WUT0_IRQn, +#endif +#if defined(ADI_NS_PRPH_WUT1) WUT1_IRQn, +#endif +#if defined(ADI_NS_PRPH_GPIO0) GPIOWAKE_IRQn, +#endif +#if defined(ADI_NS_PRPH_CRC) CRC_IRQn, +#endif +#if defined(ADI_NS_PRPH_AES) AES_IRQn, +#endif ERFO_IRQn, BOOST_IRQn, - ECC_IRQn, BTLE_TX_DONE_IRQn, BTLE_RX_RCVD_IRQn, BTLE_RX_ENG_DET_IRQn, From 4436d965b8dcc587d9577d6e2334bec9e3bff144 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 20 Mar 2025 11:47:44 +0300 Subject: [PATCH 031/133] [zep fromtree] platform: ext: adi: Add hal_adi peripheral files Add other hal_adi peripeherals files. Conditional build flag added to decrease build time by excluding files Condition build flags not added for some peripherals, like trng to simplify use them Change-Id: Ib4c6330334483776f115beaf5b1334afe0e27c06 Signed-off-by: Sadik Ozer (cherry picked from commit 45609be7639d10c41b41967209680ed7b69ab41a) --- .../ext/target/adi/max32657/hal_adi.cmake | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/platform/ext/target/adi/max32657/hal_adi.cmake b/platform/ext/target/adi/max32657/hal_adi.cmake index a3a8bd76ca..e19dd40723 100644 --- a/platform/ext/target/adi/max32657/hal_adi.cmake +++ b/platform/ext/target/adi/max32657/hal_adi.cmake @@ -60,6 +60,9 @@ if(BL2) ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_reva.c ) target_compile_definitions(platform_bl2 @@ -91,6 +94,23 @@ target_include_directories(platform_s PUBLIC ${HAL_ADI_PERIPH_INC_DIR} ${HAL_ADI_CMSIS_INC_DIR} + + ${HAL_ADI_PERIPH_SRC_DIR}/SYS + ${HAL_ADI_PERIPH_SRC_DIR}/AES + ${HAL_ADI_PERIPH_SRC_DIR}/CRC + ${HAL_ADI_PERIPH_SRC_DIR}/DMA + ${HAL_ADI_PERIPH_SRC_DIR}/FLC + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO + ${HAL_ADI_PERIPH_SRC_DIR}/I3C + ${HAL_ADI_PERIPH_SRC_DIR}/ICC + ${HAL_ADI_PERIPH_SRC_DIR}/LP + ${HAL_ADI_PERIPH_SRC_DIR}/RTC + ${HAL_ADI_PERIPH_SRC_DIR}/SPI + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG + ${HAL_ADI_PERIPH_SRC_DIR}/TMR + ${HAL_ADI_PERIPH_SRC_DIR}/UART + ${HAL_ADI_PERIPH_SRC_DIR}/WDT + ${HAL_ADI_PERIPH_SRC_DIR}/WUT ) target_sources(platform_s @@ -118,4 +138,73 @@ target_sources(platform_s ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG/trng_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG/trng_revb.c + + ${HAL_ADI_PERIPH_SRC_DIR}/AES/aes_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/AES/aes_revb.c + + ${HAL_ADI_PERIPH_SRC_DIR}/CRC/crc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/CRC/crc_reva.c ) + +if(NOT ADI_NS_PRPH_I3C) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/I3C/i3c_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/I3C/i3c_reva.c + ) +endif() + +if(NOT ADI_NS_PRPH_SPI) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/SPI/spi_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SPI/spi_reva1.c + ) +endif() + +if(NOT ADI_NS_PRPH_WDT) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/WDT/wdt_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/WDT/wdt_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/WDT/wdt_revb.c + ) +endif() + +if(NOT ADI_NS_PRPH_RTC) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/RTC/rtc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/RTC/rtc_reva.c + ) +endif() + +if(NOT (ADI_NS_PRPH_WUT0 AND ADI_NS_PRPH_WUT1)) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/WUT/wut_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/WUT/wut_reva.c + ) +endif() + +if(NOT ( ADI_NS_PRPH_TIMER0 + AND ADI_NS_PRPH_TIMER1 + AND ADI_NS_PRPH_TIMER2 + AND ADI_NS_PRPH_TIMER3 + AND ADI_NS_PRPH_TIMER4 + AND ADI_NS_PRPH_TIMER5 + ) + ) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/TMR/tmr_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/TMR/tmr_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/TMR/tmr_revb.c + ) +endif() From fdeb4db50a06d020714c28155277f772c729f290 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 20 Mar 2025 13:02:40 +0300 Subject: [PATCH 032/133] [zep fromtree] platform: ext: adi: Add a weak function for peripheral init Allow user to configure peripherals by overwrite PeripheralInit function. This feature will be used by ADI Code Fusion Stuido (CFS) tool which provides a GUI interface that allow user select peripheral and configuration device peripherals. The CFS will generate source code as per of user selection over GUI. The source code will be written in adi_soc_init.c file under project root folder. Change-Id: I758a10c61b32b2c5a6c72aae55be6a10eeeb93fa Signed-off-by: Sadik Ozer (cherry picked from commit 935b59f6f36a05c2e70f3cc5b4bcff04a451b1d1) --- platform/ext/target/adi/max32657/CMakeLists.txt | 7 +++++++ .../target/adi/max32657/device/src/system_max32657.c | 10 ++++++++++ 2 files changed, 17 insertions(+) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 1368217246..9b310c5310 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -89,6 +89,13 @@ target_sources(tfm_s ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c ) +if(EXISTS "${CMAKE_BINARY_DIR}/../../adi_soc_peripheral_init.c") + target_sources(tfm_s + PRIVATE + ${CMAKE_BINARY_DIR}/../../adi_soc_peripheral_init.c + ) +endif() + target_compile_definitions(tfm_s PUBLIC TARGET=${TARGET_UC} diff --git a/platform/ext/target/adi/max32657/device/src/system_max32657.c b/platform/ext/target/adi/max32657/device/src/system_max32657.c index 7fa6aa865d..be04a63baa 100644 --- a/platform/ext/target/adi/max32657/device/src/system_max32657.c +++ b/platform/ext/target/adi/max32657/device/src/system_max32657.c @@ -46,6 +46,11 @@ __weak int _kill(void) return E_NOT_SUPPORTED; } +__weak int PeripheralInit(void) +{ + return E_NO_ERROR; +} + __weak void SystemCoreClockUpdate(void) { uint32_t base_freq, div, clk_src; @@ -125,6 +130,11 @@ void SystemInit(void) MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); +#if CONFIG_TRUSTED_EXECUTION_SECURE + /* Init peripherals */ + PeripheralInit(); +#endif + /* * FPCA bit of CONTROL register can be enabled while * performing floating point operation in Secure domain. From 63d885b95a324b90cbdd8f2c2a8e58ff20d08ff3 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 11 Mar 2025 14:37:00 +0300 Subject: [PATCH 033/133] [zep fromtree] platform: ext: adi: Configure SRAM over overlay file Add configuration parameters for SRAM to it be configurable over an overlay file this. Change-Id: Icad005694324033f4aff623755b23ec01d701c30 Signed-off-by: Sadik Ozer (cherry picked from commit a51835d11fb7c8383b98fad2128552ccb171aa6d) --- .../adi/max32657/partition/flash_layout.h | 67 +++++++++++++++++++ .../adi/max32657/partition/region_defs.h | 10 ++- .../ext/target/adi/max32657/s_ns_access.cmake | 17 +++++ platform/ext/target/adi/max32657/target_cfg.c | 20 ++++++ 4 files changed, 112 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/adi/max32657/partition/flash_layout.h b/platform/ext/target/adi/max32657/partition/flash_layout.h index 86b6bcba0e..c5b81a1c22 100644 --- a/platform/ext/target/adi/max32657/partition/flash_layout.h +++ b/platform/ext/target/adi/max32657/partition/flash_layout.h @@ -225,4 +225,71 @@ #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE #define TOTAL_RAM_SIZE KB(256) +// SRAM_0 +#define MAX32657_SRAM0_OFFSET 0 +#define MAX32657_SRAM0_SIZE KB(32) +// SRAM_1 +#define MAX32657_SRAM1_OFFSET 0x00008000UL +#define MAX32657_SRAM1_SIZE KB(32) +// SRAM_2 +#define MAX32657_SRAM2_OFFSET 0x00010000UL +#define MAX32657_SRAM2_SIZE KB(64) +// SRAM_3 +#define MAX32657_SRAM3_OFFSET 0x00020000UL +#define MAX32657_SRAM3_SIZE KB(64) +// SRAM_4 +#define MAX32657_SRAM4_OFFSET 0x00030000UL +#define MAX32657_SRAM4_SIZE KB(64) + + +#if defined(ADI_NS_SRAM_0) + #define MAX32657_S_SRAM0_SIZE 0 +#else + #define MAX32657_S_SRAM0_SIZE MAX32657_SRAM0_SIZE +#endif + +#if defined(ADI_NS_SRAM_1) + #define MAX32657_S_SRAM1_SIZE 0 +#else + #define MAX32657_S_SRAM1_SIZE MAX32657_SRAM1_SIZE +#endif + +#if defined(ADI_NS_SRAM_2) + #define MAX32657_S_SRAM2_SIZE 0 +#else + #define MAX32657_S_SRAM2_SIZE MAX32657_SRAM2_SIZE +#endif + +#if defined(ADI_NS_SRAM_3) + #define MAX32657_S_SRAM3_SIZE 0 +#else + #define MAX32657_S_SRAM3_SIZE MAX32657_SRAM3_SIZE +#endif + +#if defined(ADI_NS_SRAM_4) + #define MAX32657_S_SRAM4_SIZE 0 +#else + #define MAX32657_S_SRAM4_SIZE MAX32657_SRAM4_SIZE +#endif + +/* RAM shall be defined sequential */ +#if !defined(ADI_NS_SRAM_0) + // SRAM0 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM0_OFFSET +#elif !defined(ADI_NS_SRAM_1) + // SRAM1 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM1_OFFSET +#elif !defined(ADI_NS_SRAM_2) + // SRAM2 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM2_OFFSET +#elif !defined(ADI_NS_SRAM_3) + // SRAM3 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM3_OFFSET +#elif !defined(ADI_NS_SRAM_4) + // SRAM4 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM4_OFFSET +#else + #error "SRAM Not Defined for TF-M" +#endif + #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h index 5de67cd5d0..575cd724b6 100644 --- a/platform/ext/target/adi/max32657/partition/region_defs.h +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -92,10 +92,16 @@ /* Size of vector table: 69 interrupt handlers + 16 bytes of reserved space */ #define S_CODE_VECTOR_TABLE_SIZE (0x00000124) -#define S_TOTAL_DATA_SIZE KB(64) +/* Set Secure FW SRAM Size */ +#define S_TOTAL_DATA_SIZE ( MAX32657_S_SRAM0_SIZE + \ + MAX32657_S_SRAM1_SIZE + \ + MAX32657_S_SRAM2_SIZE + \ + MAX32657_S_SRAM3_SIZE + \ + MAX32657_S_SRAM4_SIZE ) + #define S_RAM_CODE_SIZE KB(1) /* ramfuncs section size*/ -#define S_DATA_START (S_RAM_ALIAS(0x00000000)) +#define S_DATA_START (S_RAM_ALIAS(MAX32657_S_DATA_OFFSET)) #define S_DATA_SIZE (S_TOTAL_DATA_SIZE - S_RAM_CODE_SIZE) #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake index 315d9fa64b..13eab97fd1 100644 --- a/platform/ext/target/adi/max32657/s_ns_access.cmake +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -35,9 +35,26 @@ set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") set(ADI_NS_PRPH_PWR ON CACHE BOOL "") set(ADI_NS_PRPH_MCR ON CACHE BOOL "") +# SRAMs +set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") +set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") +set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") +set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") +set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") + # # Allow user set S-NS resources ownership by overlay file # if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) endif() + +target_compile_definitions(platform_region_defs + INTERFACE + # SRAMs + $<$:ADI_NS_SRAM_0> + $<$:ADI_NS_SRAM_1> + $<$:ADI_NS_SRAM_2> + $<$:ADI_NS_SRAM_3> + $<$:ADI_NS_SRAM_4> +) diff --git a/platform/ext/target/adi/max32657/target_cfg.c b/platform/ext/target/adi/max32657/target_cfg.c index a68eab51e5..45e008dbe4 100644 --- a/platform/ext/target/adi/max32657/target_cfg.c +++ b/platform/ext/target/adi/max32657/target_cfg.c @@ -102,21 +102,41 @@ typedef struct { * */ static NS_MPC_Config ns_mpc_config_arr[] = { +#if defined(ADI_NS_SRAM_0) + { + &Driver_SRAM0_MPC, + MPC_SRAM0_RANGE_BASE_NS, + MPC_SRAM0_RANGE_LIMIT_NS + }, +#endif +#if defined(ADI_NS_SRAM_1) + { + &Driver_SRAM1_MPC, + MPC_SRAM1_RANGE_BASE_NS, + MPC_SRAM1_RANGE_LIMIT_NS + }, +#endif +#if defined(ADI_NS_SRAM_2) { &Driver_SRAM2_MPC, MPC_SRAM2_RANGE_BASE_NS, MPC_SRAM2_RANGE_LIMIT_NS }, +#endif +#if defined(ADI_NS_SRAM_3) { &Driver_SRAM3_MPC, MPC_SRAM3_RANGE_BASE_NS, MPC_SRAM3_RANGE_LIMIT_NS }, +#endif +#if defined(ADI_NS_SRAM_4) { &Driver_SRAM4_MPC, MPC_SRAM4_RANGE_BASE_NS, MPC_SRAM4_RANGE_LIMIT_NS }, +#endif { &Driver_FLASH_MPC, memory_regions.non_secure_partition_base, From 60567eac300ac21ae74fd1e9600aef2e155e314c Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 18 Mar 2025 11:42:08 +0300 Subject: [PATCH 034/133] [zep fromtree] platform: ext: adi: Configure flash section over overlay file Add configuration parameters for flash to it be configurable over an overlay file. Co-authored-by: Jayashree Srinivasan Change-Id: I2719f957d835e780019b4bcdce9ac0d281698a7d Signed-off-by: Sadik Ozer (cherry picked from commit 26f9846c071382ccf694cfe036d769ac1f16ae2e) --- .../ext/target/adi/max32657/partition/flash_layout.h | 6 +++--- platform/ext/target/adi/max32657/s_ns_access.cmake | 10 ++++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/adi/max32657/partition/flash_layout.h b/platform/ext/target/adi/max32657/partition/flash_layout.h index c5b81a1c22..ac541f440c 100644 --- a/platform/ext/target/adi/max32657/partition/flash_layout.h +++ b/platform/ext/target/adi/max32657/partition/flash_layout.h @@ -67,8 +67,8 @@ #endif /* Size of a Secure and of a Non-secure image */ -#define FLASH_S_PARTITION_SIZE (0x50000) /* S partition: 320 KB */ -#define FLASH_NS_PARTITION_SIZE (0x90000) /* NS partition: 576 KB */ +#define FLASH_S_PARTITION_SIZE ADI_FLASH_S_PARTITION_SIZE +#define FLASH_NS_PARTITION_SIZE ADI_FLASH_NS_PARTITION_SIZE #if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) #define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE @@ -90,7 +90,7 @@ * swapping. */ #define FLASH_AREA_BL2_OFFSET (0) -#define FLASH_AREA_BL2_SIZE KB(64) +#define FLASH_AREA_BL2_SIZE ADI_FLASH_AREA_BL2_SIZE #if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) /* Secure + Non-secure image primary slot */ diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake index 13eab97fd1..d429293978 100644 --- a/platform/ext/target/adi/max32657/s_ns_access.cmake +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -42,6 +42,11 @@ set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") +# Flash: BL2, TFM and Zephyr are contiguous sections. +set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") +set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") +set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") + # # Allow user set S-NS resources ownership by overlay file # @@ -57,4 +62,9 @@ target_compile_definitions(platform_region_defs $<$:ADI_NS_SRAM_2> $<$:ADI_NS_SRAM_3> $<$:ADI_NS_SRAM_4> + + # Flash + ADI_FLASH_AREA_BL2_SIZE=${ADI_FLASH_AREA_BL2_SIZE} + ADI_FLASH_S_PARTITION_SIZE=${ADI_FLASH_S_PARTITION_SIZE} + ADI_FLASH_NS_PARTITION_SIZE=${ADI_FLASH_NS_PARTITION_SIZE} ) From 604f051d16444d09383b59498fabffa264cc69d9 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Wed, 19 Mar 2025 18:38:29 +0300 Subject: [PATCH 035/133] [zep fromtree] platform: ext: adi: Update tfm_common_s.ld file path tfm_common_s file location is changed on main branch This commit update it. Change-Id: Iaf4f3b162e826570482d3262a54a71a7e52e3f3c Signed-off-by: Sadik Ozer (cherry picked from commit ac4218ae00dae87d0a2d602c77037ac0e9eabcd4) --- platform/ext/target/adi/max32657/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 9b310c5310..1f50bfed6e 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -80,7 +80,7 @@ target_compile_definitions(tfm_s ) target_add_scatter_file(tfm_s - $<$:${PLATFORM_DIR}/ext/common/gcc/tfm_common_s.ld> + $<$:${CMAKE_BINARY_DIR}/generated/platform/ext/common/gcc/tfm_common_s.ld> ) target_sources(tfm_s From 8fa71ece63dd7bf0694f3379b4c75da11050c73d Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Fri, 21 Mar 2025 14:57:27 -0400 Subject: [PATCH 036/133] [zep fromtree] platform: ext: adi: pull in update from TF-M main Pull in TF-M main commit 152f7866f4e87d105277bd0375d57f8837d6015f Change-Id: I7d5acb11ab1e8f7a8677b65404133d15630536a9 Signed-off-by: Hao Zhang (cherry picked from commit dd897dee83aeb7be204c4f27ea317743c6f78e65) --- platform/ext/target/adi/max32657/partition/region_defs.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h index 575cd724b6..a6d0c55ea5 100644 --- a/platform/ext/target/adi/max32657/partition/region_defs.h +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -167,6 +167,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE KB(1) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START (BL2_DATA_START + BL2_DATA_SIZE - KB(32)) #define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) From 72f70491970fc9d53ab37a2bc30825c242b4fa39 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Fri, 21 Mar 2025 14:57:27 -0400 Subject: [PATCH 037/133] [zep fromtree] platform: ext: adi: Fix MAX32657 build issue Update adi MAX32657 to resolve build error Driver Driver_USART.h and Driver_Common.h not necessary anymore for main branch Change-Id: I7437923b5a7737d459e235e9ed25c34d6bb67650 Signed-off-by: Hao Zhang (cherry picked from commit ab903e80daf5fa0fc38c8190a683f113ee01f2da) --- platform/ext/target/adi/max32657/CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 1f50bfed6e..1d28526229 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -178,8 +178,6 @@ install(FILES ${TARGET_PLATFORM_PATH}/partition/region_defs.h ${TARGET_PLATFORM_PATH}/RTE_Device.h ${TARGET_PLATFORM_PATH}/cmsis.h ${PLATFORM_DIR}/ext/common/test_interrupt.h - ${PLATFORM_DIR}/ext/driver/Driver_USART.h - ${PLATFORM_DIR}/ext/driver/Driver_Common.h ${PLATFORM_DIR}/include/tfm_plat_defs.h ${CMAKE_SOURCE_DIR}/lib/fih/inc/fih.h DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include) From 7716e2fbdc967874e80383fb4539d1695a1a1eda Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 25 Mar 2025 10:49:04 +0300 Subject: [PATCH 038/133] [zep fromtree] platform: ext: adi: Add configuration flags for ITS, PS... Add configuration flags for ITS, PS, and CODE_RAM section To they be configurable over CFS GUI incase of need. Change-Id: I70cae914745a90f8d1858be7895755912d25d8bb Signed-off-by: Sadik Ozer (cherry picked from commit 2468124b3cbc1e76d2314dc0be41d50f495178b1) --- .../ext/target/adi/max32657/partition/flash_layout.h | 4 ++-- .../ext/target/adi/max32657/partition/region_defs.h | 2 +- platform/ext/target/adi/max32657/s_ns_access.cmake | 11 +++++++++++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/adi/max32657/partition/flash_layout.h b/platform/ext/target/adi/max32657/partition/flash_layout.h index ac541f440c..bd6833db83 100644 --- a/platform/ext/target/adi/max32657/partition/flash_layout.h +++ b/platform/ext/target/adi/max32657/partition/flash_layout.h @@ -144,11 +144,11 @@ /* Protected Storage (PS) Service definitions */ #define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + FLASH_AREA_SCRATCH_SIZE) -#define FLASH_PS_AREA_SIZE KB(0) /* 0 KB */ +#define FLASH_PS_AREA_SIZE ADI_FLASH_PS_AREA_SIZE /* Internal Trusted Storage (ITS) Service definitions */ #define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) -#define FLASH_ITS_AREA_SIZE KB(16) +#define FLASH_ITS_AREA_SIZE ADI_FLASH_ITS_AREA_SIZE /* Placing OTP backup area in Flash because of limited availability of Secure Flash Info area */ #define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h index a6d0c55ea5..722011cc9b 100644 --- a/platform/ext/target/adi/max32657/partition/region_defs.h +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -99,7 +99,7 @@ MAX32657_S_SRAM3_SIZE + \ MAX32657_S_SRAM4_SIZE ) -#define S_RAM_CODE_SIZE KB(1) /* ramfuncs section size*/ +#define S_RAM_CODE_SIZE ADI_S_RAM_CODE_SIZE /* ramfuncs section size*/ #define S_DATA_START (S_RAM_ALIAS(MAX32657_S_DATA_OFFSET)) #define S_DATA_SIZE (S_TOTAL_DATA_SIZE - S_RAM_CODE_SIZE) diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake index d429293978..61e6f04625 100644 --- a/platform/ext/target/adi/max32657/s_ns_access.cmake +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -42,10 +42,16 @@ set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") +# Ramfuncs section size +set(ADI_S_RAM_CODE_SIZE "0x400" CACHE STRING "Default: 1KB") + # Flash: BL2, TFM and Zephyr are contiguous sections. set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") +set(ADI_FLASH_PS_AREA_SIZE "0" CACHE STRING "Default: 0KB") +set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + # # Allow user set S-NS resources ownership by overlay file @@ -63,8 +69,13 @@ target_compile_definitions(platform_region_defs $<$:ADI_NS_SRAM_3> $<$:ADI_NS_SRAM_4> + # ramfunc section size + ADI_S_RAM_CODE_SIZE=${ADI_S_RAM_CODE_SIZE} + # Flash ADI_FLASH_AREA_BL2_SIZE=${ADI_FLASH_AREA_BL2_SIZE} ADI_FLASH_S_PARTITION_SIZE=${ADI_FLASH_S_PARTITION_SIZE} ADI_FLASH_NS_PARTITION_SIZE=${ADI_FLASH_NS_PARTITION_SIZE} + ADI_FLASH_PS_AREA_SIZE=${ADI_FLASH_PS_AREA_SIZE} + ADI_FLASH_ITS_AREA_SIZE=${ADI_FLASH_ITS_AREA_SIZE} ) From e261aa10c4b631c9be48b0eced7feaf33c45699c Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 25 Mar 2025 11:52:32 +0300 Subject: [PATCH 039/133] [zep fromtree] platform: ext: adi Increase RAM_CODE size Incase of CONFIG_NO_OPTIMIZATION flag been set or CONFIG_DEBUG flag been set 1KB RAM_CODE section not enought to store flags, info... the section overflow it is increased to 2KB to meet size Change-Id: I7371044cd5e04f543f254665e9be730aa3a2b1a6 Signed-off-by: Sadik Ozer (cherry picked from commit fd768fe51ac234c5abbe22afd41d0b68bd815fd7) --- platform/ext/target/adi/max32657/s_ns_access.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake index 61e6f04625..1f051be804 100644 --- a/platform/ext/target/adi/max32657/s_ns_access.cmake +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -43,7 +43,7 @@ set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") # Ramfuncs section size -set(ADI_S_RAM_CODE_SIZE "0x400" CACHE STRING "Default: 1KB") +set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") # Flash: BL2, TFM and Zephyr are contiguous sections. set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") From 83afaeb362bce8e20c2e144abb5d79e489f6868c Mon Sep 17 00:00:00 2001 From: Jayashree Srinivasan Date: Mon, 7 Apr 2025 14:38:53 -0400 Subject: [PATCH 040/133] [zep fromtree] platform: ext: adi: Enable Protected Storage partition Protected Storage partition is enabled in the configuration file for the MAX32657 platform. Sufficient flash space is allocated for the services. Note that PS is not enabled by default in case of small profile of TF-M. Change-Id: I299655d1cc27c7246b70e8d5742806816b8710a9 Signed-off-by: Jayashree Srinivasan (cherry picked from commit 62bcea881ddc6bcd42f4aca23d20d131cc1d45fc) --- platform/ext/target/adi/max32657/config.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index bae7ce1220..508e4861a5 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -11,6 +11,7 @@ set(TFM_BL2_SIGNING_KEY_PATH "" CACHE FILEPATH "") set(BL2 ON CACHE BOOL "Whether to build BL2") set(CONFIG_TFM_USE_TRUSTZONE ON) +set(TFM_PARTITION_PROTECTED_STORAGE ON CACHE BOOL "Enable Protected Stroage partition") set(TFM_PARTITION_PLATFORM OFF CACHE BOOL "Enable Platform partition") set(TFM_PARTITION_CRYPTO ON CACHE BOOL "Enable Crypto partition") set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE ON CACHE BOOL "Enable Internal Trusted Storage partition") From 15c872ecdd9baec4ddd15dcea005d2b28f70ede6 Mon Sep 17 00:00:00 2001 From: Jayashree Srinivasan Date: Mon, 7 Apr 2025 14:42:39 -0400 Subject: [PATCH 041/133] [zep fromtree] platform: ext: adi: Enable Single Part Functions for PS Encryption Default small profile configurations does not support Protected Storage encryption. This commit enables single part functions in crypto library needed for PS Encryption. Algorithms needs for PS Encryption and Key derivation are done in zephyr configuration. Furthermore, 16KB flash is provided for PS. Change-Id: Ib8be41c52f8b4078931bed86db2632e191eac48e Signed-off-by: Jayashree Srinivasan (cherry picked from commit fd319d48ef52db21be9f2b524942c76d7c266a8b) --- platform/ext/target/adi/max32657/config.cmake | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 508e4861a5..4be71e55b9 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -39,3 +39,8 @@ if (CONFIG_TFM_PROFILE_SMALL) # to ensure that initial attestation testcases in regression build passes add_compile_definitions(CRYPTO_ENGINE_BUF_SIZE=0x500) endif() + +if(TFM_PARTITION_PROTECTED_STORAGE) + # Enable single part functions in crypto library needed for PS Encryption + set(CRYPTO_SINGLE_PART_FUNCS_DISABLED OFF CACHE BOOL "Disable single part functions in crypto library") +endif() From 6a644d9f823895cbbc2bb2abba4e864bc227667e Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 29 Apr 2025 10:02:35 +0300 Subject: [PATCH 042/133] [zep fromtree] docs: Update MAX32657 Remove unneeded section from tf-m doc Change-Id: I824d4788e50b478bebc85310e6f6fab3ce401293 Signed-off-by: Sadik Ozer (cherry picked from commit 9abf230118202a82a4159903a86be282c91e4882) --- docs/platform/adi/max32657/README.rst | 2 -- 1 file changed, 2 deletions(-) diff --git a/docs/platform/adi/max32657/README.rst b/docs/platform/adi/max32657/README.rst index 2e889c6465..93024ad955 100644 --- a/docs/platform/adi/max32657/README.rst +++ b/docs/platform/adi/max32657/README.rst @@ -9,8 +9,6 @@ The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) with digital signal processing (DSP) instructions, large flash and SRAM memories, and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. -This device unites processing horsepower with the connectivity required for -continuous glucose monitoring (CGM), wearables, and other medical applications. The nano-power modes increase battery life substantially. MAX32657 1MB flash and 256KB RAM split to define section for MCUBoot, From c4c44aac2ad5c7a85a69f227410701fb05e0c875 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Mon, 12 May 2025 16:25:05 -0400 Subject: [PATCH 043/133] [zep fromtree] platform: ext: adi: change how s_ns_access.cmake is included to ns side Previous s_ns_access.cmake export to ns only work for Zephyr build environment and does not work when building standalone TF-M. Hence, this change. Change-Id: I3c0294817260dcb8c3e0e995e56bca786d9a5b7e Signed-off-by: Hao Zhang (cherry picked from commit fb4ddc48eb659b333205fa87708be642d632fa07) --- platform/ext/target/adi/max32657/CMakeLists.txt | 2 +- platform/ext/target/adi/max32657/ns/CMakeLists.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 1d28526229..7e2c848e2c 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -215,7 +215,7 @@ install(DIRECTORY ${TARGET_PLATFORM_PATH}/tests # Copy the S-NS peripheral & memory configuration install(FILES ${TARGET_PLATFORM_PATH}/s_ns_access.cmake - DESTINATION ${CMAKE_BINARY_DIR}/../) + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) # Export configuration flags target_compile_definitions(tfm_spm diff --git a/platform/ext/target/adi/max32657/ns/CMakeLists.txt b/platform/ext/target/adi/max32657/ns/CMakeLists.txt index ed25b8df6d..b9772968f8 100644 --- a/platform/ext/target/adi/max32657/ns/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/ns/CMakeLists.txt @@ -86,4 +86,4 @@ target_include_directories(platform_region_defs ) # Get S - NS peripheral and memory access -include(${CMAKE_BINARY_DIR}/../s_ns_access.cmake) +include(s_ns_access.cmake) From ba8b0bed350a82b62e384c8307d9d66dcf32183a Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 14 May 2025 14:56:33 -0400 Subject: [PATCH 044/133] [zep fromtree] platform: ext: adi: turn on TFM_PARTITION_PLATFORM TFM_PARTITION_PROTECTED_STORAGE requires TFM_PARTITION_PLATFORM to be turned ON. Change-Id: I192865b6bb59f092fda479243fd1ba45b49be765 Signed-off-by: Hao Zhang (cherry picked from commit 13a5caf0a7db2f0fd336e4be00434d6062c24233) --- platform/ext/target/adi/max32657/config.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 4be71e55b9..9b6ca1ab93 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -12,7 +12,7 @@ set(TFM_BL2_SIGNING_KEY_PATH "" CACHE FILEPATH "") set(BL2 ON CACHE BOOL "Whether to build BL2") set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_PARTITION_PROTECTED_STORAGE ON CACHE BOOL "Enable Protected Stroage partition") -set(TFM_PARTITION_PLATFORM OFF CACHE BOOL "Enable Platform partition") +set(TFM_PARTITION_PLATFORM ON CACHE BOOL "Enable Platform partition") set(TFM_PARTITION_CRYPTO ON CACHE BOOL "Enable Crypto partition") set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE ON CACHE BOOL "Enable Internal Trusted Storage partition") set(TFM_PARTITION_NS_AGENT_TZ ON CACHE BOOL "Enable Non-Secure Agent in Secure partition") From 627eb0b3b8f7062ee7ada463b846e3664e919136 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 10 Jun 2025 14:42:01 +0300 Subject: [PATCH 045/133] [zep fromtree] docs: platform: adi: Update doc Update build command to align with final state of repository Change-Id: Ia48fb3c066cf0437864eac57010fcd527e1c837a Signed-off-by: Sadik Ozer (cherry picked from commit dd365ac9ee428770ac53aa516fe95b2d8a32ff94) --- docs/platform/adi/max32657/README.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/platform/adi/max32657/README.rst b/docs/platform/adi/max32657/README.rst index 93024ad955..4ff1024b63 100644 --- a/docs/platform/adi/max32657/README.rst +++ b/docs/platform/adi/max32657/README.rst @@ -109,10 +109,11 @@ Prepare the tf-m-tests repository inside the TF-M base folder. cd /tf-m-test/tests_reg - cmake -S -B build_spe \ + cmake -S spe -B build_spe \ -G"Unix Makefiles" \ -DTFM_PLATFORM=adi/max32657 \ - -DTFM_TOOLCHAIN_FILE=[tf-m path]/toolchain_GNUARM.cmake \ + -DCONFIG_TFM_SOURCE_PATH=/trusted-firmware-m \ + -DTFM_TOOLCHAIN_FILE=/trusted-firmware-m/toolchain_GNUARM.cmake \ -DTEST_S=OFF \ -DTEST_NS=ON \ -DTFM_NS_REG_TEST=ON \ @@ -122,7 +123,7 @@ Prepare the tf-m-tests repository inside the TF-M base folder. cmake -S . -B build_test \ -G"Unix Makefiles" \ - -DCONFIG_SPE_PATH=[tf-m-tests path]/tests_reg/build_spe/api_ns \ + -DCONFIG_SPE_PATH=/tf-m-tests/tests_reg/build_spe/api_ns \ -DTFM_TOOLCHAIN_FILE=cmake/toolchain_ns_GNUARM.cmake \ -DTFM_NS_REG_TEST=ON cmake --build build_test From da7dbaa5d6f6357f086ef9cd2f7d02963d8623a6 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Tue, 27 May 2025 14:16:37 -0400 Subject: [PATCH 046/133] [zep fromtree] platform: ext: adi: define add_subdirectory_ifdef remote_library.cmake uses FetchContent_MakeAvailable, it auto include hal_adi, where the source CMakeLists has add_subdirectory_ifdef that is not defined. Hence, define it. Change-Id: I12cc6bacb3d5523ddf09f3c11f2e94e16b490d92 Signed-off-by: Hao Zhang (cherry picked from commit 0b91bbf855b80072aa8fca06d5f0b4733f085c2c) --- platform/ext/target/adi/max32657/hal_adi.cmake | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/platform/ext/target/adi/max32657/hal_adi.cmake b/platform/ext/target/adi/max32657/hal_adi.cmake index e19dd40723..b3832e19ed 100644 --- a/platform/ext/target/adi/max32657/hal_adi.cmake +++ b/platform/ext/target/adi/max32657/hal_adi.cmake @@ -8,6 +8,13 @@ cmake_policy(SET CMP0076 NEW) set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +###### CMake-generic extensions ################################################ +function(add_subdirectory_ifdef feature_toggle source_dir) + if(${${feature_toggle}}) + add_subdirectory(${source_dir} ${ARGN}) + endif() +endfunction() + ################################################################################ # Fetch hal_adi repository set(FETCHCONTENT_QUIET TRUE) From 0b245ecdb728ecc99b0655f860ba78697b425b6f Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Thu, 29 May 2025 14:34:32 -0400 Subject: [PATCH 047/133] [zep fromtree] platform: ext: adi: fix flash driver Seeing flash inconsistency during some flash operations (e.g. program data). Fix by disabling Internal Cache Controller (ICC) before these flash operation then turn it back on after these flash operations Change-Id: I2459e2e1554af96ed084bf4f515bfe1b97fdb3ee Co-authored-by: Alperen Guclu Signed-off-by: Hao Zhang (cherry picked from commit b2ae7c3e90f2387c7fd4ab9a247895e5c4eae897) --- .../adi/max32657/cmsis_drivers/Driver_Flash.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c index 4fd67258e7..709a8da7d0 100644 --- a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c @@ -23,6 +23,7 @@ #include "RTE_Device.h" #include "mxc_errors.h" #include "flc.h" +#include "icc.h" #ifndef ARG_UNUSED #define ARG_UNUSED(arg) ((void)arg) @@ -160,11 +161,12 @@ static int32_t ARM_Flash_ProgramData(uint32_t offset, const void *data, uint32_t } uint32_t addr = FLASH0_DEV->memory_base + offset; - - if(MXC_FLC_Write(addr, cnt, (uint32_t *)data) != E_NO_ERROR) { + MXC_ICC_Disable(); + int result = MXC_FLC_Write(addr, cnt, (uint32_t *)data); + MXC_ICC_Enable(); + if (result != E_NO_ERROR) { return ARM_DRIVER_ERROR_PARAMETER; } - return cnt; } @@ -181,8 +183,10 @@ static int32_t ARM_Flash_EraseSector(uint32_t offset) } uint32_t addr = FLASH0_DEV->memory_base + offset; - - if (MXC_FLC_PageErase(addr) != E_NO_ERROR) { + MXC_ICC_Disable(); + int result = MXC_FLC_PageErase(addr); + MXC_ICC_Enable(); + if (result != E_NO_ERROR) { return ARM_DRIVER_ERROR_PARAMETER; } @@ -192,7 +196,10 @@ static int32_t ARM_Flash_EraseSector(uint32_t offset) static int32_t ARM_Flash_EraseChip(void) { if (DriverCapabilities.erase_chip == 1) { - if(MXC_FLC_MassErase() != E_NO_ERROR) { + MXC_ICC_Disable(); + int result = MXC_FLC_MassErase(); + MXC_ICC_Enable(); + if (result != E_NO_ERROR) { return ARM_DRIVER_ERROR_PARAMETER; } } else { From 4af241a77674972fd044253762c00dda64f13838 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Tue, 27 May 2025 14:20:34 -0400 Subject: [PATCH 048/133] [zep fromtree] docs: platform: adi: Change build instructions 1. Due to update of BL2 logging system, flag -DTFM_BL2_LOG_LEVEL=LOG_LEVEL_INFO is used to print bl2 message 2. Add instructions of converting tfm_s_signed.bin to tfm_s_signed.hex Change-Id: Ic88af29ba4028ee8a9b856cddccd1589f1a849a5 Signed-off-by: Hao Zhang (cherry picked from commit 5c42ba84af2c23dcec5ff5ce765992b0eda3832c) --- docs/platform/adi/max32657/README.rst | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/docs/platform/adi/max32657/README.rst b/docs/platform/adi/max32657/README.rst index 4ff1024b63..fbccd1205d 100644 --- a/docs/platform/adi/max32657/README.rst +++ b/docs/platform/adi/max32657/README.rst @@ -117,7 +117,7 @@ Prepare the tf-m-tests repository inside the TF-M base folder. -DTEST_S=OFF \ -DTEST_NS=ON \ -DTFM_NS_REG_TEST=ON \ - -DMCUBOOT_LOG_LEVEL="INFO" \ + -DTFM_BL2_LOG_LEVEL=LOG_LEVEL_INFO \ -DTFM_ISOLATION_LEVEL=1 cmake --build build_spe -- install @@ -139,6 +139,7 @@ Generate Intel hex files from the output binary (bin) files as follows: .. code-block:: console + srec_cat build_spe/bin/tfm_s_signed.bin -binary --offset 0x01010000 -o build_spe/bin/tfm_s_signed.hex -intel srec_cat build_test/bin/tfm_ns_signed.bin -binary --offset 0x01060000 -o build_test/bin/tfm_ns_signed.hex -intel @@ -146,7 +147,13 @@ Merge hex files as follows: .. code-block:: console - srec_cat.exe build_spe/bin/bl2.hex -Intel build_spe/bin/tfm_s_signed.hex -Intel build_test/bin/tfm_ns_signed.hex -Intel -o tfm_merged.hex -Intel + srec_cat build_spe/bin/bl2.hex -Intel build_spe/bin/tfm_s_signed.hex -Intel build_test/bin/tfm_ns_signed.hex -Intel -o tfm_merged.hex -Intel + +Alternatively, you can merge hex files with `mergehex.py `_ + +.. code-block:: console + + python /PATH/TO/mergehex.py -o tfm_merged.hex build_spe/bin/bl2.hex build_spe/bin/tfm_s_signed.hex build_test/bin/tfm_ns_signed.hex .. note:: From cde74b5050b70529bb4428bac0e1eb4f0c64fa3c Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Tue, 27 May 2025 13:01:13 -0400 Subject: [PATCH 049/133] [zep fromtree] platform: ext: adi: Enable Protected Storage partition Protected Storage partition is enabled in the configuration file for the MAX32657 platform. Sufficient flash space is allocated for the services. Note that PS is not enabled by default in case of small profile of TF-M. Co-authored-by: Jayashree Srinivasan Change-Id: I7abd1c5a32bcad041f22c01711a7bdefdb8e52dc Signed-off-by: Hao Zhang (cherry picked from commit fe4aeabec6b053a3b8f8322a19f362c22adfd582) --- platform/ext/target/adi/max32657/s_ns_access.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake index 1f051be804..39939751e7 100644 --- a/platform/ext/target/adi/max32657/s_ns_access.cmake +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -49,7 +49,7 @@ set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") -set(ADI_FLASH_PS_AREA_SIZE "0" CACHE STRING "Default: 0KB") +set(ADI_FLASH_PS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") From 307fdf9c269ea82c580fd464e2e24adc3ae04dd4 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Tue, 3 Jun 2025 22:59:02 -0400 Subject: [PATCH 050/133] [zep fromtree] platform: ext: adi: add regression test Protected Stroage was previously not suported and was manually turned off. It is now supported and is turned back on. Change-Id: I107e366ec47f2b5243f6fcf9b0feb3cfb923e283 Signed-off-by: Hao Zhang (cherry picked from commit d21b0d52fbe96c34b80a3ca2cde3ea66df477436) --- platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake | 2 -- 1 file changed, 2 deletions(-) diff --git a/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake b/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake index 04dd1d7180..49a1cc2d2b 100644 --- a/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake +++ b/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake @@ -6,7 +6,5 @@ #------------------------------------------------------------------------------- set(TEST_NS_SLIH_IRQ OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests") -set(TEST_NS_PS OFF CACHE BOOL "Whether to build NS PS tests") -set(TEST_NS_PLATFORM OFF ) set(TEST_NS_IPC OFF ) set(TEST_NS_FLIH_IRQ OFF ) From 548087f055573d7c74e9188e20096581fc2570d2 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 18 Jun 2025 11:26:40 -0400 Subject: [PATCH 051/133] [zep fromtree] platform: ext: adi: mbedtls TRNG with external HW psa_generate_random is capable of making use of hardware TRNG for random generation through PSA crypto driver interface Change-Id: I14b8192661657027ab20224a79e1fd15fd1d3f56 Signed-off-by: Hao Zhang (cherry picked from commit 0fb1c5f89847bc297c49bbcb3adf5d046f392df5) --- platform/ext/accelerator/adi/CMakeLists.txt | 32 ++++++++++++ .../ext/target/adi/max32657/CMakeLists.txt | 5 ++ .../adi/max32657/accelerator/CMakeLists.txt | 37 +++++++++++++ .../accelerator/include/adi_psa_random.h | 48 +++++++++++++++++ .../include/crypto_accelerator_config.h | 23 ++++++++ .../include/mbedtls_accelerator_config.h | 24 +++++++++ .../accelerator/src/adi_accelerator.c | 25 +++++++++ .../max32657/accelerator/src/adi_psa_random.c | 52 +++++++++++++++++++ platform/ext/target/adi/max32657/config.cmake | 12 +++-- .../adi/max32657/device/src/system_max32657.c | 3 +- .../ext/target/adi/max32657/ns/CMakeLists.txt | 1 + .../ext/target/adi/max32657/s_ns_access.cmake | 2 +- 12 files changed, 257 insertions(+), 7 deletions(-) create mode 100644 platform/ext/accelerator/adi/CMakeLists.txt create mode 100644 platform/ext/target/adi/max32657/accelerator/CMakeLists.txt create mode 100644 platform/ext/target/adi/max32657/accelerator/include/adi_psa_random.h create mode 100644 platform/ext/target/adi/max32657/accelerator/include/crypto_accelerator_config.h create mode 100644 platform/ext/target/adi/max32657/accelerator/include/mbedtls_accelerator_config.h create mode 100644 platform/ext/target/adi/max32657/accelerator/src/adi_accelerator.c create mode 100644 platform/ext/target/adi/max32657/accelerator/src/adi_psa_random.c diff --git a/platform/ext/accelerator/adi/CMakeLists.txt b/platform/ext/accelerator/adi/CMakeLists.txt new file mode 100644 index 0000000000..5012e90658 --- /dev/null +++ b/platform/ext/accelerator/adi/CMakeLists.txt @@ -0,0 +1,32 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/CMakeLists.txt) +if(BL2) + target_compile_definitions(bl2_crypto_config + INTERFACE + MBEDTLS_ACCELERATOR_CONFIG_FILE="${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include/mbedtls_accelerator_config.h" + MBEDTLS_ACCELERATOR_PSA_CRYPTO_CONFIG_FILE="${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include/crypto_accelerator_config.h" +) +endif() + +if (TFM_PARTITION_CRYPTO) + target_link_libraries(crypto_service_mbedcrypto + PUBLIC + crypto_service_crypto_hw + ) + + target_compile_definitions(crypto_service_mbedcrypto + PUBLIC + CRYPTO_HW_ACCELERATOR + ) + + target_compile_options(crypto_service_mbedcrypto + PRIVATE + $<$:-Wno-unused-parameter> + ) +endif() diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt index 7e2c848e2c..407ccf0050 100644 --- a/platform/ext/target/adi/max32657/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -195,6 +195,11 @@ install(FILES ${TARGET_PLATFORM_PATH}/device/src/startup_${TARGET_LC}.c install(FILES ${HAL_ADI_CMSIS_INC_DIR}/max32657.h DESTINATION ${INSTALL_PLATFORM_NS_DIR}/device/inc) +install(FILES ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include/adi_psa_random.h + ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include/crypto_accelerator_config.h + ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include/mbedtls_accelerator_config.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/accelerator/include) + install(FILES ${PLATFORM_DIR}/ext/common/gcc/tfm_common_ns.ld DESTINATION ${INSTALL_PLATFORM_NS_DIR}/linker_scripts) diff --git a/platform/ext/target/adi/max32657/accelerator/CMakeLists.txt b/platform/ext/target/adi/max32657/accelerator/CMakeLists.txt new file mode 100644 index 0000000000..c561d6a767 --- /dev/null +++ b/platform/ext/target/adi/max32657/accelerator/CMakeLists.txt @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +############################ Crypto Service #################################### + +if(TFM_PARTITION_CRYPTO) + target_sources(crypto_service_crypto_hw + PUBLIC + ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/src/adi_psa_random.c + ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/src/adi_accelerator.c + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG/trng_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG/trng_revb.c + ) + + target_include_directories(crypto_service_crypto_hw + PUBLIC + ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} + ) + + target_include_directories(platform_s + PUBLIC + ${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/include + ) + + target_link_libraries(crypto_service_crypto_hw + PRIVATE + crypto_service_mbedcrypto + platform_s + ) +endif() diff --git a/platform/ext/target/adi/max32657/accelerator/include/adi_psa_random.h b/platform/ext/target/adi/max32657/accelerator/include/adi_psa_random.h new file mode 100644 index 0000000000..35343780e8 --- /dev/null +++ b/platform/ext/target/adi/max32657/accelerator/include/adi_psa_random.h @@ -0,0 +1,48 @@ +/****************************************************************************** + * + * Copyright (C) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#ifndef __ADI_PSA_RANDOM_H__ +#define __ADI_PSA_RANDOM_H__ + +/** @file adi_psa_random.h + * + * This file contains the declaration of the entry points associated to the + * random generation capability as described by the PSA Cryptoprocessor + * Driver interface specification + * + */ + +#include "psa/crypto.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +/* ADI uses TRNG peripheral for random number generation +* No context is needed for this driver +*/ + +typedef void adi_random_context_t; + +/** + * @brief Generates random numbers with a uniform distribution + * + * @param[in,out] context A void pointer that is currently not being used. This argument is + * to comply with PSA random number generation entry point defintion. + * @param[out] output Buffer containing the random data collected + * @param[in] output_size Size in bytes of the buffer to fill + * @param[out] output_length Number of bytes effectively returned in \ref buffer + * @return psa_status_t + */ + +psa_status_t adi_get_random(adi_random_context_t *context, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#endif /* __ADI_PSA_RANDOM_H__ */ diff --git a/platform/ext/target/adi/max32657/accelerator/include/crypto_accelerator_config.h b/platform/ext/target/adi/max32657/accelerator/include/crypto_accelerator_config.h new file mode 100644 index 0000000000..d43c6a5851 --- /dev/null +++ b/platform/ext/target/adi/max32657/accelerator/include/crypto_accelerator_config.h @@ -0,0 +1,23 @@ + +/* + * Copyright (c) 2025 Analog Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef __CRYPTO_ACCELERATOR_CONF_H__ +#define __CRYPTO_ACCELERATOR_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/****************************************************************/ +/* Require built-in implementations based on PSA requirements */ +/****************************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __CRYPTO_ACCELERATOR_CONF_H__ */ diff --git a/platform/ext/target/adi/max32657/accelerator/include/mbedtls_accelerator_config.h b/platform/ext/target/adi/max32657/accelerator/include/mbedtls_accelerator_config.h new file mode 100644 index 0000000000..3dc86ddd53 --- /dev/null +++ b/platform/ext/target/adi/max32657/accelerator/include/mbedtls_accelerator_config.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MBEDTLS_ACCELERATOR_CONF_H__ +#define __MBEDTLS_ACCELERATOR_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* RNG Config */ +#undef MBEDTLS_ENTROPY_NV_SEED +#undef MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MBEDTLS_ACCELERATOR_CONF_H__ */ diff --git a/platform/ext/target/adi/max32657/accelerator/src/adi_accelerator.c b/platform/ext/target/adi/max32657/accelerator/src/adi_accelerator.c new file mode 100644 index 0000000000..bae4424bcc --- /dev/null +++ b/platform/ext/target/adi/max32657/accelerator/src/adi_accelerator.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "crypto_hw.h" + +/* + * \brief Initialize crypto accelerator + */ + +int crypto_hw_accelerator_init(void) +{ + return 0; +} + +/* + * \brief Deallocate crypto accelerator + */ +int crypto_hw_accelerator_finish(void) +{ + return 0; +} diff --git a/platform/ext/target/adi/max32657/accelerator/src/adi_psa_random.c b/platform/ext/target/adi/max32657/accelerator/src/adi_psa_random.c new file mode 100644 index 0000000000..7ee2366f56 --- /dev/null +++ b/platform/ext/target/adi/max32657/accelerator/src/adi_psa_random.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2025 Analog Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "adi_psa_random.h" +#include "trng.h" +#include "mxc_errors.h" + +psa_status_t adi_get_random(adi_random_context_t *context, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + ARG_UNUSED(context); + + int ret; + ret = MXC_TRNG_Random(output, output_size); + + if (ret != E_NO_ERROR) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + *output_length = output_size; + return PSA_SUCCESS; +} + +/* As of mbed TLS 3.6, there is no support in the Core for the random entry points, + * so the integration happens through the definition of MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * as the function that mbed TLS uses to retrieve random numbers from an external + * generator. Note that we don't rely on redefining the type + * mbedtls_psa_external_random_context_t available to the PSA Crypto core to make + * keep integration simple, as there is no real gain in doing that. + */ +psa_status_t mbedtls_psa_external_get_random( + mbedtls_psa_external_random_context_t *context, + uint8_t *output, size_t output_size, size_t *output_length) +{ + psa_status_t status; + ARG_UNUSED(context); + + if (output == NULL || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = adi_get_random(NULL, output, output_size, output_length); + + return status; +} diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake index 9b6ca1ab93..4d44924d87 100644 --- a/platform/ext/target/adi/max32657/config.cmake +++ b/platform/ext/target/adi/max32657/config.cmake @@ -32,15 +32,17 @@ set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") set(MCUBOOT_USE_PSA_CRYPTO ON CACHE BOOL "Use PSA Crypto for MCUBOOT") -set(CRYPTO_HW_ACCELERATOR OFF) -if (CONFIG_TFM_PROFILE_SMALL) +set(CRYPTO_HW_ACCELERATOR ON CACHE BOOL "Enable hardware crypto accelerator") +set(CRYPTO_HW_ACCELERATOR_TYPE "adi" CACHE STRING "The hardware accelerator platform") + +if (TFM_PROFILE STREQUAL "profile_small") # Static Buffer size for MBEDTLS allocations - Has been increased from the default value of small profile - # to ensure that initial attestation testcases in regression build passes - add_compile_definitions(CRYPTO_ENGINE_BUF_SIZE=0x500) + # to ensure that initial attestation testcases in regression build passes and generate random number successfully. + add_compile_definitions(CRYPTO_ENGINE_BUF_SIZE=0x800) endif() if(TFM_PARTITION_PROTECTED_STORAGE) # Enable single part functions in crypto library needed for PS Encryption - set(CRYPTO_SINGLE_PART_FUNCS_DISABLED OFF CACHE BOOL "Disable single part functions in crypto library") + set(CRYPTO_SINGLE_PART_FUNCS_DISABLED OFF CACHE BOOL "Disable single part functions in crypto library") endif() diff --git a/platform/ext/target/adi/max32657/device/src/system_max32657.c b/platform/ext/target/adi/max32657/device/src/system_max32657.c index be04a63baa..74b5ffc6f8 100644 --- a/platform/ext/target/adi/max32657/device/src/system_max32657.c +++ b/platform/ext/target/adi/max32657/device/src/system_max32657.c @@ -133,12 +133,13 @@ void SystemInit(void) #if CONFIG_TRUSTED_EXECUTION_SECURE /* Init peripherals */ PeripheralInit(); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif /* * FPCA bit of CONTROL register can be enabled while * performing floating point operation in Secure domain. - * It will trigger fault if it is not cleared before + * It will trigger fault if it is not cleared before * switching to Non-secure domain. * Hence, clearing FPCA bit during initialization firmware */ diff --git a/platform/ext/target/adi/max32657/ns/CMakeLists.txt b/platform/ext/target/adi/max32657/ns/CMakeLists.txt index b9772968f8..8982594321 100644 --- a/platform/ext/target/adi/max32657/ns/CMakeLists.txt +++ b/platform/ext/target/adi/max32657/ns/CMakeLists.txt @@ -77,6 +77,7 @@ target_include_directories(platform_ns ext/cmsis/Include/m-profile device/inc ext/common + accelerator/include ) # Include region_defs.h and flash_layout.h diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake index 39939751e7..3d8449c81a 100644 --- a/platform/ext/target/adi/max32657/s_ns_access.cmake +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -22,7 +22,7 @@ set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") set(ADI_NS_PRPH_I3C ON CACHE BOOL "") set(ADI_NS_PRPH_UART ON CACHE BOOL "") set(ADI_NS_PRPH_SPI ON CACHE BOOL "") -set(ADI_NS_PRPH_TRNG ON CACHE BOOL "") +set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") From 44657441c5a391605a0ace750d3c5f069918aa6b Mon Sep 17 00:00:00 2001 From: Nicola Mazzucato Date: Wed, 26 Mar 2025 12:06:27 +0000 Subject: [PATCH 052/133] [zep fromtree] SPM: backend_ipc: Remove unnecessary FIH guard for checks in ipc_schedule A previous patch 835b161d2 introduced additional checks for the context. Those have been placed within a TFM_FIH_PROFILE_ON block, but they do not rely on any FIH functionality. Thus, remove the guard and always perform the additional scheduling checks. Signed-off-by: Nicola Mazzucato Change-Id: I81d5b64f0114a24f60d6068f476ba7bc80fe6545 (cherry picked from commit 0bf66d999f7244a9cf998745beb4fe2588ca6d96) --- secure_fw/spm/core/backend_ipc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/secure_fw/spm/core/backend_ipc.c b/secure_fw/spm/core/backend_ipc.c index b0b668a180..7e9dfb0495 100644 --- a/secure_fw/spm/core/backend_ipc.c +++ b/secure_fw/spm/core/backend_ipc.c @@ -613,7 +613,6 @@ uint64_t ipc_schedule(uint32_t exc_return) } p_partition_metadata = (uintptr_t)(p_part_next->p_metadata); -#ifdef TFM_FIH_PROFILE_ON /* * ctx_ctrl is set from struct thread_t's p_context_ctrl, and p_part_curr * and p_part_next are calculated from the thread pointer. @@ -638,7 +637,6 @@ uint64_t ipc_schedule(uint32_t exc_return) if ((uintptr_t)GET_CTX_OWNER(ctx_ctrls.u32_regs.r1)->p_metadata != p_partition_metadata) { tfm_core_panic(); } -#endif CRITICAL_SECTION_LEAVE(cs); From 0078c08235bda03b854e26726752b89f3c52b06c Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Thu, 20 Mar 2025 19:37:32 +0100 Subject: [PATCH 053/133] [zep fromtree] platform: nordic_nrf: Create a nrf54l folder Create a nrf54l folder which can be used for other devices in the series as well. This is preparation work for the addition of the nrf54l10. This also updates the the source and header files which use ifdefs with nrf54l15 specific defines with the macro NRF54L_SERIES. Also removes the executable permissions from the region_defs.h which was enabled by accident. Change-Id: I1b2a0876fefef3fb460cf8995b9b802aa089b7aa Signed-off-by: Georgios Vasilakis (cherry picked from commit a49f175edadc8b36a01517f8bcc746d05991f1d5) --- .../nordic_nrf/common/core/nrfx_config.h | 4 ++-- .../services/src/tfm_platform_hal_ioctl.c | 2 +- .../{startup_nrf54l15.c => startup_nrf54l.c} | 0 .../nordic_nrf/common/core/target_cfg.c | 20 +++++++++---------- .../nordic_nrf/common/core/target_cfg.h | 4 ++-- .../nordic_nrf/common/nrf54l/config.cmake | 14 +++++++++++++ .../common/{nrf54l15 => nrf54l}/mmio_defs.h | 0 .../nrf54l15_init.c => nrf54l/nrf54l_init.c} | 0 .../nrfx_config_nrf54l.h} | 0 .../{nrf54l15 => nrf54l}/tfm_interrupts.c | 0 .../tfm_peripherals_config_nrf54l.h} | 0 .../tfm_peripherals_def.h | 0 .../nordic_nrf/common/nrf54l15/CMakeLists.txt | 9 +++++---- .../nordic_nrf/common/nrf54l15/config.cmake | 6 +----- .../nordic_nrf/common/nrf54l15/cpuarch.cmake | 1 + .../common/nrf54l15/ns/CMakeLists.txt | 2 +- .../common/nrf54l15/partition/region_defs.h | 0 17 files changed, 37 insertions(+), 25 deletions(-) rename platform/ext/target/nordic_nrf/common/core/{startup_nrf54l15.c => startup_nrf54l.c} (100%) create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l/config.cmake rename platform/ext/target/nordic_nrf/common/{nrf54l15 => nrf54l}/mmio_defs.h (100%) rename platform/ext/target/nordic_nrf/common/{nrf54l15/nrf54l15_init.c => nrf54l/nrf54l_init.c} (100%) rename platform/ext/target/nordic_nrf/common/{nrf54l15/nrfx_config_nrf54l15_application.h => nrf54l/nrfx_config_nrf54l.h} (100%) rename platform/ext/target/nordic_nrf/common/{nrf54l15 => nrf54l}/tfm_interrupts.c (100%) rename platform/ext/target/nordic_nrf/common/{nrf54l15/tfm_peripherals_config_nrf54l15.h => nrf54l/tfm_peripherals_config_nrf54l.h} (100%) rename platform/ext/target/nordic_nrf/common/{nrf54l15 => nrf54l}/tfm_peripherals_def.h (100%) mode change 100755 => 100644 platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h diff --git a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h index dbaf8fbf06..8d192b5887 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h +++ b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h @@ -100,8 +100,8 @@ #include #elif defined(NRF91_SERIES) #include -#elif defined(NRF54L15_XXAA) - #include +#elif defined(NRF54L_SERIES) + #include #else #error "Unknown device." #endif diff --git a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c index ae909ca5b9..15fd17e316 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c +++ b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c @@ -103,7 +103,7 @@ tfm_platform_hal_read_service(const psa_invec *in_vec, static bool valid_mcu_select(uint32_t mcu) { switch (mcu) { -#if defined(NRF54L15_XXAA) +#if defined(NRF54L_SERIES) case NRF_GPIO_PIN_SEL_GPIO: case NRF_GPIO_PIN_SEL_VPR: case NRF_GPIO_PIN_SEL_GRTC: diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l15.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c similarity index 100% rename from platform/ext/target/nordic_nrf/common/core/startup_nrf54l15.c rename to platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.c b/platform/ext/target/nordic_nrf/common/core/target_cfg.c index dc345888ba..75afa398be 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.c @@ -69,7 +69,7 @@ #define PIN_XL2 1 #endif -#ifdef NRF54L15_XXAA +#ifdef NRF54L_SERIES /* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ #define PIN_XL1 32 #define PIN_XL2 33 @@ -816,7 +816,7 @@ enum tfm_plat_err_t init_debug(void) #error "Debug access controlled by NRF_APPROTECT and NRF_SECURE_APPROTECT." #endif -#if defined(NRF_APPROTECT) && !defined(NRF54L15_XXAA) +#if defined(NRF_APPROTECT) && !defined(NRF54L_SERIES) /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot.*/ if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, UICR_APPROTECT_PALL_Protected)) { @@ -825,7 +825,7 @@ enum tfm_plat_err_t init_debug(void) return TFM_PLAT_ERR_SYSTEM_ERR; } #endif -#if defined(NRF_SECURE_APPROTECT) && !defined(NRF54L15_XXAA) +#if defined(NRF_SECURE_APPROTECT) && !defined(NRF54L_SERIES) /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot. */ if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, UICR_SECUREAPPROTECT_PALL_Protected)) { @@ -836,7 +836,7 @@ enum tfm_plat_err_t init_debug(void) } #endif -#elif defined(NRF91_SERIES) || defined(NRF54L15_XXAA) +#elif defined(NRF91_SERIES) || defined(NRF54L_SERIES) #if !defined(DAUTH_CHIP_DEFAULT) #error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." @@ -942,7 +942,7 @@ void sau_and_idau_cfg(void) * (53/91) and new (54++) platforms. New platforms have a proper SAU * and IDAU, whereas old platforms do not. */ -#ifdef NRF54L15_XXAA +#ifdef NRF54L_SERIES /* * This SAU configuration aligns with ARM's RSS implementation of * sau_and_idau_cfg when possible. @@ -1247,7 +1247,7 @@ static void dppi_channel_configuration(void) enum tfm_plat_err_t spu_periph_init_cfg(void) { /* Peripheral configuration */ -#ifdef NRF54L15_XXAA +#ifdef NRF54L_SERIES /* Configure features to be non-secure */ /* @@ -1318,7 +1318,7 @@ enum tfm_plat_err_t spu_periph_init_cfg(void) * have the same security configuration. */ spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); -#else /* NRF54L15_XXAA */ +#else /* NRF54L_SERIES */ static const uint32_t target_peripherals[] = { /* The following peripherals share ID: * - FPU (FPU cannot be configured in NRF91 series, it's always NS) @@ -1450,7 +1450,7 @@ static const uint32_t target_peripherals[] = { spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); } -#endif /* NRF54L15_XXAA */ +#endif /* NRF54L_SERIES */ /* DPPI channel configuration */ dppi_channel_configuration(); @@ -1511,7 +1511,7 @@ static const uint32_t target_peripherals[] = { nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); #endif /* NRF53_SERIES */ -#ifdef NRF54L15_XXAA +#ifdef NRF54L_SERIES /* NRF54L has a different define */ nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_GPIO); nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_GPIO); @@ -1567,7 +1567,7 @@ static const uint32_t target_peripherals[] = { } #endif /* RRAMC_PRESENT */ -#ifdef NRF54L15_XXAA +#ifdef NRF54L_SERIES /* SOC configuration from Zephyr's soc.c. */ int soc_err = nordicsemi_nrf54l_init(); if (soc_err) { diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.h b/platform/ext/target/nordic_nrf/common/core/target_cfg.h index adcf67e4c1..1b3072582c 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.h +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.h @@ -56,7 +56,7 @@ /* Only UART20 and UART30 are supported for TF-M tests, which are the * Non-secure applications build via the TF-M build system */ -#ifdef NRF54L15_XXAA +#ifdef NRF54L_SERIES #if NRF_SECURE_UART_INSTANCE == 20 #define NS_DRIVER_STDIO Driver_USART30 #else @@ -64,7 +64,7 @@ #endif #else #define NS_DRIVER_STDIO Driver_USART0 -#endif /* NRF54L15_XXAA */ +#endif /* NRF54L_SERIES */ /** * \brief Store the addresses of memory regions diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake new file mode 100644 index 0000000000..e35ee17ebc --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/config.cmake) + +set(SECURE_UART30 ON CACHE BOOL "Enable secure UART" FORCE) +set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) +set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/mmio_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h similarity index 100% rename from platform/ext/target/nordic_nrf/common/nrf54l15/mmio_defs.h rename to platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/nrf54l15_init.c b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c similarity index 100% rename from platform/ext/target/nordic_nrf/common/nrf54l15/nrf54l15_init.c rename to platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/nrfx_config_nrf54l15_application.h b/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h similarity index 100% rename from platform/ext/target/nordic_nrf/common/nrf54l15/nrfx_config_nrf54l15_application.h rename to platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/tfm_interrupts.c b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c similarity index 100% rename from platform/ext/target/nordic_nrf/common/nrf54l15/tfm_interrupts.c rename to platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/tfm_peripherals_config_nrf54l15.h b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h similarity index 100% rename from platform/ext/target/nordic_nrf/common/nrf54l15/tfm_peripherals_config_nrf54l15.h rename to platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h similarity index 100% rename from platform/ext/target/nordic_nrf/common/nrf54l15/tfm_peripherals_def.h rename to platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt index fb19ca3da7..71735a5410 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_policy(SET CMP0076 NEW) set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) -set(target nrf54l15) +set(target nrf54l) add_subdirectory(../core nrf_common) #========================= Platform Secure ====================================# @@ -16,6 +16,7 @@ add_subdirectory(../core nrf_common) target_include_directories(platform_s PUBLIC . + ../nrf54l ) if(NOT NRF_DIR) @@ -28,7 +29,7 @@ endif() target_sources(platform_s PRIVATE ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c - ${CMAKE_CURRENT_SOURCE_DIR}/nrf54l15_init.c + ../nrf54l/nrf54l_init.c ) target_compile_definitions(platform_s @@ -40,12 +41,12 @@ target_compile_definitions(platform_s target_sources(tfm_spm PRIVATE - $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/tfm_interrupts.c> + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> ) #========================= Files for building NS side platform ================# -install(FILES nrfx_config_nrf54l15_application.h +install(FILES ../nrf54l/nrfx_config_nrf54l.h ns/CMakeLists.txt config.cmake cpuarch.cmake diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake index e35ee17ebc..2222734d24 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake @@ -6,9 +6,5 @@ # #------------------------------------------------------------------------------- -include(${PLATFORM_PATH}/common/core/config.cmake) +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) -set(SECURE_UART30 ON CACHE BOOL "Enable secure UART" FORCE) -set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) -set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) -set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake index e9fc59b844..24d4703f9f 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake @@ -16,6 +16,7 @@ set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") add_compile_definitions( NRF54L15_XXAA + NRF54L_SERIES NRF_APPLICATION # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs NRF_SKIP_SAU_CONFIGURATION diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt index 94c6d77258..6e8396c35d 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_policy(SET CMP0076 NEW) set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) -set(target nrf54l15) +set(target nrf54l) add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) target_include_directories(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h old mode 100755 new mode 100644 From a54b44102a91cd89d5f25e41b043857664901d0d Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Mon, 24 Mar 2025 16:46:25 +0100 Subject: [PATCH 054/133] [zep fromtree] platform: nordic_nrf: Add initial support for nRF54L10 This adds nRF54L10 initial support for TF-M. This is NOT full upstream support. There are important limitations: - Hardware crypto acceleration with Cracen is not supported - Random number generation with Cracen is not supported - The tests suites PSA arch tests and TF-M regression tests are not tested - BL2 is not supported - Some soc related configurations are not supported and they rely on hard-coded values (check nordicsemi_nrf54l_init for more info) This was tested using some basic Zephyr samples. Only one flash/RAM layout is supported at the moment. This adds the same level of support with the nRF54L15, the configuration is nearly identical, the main difference is the partitioning scheme since these devices have different RRAM/RAM sizes. Signed-off-by: Georgios Vasilakis Change-Id: I396d0d570ebd9b471138b7f02019bc0a1279e0d1 (cherry picked from commit d301766d63703596114beda0934b8c70497e33ca) --- .../nordic_nrf/common/core/CMakeLists.txt | 2 +- .../nordic_nrf/common/nrf54l10/CMakeLists.txt | 52 ++++++ .../nordic_nrf/common/nrf54l10/config.cmake | 10 ++ .../nordic_nrf/common/nrf54l10/cpuarch.cmake | 24 +++ .../common/nrf54l10/ns/CMakeLists.txt | 29 ++++ .../common/nrf54l10/partition/flash_layout.h | 162 ++++++++++++++++++ .../common/nrf54l10/partition/region_defs.h | 132 ++++++++++++++ .../tests/psa_arch_tests_config.cmake | 9 + .../nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt | 70 ++++++++ .../nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h | 44 +++++ .../nrf54l15dk_nrf54l10_cpuapp/config.cmake | 10 ++ .../nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake | 9 + .../nrf54l15dk_nrf54l10_cpuapp/device_cfg.h | 32 ++++ .../ns/cpuarch_ns.cmake | 12 ++ .../include/tfm_platform_user_memory_ranges.h | 24 +++ .../services/src/tfm_platform_system.c | 30 ++++ .../tests/psa_arch_tests_config.cmake | 8 + .../tests/tfm_tests_config.cmake | 8 + .../tfm_hal_platform.c | 14 ++ .../tfm_peripherals_config.h | 28 +++ 20 files changed, 708 insertions(+), 1 deletion(-) create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c create mode 100644 platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index b85a0240df..33b49909f4 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -24,7 +24,7 @@ endif() # At the time of writing there is no systematic way to identify which # NVM technology is used by the SoC from the Kconfig, so we just # hardcode this information here instead. -if((NRF_SOC_VARIANT STREQUAL nrf54l15) OR (TFM_PLATFORM STREQUAL "nordic_nrf/nrf54l15dk_nrf54l15_cpuapp") OR (PSA_API_TEST_TARGET STREQUAL nrf54l15)) +if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR (TFM_PLATFORM MATCHES "nordic\_nrf\/nrf54l15dk\_nrf54l1[05]\_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$")) # Maybe we only need to check one of these options but these # variables keep changing so we check both to be future proof set(HAS_RRAMC 1) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt new file mode 100644 index 0000000000..bab0c714d9 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ns/CMakeLists.txt + config.cmake + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10 +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake new file mode 100644 index 0000000000..2222734d24 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake new file mode 100644 index 0000000000..ddd6400b4e --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54L10_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt new file mode 100644 index 0000000000..6e8396c35d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h new file mode 100644 index 0000000000..ab55734ec7 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54L15 Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (384 KB) + * 0x0006_0000 Protected Storage Area (16 KB) + * 0x0006_4000 Internal Trusted Storage Area (16 KB) + * 0x0006_8000 OTP / NV counters area (8 KB) + * 0x0006_A000 Non-secure image primary (504 KB) + * 0x000E_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the last 62kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0xF0000) /* 960 kB since the last 62kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 48kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00024000) /* 144 kB since the last 48kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x7E000) /* NS partition: 504 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h new file mode 100644 index 0000000000..79112d5bac --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x47C) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..39adcd4da1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54l10") diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt new file mode 100644 index 0000000000..e54ab77214 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt @@ -0,0 +1,70 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54l10 nrf54l10) + +target_include_directories(platform_region_defs + INTERFACE + ../common/nrf54l10/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54l10/partition + services/include +) + +if(BL2) + target_include_directories(platform_bl2 + PUBLIC + partition + ../common/nrf54l10/partition + PRIVATE + . + ) +endif() + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h new file mode 100644 index 0000000000..3cba0224c8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake new file mode 100644 index 0000000000..72efe7db74 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54l10/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake new file mode 100644 index 0000000000..eb59334c85 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54l10/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h new file mode 100644 index 0000000000..22ddb39ce1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 0000000000..97f8d12093 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54l10/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..9ff8f6c37c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..796ca66746 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l10/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..619f1f92cf --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c new file mode 100644 index 0000000000..5f682a8253 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h new file mode 100644 index 0000000000..6159c19f4b --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ From 985c698580522a6bcfab21f7c7e6bd9da1045710 Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Mon, 4 Aug 2025 16:28:17 +0200 Subject: [PATCH 055/133] [zep fromtree] platform: nordic: Fix nrF54L10 RRAM size The RRAM size of the nRF54L10 platform is 1012 Kb and not 1022 Kb so update the flash layout accordingly. Signed-off-by: Georgios Vasilakis Change-Id: I72ab05c3a7b0356408bbc0969fcb848718d67806 (cherry picked from commit 1a5763737453286783dcb4cb164193b2974675a1) --- .../common/nrf54l10/partition/flash_layout.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h index ab55734ec7..0a8df4ae90 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h @@ -27,8 +27,8 @@ * 0x0006_0000 Protected Storage Area (16 KB) * 0x0006_4000 Internal Trusted Storage Area (16 KB) * 0x0006_8000 OTP / NV counters area (8 KB) - * 0x0006_A000 Non-secure image primary (504 KB) - * 0x000E_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * 0x0006_A000 Non-secure image primary (494 KB) + * 0x000E_5800 Non-secure storage, used when built with NRF_NS_STORAGE=ON, * otherwise unused (32 KB) */ @@ -42,10 +42,10 @@ /* Use Flash memory to store Code data */ #define FLASH_BASE_ADDRESS (0x0) -/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the last 62kB are reserved +/* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the last 62kB are reserved * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along * with TF-M later FLPR non volatile memory is not used by TF-M. */ -#define FLASH_TOTAL_SIZE (0xF0000) /* 960 kB since the last 62kB are reserved for FLPR */ +#define FLASH_TOTAL_SIZE (0xED800) /* 950 kB since the last 62kB are reserved for FLPR */ #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE /* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 48kB are reserved @@ -55,7 +55,7 @@ #define TOTAL_RAM_SIZE (0x00024000) /* 144 kB since the last 48kB are reserved for FLPR */ #define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ -#define FLASH_NS_PARTITION_SIZE (0x7E000) /* NS partition: 504 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x7B800) /* NS partition: 494 kB*/ #define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS #define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS From bb31e8d3e75f8ad88e28c4254e2be65cb15e9548 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Jun 2025 17:01:10 -0700 Subject: [PATCH 056/133] [zep fromtree] platform: nordic_nrf: Add missing memory service header Commit eea63f1e12a1230217b5c3835e5dedaf0eee6e58 added memory service headers to common the common folder but missed the one for nrf54l10. Change-Id: I2dae5afc89bff7e44c1365a965cae9e46cc09d87 Signed-off-by: Flavio Ceolin Signed-off-by: Tomi Fontanilles (cherry picked from commit 0f1131be69825e08a3d57dc1e38da5667f519b03) --- .../nordic_nrf/common/nrf54l10/CMakeLists.txt | 7 ++++++ .../tfm_platform_user_memory_ranges.h | 24 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt index bab0c714d9..fd83dd0f1c 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt @@ -19,6 +19,13 @@ target_include_directories(platform_s ../nrf54l ) +if(NOT NRF_DIR) +target_include_directories(platform_s + PUBLIC + memory_service_ranges +) +endif() + target_sources(platform_s PRIVATE ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ From d44e409d0fdb9dc6b4ba7af16c197ecbdb3727e3 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 17:16:09 +0200 Subject: [PATCH 057/133] [zep fromtree] STM32WBA6 : duplicated macro definitions for ecp_alt Remove definition of MBEDTLS_ECP_MAX_BYTES and MBEDTLS_ECP_MAX_PT_LEN in stm/common/hal/accelerator/ecp_alt.h since these macros are already defined with the very same values in ecp.h. This change prevents build warning trace messages as those shown below as for example when building platform stm32l562e_dk. In file included from .../mbedtls/library/ecp_curves.c:14: .../mbedtls/include/mbedtls/ecp.h:354: warning: "MBEDTLS_ECP_MAX_BYTES" redefined 354 | #define MBEDTLS_ECP_MAX_BYTES ((MBEDTLS_ECP_MAX_BITS + 7) / 8) | In file included from .../mbedtls/include/mbedtls/ecp.h:313: .../trusted-firmware-m/platform/ext/target/stm/common/hal/accelerator/ecp_alt.h:135: note: this is the location of the previous definition 135 | #define MBEDTLS_ECP_MAX_BYTES ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 ) | .../mbedtls/include/mbedtls/ecp.h:355: warning: "MBEDTLS_ECP_MAX_PT_LEN" redefined 355 | #define MBEDTLS_ECP_MAX_PT_LEN (2 * MBEDTLS_ECP_MAX_BYTES + 1) | .../trusted-firmware-m/platform/ext/target/stm/common/hal/accelerator/ecp_alt.h:136: note: this is the location of the previous definition 136 | #define MBEDTLS_ECP_MAX_PT_LEN ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 ) | Change-Id: If0522f2249e8d213223ef2aa4fdb575ddee699b5 Signed-off-by: Ahmad EL JOUAID (cherry picked from commit 5cee012e8ccadeec24a556c87132d36493577a79) --- platform/ext/target/stm/common/hal/accelerator/ecp_alt.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/platform/ext/target/stm/common/hal/accelerator/ecp_alt.h b/platform/ext/target/stm/common/hal/accelerator/ecp_alt.h index 2afb0b19d8..b8c6cd6f88 100644 --- a/platform/ext/target/stm/common/hal/accelerator/ecp_alt.h +++ b/platform/ext/target/stm/common/hal/accelerator/ecp_alt.h @@ -132,9 +132,6 @@ mbedtls_ecp_group; * \{ */ -#define MBEDTLS_ECP_MAX_BYTES ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 ) -#define MBEDTLS_ECP_MAX_PT_LEN ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 ) - #if !defined(MBEDTLS_ECP_WINDOW_SIZE) /* * Maximum "window" size used for point multiplication. @@ -181,4 +178,4 @@ mbedtls_ecp_group; } #endif -#endif /* MBEDTLS_ECP_ALT_H */ \ No newline at end of file +#endif /* MBEDTLS_ECP_ALT_H */ From 541037ae2f771a333359c35ea2f8c9f0f9eb5807 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 17:17:54 +0200 Subject: [PATCH 058/133] [zep fromtree] STM32WBA : fix mbedtls_sha256_finish() argument Fix type of argument output in mbedtls_sha256_finish() for STM alternate SHA256 implementation. Both Mbedtls header file and STM LL header file define the argument as a unsigned pointer, not as a 32 cell unsigned array. This change fixes a build warning trace message as the one shown below: .../trusted-firmware-m/platform/ext/target/stm/common/hal/accelerator/sha256_alt.c:225:70: warning: argument 2 of type 'unsigned char[32]' with mismatched bound [-Warray-parameter=] 225 | int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32]) | ~~~~~~~~~~~~~~^~~~~~~~~~ In file included from .../trusted-firmware-m/platform/ext/target/stm/common/hal/accelerator/sha256_alt.c:29: .../mbedtls/include/mbedtls/sha256.h:128:42: note: previously declared as 'unsigned char *' 128 | unsigned char *output); | ~~~~~~~~~~~~~~~^~~~~~ Change-Id: I4ee281583c288f6270a5e35122dc00b51c67c498 Signed-off-by: Ahmad EL JOUAID Signed-off-by: Etienne Carriere (cherry picked from commit 8f4e379417aa1a7aa6bcc438a20cae5b21134fbc) --- platform/ext/target/stm/common/hal/accelerator/sha256_alt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/hal/accelerator/sha256_alt.c b/platform/ext/target/stm/common/hal/accelerator/sha256_alt.c index 3e0590834c..722957076e 100644 --- a/platform/ext/target/stm/common/hal/accelerator/sha256_alt.c +++ b/platform/ext/target/stm/common/hal/accelerator/sha256_alt.c @@ -222,7 +222,7 @@ int mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inpu return 0; } -int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32]) +int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char *output) { SHA256_VALIDATE_RET( ctx != NULL ); SHA256_VALIDATE_RET( (unsigned char *)output != NULL ); From c8b4a41257cbadb2d1b75b6027629034bf910091 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 17:19:40 +0200 Subject: [PATCH 059/133] [zep fromtree] STM32U5: fix unused variable fix build warning. Change-Id: I7d517148604fb109ddc7f437545188d60572dcd4 Signed-off-by: Ahmad EL JOUAID (cherry picked from commit 7350b3d6a91d8ee7bf0779960d06d502aa5122d5) --- .../ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c index 41eb8fd08d..55e8d34fee 100644 --- a/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c +++ b/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c @@ -361,8 +361,8 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_bind_boundary( bool ns_agent; uint32_t partition_attrs = 0; const struct asset_desc_t *p_asset; - struct platform_data_t *plat_data_ptr; #if TFM_ISOLATION_LEVEL == 2 + struct platform_data_t *plat_data_ptr; struct mpu_armv8m_region_cfg_t localcfg; #endif From b9e83985b780d89ec6e5f3de42d4ca5bba390508 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 17:20:56 +0200 Subject: [PATCH 060/133] [zep fromtree] STM32WBA6: nv_counter: fix build warnings Fix build warnings (see the build trace messages below) emitted when building STM platforms b_u585i_iot02a, nucleo_l552ze_q, stm32h573i_dk and stm32l562e_dk. All these are due to comparison between an unsigned and a signed values. .../trusted-firmware-m/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c:108:13: warning: comparison of integer expressions of different signedness: 'int32_t' {aka 'long int'} and 'unsigned int' [-Wsign-compare] 108 | if (ret != (sizeof(struct nv_counters_t) / data_width)) { | ^~ .../trusted-firmware-m/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c:120:13: warning: comparison of integer expressions of different signedness: 'int32_t' {aka 'long int'} and 'unsigned int' [-Wsign-compare] 120 | if (ret != (sizeof(struct nv_counters_t) / data_width)) { | ^~ .../trusted-firmware-m/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c:135:17: warning: comparison of integer expressions of different signedness: 'int32_t' {aka 'long int'} and 'unsigned int' [-Wsign-compare] 135 | if (ret != (sizeof(struct nv_counters_t) / data_width)) { | ^~ Signed-off-by: Ahmad EL JOUAID Signed-off-by: Etienne Carriere Change-Id: Ief59f8ba9b91cec0185c2621ff314dfc9565dde5 (cherry picked from commit 93d4badf44bed0bcbfa1dc4944a232086f02fef8) --- .../common/hal/Native_Driver/nv_counters.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c b/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c index 627177cb12..c34a1ed507 100644 --- a/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c +++ b/platform/ext/target/stm/common/hal/Native_Driver/nv_counters.c @@ -105,7 +105,7 @@ enum tfm_plat_err_t tfm_plat_init_nv_counter(void) ret = DEVICE_NV_COUNTERS_FLASH_NAME.ReadData(VALID_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -117,7 +117,7 @@ enum tfm_plat_err_t tfm_plat_init_nv_counter(void) ret = DEVICE_NV_COUNTERS_FLASH_NAME.ReadData(BACKUP_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -132,7 +132,7 @@ enum tfm_plat_err_t tfm_plat_init_nv_counter(void) ret = DEVICE_NV_COUNTERS_FLASH_NAME.ProgramData(VALID_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -153,7 +153,7 @@ enum tfm_plat_err_t tfm_plat_init_nv_counter(void) ret = DEVICE_NV_COUNTERS_FLASH_NAME.ProgramData(VALID_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -185,7 +185,7 @@ enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id, data_width = data_width_byte[DriverCapabilities.data_width]; ret = DEVICE_NV_COUNTERS_FLASH_NAME.ReadData(flash_addr, val, NV_COUNTER_SIZE / data_width); - if (ret != (NV_COUNTER_SIZE / data_width)) { + if (ret != (int32_t)(NV_COUNTER_SIZE / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -205,16 +205,16 @@ enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id, sizeof(uint16_t), sizeof(uint32_t), }; - + DriverCapabilities = DEVICE_NV_COUNTERS_FLASH_NAME.GetCapabilities(); /* Since struct nv_counter is aligned on 32 bits , a single read /write is possible */ data_width = data_width_byte[DriverCapabilities.data_width]; - + /* Read the whole sector so we can write it back to flash later */ ret = DEVICE_NV_COUNTERS_FLASH_NAME.ReadData(VALID_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -238,7 +238,7 @@ enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id, ret = DEVICE_NV_COUNTERS_FLASH_NAME.ProgramData(BACKUP_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } @@ -252,7 +252,7 @@ enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id, ret = DEVICE_NV_COUNTERS_FLASH_NAME.ProgramData(VALID_ADDRESS, &nv_counters, sizeof(struct nv_counters_t) / data_width); - if (ret != (sizeof(struct nv_counters_t) / data_width)) { + if (ret != (int32_t)(sizeof(struct nv_counters_t) / data_width)) { return TFM_PLAT_ERR_SYSTEM_ERR; } } From 50feef214796135158e1990cb9ad494cefc48d39 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 17:22:49 +0200 Subject: [PATCH 061/133] [zep fromtree] STM32WBA6: common: nv_counter backend: fix build warnings Fix build warnings due to defined but unused variables and to declared but not defined functions. .../trusted-firmware-m/platform/ext/common/template/flash_otp_nv_counters_backend.c:172:14: warning: unused variable 'backup_swap_count' [-Wunused-variable] 172 | uint32_t backup_swap_count; | ^~~~~~~~~~~~~~~~~ .../trusted-firmware-m/platform/ext/common/template/flash_otp_nv_counters_backend.c:22:28: warning: 'create_or_restore_layout' declared 'static' but never defined [-Wunused-function] 22 | static enum tfm_plat_err_t create_or_restore_layout(void); | ^~~~~~~~~~~~~~~~~~~~~~~~ .../trusted-firmware-m/platform/ext/common/template/flash_otp_nv_counters_backend.c:122:16: warning: 'block' defined but not used [-Wunused-variable] 122 | static uint8_t block[OTP_NV_COUNTERS_WRITE_BLOCK_SIZE]; | ^~~~~ Also rename copy_data_into_block() argument 'block' to 'block_ptr' to disambiguous it with the source file global variable 'block". Signed-off-by: Ahmad EL JOUAID Signed-off-by: Etienne Carriere Change-Id: Ifd56ecf53536a559e8034571eb7e2988aee444d9 (cherry picked from commit b5bb3ae59230a5662e65363543da8b8efa4644de) --- .../common/template/flash_otp_nv_counters_backend.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/platform/ext/common/template/flash_otp_nv_counters_backend.c b/platform/ext/common/template/flash_otp_nv_counters_backend.c index 224d08f532..d25eae52a8 100644 --- a/platform/ext/common/template/flash_otp_nv_counters_backend.c +++ b/platform/ext/common/template/flash_otp_nv_counters_backend.c @@ -19,7 +19,9 @@ #include +#if defined(OTP_WRITEABLE) static enum tfm_plat_err_t create_or_restore_layout(void); +#endif #if OTP_NV_COUNTERS_RAM_EMULATION @@ -119,7 +121,9 @@ static enum tfm_plat_err_t make_backup(void); #endif /* End of compilation time checks to be sure the defines are well defined */ +#if defined(OTP_WRITEABLE) static uint8_t block[OTP_NV_COUNTERS_WRITE_BLOCK_SIZE]; +#endif /* Import the CMSIS flash device driver */ extern ARM_DRIVER_FLASH OTP_NV_COUNTERS_FLASH_DEV; @@ -169,7 +173,6 @@ enum tfm_plat_err_t init_otp_nv_counters_flash(void) enum tfm_plat_err_t err = TFM_PLAT_ERR_SUCCESS; uint32_t init_value; uint32_t swap_count; - uint32_t backup_swap_count; if ((TFM_OTP_NV_COUNTERS_AREA_SIZE) < sizeof(struct flash_otp_nv_counters_region_t)) { return TFM_PLAT_ERR_SYSTEM_ERR; @@ -200,6 +203,8 @@ enum tfm_plat_err_t init_otp_nv_counters_flash(void) } else { + uint32_t backup_swap_count; + err = read_otp_nv_counters_flash(offsetof(struct flash_otp_nv_counters_region_t, swap_count) + TFM_OTP_NV_COUNTERS_AREA_SIZE, &backup_swap_count, sizeof(backup_swap_count)); @@ -307,7 +312,7 @@ static enum tfm_plat_err_t copy_data_into_block(uint32_t data_offset, const uint8_t *data, uint32_t block_offset, size_t block_size, - uint8_t *block) + uint8_t *block_ptr) { uint32_t copy_start_offset; uint32_t copy_end_offset; @@ -327,7 +332,7 @@ static enum tfm_plat_err_t copy_data_into_block(uint32_t data_offset, copy_end_offset = data_offset + data_size; } - memcpy(block + (copy_start_offset - block_offset), + memcpy(block_ptr + (copy_start_offset - block_offset), data + (copy_start_offset - data_offset), copy_end_offset - copy_start_offset); } From 84a68fbe92fe47ad07f111454ea1b6efce19542a Mon Sep 17 00:00:00 2001 From: Ronan Gabou Date: Fri, 18 Apr 2025 16:22:59 +0200 Subject: [PATCH 062/133] [zep fromtree] Platform: STM32WBA6 update regression.sh script to be compatible with flash_layout.h Change-Id: Ic4651000ac3c22f54f329d0e0aebb41ffb839b34 Signed-off-by: Ronan Gabou (cherry picked from commit d985df0942d4add420aa0dca2b4780aa8cea0458) --- .../ext/target/stm/common/stm32wbaxx/scripts/regression.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh b/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh index dca0597e37..9ce8a0f42a 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh +++ b/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh @@ -24,10 +24,10 @@ secbootadd0=0x180188 connect="-c port=SWD "$sn_option" mode=UR AP=1" connect_no_reset="-c port=SWD "$sn_option" mode=HotPlug AP=1" rdp_0="-ob RDP=0xAA TZEN=1" -remove_bank1_protect="-ob SECWM1_PSTRT=0x7f SECWM1_PEND=0" -remove_bank2_protect="-ob SECWM2_PSTRT=0x7f SECWM2_PEND=0" +remove_bank1_protect="-ob SECWM1_PSTRT=0x7f SECWM1_PEND=0x0" +remove_bank2_protect="-ob SECWM2_PSTRT=0x7f SECWM2_PEND=0x0" erase_all="-e all" -default_ob1="-ob SRAM2_RST=1 SECBOOTADD0="0x180488" DBANK=1 SWAP_BANK=0 SECWM1_PSTRT=12 SECWM1_PEND=0x42 SECWM2_PSTRT=0x0 SECWM2_PEND=0x7f" +default_ob1="-ob SRAM2_RST=1 SECBOOTADD0="0x180488" DBANK=1 SWAP_BANK=0 SECWM1_PSTRT=0x0 SECWM1_PEND=0x41 SECWM2_PSTRT=0x0 SECWM2_PEND=0x7f" echo "Regression to RDP 0, enable tz" $stm32programmercli $connect $rdp_0 From 4ceeb246466c065aa8c3371645f6c85e774f03fa Mon Sep 17 00:00:00 2001 From: Matthew Dalzell Date: Thu, 17 Apr 2025 14:41:06 +0100 Subject: [PATCH 063/133] [zep fromtree] Platform: stm: Re-aligns stm32wba65i dk naming. Re-names platform folder from stm32wba65i-dk to stm32wba65i_dk to align closer to other platforms. Change-Id: I7f14ea5be18a97031bf2f6f776bbdf2e2adeab8e Signed-off-by: Matthew Dalzell (cherry picked from commit 3d938829cc670c40a38b555b8bfc31d921930655) --- .../target/stm/{stm32wba65i-dk => stm32wba65i_dk}/CMakeLists.txt | 0 .../{stm32wba65i-dk => stm32wba65i_dk}/accelerator/CMakeLists.txt | 0 .../accelerator/crypto_accelerator_config.h | 0 .../accelerator/mbedtls_accelerator_config.h | 0 .../target/stm/{stm32wba65i-dk => stm32wba65i_dk}/config.cmake | 0 .../stm/{stm32wba65i-dk => stm32wba65i_dk}/config_tfm_target.h | 0 .../target/stm/{stm32wba65i-dk => stm32wba65i_dk}/cpuarch.cmake | 0 .../target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/board.h | 0 .../stm/{stm32wba65i-dk => stm32wba65i_dk}/include/boot_hal_cfg.h | 0 .../stm/{stm32wba65i-dk => stm32wba65i_dk}/include/device_cfg.h | 0 .../include/flash_layout_test.h | 0 .../include/platform_nv_counters_ids.h | 0 .../stm/{stm32wba65i-dk => stm32wba65i_dk}/include/stm32hal.h | 0 .../include/stm32wbaxx_hal_conf.h | 0 .../stm/{stm32wba65i-dk => stm32wba65i_dk}/ns/CMakeLists.txt | 0 .../{stm32wba65i-dk => stm32wba65i_dk}/partition/flash_layout.h | 0 .../{stm32wba65i-dk => stm32wba65i_dk}/partition/region_defs.h | 0 .../tests/psa_arch_tests_config.cmake | 0 18 files changed, 0 insertions(+), 0 deletions(-) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/CMakeLists.txt (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/accelerator/CMakeLists.txt (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/accelerator/crypto_accelerator_config.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/accelerator/mbedtls_accelerator_config.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/config.cmake (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/config_tfm_target.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/cpuarch.cmake (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/board.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/boot_hal_cfg.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/device_cfg.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/flash_layout_test.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/platform_nv_counters_ids.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/stm32hal.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/include/stm32wbaxx_hal_conf.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/ns/CMakeLists.txt (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/partition/flash_layout.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/partition/region_defs.h (100%) rename platform/ext/target/stm/{stm32wba65i-dk => stm32wba65i_dk}/tests/psa_arch_tests_config.cmake (100%) diff --git a/platform/ext/target/stm/stm32wba65i-dk/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/CMakeLists.txt rename to platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt diff --git a/platform/ext/target/stm/stm32wba65i-dk/accelerator/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/accelerator/CMakeLists.txt similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/accelerator/CMakeLists.txt rename to platform/ext/target/stm/stm32wba65i_dk/accelerator/CMakeLists.txt diff --git a/platform/ext/target/stm/stm32wba65i-dk/accelerator/crypto_accelerator_config.h b/platform/ext/target/stm/stm32wba65i_dk/accelerator/crypto_accelerator_config.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/accelerator/crypto_accelerator_config.h rename to platform/ext/target/stm/stm32wba65i_dk/accelerator/crypto_accelerator_config.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/accelerator/mbedtls_accelerator_config.h b/platform/ext/target/stm/stm32wba65i_dk/accelerator/mbedtls_accelerator_config.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/accelerator/mbedtls_accelerator_config.h rename to platform/ext/target/stm/stm32wba65i_dk/accelerator/mbedtls_accelerator_config.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/config.cmake b/platform/ext/target/stm/stm32wba65i_dk/config.cmake similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/config.cmake rename to platform/ext/target/stm/stm32wba65i_dk/config.cmake diff --git a/platform/ext/target/stm/stm32wba65i-dk/config_tfm_target.h b/platform/ext/target/stm/stm32wba65i_dk/config_tfm_target.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/config_tfm_target.h rename to platform/ext/target/stm/stm32wba65i_dk/config_tfm_target.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/cpuarch.cmake b/platform/ext/target/stm/stm32wba65i_dk/cpuarch.cmake similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/cpuarch.cmake rename to platform/ext/target/stm/stm32wba65i_dk/cpuarch.cmake diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/board.h b/platform/ext/target/stm/stm32wba65i_dk/include/board.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/board.h rename to platform/ext/target/stm/stm32wba65i_dk/include/board.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/boot_hal_cfg.h b/platform/ext/target/stm/stm32wba65i_dk/include/boot_hal_cfg.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/boot_hal_cfg.h rename to platform/ext/target/stm/stm32wba65i_dk/include/boot_hal_cfg.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/device_cfg.h b/platform/ext/target/stm/stm32wba65i_dk/include/device_cfg.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/device_cfg.h rename to platform/ext/target/stm/stm32wba65i_dk/include/device_cfg.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/flash_layout_test.h b/platform/ext/target/stm/stm32wba65i_dk/include/flash_layout_test.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/flash_layout_test.h rename to platform/ext/target/stm/stm32wba65i_dk/include/flash_layout_test.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/platform_nv_counters_ids.h b/platform/ext/target/stm/stm32wba65i_dk/include/platform_nv_counters_ids.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/platform_nv_counters_ids.h rename to platform/ext/target/stm/stm32wba65i_dk/include/platform_nv_counters_ids.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/stm32hal.h b/platform/ext/target/stm/stm32wba65i_dk/include/stm32hal.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/stm32hal.h rename to platform/ext/target/stm/stm32wba65i_dk/include/stm32hal.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/include/stm32wbaxx_hal_conf.h b/platform/ext/target/stm/stm32wba65i_dk/include/stm32wbaxx_hal_conf.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/include/stm32wbaxx_hal_conf.h rename to platform/ext/target/stm/stm32wba65i_dk/include/stm32wbaxx_hal_conf.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/ns/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/ns/CMakeLists.txt similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/ns/CMakeLists.txt rename to platform/ext/target/stm/stm32wba65i_dk/ns/CMakeLists.txt diff --git a/platform/ext/target/stm/stm32wba65i-dk/partition/flash_layout.h b/platform/ext/target/stm/stm32wba65i_dk/partition/flash_layout.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/partition/flash_layout.h rename to platform/ext/target/stm/stm32wba65i_dk/partition/flash_layout.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/partition/region_defs.h b/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/partition/region_defs.h rename to platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h diff --git a/platform/ext/target/stm/stm32wba65i-dk/tests/psa_arch_tests_config.cmake b/platform/ext/target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake similarity index 100% rename from platform/ext/target/stm/stm32wba65i-dk/tests/psa_arch_tests_config.cmake rename to platform/ext/target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake From 49c3a218cd656efa075c612a7d61a86921769ea5 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 10:33:55 +0200 Subject: [PATCH 064/133] [zep fromtree] STM32WBA6 : fix C sources build warning Fix build warnings due to unused variables in a few C source files. Signed-off-by: Ahmad EL JOUAID Change-Id: If80baaf3f8c6905135924dafa0d2a2de9f82d536 (cherry picked from commit 6104cfc6f05f5a7b922d4bf64bddee54dd9f92f7) --- .../stm/common/stm32wbaxx/secure/target_cfg.c | 2 ++ .../common/stm32wbaxx/secure/tfm_hal_isolation.c | 2 +- .../stm/common/stm32wbaxx/secure/tfm_hal_platform.c | 13 ------------- 3 files changed, 3 insertions(+), 14 deletions(-) diff --git a/platform/ext/target/stm/common/stm32wbaxx/secure/target_cfg.c b/platform/ext/target/stm/common/stm32wbaxx/secure/target_cfg.c index a2fbfb8fef..20513fbf2f 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/secure/target_cfg.c +++ b/platform/ext/target/stm/common/stm32wbaxx/secure/target_cfg.c @@ -451,6 +451,8 @@ void gtzc_init_cfg(void) { uint32_t gtzc_periph_att; + (void)gtzc_periph_att; + if (uFlowStage == FLOW_STAGE_CFG) { /* Check VTOR Is locked */ diff --git a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c index 5aba704828..6ac0d762c4 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c +++ b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c @@ -304,8 +304,8 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_bind_boundary( bool ns_agent; uint32_t partition_attrs = 0; const struct asset_desc_t *p_asset; - struct platform_data_t *plat_data_ptr; #if TFM_ISOLATION_LEVEL == 2 + struct platform_data_t *plat_data_ptr; struct mpu_armv8m_region_cfg_t localcfg; #endif diff --git a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c index 35ead4e400..10a2a5090e 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c +++ b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c @@ -18,13 +18,6 @@ extern const struct memory_region_limits memory_regions; void icache_init(void); -#ifdef TFM_OTP_DEFAULT_PROVIONNING - -extern struct flash_otp_nv_counters_region_t otp_stm_provision; -#define OTP_KEEP otp_stm_provision.init_value - -#endif /*TFM_OTP_DEFAULT_PROVIONNING*/ - /* When BL2 is not activated, dummy SRAM shared data area is provided below. This is required by Firmware Update (FWU) and Initial Attestation (IAT) services. @@ -63,12 +56,6 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) FIH_RET(fih_int_encode(TFM_HAL_ERROR_GENERIC)); } -#ifdef TFM_OTP_DEFAULT_PROVIONNING - - /* Place here to force linker to keep provision and init const */ - __IO uint32_t otp = OTP_KEEP; -#endif /*TFM_OTP_DEFAULT_PROVIONNING*/ - #ifdef DEFAULT_SHARED_DATA unsigned char *boot_data = (unsigned char *)BOOT_TFM_SHARED_DATA_BASE; memcpy(boot_data, dummy_data, sizeof(dummy_data)); From a6f55e47fe2e6f0c5a522c283b4601d46a2135a4 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 10:58:06 +0200 Subject: [PATCH 065/133] [zep fromtree] STM32WBA6 : remove duplicated platform_bl2 directives Remove platform_bl2 compile definition duplicates in stm accelerator CMake file. Signed-off-by: Ahmad EL JOUAID Change-Id: I60472e476395e2d6fbd87cd970e2357c051237d5 (cherry picked from commit eea80dd686b879b8d64737e9ea0293fdf7fc9485) --- platform/ext/accelerator/stm/CMakeLists.txt | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/platform/ext/accelerator/stm/CMakeLists.txt b/platform/ext/accelerator/stm/CMakeLists.txt index 2051284895..7c6cf6bca4 100644 --- a/platform/ext/accelerator/stm/CMakeLists.txt +++ b/platform/ext/accelerator/stm/CMakeLists.txt @@ -14,20 +14,6 @@ if(NOT DEFINED PLATFORM_DIR) set(PLATFORM_DIR ../../.. CACHE PATH "Path to plaform dir") endif() -if(BL2) -target_compile_definitions(platform_bl2 - PRIVATE - CRYPTO_HW_ACCELERATOR -) -endif() - -if(BL2) -target_compile_definitions(platform_bl2 - PRIVATE - CRYPTO_HW_ACCELERATOR -) -endif() - if (PLATFORM_DEFAULT_PROVISIONING) # mbedtls_accelerator_config.h is included from the profile config files and must # be visible in the platform_s always, due to the compilation of provisioning.c From 0d71d8f501367ab6a10a594797f5992ed4bbe2e5 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 11:05:36 +0200 Subject: [PATCH 066/133] [zep fromtree] STM32WBA6 : disable MPU before its reconfigured Disable STM32WBA6 MPU prior its configuration to not be dependent on prior boot stage configuration. This fixes a issue when TF-M isolation level above 1 and is booted by an earlier boot stage. Signed-off-by: Ahmad EL JOUAID Change-Id: If367ae1ab17198446b24e7b4bdd8671de1c98448 (cherry picked from commit 81228ea3d7b68856210e8bd657068f54f7035d2c) --- .../ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c index 6ac0d762c4..e54567e486 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c +++ b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_isolation.c @@ -142,6 +142,7 @@ static enum tfm_hal_status_t mpu_init(void) /* configuration stage */ if (uFlowStage == FLOW_STAGE_CFG) { + mpu_armv8m_disable(&dev_mpu_s); mpu_armv8m_clean(&dev_mpu_s); /* configure secure MPU regions */ From 37d77749aaeedbe1af51d27d5a6be0d5056e8f84 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 11:38:40 +0200 Subject: [PATCH 067/133] [zep fromtree] STM32WBA6 : remove unused BL2 macros Remove definitions of TF-M BL2 macros that are not used in the scope of target platform stm32wba65i_dk. Signed-off-by: Ahmad EL JOUAID Change-Id: Icfc5b4e9fecbd38b07bdb462fb130016679956cd (cherry picked from commit a6db3810fb946ca31770e207b4a45a1b4469fb92) --- .../stm32wba65i_dk/partition/region_defs.h | 126 ------------------ 1 file changed, 126 deletions(-) diff --git a/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h b/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h index 164e2054cc..b95e3fdb10 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h +++ b/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h @@ -18,22 +18,8 @@ #define __REGION_DEFS_H__ #include "flash_layout.h" -#ifdef TFM_PARTITION_FIRMWARE_UPDATE #define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) -#endif - -#define BL2_HEAP_SIZE 0x0000000 -#define BL2_MSP_STACK_SIZE 0x0002000 - -#define LOADER_NS_MSP_STACK_SIZE 0x0000400 -#define LOADER_NS_HEAP_SIZE 0x0000200 -#define LOADER_NS_PSP_STACK_SIZE 0x0000400 - -#define LOADER_S_MSP_STACK_SIZE 0x0000400 -#define LOADER_S_HEAP_SIZE 0x0000200 -#define LOADER_S_PSP_STACK_SIZE 0x0000400 - #define S_HEAP_SIZE 0x00000C0 #define S_MSP_STACK_SIZE_INIT 0x0000400 @@ -95,7 +81,6 @@ #define BL2_DATA_HEADER_SIZE (0x20) /*!< Data image header size */ -#define S_IMAGE_PRIMARY_PARTITION_OFFSET FLASH_AREA_0_OFFSET #define NS_IMAGE_PRIMARY_PARTITION_OFFSET FLASH_AREA_1_OFFSET @@ -168,117 +153,11 @@ #define OTP_AREA_SIZE (TFM_OTP_NV_COUNTERS_AREA_SIZE) #endif //TFM_OTP_DEFAULT_PROVIONNING// -#ifdef BL2 -/* Personalized region */ -#define PERSO_START (S_ROM_ALIAS(FLASH_AREA_PERSO_OFFSET)) -#define PERSO_SIZE (FLASH_AREA_PERSO_SIZE) -#define PERSO_LIMIT (PERSO_START + PERSO_SIZE - 1) - -/* Bootloader region protected by hdp */ -#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) -#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) -#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) - -/* Bootloader region not protected by hdp */ -#define BL2_NOHDP_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_NOHDP_OFFSET)) -#define BL2_NOHDP_CODE_SIZE (FLASH_AREA_BL2_NOHDP_SIZE) -#define BL2_NOHDP_CODE_LIMIT (BL2_NOHDP_CODE_START + BL2_NOHDP_CODE_SIZE - 1) - -/* Bootloader boot address */ -#define BL2_BOOT_VTOR_ADDR (BL2_CODE_START) - -/* keep 256 bytes unused to place while(1) for non secure to enable */ -/* regression from local tool with non secure attachment - * This avoid blocking board in case of hardening error */ -#define BL2_DATA_START (S_RAM_ALIAS(_SRAM1_SIZE_MAX)) -#define BL2_DATA_SIZE (BOOT_TFM_SHARED_DATA_BASE - BL2_DATA_START) -#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) - -/* Define BL2 MPU SRAM protection to remove execution capability */ -/* Area is covering the complete SRAM memory space non secure alias and secure alias */ -#define BL2_SRAM_AREA_BASE (_SRAM1_BASE_NS) -#define BL2_SRAM_AREA_END (_SRAM4_BASE_S + _SRAM4_SIZE_MAX -1) - -/* Define Area provision by BL2 */ -#define BL2_OTP_AREA_BASE S_ROM_ALIAS(TFM_OTP_NV_COUNTERS_AREA_ADDR) -#define BL2_OTP_AREA_SIZE (TFM_OTP_NV_COUNTERS_AREA_SIZE) -/* Define Area for Initializing NVM counter */ -/* backup sector is initialised */ -#define BL2_NVM_AREA_BASE S_ROM_ALIAS(TFM_NV_COUNTERS_AREA_ADDR+FLASH_AREA_IMAGE_SECTOR_SIZE) -#define BL2_NVM_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) -/* Define Area for initializing BL2_NVCNT */ -/* backup sector is initialised */ -#define BL2_NVMCNT_AREA_BASE S_ROM_ALIAS(FLASH_BL2_NVCNT_AREA_OFFSET+FLASH_AREA_IMAGE_SECTOR_SIZE) -#define BL2_NVMCNT_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) -#endif /* BL2 */ - -#define LOADER_NS_CODE_SIZE (0x6000) /* 24 Kbytes */ - -#if defined(MCUBOOT_PRIMARY_ONLY) -/* Secure Loader Image */ -#define FLASH_AREA_LOADER_BANK_OFFSET (FLASH_B_SIZE-LOADER_IMAGE_S_CODE_SIZE-LOADER_NS_CODE_SIZE) -#define FLASH_AREA_LOADER_OFFSET (FLASH_TOTAL_SIZE-LOADER_IMAGE_S_CODE_SIZE-LOADER_NS_CODE_SIZE) -/* Control Secure Loader Image */ -#if (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "FLASH_AREA_LOADER_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ - -/* Non-Secure Loader Image */ -#define LOADER_NS_CODE_START (LOADER_NS_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET + LOADER_IMAGE_S_CODE_SIZE)) -/* Control Non-Secure Loader Image */ -#if (LOADER_NS_CODE_START % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "LOADER_NS_CODE_START not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (LOADER_NS_CODE_START % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ - -/* define used for checking possible overlap */ -#define LOADER_CODE_SIZE (LOADER_NS_CODE_SIZE+LOADER_IMAGE_S_CODE_SIZE) -#else -/* Loader Image */ -#define FLASH_AREA_LOADER_BANK_OFFSET (FLASH_B_SIZE-LOADER_NS_CODE_SIZE) -#define FLASH_AREA_LOADER_OFFSET (FLASH_TOTAL_SIZE-LOADER_NS_CODE_SIZE) -/* Control Loader Image */ -#if (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "FLASH_AREA_LOADER_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ - -#define LOADER_NS_CODE_START (LOADER_NS_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET)) -/* define used for checking possible overlap */ -#define LOADER_CODE_SIZE (LOADER_NS_CODE_SIZE) -#endif /* MCUBOOT_PRIMARY_ONLY */ - -#define LOADER_IMAGE_S_CODE_SIZE (0x4000) /* 16 Kbytes */ -#define LOADER_CMSE_VENEER_REGION_SIZE (0x100) -#define LOADER_S_CODE_START (LOADER_S_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET)) -#define LOADER_S_CODE_SIZE (LOADER_IMAGE_S_CODE_SIZE - LOADER_CMSE_VENEER_REGION_SIZE) -#define LOADER_S_CODE_LIMIT (LOADER_S_CODE_START + LOADER_S_CODE_SIZE -1) -#define LOADER_S_DATA_START (S_RAM_ALIAS(_SRAM1_SIZE_MAX)) -#define LOADER_S_DATA_SIZE (_SRAM2_SIZE_MAX) -#define LOADER_S_DATA_LIMIT (LOADER_S_DATA_START + LOADER_S_DATA_SIZE - 1) -#define LOADER_CMSE_VENEER_REGION_START (LOADER_S_CODE_LIMIT + 1) -#define LOADER_CMSE_VENEER_REGION_LIMIT (LOADER_S_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET+LOADER_IMAGE_S_CODE_SIZE - 1)) - -#define LOADER_NS_CODE_LIMIT (LOADER_NS_CODE_START+LOADER_NS_CODE_SIZE - 1) -#define LOADER_NS_DATA_START (NS_RAM_ALIAS(0x0)) -#define LOADER_NS_DATA_SIZE (_SRAM1_SIZE_MAX) -#define LOADER_NS_DATA_LIMIT (LOADER_NS_DATA_START + LOADER_NS_DATA_SIZE - 1) - -#ifdef MCUBOOT_PRIMARY_ONLY -#define LOADER_MAX_CODE_SIZE (FLASH_TOTAL_SIZE - FLASH_AREA_1_OFFSET - FLASH_AREA_1_SIZE) -#else -#define LOADER_MAX_CODE_SIZE (FLASH_TOTAL_SIZE - FLASH_AREA_3_OFFSET - FLASH_AREA_3_SIZE) -#endif /* MCUBOOT_PRIMARY_ONLY */ - -#if LOADER_CODE_SIZE > LOADER_MAX_CODE_SIZE -#error "Loader mapping overlapping slot %LOADER_CODE_SIZE %LOADER_MAX_CODE_SIZE" -#endif /* LOADER_CODE_SIZE > LOADER_MAX_CODE_SIZE */ - /* TFM non volatile data (NVCNT/PS/ITS) region */ #define TFM_NV_DATA_START (S_ROM_ALIAS(FLASH_OTP_NV_COUNTERS_AREA_OFFSET)) #define TFM_NV_DATA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE + FLASH_NV_COUNTER_AREA_SIZE \ + FLASH_PS_AREA_SIZE + FLASH_ITS_AREA_SIZE) #define TFM_NV_DATA_LIMIT (TFM_NV_DATA_START + TFM_NV_DATA_SIZE - 1) -/* Additional Check to detect flash download slot overlap or overflow */ -#define FLASH_AREA_END_OFFSET_MAX (FLASH_TOTAL_SIZE) #if (MCUBOOT_S_DATA_IMAGE_NUMBER == 1) /* S DATA image layout */ @@ -291,9 +170,4 @@ #define NS_DATA_IMAGE_DATA1_SIZE (32U) #endif /* (MCUBOOT_NS_DATA_IMAGE_NUMBER == 1) */ -#if FLASH_AREA_END_OFFSET > FLASH_AREA_END_OFFSET_MAX -#error "Flash memory overflow" -#endif /* FLASH_AREA_END_OFFSET > FLASH_AREA_END_OFFSET_MAX */ - - #endif /* __REGION_DEFS_H__ */ \ No newline at end of file From 5bd37727c99290697bad0fd962145387da5b8aad Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 12:05:09 +0200 Subject: [PATCH 068/133] [zep fromtree] STM32WBA6: Split firmware and OTP binary images Generate TF-M firmware image and OTP provisioning image binary files from the TF-M linked image for platform stm32wba65i_dk. This allows to sign only thee TF-M firmware image blob and loading the OTP provisioning image when using a boot loader stage external to TF-M. Signed-off-by: Ahmad EL JOUAID Change-Id: Ic4a9a741dbd9916423ca69d8749e2d45141e1b5e (cherry picked from commit 201efdfb09bb751fc0e3556e561921fbe7a3640b) --- .../target/stm/stm32wba65i_dk/CMakeLists.txt | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt index c1ca7edc70..0406e0394d 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt +++ b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt @@ -74,4 +74,30 @@ install(DIRECTORY ${PLATFORM_DIR}/ext/common # Install test configs install(DIRECTORY ${TARGET_PLATFORM_PATH}/tests - DESTINATION ${INSTALL_PLATFORM_NS_DIR}) \ No newline at end of file + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Extract firmware and OTP binary image files +get_target_property(tfm_s_bin_dir tfm_s RUNTIME_OUTPUT_DIRECTORY) + +set(tfm_s_split_out + ${tfm_s_bin_dir}/tfm_s_fmw.bin + ${tfm_s_bin_dir}/tfm_s_otp.bin +) + +add_custom_target(tfm_s_fmw ALL SOURCES ${tfm_s_split_out}) + +if(CMAKE_C_COMPILER STREQUAL "iccarm") +add_custom_command( + OUTPUT ${tfm_s_split_out} + DEPENDS tfm_s_binaries + COMMAND ielftool --silent --exclude=.BL2_OTP --bin $ ${tfm_s_bin_dir}/tfm_s_fmw.bin + COMMAND ielftool --silent --only=.BL2_OTP --bin $ ${tfm_s_bin_dir}/tfm_s_otp.bin +) +else() +add_custom_command( + OUTPUT ${tfm_s_split_out} + DEPENDS tfm_s_binaries + COMMAND ${CMAKE_OBJCOPY} --remove-section .BL2_OTP -O binary $ ${tfm_s_bin_dir}/tfm_s_fmw.bin + COMMAND ${CMAKE_OBJCOPY} --only-section .BL2_OTP -O binary $ ${tfm_s_bin_dir}/tfm_s_otp.bin +) +endif() From 80c7bf71df810722deff652087e9119829e6e69f Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 12:07:01 +0200 Subject: [PATCH 069/133] [zep fromtree] STM32WBA6: Make flash offset gap configurable Add support for configuration directive STM32_FLASH_LAYOUT_BEGIN_OFFSET in TF-M for platform stm32wba65i_dk to define the offset from flash beginning where TF-M storage location starts. This replaces the static offset of 96kB introduced in commit 1930dcd99bf7 ("STM platform : some update for TF-Mv2.1.1"). Having a build configuration directive instead makes it easier for platforms to build TF-M according to the flash area consumed by their bootloader resources. Update the platform flash_layout.h header file is update accordingly including the inline description comment. Update the regression script accordingly, and also change it to make internal flash bank1 non-secure. Signed-off-by: Ahmad EL JOUAID Signed-off-by: Etienne Carriere Change-Id: Iae77d1c50e73d79f4fd4402e8ffec6c6ce680234 (cherry picked from commit fc035b874e0ab86e2a13a328da3dce0cf18eb566) --- .../stm/common/stm32wbaxx/CMakeLists.txt | 9 +- .../common/stm32wbaxx/scripts/postbuild.sh | 6 +- .../common/stm32wbaxx/scripts/regression.sh | 7 +- .../target/stm/stm32wba65i_dk/config.cmake | 1 + .../stm32wba65i_dk/partition/flash_layout.h | 126 ++++++------------ 5 files changed, 55 insertions(+), 94 deletions(-) diff --git a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt index 8c6326353f..68627e48a0 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt @@ -23,6 +23,7 @@ target_compile_definitions(platform_region_defs $<$:TFM_OTP_DEFAULT_PROVIONNING> $<$:DEFAULT_SHARED_DATA> $<$,$>:FLASH_LAYOUT_FOR_TEST> + STM32_FLASH_LAYOUT_BEGIN_OFFSET=${STM32_FLASH_LAYOUT_BEGIN_OFFSET} ) #========================= Platform common defs ===============================# @@ -50,6 +51,7 @@ target_compile_definitions(platform_s PUBLIC $<$:TFM_OTP_DEFAULT_PROVIONNING> $<$:DEFAULT_SHARED_DATA> + STM32_FLASH_LAYOUT_BEGIN_OFFSET=${STM32_FLASH_LAYOUT_BEGIN_OFFSET} ) target_sources(platform_s @@ -233,6 +235,7 @@ else() endif() set(CONTENT_FOR_PREPROCESSING + "#define STM32_FLASH_LAYOUT_BEGIN_OFFSET (${STM32_FLASH_LAYOUT_BEGIN_OFFSET})\n\n" "#include \"flash_layout.h\"\n\n" "enum image_attributes {\n" "\tRE_IMAGE_FLASH_ADDRESS_SECURE = (FLASH_BASE_ADDRESS+FLASH_AREA_0_OFFSET),\n" @@ -244,10 +247,12 @@ set(CONTENT_FOR_PREPROCESSING "#else\n" "\tRE_BL2_PROVISION_ADDRESS = 0x0,\n" "#endif\n" - "\tRE_BOOT_ADDRESS = (FLASH_BASE_ADDRESS+FLASH_AREA_0_OFFSET),\n" + "\tRE_BOOT_ADDRESS = (FLASH_BASE_ADDRESS+FLASH_AREA_0_OFFSET+BL2_HEADER_SIZE),\n" "\tRE_IMAGE_FLASH_NV_COUNTERS = (FLASH_BASE_ADDRESS+FLASH_OTP_NV_COUNTERS_AREA_OFFSET),\n" "\tRE_IMAGE_FLASH_NV_PS = (FLASH_BASE_ADDRESS+FLASH_PS_AREA_OFFSET),\n" - "\tRE_IMAGE_FLASH_NV_ITS = (FLASH_BASE_ADDRESS+FLASH_ITS_AREA_OFFSET),\n}\;" + "\tRE_IMAGE_FLASH_NV_ITS = (FLASH_BASE_ADDRESS+FLASH_ITS_AREA_OFFSET),\n" + "\tRE_IMAGE_FLASH_SECURE_LAST_OFFSET = (FLASH_AREA_1_OFFSET-0x1),\n" + "}\;" ) string(CONCAT BL2_PREPROCESSING ${FLAGS_FOR_BL2_PREPROCESSING} diff --git a/platform/ext/target/stm/common/stm32wbaxx/scripts/postbuild.sh b/platform/ext/target/stm/common/stm32wbaxx/scripts/postbuild.sh index 58c010c9f1..84353c442a 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/scripts/postbuild.sh +++ b/platform/ext/target/stm/common/stm32wbaxx/scripts/postbuild.sh @@ -51,7 +51,9 @@ if [ $ret != 0 ]; then fi fi -command=$cmd" "$stm_tool" flash --layout "$preprocess_bl2_file" -b stm32wba6xx -m RE_STM32WBA6 -s 0 "$regressionsh +flash_sector_size=8192 + +command=$cmd" "$stm_tool" flash --layout "$preprocess_bl2_file" -b secbootadd0 -m RE_BOOT_ADDRESS -d 0x80 -s 0 "$regressionsh $command >> $projectdir"/output.txt" ret=$? if [ $ret != 0 ]; then @@ -60,7 +62,7 @@ echo $command exit 1 fi -command=$cmd" "$stm_tool" flash --layout "$preprocess_bl2_file" -b secbootadd0 -m RE_BOOT_ADDRESS -d 0x80 -s 0 "$regressionsh +command=$cmd" "$stm_tool" flash --layout "$preprocess_bl2_file" -b sec_pend_offset -m RE_IMAGE_FLASH_SECURE_LAST_OFFSET -d $flash_sector_size -s 0 "$regressionsh $command >> $projectdir"/output.txt" ret=$? if [ $ret != 0 ]; then diff --git a/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh b/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh index 9ce8a0f42a..c38113a2c0 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh +++ b/platform/ext/target/stm/common/stm32wbaxx/scripts/regression.sh @@ -20,14 +20,15 @@ fi PATH="/C/Program Files/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin/":$PATH stm32programmercli="STM32_Programmer_CLI" # remove write protection -secbootadd0=0x180188 +secbootadd0= +sec_pend_offset= connect="-c port=SWD "$sn_option" mode=UR AP=1" connect_no_reset="-c port=SWD "$sn_option" mode=HotPlug AP=1" rdp_0="-ob RDP=0xAA TZEN=1" remove_bank1_protect="-ob SECWM1_PSTRT=0x7f SECWM1_PEND=0x0" remove_bank2_protect="-ob SECWM2_PSTRT=0x7f SECWM2_PEND=0x0" erase_all="-e all" -default_ob1="-ob SRAM2_RST=1 SECBOOTADD0="0x180488" DBANK=1 SWAP_BANK=0 SECWM1_PSTRT=0x0 SECWM1_PEND=0x41 SECWM2_PSTRT=0x0 SECWM2_PEND=0x7f" +default_ob1="-ob SRAM2_RST=1 SECBOOTADD0="$secbootadd0" DBANK=1 SWAP_BANK=0 SECWM1_PSTRT=0x0 SECWM1_PEND="$sec_pend_offset" SECWM2_PSTRT=0x7f SECWM2_PEND=0x0" echo "Regression to RDP 0, enable tz" $stm32programmercli $connect $rdp_0 @@ -37,6 +38,6 @@ echo "Remove bank2 protection and erase all" $stm32programmercli $connect_no_reset $remove_bank2_protect $erase_all echo "-----------erasing-----------" $stm32programmercli $connect $erase_all -echo "Set default OB 1 (dual bank, swap bank, sram2 reset, secure entry point, bank 1 full secure)" +echo "Set default OB 1 (dual bank, swap bank, sram2 reset, secure entry point, bank 1 full non-secure)" $stm32programmercli $connect_no_reset $default_ob1 echo "regression script done, press key" diff --git a/platform/ext/target/stm/stm32wba65i_dk/config.cmake b/platform/ext/target/stm/stm32wba65i_dk/config.cmake index 6321f9775d..05a60d04d0 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/config.cmake +++ b/platform/ext/target/stm/stm32wba65i_dk/config.cmake @@ -30,6 +30,7 @@ set(TFM_MULTI_CORE_TOPOLOGY OFF CACHE BOOL "Platfor set(PLATFORM_HAS_FIRMWARE_UPDATE_SUPPORT ON CACHE BOOL "Wheter the platform has firmware update support") set(TFM_OTP_DEFAULT_PROVIONNING ON CACHE BOOL "OTP AREA provisionning by TFM") set(DEFAULT_SHARED_DATA ON CACHE BOOL "SHARED_DATA provisionning by TFM") +set(STM32_FLASH_LAYOUT_BEGIN_OFFSET 0 CACHE STRING "Byte offset gap from flash begin TF-M resources are located") ################################## LOG LEVEL ############################################################# set(TFM_SPM_LOG_LEVEL TFM_SPM_LOG_LEVEL_DEBUG CACHE STRING "Set default SPM log level as INFO level") set(TFM_PARTITION_LOG_LEVEL TFM_PARTITION_LOG_LEVEL_DEBUG CACHE STRING "Set default Secure Partition log level as INFO level") diff --git a/platform/ext/target/stm/stm32wba65i_dk/partition/flash_layout.h b/platform/ext/target/stm/stm32wba65i_dk/partition/flash_layout.h index 7017d194ae..69d71ad77e 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/partition/flash_layout.h +++ b/platform/ext/target/stm/stm32wba65i_dk/partition/flash_layout.h @@ -17,20 +17,32 @@ #ifndef __FLASH_LAYOUT_H__ #define __FLASH_LAYOUT_H__ -/* Flash layout with BL2: +/* Flash layout with TF-M BL2: * * Not supported * - * Flash layout for stm32wba65i-dk without BL2 : + * Default flash offsets for stm32wba65i-dk: * - * 0x000_0000 OTP / NV counters area (8 KB) - * 0x000_4000 Protected Storage Area (16 KB) - * 0x000_8000 Internal Trusted Storage Area (16 KB) - * 0x000_c400 Secure image (384 KB) - * 0x006_c400 Non-secure image primary (512 KB) + * 0x000_0000 OTP / NV counters area (16 KB) + * 0x000_4000 Protected Storage Area (16 KB) + * 0x000_8000 Internal Trusted Storage Area (16 KB) + * 0x000_C000 Secure primary image (256 KB) + * 0x004_C000 Non-secure primary image (512 KB) + * 0x00C_C000 Secure secondary image (256 KB) + * 0x010_C000 Non-secure secondary image (512 KB) + * 0x018_C000 Non-secure private storage (up to 464 KB) + * + * Build directive FLASH_LAYOUT_BEGIN_OFFSET may define an offset + * applied to the values above. This offset is used when an external + * boot loader is embedded an occupies the begnining of the flash. + * + * Note: + * Secure primary image, Non-secure primary image, + * Secure secondary image and non-secure secondary image + * each include a 1kByte header and a 1kByte trialer + * before/after the firmware image content. */ - /* This header file is included from linker scatter file as well, where only a * limited C constructs are allowed. Therefore it is not possible to include * here the platform_retarget.h to access flash related defines. To resolve this @@ -44,6 +56,13 @@ #error "BL2 configuration is not supported" #endif /* BL2 */ +#ifndef BL2_HEADER_SIZE +#define BL2_HEADER_SIZE (0x400) /*!< Appli image header size */ +#endif +#ifndef BL2_TRAILER_SIZE +#define BL2_TRAILER_SIZE (0x400) +#endif + /* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ #define FLASH_AREA_IMAGE_SECTOR_SIZE (0x2000) /* 8 kB */ /* Same as FLASH0_SIZE */ @@ -53,43 +72,14 @@ /* Flash layout info for BL2 bootloader */ #define FLASH_BASE_ADDRESS (0x0c000000) /* same as FLASH0_BASE */ -#define FLASH_HASH_REF_AREA_OFFSET (0x0000) -#define FLASH_HASH_REF_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) - -/* area for HUK and anti roll back counter */ -#define FLASH_BL2_NVCNT_AREA_OFFSET (FLASH_HASH_REF_AREA_OFFSET + FLASH_HASH_REF_AREA_SIZE) -#define FLASH_BL2_NVCNT_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) - -/* scratch area */ -#define FLASH_AREA_SCRATCH_OFFSET (FLASH_BL2_NVCNT_AREA_OFFSET + FLASH_BL2_NVCNT_AREA_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (0x0000) /* Not used in MCUBOOT_OVERWRITE_ONLY mode */ -/* control scratch area */ -#if (FLASH_AREA_SCRATCH_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "FLASH_AREA_SCRATCH_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (FLASH_AREA_SCRATCH_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0*/ - -/* personal area */ -#define FLASH_AREA_PERSO_OFFSET (FLASH_BL2_NVCNT_AREA_OFFSET + FLASH_BL2_NVCNT_AREA_SIZE + \ - FLASH_AREA_SCRATCH_SIZE) -#define FLASH_AREA_PERSO_SIZE (0x2000) -/* control personal area */ -#if (FLASH_AREA_PERSO_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "FLASH_AREA_PERSO_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* FLASH_AREA_PERSO_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ - -/* area for BL2 code protected by hdp */ -#define FLASH_AREA_BL2_OFFSET (FLASH_AREA_PERSO_OFFSET+FLASH_AREA_PERSO_SIZE) -#define FLASH_AREA_BL2_SIZE (0x10000) - -/* HDP area end at this address */ -#define FLASH_BL2_HDP_END (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE-1) -/* area for BL2 code not protected by hdp */ -#define FLASH_AREA_BL2_NOHDP_OFFSET (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE) -#define FLASH_AREA_BL2_NOHDP_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) -/* control area for BL2 code protected by hdp */ -#if (FLASH_AREA_BL2_NOHDP_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "HDP area must be aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (FLASH_AREA_BL2_NOHDP_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ +#ifdef STM32_FLASH_LAYOUT_BEGIN_OFFSET +#define FLASH_BEGIN_OFFSET (STM32_FLASH_LAYOUT_BEGIN_OFFSET) +#if (FLASH_BEGIN_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 +#error "STM32_FLASH_LAYOUT_BEGIN_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" +#endif /* (FLASH_BEGIN_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0*/ +#else +#define FLASH_BEGIN_OFFSET 0 +#endif /*TFM_PARTITION_FIRMWARE_UPDATE*/ /* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ @@ -115,7 +105,7 @@ /* Secure image secondary slot */ #define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) -#define FLASH_AREA_2_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET + FLASH_B_SIZE) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) #define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE) /* Non-secure image secondary slot */ #define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) @@ -145,9 +135,9 @@ /*TFM_PARTITION_FIRMWARE_UPDATE*/ /* The size of S partition */ -#define FLASH_S_PARTITION_SIZE (0x60000) /* 384 KB for S partition */ +#define FLASH_S_PARTITION_SIZE (0x40000) /* 256 KB for S partition */ /* The size of NS partition */ -#define FLASH_NS_PARTITION_SIZE (0x60000) /* 512 KB for NS partition */ +#define FLASH_NS_PARTITION_SIZE (0x80000) /* 512 KB for NS partition */ /* Non Volatile Counters definitions */ #define FLASH_NV_COUNTERS_AREA_OFFSET (0x0000) @@ -160,8 +150,7 @@ /* OTP / Non Volatile Counters definitions */ #define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) -#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET + \ - FLASH_AREA_BL2_NOHDP_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_BEGIN_OFFSET) #define FLASH_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_SECTOR_SIZE + \ FLASH_OTP_NV_COUNTERS_SECTOR_SIZE) @@ -185,23 +174,6 @@ #define FLASH_AREA_BEGIN_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) -/* Secure app image primary slot */ -#define FLASH_AREA_0_OFFSET (FLASH_AREA_BEGIN_OFFSET) -#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) -/* Control Secure app image primary slot */ -#if (FLASH_AREA_0_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "FLASH_AREA_0_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (FLASH_AREA_0_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ - -/* Non-secure app image primary slot */ -#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) -#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) -/* Control Non-secure app image primary slot */ -#if (FLASH_AREA_1_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 -#error "FLASH_AREA_1_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" -#endif /* (FLASH_AREA_1_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ - - /* flash areas end offset */ #define FLASH_AREA_END_OFFSET (FLASH_AREA_BEGIN_OFFSET + FLASH_AREA_0_SIZE + FLASH_AREA_1_SIZE) @@ -218,13 +190,6 @@ #define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE #endif - -#define SECURE_IMAGE_OFFSET (0x0) -#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE - -#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + SECURE_IMAGE_MAX_SIZE) -#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE - /* Flash device name used by BL2 and NV Counter * Name is defined in flash driver file: low_level_flash.c */ @@ -283,19 +248,6 @@ #define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE #define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ TFM_OTP_NV_COUNTERS_AREA_SIZE) -/* NV Counters definitions */ -#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET -#define TFM_NV_COUNTERS_AREA_SIZE (0x20)/* 32 Bytes */ -#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET -#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE - -/* BL2 NV Counters definitions */ -#define BL2_NV_COUNTERS_AREA_ADDR FLASH_BL2_NVCNT_AREA_OFFSET -#define BL2_NV_COUNTERS_AREA_SIZE FLASH_BL2_NVCNT_AREA_SIZE - -/* FIXME: not valid today */ -#define BL2_S_RAM_ALIAS_BASE (0x30000000) -#define BL2_NS_RAM_ALIAS_BASE (0x20000000) /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) From e42754dc442b2db70eca5dd18459cda062b7d7da Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 22 May 2025 15:06:41 +0200 Subject: [PATCH 070/133] [zep fromtree] STM32WBA6: fix typo on MCUBOOT_UPGRADE_STRATEGY config Remove MCUBOOT_UPGRADE_STRATEGY configuration directive for platform stm32wba65i_dk that was wrongly set and not considered. Because of the typo (leading 'D' char), the configuration defaulted to TF-M default config that is OVERWRITE_ONLY. No functional change. Signed-off-by: Ahmad EL JOUAID Change-Id: Ic2397a373bd3d69a3aba1d8c1d85cadfafc00b49 (cherry picked from commit b456fe740e351cfa6888a47ec80f66cc1e4a86c3) --- platform/ext/target/stm/stm32wba65i_dk/config.cmake | 1 - 1 file changed, 1 deletion(-) diff --git a/platform/ext/target/stm/stm32wba65i_dk/config.cmake b/platform/ext/target/stm/stm32wba65i_dk/config.cmake index 05a60d04d0..bc66fe6a1c 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/config.cmake +++ b/platform/ext/target/stm/stm32wba65i_dk/config.cmake @@ -40,5 +40,4 @@ set(TFM_FWU_BOOTLOADER_LIB "mcuboot" CACHE STRING "Bootload set(TFM_CONFIG_FWU_MAX_WRITE_SIZE 1024 CACHE STRING "The maximum permitted size for block in psa_fwu_write, in bytes.") set(TFM_CONFIG_FWU_MAX_MANIFEST_SIZE 0 CACHE STRING "The maximum permitted size for manifest in psa_fwu_start(), in bytes.") set(FWU_DEVICE_CONFIG_FILE "" CACHE STRING "The device configuration file for Firmware Update partition") -set(DMCUBOOT_UPGRADE_STRATEGY SWAP_USING_MOVE) set(MCUBOOT_DATA_SHARING ON CACHE BOOL "Add sharing of application specific data using the same shared data area as for the measured boot") From 82f11dad20b13f1bcb5c082084858ba03835d976 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Wed, 28 May 2025 18:25:58 +0200 Subject: [PATCH 071/133] [zep fromtree] STM32WBA: fix some issue. 1- Force linker to keep provision and init const. 2- check flash memory overflow. Signed-off-by: Ahmad EL JOUAID Change-Id: Iaebf4dfad998a02c7d67ecd7b31c2abff23f9d94 (cherry picked from commit 800f8a872c915ad74f619f28d4b3a62c1fe3d978) --- .../stm/common/stm32wbaxx/secure/tfm_hal_platform.c | 11 +++++++++++ .../target/stm/stm32wba65i_dk/partition/region_defs.h | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c index 10a2a5090e..923f20d2fd 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c +++ b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c @@ -18,6 +18,12 @@ extern const struct memory_region_limits memory_regions; void icache_init(void); +#ifdef TFM_OTP_DEFAULT_PROVIONNING + +extern struct flash_otp_nv_counters_region_t otp_stm_provision; +#define OTP_KEEP otp_stm_provision.init_value + +#endif /*TFM_OTP_DEFAULT_PROVIONNING*/ /* When BL2 is not activated, dummy SRAM shared data area is provided below. This is required by Firmware Update (FWU) and Initial Attestation (IAT) services. @@ -56,6 +62,11 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) FIH_RET(fih_int_encode(TFM_HAL_ERROR_GENERIC)); } +#ifdef TFM_OTP_DEFAULT_PROVIONNING + /* Place here to force linker to keep provision and init const */ + __IO uint32_t otp = OTP_KEEP; +#endif /*TFM_OTP_DEFAULT_PROVIONNING*/ + #ifdef DEFAULT_SHARED_DATA unsigned char *boot_data = (unsigned char *)BOOT_TFM_SHARED_DATA_BASE; memcpy(boot_data, dummy_data, sizeof(dummy_data)); diff --git a/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h b/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h index b95e3fdb10..9fa80cccde 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h +++ b/platform/ext/target/stm/stm32wba65i_dk/partition/region_defs.h @@ -158,6 +158,8 @@ #define TFM_NV_DATA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE + FLASH_NV_COUNTER_AREA_SIZE \ + FLASH_PS_AREA_SIZE + FLASH_ITS_AREA_SIZE) #define TFM_NV_DATA_LIMIT (TFM_NV_DATA_START + TFM_NV_DATA_SIZE - 1) +/* Additional Check to detect flash download slot overlap or overflow */ +#define FLASH_AREA_END_OFFSET_MAX (FLASH_TOTAL_SIZE) #if (MCUBOOT_S_DATA_IMAGE_NUMBER == 1) /* S DATA image layout */ @@ -170,4 +172,8 @@ #define NS_DATA_IMAGE_DATA1_SIZE (32U) #endif /* (MCUBOOT_NS_DATA_IMAGE_NUMBER == 1) */ +#if FLASH_AREA_END_OFFSET > FLASH_AREA_END_OFFSET_MAX +#error "Flash memory overflow" +#endif /* FLASH_AREA_END_OFFSET > FLASH_AREA_END_OFFSET_MAX */ + #endif /* __REGION_DEFS_H__ */ \ No newline at end of file From 793892e1f8cfe9cf904290b5690d800ad6455418 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Tue, 3 Jun 2025 14:30:25 +0200 Subject: [PATCH 072/133] [zep fromtree] STM : Add STM32WBA && STM32U5 drivers to psa-arch-tests Change the define PSA_API_TEST_TARGET to be able to launch the PSA API tests. STM32H5 && STM32L5 use the same drivers for PSA API tests. Signed-off-by: Ahmad EL JOUAID Change-Id: If71703e4d62945da2b4b891cd1c52724f272bffd (cherry picked from commit 30fae6a9003b7551f4ad98f0239b0bfcf97cd51d) --- .../target/stm/stm32h573i_dk/tests/psa_arch_tests_config.cmake | 2 +- .../target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/stm/stm32h573i_dk/tests/psa_arch_tests_config.cmake b/platform/ext/target/stm/stm32h573i_dk/tests/psa_arch_tests_config.cmake index f78bacbfc1..419c06adac 100644 --- a/platform/ext/target/stm/stm32h573i_dk/tests/psa_arch_tests_config.cmake +++ b/platform/ext/target/stm/stm32h573i_dk/tests/psa_arch_tests_config.cmake @@ -5,4 +5,4 @@ # #------------------------------------------------------------------------------- -set(PSA_API_TEST_TARGET stm32h573i_dk) +set(PSA_API_TEST_TARGET stm32l562e_dk) diff --git a/platform/ext/target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake b/platform/ext/target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake index c4fb108939..c118615505 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake +++ b/platform/ext/target/stm/stm32wba65i_dk/tests/psa_arch_tests_config.cmake @@ -4,4 +4,4 @@ # SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- -set(PSA_API_TEST_TARGET stm32l562e_dk) \ No newline at end of file +set(PSA_API_TEST_TARGET stm32wba) From 13a81cad2c9f2e2cdc2ac7960c25a41eb4edc886 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Thu, 5 Jun 2025 16:29:33 +0200 Subject: [PATCH 073/133] [zep fromtree] STM32U5 : TFM doesn't work properly if NS enter/exit low power mode. SHCI clock is enabled only in crypto_hw_accelerator_init() during crypto_init. As the clock is stopped after entering into stop modes, and not started automatically after that, any crypto operation using SAES crypto accelerator fails after wakup from stop mode. Signed-off-by: Ahmad EL JOUAID Change-Id: I2500a2241a2fe05653fe460acbdccd5bb4dfaa87 (cherry picked from commit b4f636eac270b07832ee0c50b7b719665103d6d4) --- platform/ext/target/stm/common/hal/accelerator/aes_alt.c | 3 +++ platform/ext/target/stm/common/hal/accelerator/gcm_alt.c | 6 +++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/hal/accelerator/aes_alt.c b/platform/ext/target/stm/common/hal/accelerator/aes_alt.c index 2b279788df..4a38239807 100644 --- a/platform/ext/target/stm/common/hal/accelerator/aes_alt.c +++ b/platform/ext/target/stm/common/hal/accelerator/aes_alt.c @@ -138,7 +138,10 @@ static int aes_set_key(mbedtls_aes_context *ctx, } #if defined(GENERATOR_HW_CRYPTO_DPA_SUPPORTED) && defined(HW_CRYPTO_DPA_AES) +#ifdef STM32U5 /* Enable SAES clock */ + __HAL_RCC_SHSI_ENABLE(); +#endif __HAL_RCC_SAES_CLK_ENABLE(); #else /* Enable AES clock */ diff --git a/platform/ext/target/stm/common/hal/accelerator/gcm_alt.c b/platform/ext/target/stm/common/hal/accelerator/gcm_alt.c index 9d60673547..188033372e 100644 --- a/platform/ext/target/stm/common/hal/accelerator/gcm_alt.c +++ b/platform/ext/target/stm/common/hal/accelerator/gcm_alt.c @@ -100,7 +100,10 @@ void mbedtls_gcm_init( mbedtls_gcm_context *ctx ) GCM_VALIDATE( ctx != NULL ); #if defined(GENERATOR_HW_CRYPTO_DPA_SUPPORTED) && defined(HW_CRYPTO_DPA_GCM) - /* Enable SAES clock */ +#ifdef STM32U5 + /* Enable SAES clock */ + __HAL_RCC_SHSI_ENABLE(); +#endif __HAL_RCC_SAES_CLK_ENABLE(); #endif memset( ctx, 0, sizeof( mbedtls_gcm_context ) ); @@ -257,6 +260,7 @@ int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, } #if defined(GENERATOR_HW_CRYPTO_DPA_SUPPORTED) && defined(HW_CRYPTO_DPA_GCM) /* Enable SAES clock */ + __HAL_RCC_SHSI_ENABLE(); __HAL_RCC_SAES_CLK_ENABLE(); #else __HAL_RCC_AES_CLK_ENABLE(); From 8f55b2d6fc9c7f3ba681735e6257215f659dc1c1 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Thu, 5 Jun 2025 07:46:16 +0200 Subject: [PATCH 074/133] [zep fromtree] STM32WBA6: fix C sources build warning in tfm_hal_platform.c Fix build warning in STM32WBA6 platform file tfm_hal_platform.c due to unused variable reported by build trace message like: .../trusted-firmware-m/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c: In function 'tfm_hal_platform_init': .../trusted-firmware-m/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c:67:19: warning: unused variable 'otp' [-Wunused-variable] 67 | __IO uint32_t otp = OTP_KEEP; | ^~~ Change-Id: I49e63f63c007188b6e9217f83a64084389b970fb Signed-off-by: Etienne Carriere Signed-off-by: Ahmad EL JOUAID (cherry picked from commit f140e4d5810835b8138db410c389c4b87788f81b) --- .../target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c index 923f20d2fd..ffc07f39cf 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c +++ b/platform/ext/target/stm/common/stm32wbaxx/secure/tfm_hal_platform.c @@ -65,6 +65,8 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) #ifdef TFM_OTP_DEFAULT_PROVIONNING /* Place here to force linker to keep provision and init const */ __IO uint32_t otp = OTP_KEEP; + + (void)otp; #endif /*TFM_OTP_DEFAULT_PROVIONNING*/ #ifdef DEFAULT_SHARED_DATA @@ -105,4 +107,4 @@ void icache_init(void) { Error_Handler(); } -} \ No newline at end of file +} From 5beee685ffd790c9e5e91e1ffeb4ae9f93e214e5 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 7 Apr 2025 13:58:53 +0200 Subject: [PATCH 075/133] [zep fromtree] STM32WBA: issue related to zephyr project. no inline for DMA_List_CheckNodesBaseAddresses(). Make local function DMA_List_CheckNodesBaseAddresses() never inlined. This fixes a build issue faced with with STM32WBAXX DMA HAL when building TF-M for regression tests with GCC11 and GCC12 compilers with optimization directives. The build issue is not very explicit, as reported by the build error trace message below: during GIMPLE pass: evrp .../build/tfm/api_ns/platform/hal/Src/stm32wbaxx_hal_dma_ex.c: In function 'HAL_DMAEx_List_ReplaceNode_Head': .../build/tfm/api_ns/platform/hal/Src/stm32wbaxx_hal_dma_ex.c:4350:1: internal compiler error: Segmentation fault 4350 | } | ^ 0x74708724251f ??? ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0 0x747087229d8f __libc_start_call_main ../sysdeps/nptl/libc_start_call_main.h:58 0x747087229e3f __libc_start_main_impl ../csu/libc-start.c:392 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See for instructions. The issue was tracked in GCC (e.g. [1] as pointed by [2]) and has been addressed in GCC 13 and later. This fix is equivalent to a fix already applied to HAL driver of stm32u5 platforms, see commit 2f138475047d ("stm32u5 hal dma_ex function not inlined with GCC 11 or 12"). Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106878 [1] Link: https://github.com/zephyrproject-rtos/zephyr/issues/80932#issuecomment-2459744553 [2] Change-Id: I4abacb65a3abcd805b8b0eeb4d82b53de263000c Signed-off-by: Ahmad EL JOUAID Signed-off-by: Etienne Carriere (cherry picked from commit ec61e691a08bd21d15437ee2cff19f1d4688d5ee) --- .../stm/common/stm32wbaxx/hal/Src/stm32wbaxx_hal_dma_ex.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/platform/ext/target/stm/common/stm32wbaxx/hal/Src/stm32wbaxx_hal_dma_ex.c b/platform/ext/target/stm/common/stm32wbaxx/hal/Src/stm32wbaxx_hal_dma_ex.c index 1cd97cdd2a..55f8985925 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/hal/Src/stm32wbaxx_hal_dma_ex.c +++ b/platform/ext/target/stm/common/stm32wbaxx/hal/Src/stm32wbaxx_hal_dma_ex.c @@ -498,7 +498,11 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, DMA_NodeTypeDef *const pNode); static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); +#if (__GNUC__ == 11) || (__GNUC__ == 12) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#endif DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3); static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, @@ -3755,7 +3759,11 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ +#if (__GNUC__ == 11) || (__GNUC__ == 12) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#endif DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3) { From ec156941630a9ca02289d3aca2605cf24d323d22 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Fri, 13 Jun 2025 15:11:07 +0200 Subject: [PATCH 076/133] [zep fromtree] STM : low_level_flash drivers doesn't disable icache when erasing or writing flash memory. 1- Erasing or writing flash memory while ICACHE is enabled, causes ERRF bit to be set in ICACHE status register. So, should disables ICACHE before erase/write operations and re-enables it afterwards, and that's what this patch support. 2- Enable Icache on H5 platform. Signed-off-by: Ahmad EL JOUAID Change-Id: Id60631bff10c1c92361b3f8f9969a7650f5e3063 (cherry picked from commit a68b8117235f12568bfd31e9c14b1bf0a1e7f957) --- .../common/hal/CMSIS_Driver/low_level_flash.c | 123 ++++++++++++++++++ .../stm/common/stm32h5xx/CMakeLists.txt | 1 + .../stm/common/stm32u5xx/CMakeLists.txt | 1 + .../stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h | 1 + .../stm32u5xx/hal/Src/stm32u5xx_hal_icache.c | 9 ++ .../stm/common/stm32wbaxx/CMakeLists.txt | 1 + .../stm/stm32h573i_dk/include/boot_hal_cfg.h | 2 +- .../target/stm/stm32wba65i_dk/CMakeLists.txt | 4 +- 8 files changed, 139 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/stm/common/hal/CMSIS_Driver/low_level_flash.c b/platform/ext/target/stm/common/hal/CMSIS_Driver/low_level_flash.c index e0ef151383..1a68a81421 100644 --- a/platform/ext/target/stm/common/hal/CMSIS_Driver/low_level_flash.c +++ b/platform/ext/target/stm/common/hal/CMSIS_Driver/low_level_flash.c @@ -22,11 +22,20 @@ #include "stm32hal.h" #include #include "board.h" +#include "boot_hal_cfg.h" #ifndef ARG_UNUSED #define ARG_UNUSED(arg) ((void)arg) #endif /* ARG_UNUSED */ +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants + * @{ + */ +#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ +#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ + /* config for flash driver */ /* #define DEBUG_FLASH_ACCESS @@ -414,6 +423,81 @@ static int32_t Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) } } +#ifdef TFM_ICACHE_ENABLE +#define HAL_ICACHE_MODULE_ENABLED +static int stm32_icache_disable(void) +{ + int status = 0; + uint32_t tickstart; + + /* Clear BSYENDF flag first and then disable the instruction cache + * that starts a cache invalidation procedure + */ + CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + HAL_ICACHE_Disable(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for instruction cache to get disabled */ + while (HAL_ICACHE_IsEnabled()) { + if ((HAL_GetTick() - tickstart) > + ICACHE_DISABLE_TIMEOUT_VALUE) { + /* New check to avoid false timeout detection in case + * of preemption. + */ + if (HAL_ICACHE_IsEnabled()) { + status = ARM_DRIVER_ERROR_TIMEOUT; + break; + } + } + } + + return status; +} + +static void stm32_icache_enable(void) +{ + HAL_ICACHE_Enable(); +} + +static int icache_wait_for_invalidate_complete(void) +{ + int status = ARM_DRIVER_ERROR; + uint32_t tickstart; + + /* Check if ongoing invalidation operation */ + if (__HAL_ICACHE_GET_FLAG(ICACHE_FLAG_BUSY)) { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for end of cache invalidation */ + while (!__HAL_ICACHE_GET_FLAG(ICACHE_FLAG_BUSYEND)) { + if ((HAL_GetTick() - tickstart) > + ICACHE_INVALIDATE_TIMEOUT_VALUE) { + break; + } + } + } + + /* Clear any pending flags */ + if (__HAL_ICACHE_GET_FLAG(ICACHE_FLAG_BUSYEND)) { + __HAL_ICACHE_CLEAR_FLAG(ICACHE_FLAG_BUSYEND); + status = 0; + } else { + status = ARM_DRIVER_ERROR_TIMEOUT; + } + + if (__HAL_ICACHE_GET_FLAG(ICACHE_FLAG_ERROR)) { + __HAL_ICACHE_CLEAR_FLAG(ICACHE_FLAG_ERROR); + status = ARM_DRIVER_ERROR; + } + + return status; +} +#endif // TFM_ICACHE_ENABLE + static int32_t Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt) { @@ -476,6 +560,15 @@ static int32_t Flash_ProgramData(uint32_t addr, return ARM_DRIVER_ERROR_PARAMETER; } +#ifdef TFM_ICACHE_ENABLE + /* Disable icache, this will start the invalidation procedure. + * All changes(erase/write) to flash memory should happen when + * i-cache is disabled. A write to flash performed without + * disabling i-cache will set ERRF error flag in SR register. + */ + stm32_icache_disable(); +#endif /* TFM_ICACHE_ENABLE */ + HAL_FLASH_Unlock(); ARM_FLASH0_STATUS.busy = DRIVER_STATUS_BUSY; do @@ -505,6 +598,16 @@ static int32_t Flash_ProgramData(uint32_t addr, ARM_FLASH0_STATUS.busy = DRIVER_STATUS_IDLE; HAL_FLASH_Lock(); + +#ifdef TFM_ICACHE_ENABLE + icache_wait_for_invalidate_complete(); + + /* I-cache should be enabled only after the + * invalidation is complete. + */ + stm32_icache_enable(); +#endif /* TFM_ICACHE_ENABLE */ + /* compare data written */ #ifdef CHECK_WRITE if ((err == HAL_OK) && memcmp(dest, data, cnt)) @@ -587,12 +690,32 @@ static int32_t Flash_EraseSector(uint32_t addr) #else EraseInit.Page = page_number(&ARM_FLASH0_DEV, addr); #endif + +#ifdef TFM_ICACHE_ENABLE + /* Disable icache, this will start the invalidation procedure. + * All changes(erase/write) to flash memory should happen when + * i-cache is disabled. A write to flash performed without + * disabling i-cache will set ERRF error flag in SR register. + */ + stm32_icache_disable(); +#endif /* TFM_ICACHE_ENABLE */ + ARM_FLASH0_STATUS.error = DRIVER_STATUS_NO_ERROR; HAL_FLASH_Unlock(); ARM_FLASH0_STATUS.busy = DRIVER_STATUS_BUSY; err = HAL_FLASHEx_Erase(&EraseInit, &pageError); ARM_FLASH0_STATUS.busy = DRIVER_STATUS_IDLE; HAL_FLASH_Lock(); + +#ifdef TFM_ICACHE_ENABLE + icache_wait_for_invalidate_complete(); + + /* I-cache should be enabled only after the + * invalidation is complete. + */ + stm32_icache_enable(); +#endif /* TFM_ICACHE_ENABLE */ + #ifdef DEBUG_FLASH_ACCESS if (err != HAL_OK) { diff --git a/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt b/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt index ce11ec7f7c..6c5f73f600 100644 --- a/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt @@ -84,6 +84,7 @@ target_sources(platform_s ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32h5xx_hal_pka.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32h5xx_hal_cryp.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32h5xx_hal_cryp_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32h5xx_hal_icache.c ${STM_COMMON_DIR}/hal/Native_Driver/low_level_rng.c ) diff --git a/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt b/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt index f98d0d6a59..c1346f670b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt @@ -90,6 +90,7 @@ target_sources(platform_s ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32u5xx_hal_cryp_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32u5xx_hal_i2c.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32u5xx_hal_i2c_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32u5xx_hal_icache.c ${STM_COMMON_DIR}/hal/Native_Driver/low_level_rng.c ${STM_COMMON_DIR}/hal/Native_Driver/nv_counters.c ) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h index 25c90755fa..823ef792d3 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h @@ -227,6 +227,7 @@ typedef struct /* Peripheral Control functions **********************************************/ HAL_StatusTypeDef HAL_ICACHE_Enable(void); HAL_StatusTypeDef HAL_ICACHE_Disable(void); +uint32_t HAL_ICACHE_IsEnabled(void); HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); HAL_StatusTypeDef HAL_ICACHE_DeInit(void); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c index 5e8a0ce438..3560393083 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c @@ -260,6 +260,15 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void) return status; } +/** + * @brief Check whether the Instruction Cache is enabled or not. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); +} + /** * @brief Invalidate the Instruction Cache. * @note This function waits for the end of cache invalidation procedure diff --git a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt index 68627e48a0..55fb9a64e0 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt @@ -91,6 +91,7 @@ target_sources(platform_s ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal_cryp_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal_i2c.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal_i2c_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal_icache.c ${STM_COMMON_DIR}/hal/Native_Driver/low_level_rng.c ) diff --git a/platform/ext/target/stm/stm32h573i_dk/include/boot_hal_cfg.h b/platform/ext/target/stm/stm32h573i_dk/include/boot_hal_cfg.h index 8cfe8b7227..3ee89df7ef 100644 --- a/platform/ext/target/stm/stm32h573i_dk/include/boot_hal_cfg.h +++ b/platform/ext/target/stm/stm32h573i_dk/include/boot_hal_cfg.h @@ -39,7 +39,7 @@ #define TFM_DEV_MODE /* ICache */ -/*#define TFM_ICACHE_ENABLE*/ /*!< Instruction cache enable */ +#define TFM_ICACHE_ENABLE /*!< Instruction cache enable */ /* Static protections */ #define TFM_WRP_PROTECT_ENABLE /*!< Write Protection */ diff --git a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt index 0406e0394d..9b5587bfa0 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt +++ b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt @@ -89,14 +89,14 @@ add_custom_target(tfm_s_fmw ALL SOURCES ${tfm_s_split_out}) if(CMAKE_C_COMPILER STREQUAL "iccarm") add_custom_command( OUTPUT ${tfm_s_split_out} - DEPENDS tfm_s_binaries +# DEPENDS tfm_s_binaries COMMAND ielftool --silent --exclude=.BL2_OTP --bin $ ${tfm_s_bin_dir}/tfm_s_fmw.bin COMMAND ielftool --silent --only=.BL2_OTP --bin $ ${tfm_s_bin_dir}/tfm_s_otp.bin ) else() add_custom_command( OUTPUT ${tfm_s_split_out} - DEPENDS tfm_s_binaries +# DEPENDS tfm_s_binaries COMMAND ${CMAKE_OBJCOPY} --remove-section .BL2_OTP -O binary $ ${tfm_s_bin_dir}/tfm_s_fmw.bin COMMAND ${CMAKE_OBJCOPY} --only-section .BL2_OTP -O binary $ ${tfm_s_bin_dir}/tfm_s_otp.bin ) From e73f71abd33296ec178864075104575d3ade26e1 Mon Sep 17 00:00:00 2001 From: Anton Komlev Date: Fri, 13 Jun 2025 17:50:57 +0100 Subject: [PATCH 077/133] [zep fromtree] Build: Fix stm32wba65i_dk platform build issues - Use `tfm_s_bin` target, aligning with changes in the GNUARM toolchain. - Updated logic for emulating `mcuboot_config.h` used by FWU partition. - Move `BL2` before `secure_fw` because FWU partition depends on MCUBoot. Signed-off-by: Anton Komlev Change-Id: I4a2935d68df52e9194c21ab7cf20aeecc63c5bb2 (cherry picked from commit d090f3cd5357e94cc823cc30c6940f79ced1808f) --- CMakeLists.txt | 8 ++++---- platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt | 8 +------- .../boards/{ => mcuboot_config}/mcuboot_config.h | 0 platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt | 6 +++--- 4 files changed, 8 insertions(+), 14 deletions(-) rename platform/ext/target/stm/common/stm32wbaxx/boards/{ => mcuboot_config}/mcuboot_config.h (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2560dd15e3..0b8efb1f30 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -42,6 +42,10 @@ set(CMAKE_CXX_COMPILER_FORCED true) project("Trusted Firmware M" VERSION ${TFM_VERSION} LANGUAGES C CXX ASM) +if(BL2) + add_subdirectory(bl2) +endif() + add_subdirectory(lib/backtrace) add_subdirectory(lib/ext) add_subdirectory(lib/fih) @@ -50,11 +54,7 @@ add_subdirectory(lib/tfm_log_unpriv) add_subdirectory(lib/tfm_vprintf) add_subdirectory(tools) add_subdirectory(secure_fw) - add_subdirectory(interface) -if(BL2) - add_subdirectory(bl2) -endif() if(BL1 AND PLATFORM_DEFAULT_BL1) add_subdirectory(bl1/bl1_2) diff --git a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt index 55fb9a64e0..858ccb03ab 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt @@ -1,5 +1,5 @@ #------------------------------------------------------------------------------- -# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors # Copyright (c) 2021-2024 STMicroelectronics. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -95,12 +95,6 @@ target_sources(platform_s ${STM_COMMON_DIR}/hal/Native_Driver/low_level_rng.c ) -# To compile FWU support and test, should add mcuboot_config.h file in mcuboot_config folder -file(MAKE_DIRECTORY ${CMAKE_INSTALL_PREFIX}/../build-spe/bl2/ext/mcuboot/mcuboot_config) -configure_file( ${CMAKE_CURRENT_SOURCE_DIR}/boards/mcuboot_config.h - ${CMAKE_INSTALL_PREFIX}/../build-spe/bl2/ext/mcuboot/mcuboot_config - @ONLY) - target_compile_options(platform_s PUBLIC ${COMPILER_CMSE_FLAG} diff --git a/platform/ext/target/stm/common/stm32wbaxx/boards/mcuboot_config.h b/platform/ext/target/stm/common/stm32wbaxx/boards/mcuboot_config/mcuboot_config.h similarity index 100% rename from platform/ext/target/stm/common/stm32wbaxx/boards/mcuboot_config.h rename to platform/ext/target/stm/common/stm32wbaxx/boards/mcuboot_config/mcuboot_config.h diff --git a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt index 9b5587bfa0..72801ad0f4 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt +++ b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt @@ -1,5 +1,5 @@ #------------------------------------------------------------------------------- -# Copyright (c) 2020, Arm Limited. All rights reserved. +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors # # SPDX-License-Identifier: BSD-3-Clause # @@ -89,14 +89,14 @@ add_custom_target(tfm_s_fmw ALL SOURCES ${tfm_s_split_out}) if(CMAKE_C_COMPILER STREQUAL "iccarm") add_custom_command( OUTPUT ${tfm_s_split_out} -# DEPENDS tfm_s_binaries + DEPENDS tfm_s_bin COMMAND ielftool --silent --exclude=.BL2_OTP --bin $ ${tfm_s_bin_dir}/tfm_s_fmw.bin COMMAND ielftool --silent --only=.BL2_OTP --bin $ ${tfm_s_bin_dir}/tfm_s_otp.bin ) else() add_custom_command( OUTPUT ${tfm_s_split_out} -# DEPENDS tfm_s_binaries + DEPENDS tfm_s_bin COMMAND ${CMAKE_OBJCOPY} --remove-section .BL2_OTP -O binary $ ${tfm_s_bin_dir}/tfm_s_fmw.bin COMMAND ${CMAKE_OBJCOPY} --only-section .BL2_OTP -O binary $ ${tfm_s_bin_dir}/tfm_s_otp.bin ) From 0b2449afa5d4463adcd32608542218c8d180acfa Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 09:58:25 +0200 Subject: [PATCH 078/133] [zep fromtree] STM32U5 : update HAL on U5 to version 1.3.0 Change-Id: Id3831ae44dcce0e304df095b3b916d95966645bb Signed-off-by: Ahmad EL JOUAID (cherry picked from commit 958b54427156e66480489e53df6de085d62aef3a) --- .../Components/mx25lm51245g/mx25lm51245g.c | 786 +++-- .../Components/mx25lm51245g/mx25lm51245g.h | 70 +- .../stm32u5xx/Device/Include/stm32u585xx.h | 2697 ++++++++++------- .../stm32u5xx/Device/Include/stm32u5xx.h | 55 +- .../Device/Include/system_stm32u5xx.h | 18 +- .../common/stm32u5xx/bl2/stm32u5xx_hal_msp.c | 2 +- .../hal/Inc/Legacy/stm32_hal_legacy.h | 595 +++- .../common/stm32u5xx/hal/Inc/stm32u5xx_hal.h | 154 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h | 8 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h | 105 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_cryp_ex.h | 64 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_def.h | 6 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h | 94 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h | 59 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h | 20 +- .../hal/Inc/stm32u5xx_hal_flash_ex.h | 2 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h | 11 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h | 264 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h | 137 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h | 3 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h | 3 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h | 6 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h | 2 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h | 2 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h | 30 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h | 7 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h | 42 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h | 300 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h | 1616 +++++++--- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h | 607 +++- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h | 9 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h | 45 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h | 125 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h | 404 +-- .../stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h | 73 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h | 167 +- .../stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h | 29 +- .../common/stm32u5xx/hal/Src/stm32u5xx_hal.c | 222 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c | 36 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c | 782 +++-- .../stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c | 114 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_dma.c | 80 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c | 149 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_flash.c | 2 +- .../hal/Src/stm32u5xx_hal_flash_ex.c | 22 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c | 72 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c | 603 +++- .../stm32u5xx/hal/Src/stm32u5xx_hal_hash.c | 35 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c | 3 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c | 54 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c | 2 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_icache.c | 27 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c | 106 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_pka.c | 91 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c | 10 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c | 509 +++- .../stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c | 400 ++- .../stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c | 2609 ++++++++++------ .../stm32u5xx/hal/Src/stm32u5xx_hal_rng.c | 62 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c | 23 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c | 163 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c | 717 ++--- .../stm32u5xx/hal/Src/stm32u5xx_hal_uart.c | 525 +++- .../stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c | 96 +- .../stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c | 11 +- 65 files changed, 10786 insertions(+), 5356 deletions(-) diff --git a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c index aacb741d59..c81caa22fc 100644 --- a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c +++ b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c @@ -1,31 +1,31 @@ /** - ****************************************************************************** - * @file mx25lm51245g.c - * @modify MCD Application Team - * @brief This file provides the MX25LM51245G OSPI drivers. - ****************************************************************************** - * MX25LM51245G action : - * STR Octal IO protocol (SOPI) and DTR Octal IO protocol (DOPI) bits of - * Configuration Register 2 : - * DOPI = 1 and SOPI = 0: Operates in DTR Octal IO protocol (accepts 8-8-8 commands) - * DOPI = 0 and SOPI = 1: Operates in STR Octal IO protocol (accepts 8-8-8 commands) - * DOPI = 0 and SOPI = 0: Operates in Single IO protocol (accepts 1-1-1 commands) - * Enter SOPI mode by configuring DOPI = 0 and SOPI = 1 in CR2-Addr0 - * Exit SOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0 - * Enter DOPI mode by configuring DOPI = 1 and SOPI = 0 in CR2-Addr0 - * Exit DOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0 - * - * Memory commands support STR(Single Transfer Rate) & - * DTR(Double Transfer Rate) modes in OPI - * - * Memory commands support STR(Single Transfer Rate) & - * DTR(Double Transfer Rate) modes in SPI - * - ****************************************************************************** + ****************************************************************************** + * @file mx25lm51245g.c + * @modify MCD Application Team + * @brief This file provides the MX25LM51245G OSPI drivers. + ****************************************************************************** + * MX25LM51245G action : + * STR Octal IO protocol (SOPI) and DTR Octal IO protocol (DOPI) bits of + * Configuration Register 2 : + * DOPI = 1 and SOPI = 0: Operates in DTR Octal IO protocol (accepts 8-8-8 commands) + * DOPI = 0 and SOPI = 1: Operates in STR Octal IO protocol (accepts 8-8-8 commands) + * DOPI = 0 and SOPI = 0: Operates in Single IO protocol (accepts 1-1-1 commands) + * Enter SOPI mode by configuring DOPI = 0 and SOPI = 1 in CR2-Addr0 + * Exit SOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0 + * Enter DOPI mode by configuring DOPI = 1 and SOPI = 0 in CR2-Addr0 + * Exit DOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0 + * + * Memory commands support STR(Single Transfer Rate) & + * DTR(Double Transfer Rate) modes in OPI + * + * Memory commands support STR(Single Transfer Rate) & + * DTR(Double Transfer Rate) modes in SPI + * + ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 - 2025 STMicroelectronics. + * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -33,7 +33,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "mx25lm51245g.h" @@ -64,13 +64,13 @@ int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo) /* Configure the structure with the memory configuration */ pInfo->FlashSize = MX25LM51245G_FLASH_SIZE; pInfo->EraseSectorSize = MX25LM51245G_SECTOR_64K; - pInfo->EraseSectorsNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SECTOR_64K); + pInfo->EraseSectorsNumber = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_SECTOR_64K); pInfo->EraseSubSectorSize = MX25LM51245G_SUBSECTOR_4K; - pInfo->EraseSubSectorNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SUBSECTOR_4K); + pInfo->EraseSubSectorNumber = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_SUBSECTOR_4K); pInfo->EraseSubSector1Size = MX25LM51245G_SUBSECTOR_4K; - pInfo->EraseSubSector1Number = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SUBSECTOR_4K); + pInfo->EraseSubSector1Number = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_SUBSECTOR_4K); pInfo->ProgPageSize = MX25LM51245G_PAGE_SIZE; - pInfo->ProgPagesNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_PAGE_SIZE); + pInfo->ProgPagesNumber = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_PAGE_SIZE); return MX25LM51245G_OK; }; @@ -83,7 +83,8 @@ int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo) * @param Rate Transfer rate * @retval error status */ -int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate) +int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate) { OSPI_RegularCmdTypeDef s_command = {0}; OSPI_AutoPollingTypeDef s_config = {0}; @@ -96,23 +97,35 @@ int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_I /* Configure automatic polling mode to wait for memory ready */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_STATUS_REG_CMD + : MX25LM51245G_OCTA_READ_STATUS_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 0U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; @@ -148,7 +161,8 @@ int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_I * @param Size Size of data to read * @retval OSPI memory status */ -int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size) +int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -160,18 +174,26 @@ int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t M /* Initialize the read command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_FAST_READ_CMD : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) : MX25LM51245G_OCTA_READ_CMD; - s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) + ? MX25LM51245G_FAST_READ_CMD + : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) + : MX25LM51245G_OCTA_READ_CMD; + s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_ADDRESS_1_LINE + : HAL_OSPI_ADDRESS_8_LINES; s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE; - s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS; + s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) + ? HAL_OSPI_ADDRESS_24_BITS + : HAL_OSPI_ADDRESS_32_BITS; s_command.Address = ReadAddr; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; @@ -202,7 +224,7 @@ int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t M * @param Ctx Component object pointer * @param AddressSize Address size * @param pData Pointer to data to be read - * @param ReadAddr Read start addressS + * @param ReadAddr Read start address * @param Size Size of data to read * @note Only OPI mode support DTR transfer rate * @retval OSPI memory status @@ -213,11 +235,7 @@ int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t R /* Initialize the read command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES; s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE; s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS; @@ -262,7 +280,9 @@ int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t R * command is not available for the specified interface mode * @retval OSPI memory status */ -int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size) +int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, + uint32_t Size) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -274,18 +294,26 @@ int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface /* Initialize the program command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_PAGE_PROG_CMD : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) : MX25LM51245G_OCTA_PAGE_PROG_CMD; - s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) + ? MX25LM51245G_PAGE_PROG_CMD + : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) + : MX25LM51245G_OCTA_PAGE_PROG_CMD; + s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_ADDRESS_1_LINE + : HAL_OSPI_ADDRESS_8_LINES; s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE; - s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS; + s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) + ? HAL_OSPI_ADDRESS_24_BITS + : HAL_OSPI_ADDRESS_32_BITS; s_command.Address = WriteAddr; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; @@ -326,11 +354,7 @@ int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uin /* Initialize the program command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES; s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE; s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS; @@ -373,7 +397,9 @@ int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uin * @param BlockSize Block size to erase * @retval OSPI memory status */ -int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize) +int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, + MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, + MX25LM51245G_Erase_t BlockSize) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -391,17 +417,23 @@ int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_ /* Initialize the erase command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; - s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) + ? HAL_OSPI_ADDRESS_24_BITS + : HAL_OSPI_ADDRESS_32_BITS; s_command.Address = BlockAddress; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -409,34 +441,38 @@ int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_ s_command.DQSMode = HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; - switch(Mode) - { - case MX25LM51245G_OPI_MODE : - if(BlockSize == MX25LM51245G_ERASE_64K) - { - s_command.Instruction = MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD; - } - else - { - s_command.Instruction = MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD; - } - break; - - case MX25LM51245G_SPI_MODE : - default: - if(BlockSize == MX25LM51245G_ERASE_64K) - { - s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_SECTOR_ERASE_64K_CMD : MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD; - } - else - { - s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_SUBSECTOR_ERASE_4K_CMD : MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD; - } - break; + switch (Mode) + { + case MX25LM51245G_OPI_MODE : + if (BlockSize == MX25LM51245G_ERASE_64K) + { + s_command.Instruction = MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD; + } + else + { + s_command.Instruction = MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD; + } + break; + + case MX25LM51245G_SPI_MODE : + default: + if (BlockSize == MX25LM51245G_ERASE_64K) + { + s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) + ? MX25LM51245G_SECTOR_ERASE_64K_CMD + : MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD; + } + else + { + s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) + ? MX25LM51245G_SUBSECTOR_ERASE_4K_CMD + : MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD; + } + break; } /* Send the command */ - if(HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return MX25LM51245G_ERROR; } @@ -463,15 +499,19 @@ int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t /* Initialize the erase command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_BULK_ERASE_CMD : MX25LM51245G_OCTA_BULK_ERASE_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_BULK_ERASE_CMD + : MX25LM51245G_OCTA_BULK_ERASE_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -480,7 +520,7 @@ int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; /* Send the command */ - if(HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return MX25LM51245G_ERROR; } @@ -496,7 +536,8 @@ int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t * @param AddressSize Address size * @retval OSPI memory status */ -int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize) +int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_AddressSize_t AddressSize) { OSPI_RegularCmdTypeDef s_command = {0}; OSPI_MemoryMappedTypeDef s_mem_mapped_cfg = {0}; @@ -509,18 +550,24 @@ int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51 /* Initialize the read command */ s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_FAST_READ_CMD : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) : MX25LM51245G_OCTA_READ_CMD; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) + ? MX25LM51245G_FAST_READ_CMD + : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) + : MX25LM51245G_OCTA_READ_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES; s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE; - s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS; + s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) + ? HAL_OSPI_ADDRESS_24_BITS + : HAL_OSPI_ADDRESS_32_BITS; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; s_command.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE; @@ -536,7 +583,11 @@ int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51 /* Initialize the program command */ s_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_PAGE_PROG_CMD : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) : MX25LM51245G_OCTA_PAGE_PROG_CMD; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) + ? MX25LM51245G_PAGE_PROG_CMD + : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) + : MX25LM51245G_OCTA_PAGE_PROG_CMD; s_command.DummyCycles = 0U; /* Send the write command */ @@ -574,11 +625,7 @@ int32_t MX25LM51245G_EnableDTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51 /* Initialize the read command */ s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES; s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE; s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS; @@ -641,15 +688,19 @@ int32_t MX25LM51245G_Suspend(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t M /* Initialize the suspend command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_PROG_ERASE_SUSPEND_CMD : MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_PROG_ERASE_SUSPEND_CMD + : MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -686,15 +737,19 @@ int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mo /* Initialize the resume command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_PROG_ERASE_RESUME_CMD : MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_PROG_ERASE_RESUME_CMD + : MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -733,15 +788,19 @@ int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface /* Initialize the write enable command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_ENABLE_CMD : MX25LM51245G_OCTA_WRITE_ENABLE_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_WRITE_ENABLE_CMD + : MX25LM51245G_OCTA_WRITE_ENABLE_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -756,14 +815,22 @@ int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface } /* Configure automatic polling mode to wait for write enabling */ - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_STATUS_REG_CMD + : MX25LM51245G_OCTA_READ_STATUS_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 0U; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; @@ -807,15 +874,19 @@ int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interfac /* Initialize the write disable command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_DISABLE_CMD : MX25LM51245G_OCTA_WRITE_DISABLE_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_WRITE_DISABLE_CMD + : MX25LM51245G_OCTA_WRITE_DISABLE_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -841,7 +912,8 @@ int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interfac * @param Value Status register value pointer * @retval error status */ -int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value) +int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t *Value) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -853,23 +925,35 @@ int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_In /* Initialize the reading of status register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_STATUS_REG_CMD + : MX25LM51245G_OCTA_READ_STATUS_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 0U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; @@ -898,7 +982,8 @@ int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_In * @param Value Value to write to Status register * @retval error status */ -int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value) +int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t Value) { OSPI_RegularCmdTypeDef s_command = {0}; uint8_t reg[2]; @@ -921,22 +1006,30 @@ int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_I /* Initialize the writing of status register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_STATUS_REG_CMD : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_WRITE_STATUS_REG_CMD + : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 0U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; s_command.DummyCycles = 0U; s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 2U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U); s_command.DQSMode = HAL_OSPI_DQS_DISABLE; @@ -965,7 +1058,8 @@ int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_I * @param Value Value to write to configuration register * @retval error status */ -int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value) +int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t Value) { OSPI_RegularCmdTypeDef s_command = {0}; uint8_t reg[2]; @@ -992,22 +1086,30 @@ int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Inte /* Initialize the writing of configuration register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_STATUS_REG_CMD : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_WRITE_STATUS_REG_CMD + : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 1U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; s_command.DummyCycles = 0U; s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 2U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U); s_command.DQSMode = HAL_OSPI_DQS_DISABLE; @@ -1036,7 +1138,8 @@ int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Inte * @param Value configuration register value pointer * @retval error status */ -int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value) +int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t *Value) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -1048,23 +1151,35 @@ int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Inter /* Initialize the reading of configuration register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_CFG_REG_CMD : MX25LM51245G_OCTA_READ_CFG_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_CFG_REG_CMD + : MX25LM51245G_OCTA_READ_CFG_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 1U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; @@ -1093,7 +1208,8 @@ int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Inter * @param Value Value to write to configuration register * @retval error status */ -int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value) +int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -1105,22 +1221,30 @@ int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Int /* Initialize the writing of configuration register 2 */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_CFG_REG2_CMD : MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_WRITE_CFG_REG2_CMD + : MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = WriteAddr; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; s_command.DummyCycles = 0U; s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 1U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U); s_command.DQSMode = HAL_OSPI_DQS_DISABLE; @@ -1149,7 +1273,8 @@ int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Int * @param Value configuration register 2 value pointer * @retval error status */ -int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value) +int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -1161,23 +1286,35 @@ int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Inte /* Initialize the reading of status register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_CFG_REG2_CMD : MX25LM51245G_OCTA_READ_CFG_REG2_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_CFG_REG2_CMD + : MX25LM51245G_OCTA_READ_CFG_REG2_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = ReadAddr; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; @@ -1206,7 +1343,8 @@ int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Inte * @param Value Value to write to Security register * @retval error status */ -int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value) +int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t Value) { /* Prevent unused argument(s) compilation warning */ UNUSED(Value); @@ -1221,15 +1359,19 @@ int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G /* Initialize the write of security register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_SECURITY_REG_CMD : MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_WRITE_SECURITY_REG_CMD + : MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -1255,7 +1397,8 @@ int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G * @param Value Security register value pointer * @retval error status */ -int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value) +int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t *Value) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -1267,23 +1410,35 @@ int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_ /* Initialize the reading of security register */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_SECURITY_REG_CMD : MX25LM51245G_OCTA_READ_SECURITY_REG_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_SECURITY_REG_CMD + : MX25LM51245G_OCTA_READ_SECURITY_REG_CMD; s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 0U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; @@ -1315,7 +1470,8 @@ int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_ * @param DualFlash Dual flash mode state * @retval error status */ -int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID) +int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, + uint8_t *ID) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -1327,23 +1483,37 @@ int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mo /* Initialize the read ID command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_ID_CMD : MX25LM51245G_OCTA_READ_ID_CMD; - s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES; - s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_READ_ID_CMD + : MX25LM51245G_OCTA_READ_ID_CMD; + s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_ADDRESS_NONE + : HAL_OSPI_ADDRESS_8_LINES; + s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_ADDRESS_DTR_ENABLE + : HAL_OSPI_ADDRESS_DTR_DISABLE; s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS; s_command.Address = 0U; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES; - s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; - s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL); + s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_DATA_DTR_ENABLE + : HAL_OSPI_DATA_DTR_DISABLE; + s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) + ? 0U + : ((Rate == MX25LM51245G_DTR_TRANSFER) + ? DUMMY_CYCLES_REG_OCTAL_DTR + : DUMMY_CYCLES_REG_OCTAL); s_command.NbData = 3U; s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; @@ -1384,15 +1554,19 @@ int32_t MX25LM51245G_ResetEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface /* Initialize the reset enable command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_RESET_ENABLE_CMD : MX25LM51245G_OCTA_RESET_ENABLE_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_RESET_ENABLE_CMD + : MX25LM51245G_OCTA_RESET_ENABLE_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -1429,15 +1603,19 @@ int32_t MX25LM51245G_ResetMemory(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface /* Initialize the reset enable command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_RESET_MEMORY_CMD : MX25LM51245G_OCTA_RESET_MEMORY_CMD; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_RESET_MEMORY_CMD + : MX25LM51245G_OCTA_RESET_MEMORY_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -1474,14 +1652,16 @@ int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface /* Initialize the no operation command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_NOP_CMD : MX25LM51245G_OCTA_NOP_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; @@ -1507,7 +1687,8 @@ int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface * @param Rate Transfer rate STR or DTR * @retval error status */ -int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate) +int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate) { OSPI_RegularCmdTypeDef s_command = {0}; @@ -1519,15 +1700,20 @@ int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interf /* Initialize the enter power down command */ s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; -#if defined (OCTOSPI_CR_MSEL) - s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0; -#else s_command.FlashId = HAL_OSPI_FLASH_ID_1; -#endif - s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES; - s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; - s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS; - s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD : MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD; + + s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_1_LINE + : HAL_OSPI_INSTRUCTION_8_LINES; + s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) + ? HAL_OSPI_INSTRUCTION_DTR_ENABLE + : HAL_OSPI_INSTRUCTION_DTR_DISABLE; + s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) + ? HAL_OSPI_INSTRUCTION_8_BITS + : HAL_OSPI_INSTRUCTION_16_BITS; + s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) + ? MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD + : MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD; s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; s_command.DataMode = HAL_OSPI_DATA_NONE; @@ -1559,5 +1745,3 @@ int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interf /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h index 2127bceec9..f65b2268ef 100644 --- a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h +++ b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h @@ -7,8 +7,8 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 - 2025 STMicroelectronics. + * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -23,7 +23,7 @@ #define MX25LM51245G_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -257,7 +257,8 @@ /** @defgroup MX25LM51245G_Exported_Types MX25LM51245G Exported Types * @{ */ -typedef struct { +typedef struct +{ uint32_t FlashSize; /*!< Size of the flash */ uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */ uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */ @@ -269,23 +270,27 @@ typedef struct { uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */ } MX25LM51245G_Info_t; -typedef enum { +typedef enum +{ MX25LM51245G_SPI_MODE = 0, /*!< 1-1-1 commands, Power on H/W default setting */ MX25LM51245G_OPI_MODE /*!< 8-8-8 commands */ } MX25LM51245G_Interface_t; -typedef enum { +typedef enum +{ MX25LM51245G_STR_TRANSFER = 0, /*!< Single Transfer Rate */ MX25LM51245G_DTR_TRANSFER /*!< Double Transfer Rate */ } MX25LM51245G_Transfer_t; -typedef enum { +typedef enum +{ MX25LM51245G_ERASE_4K = 0, /*!< 4K size Sector erase */ MX25LM51245G_ERASE_64K, /*!< 64K size Block erase */ MX25LM51245G_ERASE_BULK /*!< Whole bulk erase */ } MX25LM51245G_Erase_t; -typedef enum { +typedef enum +{ MX25LM51245G_3BYTES_SIZE = 0, /*!< 3 Bytes address mode */ MX25LM51245G_4BYTES_SIZE /*!< 4 Bytes address mode */ } MX25LM51245G_AddressSize_t; @@ -299,16 +304,23 @@ typedef enum { */ /* Function by commands combined */ int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo); -int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); +int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate); /* Read/Write Array Commands **************************************************/ -int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size); +int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size); int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size); -int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size); +int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, + uint32_t Size); int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size); -int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize); +int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, + MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, + MX25LM51245G_Erase_t BlockSize); int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); -int32_t MX25LM51245G_EnableMemoryMappedModeSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize); +int32_t MX25LM51245G_EnableMemoryMappedModeSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_AddressSize_t AddressSize); int32_t MX25LM51245G_EnableMemoryMappedModeDTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode); int32_t MX25LM51245G_Suspend(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); @@ -316,23 +328,33 @@ int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mo /* Register/Setting Commands **************************************************/ int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); -int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value); -int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value); -int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value); -int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value); -int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value); -int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value); -int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value); -int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value); +int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t *Value); +int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t Value); +int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t Value); +int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t *Value); +int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value); +int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value); +int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t Value); +int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate, uint8_t *Value); /* ID/Security Commands *******************************************************/ -int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID); +int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, + uint8_t *ID); /* Reset Commands *************************************************************/ int32_t MX25LM51245G_ResetEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); int32_t MX25LM51245G_ResetMemory(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); -int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); +int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, + MX25LM51245G_Transfer_t Rate); /** * @} @@ -355,5 +377,3 @@ int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interf /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h index 0a6616444f..a0ffef9155 100644 --- a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h +++ b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h @@ -7,18 +7,18 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, + * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -68,10 +68,10 @@ typedef enum /* =========================================== STM32U585xx Specific Interrupt Numbers ================================= */ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ - PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ RTC_IRQn = 2, /*!< RTC non-secure interrupt */ RTC_S_IRQn = 3, /*!< RTC secure interrupt */ - TAMP_IRQn = 4, /*!< Tamper non-secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ @@ -192,6 +192,7 @@ typedef enum MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ } IRQn_Type; /* =========================================================================================================================== */ @@ -783,7 +784,7 @@ typedef struct */ typedef struct { - __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ } COMP_TypeDef; typedef struct @@ -802,8 +803,12 @@ typedef struct __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ } OPAMP_TypeDef; -/*Aliases */ -#define OPAMP_Common_TypeDef OPAMP_TypeDef +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + /** * @brief MDF/ADF @@ -850,56 +855,59 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ - __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ - __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ - __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ - __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ - __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ - __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ - uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ - __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ - __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ - __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */ - uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ - __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ - uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ - __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ - __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ - uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ - __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ - uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ - __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ - uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ - __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ - uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ - __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ - uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ - __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ - uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ - __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ - uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ - __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ - uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ - __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ - uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ - __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ - uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ - __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ - uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ - __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ - uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ - __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ - uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ - __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ - uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ - __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ -} OCTOSPI_TypeDef; + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + /** * @brief OTFDEC register @@ -928,14 +936,17 @@ typedef struct __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ } OTFDEC_TypeDef; + /** - * @brief OCTO Serial Peripheral Interface IO Manager + * @brief Serial Peripheral Interface IO Manager */ typedef struct { - __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ -} OCTOSPIM_TypeDef; + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; /** * @brief Power Control @@ -1285,7 +1296,6 @@ typedef struct /** * @brief Delay Block DLYB */ - typedef struct { __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ @@ -1299,7 +1309,7 @@ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ - uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ @@ -1558,7 +1568,7 @@ typedef struct __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - __IO uint32_t PW; /*!< ADC power register, Address offset: 0x44 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ uint32_t RESERVED1; /*!< Reserved, 0x048 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ @@ -1593,6 +1603,10 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ } ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define PW PWRR + /** * @brief CORDIC */ @@ -1830,7 +1844,6 @@ typedef struct #define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) #define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) #define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) - #define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) #define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) #define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) @@ -1855,7 +1868,7 @@ typedef struct #define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) #define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) #define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) -#define OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) #define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) @@ -1967,7 +1980,7 @@ typedef struct #define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) #define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) #define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) -#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4300UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) #define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) #define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) #define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) @@ -2040,7 +2053,7 @@ typedef struct #define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) #define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) #define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) -#define OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) #define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) @@ -2048,7 +2061,6 @@ typedef struct #define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) #define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) #define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) -#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ #define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) #define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) #define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) @@ -2059,6 +2071,7 @@ typedef struct #define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) #define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) #define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ #define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) #define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) #define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) @@ -2238,6 +2251,7 @@ typedef struct #define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) #define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) #define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) #define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) #define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) #define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) @@ -2304,7 +2318,7 @@ typedef struct #define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) #define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) #define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) -#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) OTG_FS_BASE_NS) +#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS) #define AES_NS ((AES_TypeDef *) AES_BASE_NS) #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) @@ -2321,7 +2335,6 @@ typedef struct #define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) #define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) #define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) -#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) #define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) #define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) #define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) @@ -2331,6 +2344,7 @@ typedef struct #define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) #define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) #define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) #define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) #define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) @@ -2402,6 +2416,7 @@ typedef struct #define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) #define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) #define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) #define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) #define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) #define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) @@ -2468,7 +2483,7 @@ typedef struct #define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) #define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) #define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) -#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) OTG_FS_BASE_S) +#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) #define AES_S ((AES_TypeDef *) AES_BASE_S) #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) @@ -2485,7 +2500,6 @@ typedef struct #define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) #define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) #define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) -#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) #define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) #define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) #define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) @@ -2495,6 +2509,7 @@ typedef struct #define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) #define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) #define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) #define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) #define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) @@ -2809,6 +2824,9 @@ typedef struct #define OPAMP2 OPAMP2_S #define OPAMP2_BASE OPAMP2_BASE_S +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + #define LPTIM1 LPTIM1_S #define LPTIM1_BASE LPTIM1_BASE_S @@ -3128,7 +3146,6 @@ typedef struct #define GPIOI GPIOI_NS #define GPIOI_BASE GPIOI_BASE_NS - #define LPGPIO1 LPGPIO1_NS #define LPGPIO1_BASE LPGPIO1_BASE_NS @@ -3286,6 +3303,9 @@ typedef struct #define OPAMP2 OPAMP2_NS #define OPAMP2_BASE OPAMP2_BASE_NS +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS @@ -3472,9 +3492,17 @@ typedef struct #define ADF1_Filter0 ADF1_Filter0_NS #define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS - #endif +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + /******************************************************************************/ /* */ /* Analog to Digital Converter */ @@ -3587,18 +3615,21 @@ typedef struct #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ #define ADC_CR_CALINDEX0_Pos (24U) #define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ -#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ #define ADC_CR_CALINDEX1_Pos (25U) #define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ -#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ #define ADC_CR_CALINDEX2_Pos (26U) #define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ -#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ #define ADC_CR_CALINDEX3_Pos (27U) #define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ -#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ @@ -4058,7 +4089,7 @@ typedef struct #define ADC_HTR_AWDFILT_Pos (29U) #define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ -#define ADC_HTR_AWDFILT ADC_HTR_HT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ #define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ #define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ #define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ @@ -4224,18 +4255,32 @@ typedef struct #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ /******************** Bit definition for ADC_PW register ********************/ -#define ADC4_PW_AUTOFF_Pos (0U) -#define ADC4_PW_AUTOFF_Msk (0x1UL << ADC4_PW_AUTOFF_Pos) /*!< 0x00000001 */ -#define ADC4_PW_AUTOFF ADC4_PW_AUTOFF_Msk /*!< ADC Auto-Off mode */ -#define ADC4_PW_DPD_Pos (1U) -#define ADC4_PW_DPD_Msk (0x1UL << ADC4_PW_DPD_Pos) /*!< 0x00000002 */ -#define ADC4_PW_DPD ADC4_PW_DPD_Msk /*!< ADC Deep Power mode */ -#define ADC4_PW_VREFPROT_Pos (2U) -#define ADC4_PW_VREFPROT_Msk (0x1UL << ADC4_PW_VREFPROT_Pos) /*!< 0x00000004 */ -#define ADC4_PW_VREFPROT ADC4_PW_VREFPROT_Msk /*!< ADC Vref protection */ -#define ADC4_PW_VREFSECSMP_Pos (3U) -#define ADC4_PW_VREFSECSMP_Msk (0x1UL << ADC4_PW_VREFSECSMP_Pos) /*!< 0x00000008 */ -#define ADC4_PW_VREFSECSMP ADC4_PW_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP /******************** Bit definition for ADC_JSQR register ********************/ #define ADC_JSQR_JL_Pos (0U) @@ -4346,7 +4391,7 @@ typedef struct /******************** Bit definition for ADC_OFR2 register ********************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ @@ -4378,11 +4423,11 @@ typedef struct #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR2_USAT_Pos (25U) #define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR2_SSAT_Pos (26U) -#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ #define ADC_OFR2_OFFSET2_CH_Pos (27U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ @@ -4395,7 +4440,7 @@ typedef struct /******************** Bit definition for ADC_OFR3 register ********************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ @@ -4444,7 +4489,7 @@ typedef struct /******************** Bit definition for ADC_OFR4 register ********************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ @@ -5841,6 +5886,9 @@ typedef struct #define AES_IER_KEIE_Pos (2U) #define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ #define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ /******************* Bit definition for AES_ISR register ******************/ #define AES_ISR_CCF_Pos (0U) @@ -5852,6 +5900,9 @@ typedef struct #define AES_ISR_KEIF_Pos (2U) #define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ #define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ /******************* Bit definition for AES_ICR register ******************/ #define AES_ICR_CCF_Pos (0U) @@ -5863,6 +5914,9 @@ typedef struct #define AES_ICR_KEIF_Pos (2U) #define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ #define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ /******************************************************************************/ /* */ @@ -6029,9 +6083,6 @@ typedef struct #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk -#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Pos (9U) -#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Pos) -#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZR register ***********/ #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) @@ -6633,7 +6684,7 @@ typedef struct #define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ #define DMA_CSR_SUSPF_Pos (13U) #define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ -#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ #define DMA_CSR_TOF_Pos (14U) #define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ #define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ @@ -6967,11 +7018,6 @@ typedef struct #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */ #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */ -#define DMA2D_FGPFCCR_CSS_Pos (18U) -#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */ -#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */ -#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */ -#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */ #define DMA2D_FGPFCCR_AI_Pos (20U) #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */ #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */ @@ -7223,9 +7269,6 @@ typedef struct #define EXTI_RTSR1_RT23_Pos (23U) #define EXTI_RTSR1_RT23_Msk (0x1UL << EXTI_RTSR1_RT23_Pos) /*!< 0x00800000 */ #define EXTI_RTSR1_RT23 EXTI_RTSR1_RT23_Msk /*!< Rising trigger configuration for input line 23 */ -#define EXTI_RTSR1_RT24_Pos (24U) -#define EXTI_RTSR1_RT24_Msk (0x1UL << EXTI_RTSR1_RT24_Pos) /*!< 0x01000000 */ -#define EXTI_RTSR1_RT24 EXTI_RTSR1_RT24_Msk /*!< Rising trigger configuration for input line 24 */ /****************** Bit definition for EXTI_FTSR1 register ******************/ #define EXTI_FTSR1_FT0_Pos (0U) @@ -7300,9 +7343,6 @@ typedef struct #define EXTI_FTSR1_FT23_Pos (23U) #define EXTI_FTSR1_FT23_Msk (0x1UL << EXTI_FTSR1_FT23_Pos) /*!< 0x00800000 */ #define EXTI_FTSR1_FT23 EXTI_FTSR1_FT23_Msk /*!< Falling trigger configuration for input line 23 */ -#define EXTI_FTSR1_FT24_Pos (24U) -#define EXTI_FTSR1_FT24_Msk (0x1UL << EXTI_FTSR1_FT24_Pos) /*!< 0x01000000 */ -#define EXTI_FTSR1_FT24 EXTI_FTSR1_FT24_Msk /*!< Falling trigger configuration for input line 24 */ /****************** Bit definition for EXTI_SWIER1 register *****************/ #define EXTI_SWIER1_SWI0_Pos (0U) @@ -7377,9 +7417,6 @@ typedef struct #define EXTI_SWIER1_SWI23_Pos (23U) #define EXTI_SWIER1_SWI23_Msk (0x1UL << EXTI_SWIER1_SWI23_Pos) /*!< 0x00800000 */ #define EXTI_SWIER1_SWI23 EXTI_SWIER1_SWI23_Msk /*!< Software Interrupt on line 23 */ -#define EXTI_SWIER1_SWI24_Pos (24U) -#define EXTI_SWIER1_SWI24_Msk (0x1UL << EXTI_SWIER1_SWI24_Pos) /*!< 0x01000000 */ -#define EXTI_SWIER1_SWI24 EXTI_SWIER1_SWI24_Msk /*!< Software Interrupt on line 24 */ /******************* Bit definition for EXTI_RPR1 register ******************/ #define EXTI_RPR1_RPIF0_Pos (0U) @@ -7454,9 +7491,6 @@ typedef struct #define EXTI_RPR1_RPIF23_Pos (23U) #define EXTI_RPR1_RPIF23_Msk (0x1UL << EXTI_RPR1_RPIF23_Pos) /*!< 0x00800000 */ #define EXTI_RPR1_RPIF23 EXTI_RPR1_RPIF23_Msk /*!< Rising Pending Interrupt Flag on line 23 */ -#define EXTI_RPR1_RPIF24_Pos (24U) -#define EXTI_RPR1_RPIF24_Msk (0x1UL << EXTI_RPR1_RPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_RPR1_RPIF24 EXTI_RPR1_RPIF24_Msk /*!< Rising Pending Interrupt Flag on line 24 */ /******************* Bit definition for EXTI_FPR1 register ******************/ #define EXTI_FPR1_FPIF0_Pos (0U) @@ -7531,163 +7565,154 @@ typedef struct #define EXTI_FPR1_FPIF23_Pos (23U) #define EXTI_FPR1_FPIF23_Msk (0x1UL << EXTI_FPR1_FPIF23_Pos) /*!< 0x00800000 */ #define EXTI_FPR1_FPIF23 EXTI_FPR1_FPIF23_Msk /*!< Falling Pending Interrupt Flag on line 23 */ -#define EXTI_FPR1_FPIF24_Pos (24U) -#define EXTI_FPR1_FPIF24_Msk (0x1UL << EXTI_FPR1_FPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_FPR1_FPIF24 EXTI_FPR1_FPIF24_Msk /*!< Falling Pending Interrupt Flag on line 24 */ - -/******************* Bit definition for EXTI_SECENR1 register ******************/ -#define EXTI_SECENR1_RPIF0_Pos (0U) -#define EXTI_SECENR1_RPIF0_Msk (0x1UL << EXTI_SECENR1_RPIF0_Pos) /*!< 0x00000001 */ -#define EXTI_SECENR1_RPIF0 EXTI_SECENR1_RPIF0_Msk /*!< Security enable on line 0 */ -#define EXTI_SECENR1_RPIF1_Pos (1U) -#define EXTI_SECENR1_RPIF1_Msk (0x1UL << EXTI_SECENR1_RPIF1_Pos) /*!< 0x00000002 */ -#define EXTI_SECENR1_RPIF1 EXTI_SECENR1_RPIF1_Msk /*!< Security enable on line 1 */ -#define EXTI_SECENR1_RPIF2_Pos (2U) -#define EXTI_SECENR1_RPIF2_Msk (0x1UL << EXTI_SECENR1_RPIF2_Pos) /*!< 0x00000004 */ -#define EXTI_SECENR1_RPIF2 EXTI_SECENR1_RPIF2_Msk /*!< Security enable on line 2 */ -#define EXTI_SECENR1_RPIF3_Pos (3U) -#define EXTI_SECENR1_RPIF3_Msk (0x1UL << EXTI_SECENR1_RPIF3_Pos) /*!< 0x00000008 */ -#define EXTI_SECENR1_RPIF3 EXTI_SECENR1_RPIF3_Msk /*!< Security enable on line 3 */ -#define EXTI_SECENR1_RPIF4_Pos (4U) -#define EXTI_SECENR1_RPIF4_Msk (0x1UL << EXTI_SECENR1_RPIF4_Pos) /*!< 0x00000010 */ -#define EXTI_SECENR1_RPIF4 EXTI_SECENR1_RPIF4_Msk /*!< Security enable on line 4 */ -#define EXTI_SECENR1_RPIF5_Pos (5U) -#define EXTI_SECENR1_RPIF5_Msk (0x1UL << EXTI_SECENR1_RPIF5_Pos) /*!< 0x00000020 */ -#define EXTI_SECENR1_RPIF5 EXTI_SECENR1_RPIF5_Msk /*!< Security enable on line 5 */ -#define EXTI_SECENR1_RPIF6_Pos (6U) -#define EXTI_SECENR1_RPIF6_Msk (0x1UL << EXTI_SECENR1_RPIF6_Pos) /*!< 0x00000040 */ -#define EXTI_SECENR1_RPIF6 EXTI_SECENR1_RPIF6_Msk /*!< Security enable on line 6 */ -#define EXTI_SECENR1_RPIF7_Pos (7U) -#define EXTI_SECENR1_RPIF7_Msk (0x1UL << EXTI_SECENR1_RPIF7_Pos) /*!< 0x00000080 */ -#define EXTI_SECENR1_RPIF7 EXTI_SECENR1_RPIF7_Msk /*!< Security enable on line 7 */ -#define EXTI_SECENR1_RPIF8_Pos (8U) -#define EXTI_SECENR1_RPIF8_Msk (0x1UL << EXTI_SECENR1_RPIF8_Pos) /*!< 0x00000100 */ -#define EXTI_SECENR1_RPIF8 EXTI_SECENR1_RPIF8_Msk /*!< Security enable on line 8 */ -#define EXTI_SECENR1_RPIF9_Pos (9U) -#define EXTI_SECENR1_RPIF9_Msk (0x1UL << EXTI_SECENR1_RPIF9_Pos) /*!< 0x00000200 */ -#define EXTI_SECENR1_RPIF9 EXTI_SECENR1_RPIF9_Msk /*!< Security enable on line 9 */ -#define EXTI_SECENR1_RPIF10_Pos (10U) -#define EXTI_SECENR1_RPIF10_Msk (0x1UL << EXTI_SECENR1_RPIF10_Pos) /*!< 0x00000400 */ -#define EXTI_SECENR1_RPIF10 EXTI_SECENR1_RPIF10_Msk /*!< Security enable on line 10 */ -#define EXTI_SECENR1_RPIF11_Pos (11U) -#define EXTI_SECENR1_RPIF11_Msk (0x1UL << EXTI_SECENR1_RPIF11_Pos) /*!< 0x00000800 */ -#define EXTI_SECENR1_RPIF11 EXTI_SECENR1_RPIF11_Msk /*!< Security enable on line 11 */ -#define EXTI_SECENR1_RPIF12_Pos (12U) -#define EXTI_SECENR1_RPIF12_Msk (0x1UL << EXTI_SECENR1_RPIF12_Pos) /*!< 0x00001000 */ -#define EXTI_SECENR1_RPIF12 EXTI_SECENR1_RPIF12_Msk /*!< Security enable on line 12 */ -#define EXTI_SECENR1_RPIF13_Pos (13U) -#define EXTI_SECENR1_RPIF13_Msk (0x1UL << EXTI_SECENR1_RPIF13_Pos) /*!< 0x00002000 */ -#define EXTI_SECENR1_RPIF13 EXTI_SECENR1_RPIF13_Msk /*!< Security enable on line 13 */ -#define EXTI_SECENR1_RPIF14_Pos (14U) -#define EXTI_SECENR1_RPIF14_Msk (0x1UL << EXTI_SECENR1_RPIF14_Pos) /*!< 0x00004000 */ -#define EXTI_SECENR1_RPIF14 EXTI_SECENR1_RPIF14_Msk /*!< Security enable on line 14 */ -#define EXTI_SECENR1_RPIF15_Pos (15U) -#define EXTI_SECENR1_RPIF15_Msk (0x1UL << EXTI_SECENR1_RPIF15_Pos) /*!< 0x00008000 */ -#define EXTI_SECENR1_RPIF15 EXTI_SECENR1_RPIF15_Msk /*!< Security enable on line 15 */ -#define EXTI_SECENR1_RPIF16_Pos (16U) -#define EXTI_SECENR1_RPIF16_Msk (0x1UL << EXTI_SECENR1_RPIF16_Pos) /*!< 0x00010000 */ -#define EXTI_SECENR1_RPIF16 EXTI_SECENR1_RPIF16_Msk /*!< Security enable on line 16 */ -#define EXTI_SECENR1_RPIF17_Pos (17U) -#define EXTI_SECENR1_RPIF17_Msk (0x1UL << EXTI_SECENR1_RPIF17_Pos) /*!< 0x00020000 */ -#define EXTI_SECENR1_RPIF17 EXTI_SECENR1_RPIF17_Msk /*!< Security enable on line 17 */ -#define EXTI_SECENR1_RPIF18_Pos (18U) -#define EXTI_SECENR1_RPIF18_Msk (0x1UL << EXTI_SECENR1_RPIF18_Pos) /*!< 0x00040000 */ -#define EXTI_SECENR1_RPIF18 EXTI_SECENR1_RPIF18_Msk /*!< Security enable on line 18 */ -#define EXTI_SECENR1_RPIF19_Pos (19U) -#define EXTI_SECENR1_RPIF19_Msk (0x1UL << EXTI_SECENR1_RPIF19_Pos) /*!< 0x00080000 */ -#define EXTI_SECENR1_RPIF19 EXTI_SECENR1_RPIF19_Msk /*!< Security enable on line 19 */ -#define EXTI_SECENR1_RPIF20_Pos (20U) -#define EXTI_SECENR1_RPIF20_Msk (0x1UL << EXTI_SECENR1_RPIF20_Pos) /*!< 0x00100000 */ -#define EXTI_SECENR1_RPIF20 EXTI_SECENR1_RPIF20_Msk /*!< Security enable on line 20 */ -#define EXTI_SECENR1_RPIF21_Pos (21U) -#define EXTI_SECENR1_RPIF21_Msk (0x1UL << EXTI_SECENR1_RPIF21_Pos) /*!< 0x00200000 */ -#define EXTI_SECENR1_RPIF21 EXTI_SECENR1_RPIF21_Msk /*!< Security enable on line 21 */ -#define EXTI_SECENR1_RPIF22_Pos (22U) -#define EXTI_SECENR1_RPIF22_Msk (0x1UL << EXTI_SECENR1_RPIF22_Pos) /*!< 0x00400000 */ -#define EXTI_SECENR1_RPIF22 EXTI_SECENR1_RPIF22_Msk /*!< Security enable on line 22 */ -#define EXTI_SECENR1_RPIF23_Pos (23U) -#define EXTI_SECENR1_RPIF23_Msk (0x1UL << EXTI_SECENR1_RPIF23_Pos) /*!< 0x00800000 */ -#define EXTI_SECENR1_RPIF23 EXTI_SECENR1_RPIF23_Msk /*!< Security enable on line 23 */ -#define EXTI_SECENR1_RPIF24_Pos (24U) -#define EXTI_SECENR1_RPIF24_Msk (0x1UL << EXTI_SECENR1_RPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_SECENR1_RPIF24 EXTI_SECENR1_RPIF24_Msk /*!< Security enable on line 24 */ - -/******************* Bit definition for EXTI_PRIVENR1 register ******************/ -#define EXTI_PRIVENR1_RPIF0_Pos (0U) -#define EXTI_PRIVENR1_RPIF0_Msk (0x1UL << EXTI_PRIVENR1_RPIF0_Pos) /*!< 0x00000001 */ -#define EXTI_PRIVENR1_RPIF0 EXTI_PRIVENR1_RPIF0_Msk /*!< Privilege enable on line 0 */ -#define EXTI_PRIVENR1_RPIF1_Pos (1U) -#define EXTI_PRIVENR1_RPIF1_Msk (0x1UL << EXTI_PRIVENR1_RPIF1_Pos) /*!< 0x00000002 */ -#define EXTI_PRIVENR1_RPIF1 EXTI_PRIVENR1_RPIF1_Msk /*!< Privilege enable on line 1 */ -#define EXTI_PRIVENR1_RPIF2_Pos (2U) -#define EXTI_PRIVENR1_RPIF2_Msk (0x1UL << EXTI_PRIVENR1_RPIF2_Pos) /*!< 0x00000004 */ -#define EXTI_PRIVENR1_RPIF2 EXTI_PRIVENR1_RPIF2_Msk /*!< Privilege enable on line 2 */ -#define EXTI_PRIVENR1_RPIF3_Pos (3U) -#define EXTI_PRIVENR1_RPIF3_Msk (0x1UL << EXTI_PRIVENR1_RPIF3_Pos) /*!< 0x00000008 */ -#define EXTI_PRIVENR1_RPIF3 EXTI_PRIVENR1_RPIF3_Msk /*!< Privilege enable on line 3 */ -#define EXTI_PRIVENR1_RPIF4_Pos (4U) -#define EXTI_PRIVENR1_RPIF4_Msk (0x1UL << EXTI_PRIVENR1_RPIF4_Pos) /*!< 0x00000010 */ -#define EXTI_PRIVENR1_RPIF4 EXTI_PRIVENR1_RPIF4_Msk /*!< Privilege enable on line 4 */ -#define EXTI_PRIVENR1_RPIF5_Pos (5U) -#define EXTI_PRIVENR1_RPIF5_Msk (0x1UL << EXTI_PRIVENR1_RPIF5_Pos) /*!< 0x00000020 */ -#define EXTI_PRIVENR1_RPIF5 EXTI_PRIVENR1_RPIF5_Msk /*!< Privilege enable on line 5 */ -#define EXTI_PRIVENR1_RPIF6_Pos (6U) -#define EXTI_PRIVENR1_RPIF6_Msk (0x1UL << EXTI_PRIVENR1_RPIF6_Pos) /*!< 0x00000040 */ -#define EXTI_PRIVENR1_RPIF6 EXTI_PRIVENR1_RPIF6_Msk /*!< Privilege enable on line 6 */ -#define EXTI_PRIVENR1_RPIF7_Pos (7U) -#define EXTI_PRIVENR1_RPIF7_Msk (0x1UL << EXTI_PRIVENR1_RPIF7_Pos) /*!< 0x00000080 */ -#define EXTI_PRIVENR1_RPIF7 EXTI_PRIVENR1_RPIF7_Msk /*!< Privilege enable on line 7 */ -#define EXTI_PRIVENR1_RPIF8_Pos (8U) -#define EXTI_PRIVENR1_RPIF8_Msk (0x1UL << EXTI_PRIVENR1_RPIF8_Pos) /*!< 0x00000100 */ -#define EXTI_PRIVENR1_RPIF8 EXTI_PRIVENR1_RPIF8_Msk /*!< Privilege enable on line 8 */ -#define EXTI_PRIVENR1_RPIF9_Pos (9U) -#define EXTI_PRIVENR1_RPIF9_Msk (0x1UL << EXTI_PRIVENR1_RPIF9_Pos) /*!< 0x00000200 */ -#define EXTI_PRIVENR1_RPIF9 EXTI_PRIVENR1_RPIF9_Msk /*!< Privilege enable on line 9 */ -#define EXTI_PRIVENR1_RPIF10_Pos (10U) -#define EXTI_PRIVENR1_RPIF10_Msk (0x1UL << EXTI_PRIVENR1_RPIF10_Pos) /*!< 0x00000400 */ -#define EXTI_PRIVENR1_RPIF10 EXTI_PRIVENR1_RPIF10_Msk /*!< Privilege enable on line 10 */ -#define EXTI_PRIVENR1_RPIF11_Pos (11U) -#define EXTI_PRIVENR1_RPIF11_Msk (0x1UL << EXTI_PRIVENR1_RPIF11_Pos) /*!< 0x00000800 */ -#define EXTI_PRIVENR1_RPIF11 EXTI_PRIVENR1_RPIF11_Msk /*!< Privilege enable on line 11 */ -#define EXTI_PRIVENR1_RPIF12_Pos (12U) -#define EXTI_PRIVENR1_RPIF12_Msk (0x1UL << EXTI_PRIVENR1_RPIF12_Pos) /*!< 0x00001000 */ -#define EXTI_PRIVENR1_RPIF12 EXTI_PRIVENR1_RPIF12_Msk /*!< Privilege enable on line 12 */ -#define EXTI_PRIVENR1_RPIF13_Pos (13U) -#define EXTI_PRIVENR1_RPIF13_Msk (0x1UL << EXTI_PRIVENR1_RPIF13_Pos) /*!< 0x00002000 */ -#define EXTI_PRIVENR1_RPIF13 EXTI_PRIVENR1_RPIF13_Msk /*!< Privilege enable on line 13 */ -#define EXTI_PRIVENR1_RPIF14_Pos (14U) -#define EXTI_PRIVENR1_RPIF14_Msk (0x1UL << EXTI_PRIVENR1_RPIF14_Pos) /*!< 0x00004000 */ -#define EXTI_PRIVENR1_RPIF14 EXTI_PRIVENR1_RPIF14_Msk /*!< Privilege enable on line 14 */ -#define EXTI_PRIVENR1_RPIF15_Pos (15U) -#define EXTI_PRIVENR1_RPIF15_Msk (0x1UL << EXTI_PRIVENR1_RPIF15_Pos) /*!< 0x00008000 */ -#define EXTI_PRIVENR1_RPIF15 EXTI_PRIVENR1_RPIF15_Msk /*!< Privilege enable on line 15 */ -#define EXTI_PRIVENR1_RPIF16_Pos (16U) -#define EXTI_PRIVENR1_RPIF16_Msk (0x1UL << EXTI_PRIVENR1_RPIF16_Pos) /*!< 0x00010000 */ -#define EXTI_PRIVENR1_RPIF16 EXTI_PRIVENR1_RPIF16_Msk /*!< Privilege enable on line 16 */ -#define EXTI_PRIVENR1_RPIF17_Pos (17U) -#define EXTI_PRIVENR1_RPIF17_Msk (0x1UL << EXTI_PRIVENR1_RPIF17_Pos) /*!< 0x00020000 */ -#define EXTI_PRIVENR1_RPIF17 EXTI_PRIVENR1_RPIF17_Msk /*!< Privilege enable on line 17 */ -#define EXTI_PRIVENR1_RPIF18_Pos (18U) -#define EXTI_PRIVENR1_RPIF18_Msk (0x1UL << EXTI_PRIVENR1_RPIF18_Pos) /*!< 0x00040000 */ -#define EXTI_PRIVENR1_RPIF18 EXTI_PRIVENR1_RPIF18_Msk /*!< Privilege enable on line 18 */ -#define EXTI_PRIVENR1_RPIF19_Pos (19U) -#define EXTI_PRIVENR1_RPIF19_Msk (0x1UL << EXTI_PRIVENR1_RPIF19_Pos) /*!< 0x00080000 */ -#define EXTI_PRIVENR1_RPIF19 EXTI_PRIVENR1_RPIF19_Msk /*!< Privilege enable on line 19 */ -#define EXTI_PRIVENR1_RPIF20_Pos (20U) -#define EXTI_PRIVENR1_RPIF20_Msk (0x1UL << EXTI_PRIVENR1_RPIF20_Pos) /*!< 0x00100000 */ -#define EXTI_PRIVENR1_RPIF20 EXTI_PRIVENR1_RPIF20_Msk /*!< Privilege enable on line 20 */ -#define EXTI_PRIVENR1_RPIF21_Pos (21U) -#define EXTI_PRIVENR1_RPIF21_Msk (0x1UL << EXTI_PRIVENR1_RPIF21_Pos) /*!< 0x00200000 */ -#define EXTI_PRIVENR1_RPIF21 EXTI_PRIVENR1_RPIF21_Msk /*!< Privilege enable on line 21 */ -#define EXTI_PRIVENR1_RPIF22_Pos (22U) -#define EXTI_PRIVENR1_RPIF22_Msk (0x1UL << EXTI_PRIVENR1_RPIF22_Pos) /*!< 0x00400000 */ -#define EXTI_PRIVENR1_RPIF22 EXTI_PRIVENR1_RPIF22_Msk /*!< Privilege enable on line 22 */ -#define EXTI_PRIVENR1_RPIF23_Pos (23U) -#define EXTI_PRIVENR1_RPIF23_Msk (0x1UL << EXTI_PRIVENR1_RPIF23_Pos) /*!< 0x00800000 */ -#define EXTI_PRIVENR1_RPIF23 EXTI_PRIVENR1_RPIF23_Msk /*!< Privilege enable on line 23 */ -#define EXTI_PRIVENR1_RPIF24_Pos (24U) -#define EXTI_PRIVENR1_RPIF24_Msk (0x1UL << EXTI_PRIVENR1_RPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_PRIVENR1_RPIF24 EXTI_PRIVENR1_RPIF24_Msk /*!< Privilege enable on line 24 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0U) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1U) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2U) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3U) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4U) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5U) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6U) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7U) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8U) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9U) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10U) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11U) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12U) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13U) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14U) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15U) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16U) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17U) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18U) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ +#define EXTI_SECCFGR1_SEC19_Pos (19U) +#define EXTI_SECCFGR1_SEC19_Msk (0x1UL << EXTI_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define EXTI_SECCFGR1_SEC19 EXTI_SECCFGR1_SEC19_Msk /*!< Security enable on line 19 */ +#define EXTI_SECCFGR1_SEC20_Pos (20U) +#define EXTI_SECCFGR1_SEC20_Msk (0x1UL << EXTI_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define EXTI_SECCFGR1_SEC20 EXTI_SECCFGR1_SEC20_Msk /*!< Security enable on line 20 */ +#define EXTI_SECCFGR1_SEC21_Pos (21U) +#define EXTI_SECCFGR1_SEC21_Msk (0x1UL << EXTI_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define EXTI_SECCFGR1_SEC21 EXTI_SECCFGR1_SEC21_Msk /*!< Security enable on line 21 */ +#define EXTI_SECCFGR1_SEC22_Pos (22U) +#define EXTI_SECCFGR1_SEC22_Msk (0x1UL << EXTI_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define EXTI_SECCFGR1_SEC22 EXTI_SECCFGR1_SEC22_Msk /*!< Security enable on line 22 */ +#define EXTI_SECCFGR1_SEC23_Pos (23U) +#define EXTI_SECCFGR1_SEC23_Msk (0x1UL << EXTI_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define EXTI_SECCFGR1_SEC23 EXTI_SECCFGR1_SEC23_Msk /*!< Security enable on line 23 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on line 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on line 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on line 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on line 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on line 23 */ /***************** Bit definition for EXTI_EXTICR1 register **************/ #define EXTI_EXTICR1_EXTI0_Pos (0U) @@ -7809,6 +7834,11 @@ typedef struct #define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ #define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +/***************** Bit definition for EXTI_LOCKR register **************/ +#define EXTI_LOCKR_LOCK_Pos (0U) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Global security and privilege configuration registers lock */ + /******************* Bit definition for EXTI_IMR1 register ******************/ #define EXTI_IMR1_IM0_Pos (0U) #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ @@ -7882,9 +7912,6 @@ typedef struct #define EXTI_IMR1_IM23_Pos (23U) #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR1_IM24_Pos (24U) -#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ -#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ /******************* Bit definition for EXTI_EMR1 register ******************/ #define EXTI_EMR1_EM0_Pos (0U) @@ -7959,9 +7986,6 @@ typedef struct #define EXTI_EMR1_EM23_Pos (23U) #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ -#define EXTI_EMR1_EM24_Pos (24U) -#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ -#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ /******************************************************************************/ /* */ @@ -8546,13 +8570,14 @@ typedef struct /* FLASH */ /* */ /******************************************************************************/ -#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ -#define FLASH_BLOCKBASED_NB_REG (4U) /* 4 Block-based registers for each Flash bank */ +#define FLASH_SIZE_DEFAULT 0x200000U /*!< Flash memory default size */ +#define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */ -#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x200000U : \ - ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x200000U : \ - (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U))) +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) @@ -8807,9 +8832,9 @@ typedef struct #define FLASH_OPTR_nRST_SHDW_Pos (14U) #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ -#define FLASH_OPTR_SRAM134_RST_Pos (15U) -#define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */ -#define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ #define FLASH_OPTR_IWDG_SW_Pos (16U) #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ @@ -10251,6 +10276,7 @@ typedef struct #define GPIO_SECCFGR_SEC15_Pos (15U) #define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ #define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + /******************************************************************************/ /* */ /* Low Power General Purpose IOs (LPGPIO) */ @@ -10765,55 +10791,58 @@ typedef struct /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ -/*!< ****************** Bit definition for COMPx_CSR register ********************/ + +#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */ + +/********************** Bit definition for COMP_CSR register ****************/ #define COMP_CSR_EN_Pos (0U) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ -#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ #define COMP_CSR_INMSEL_Pos (4U) -#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ -#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ -#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ -#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ -#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ -#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ #define COMP_CSR_INPSEL_Pos (8U) -#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ -#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ -#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ #define COMP_CSR_WINMODE_Pos (11U) -#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ -#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ #define COMP_CSR_WINOUT_Pos (14U) -#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ -#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ #define COMP_CSR_POLARITY_Pos (15U) -#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ -#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ #define COMP_CSR_HYST_Pos (16U) -#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ -#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ -#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ -#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ #define COMP_CSR_PWRMODE_Pos (18U) -#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ -#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ -#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ -#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ #define COMP_CSR_BLANKSEL_Pos (20U) -#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ -#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ -#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */ -#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ -#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ #define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ #define COMP_CSR_VALUE_Pos (30U) -#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ -#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ #define COMP_CSR_LOCK_Pos (31U) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ -#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ /******************************************************************************/ /* */ @@ -11961,10 +11990,10 @@ typedef struct #define TIM_DCR_DBSS_Pos (16U) #define TIM_DCR_DBSS_Msk (0xFUL << TIM_DCR_DBSS_Pos) /*!< 0x00000F00 */ #define TIM_DCR_DBSS TIM_DCR_DBSS_Msk /*!APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ +#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ + #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ -#if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP) -#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP) -#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP) -#endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */ - #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) @@ -556,6 +642,33 @@ extern HAL_TickFreqTypeDef uwTickFreq; #endif /* __ARM_FEATURE_CMSE */ + +#ifdef SYSCFG_OTGHSPHYCR_EN +#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) + +#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) + +#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) + +#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) + +#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) + +#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) +#endif /* SYSCFG_OTGHSPHYCR_EN */ + /** * @} */ @@ -606,6 +719,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); /** * @} @@ -637,10 +753,28 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void); - +#ifdef SYSCFG_OTGHSPHYCR_EN +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); +#endif /* SYSCFG_OTGHSPHYCR_EN */ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); - +void HAL_SYSCFG_EnableSRAMCached(void); +void HAL_SYSCFG_DisableSRAMCached(void); +void HAL_SYSCFG_EnableVddCompensationCell(void); +void HAL_SYSCFG_EnableVddIO2CompensationCell(void); +#if defined(SYSCFG_CCCSR_EN3) +void HAL_SYSCFG_EnableVddHSPICompensationCell(void); +#endif /* SYSCFG_CCCSR_EN3 */ +void HAL_SYSCFG_DisableVddCompensationCell(void); +void HAL_SYSCFG_DisableVddIO2CompensationCell(void); +#if defined(SYSCFG_CCCSR_EN3) +void HAL_SYSCFG_DisableVddHSPICompensationCell(void); +#endif /* SYSCFG_CCCSR_EN3 */ /** * @} */ @@ -685,6 +819,10 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri * @} */ +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h index 55e9452abc..ced44d570f 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -204,9 +204,9 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h index 7d2ed1c477..55989cfebb 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -78,7 +78,6 @@ typedef struct } CRYP_ConfigTypeDef; - /** * @brief CRYP State Structure definition */ @@ -93,6 +92,31 @@ typedef enum #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ } HAL_CRYP_STATETypeDef; +/** + * @brief CRYP Context Structure definition + */ + +typedef struct +{ + uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */ + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */ + uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */ + uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */ + uint32_t KeyMode; /*!< This parameter can be value of @ref CRYP_Key_Mode */ + uint32_t Phase; /*!< CRYP peripheral phase */ + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */ + uint32_t CR_Reg; /*!< CRYP CR register */ + uint32_t IER_Reg; /*!< CRYP IER register */ + uint32_t IVR0_Reg; /*!< CRYP IVR0 register */ + uint32_t IVR1_Reg; /*!< CRYP IVR1 register */ + uint32_t IVR2_Reg; /*!< CRYP IVR2 register */ + uint32_t IVR3_Reg; /*!< CRYP IVR3 register */ + +} CRYP_ContextTypeDef; + #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /** * @brief HAL CRYP mode suspend definitions @@ -239,6 +263,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point #define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */ #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ #define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */ +#define HAL_CRYP_ERROR_RNG 0x00000200U /*!< Rng error */ /** * @} */ @@ -340,10 +365,15 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_NO_SWAP 0x00000000U /*!< 32-bit data type (no swapping) */ -#define CRYP_HALFWORD_SWAP AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */ -#define CRYP_BYTE_SWAP AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */ -#define CRYP_BIT_SWAP AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */ +#define CRYP_DATATYPE_32B 0x00000000U +#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 +#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 +#define CRYP_DATATYPE_1B AES_CR_DATATYPE + +#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */ +#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */ +#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */ +#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */ /** * @} @@ -352,9 +382,10 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point /** @defgroup CRYP_Interrupt CRYP Interrupt * @{ */ -#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */ -#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */ -#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */ +#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */ +#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */ +#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */ +#define CRYP_IT_RNGEIE AES_IER_RNGEIE /*!< Rng error interrupt enable */ /** * @} @@ -364,14 +395,15 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden - also set when transferring a shared key from SAES peripheral */ -#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */ -#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */ -#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed flag as AES_ISR_CCF */ -#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */ -#define CRYP_FLAG_KEIF AES_ISR_KEIF /*Key error interrupt flag */ -#define CRYP_FLAG_RWEIF AES_ISR_RWEIF /*Read or write error Interrupt flag */ +#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden also set when + transferring a shared key from SAES peripheral */ +#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */ +#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */ +#define CRYP_FLAG_CCF AES_ISR_CCF /*!< Computation completed flag as AES_ISR_CCF */ +#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */ +#define CRYP_FLAG_KEIF AES_ISR_KEIF /*! 0U) && ((SIZE) <= DMA_CBR1_BNDT)) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ - (((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \ - ((ATTRIBUTE) != 0U)) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) #else #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ @@ -850,12 +894,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#else -#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ - (((INSTANCE)->MISR & (GLOBAL_FLAG))) #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) + /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h index c5ad706d51..df9b9246f9 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h @@ -6,7 +6,7 @@ ********************************************************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -302,7 +302,9 @@ typedef struct __DMA_QListTypeDef #define GPDMA1_TRIGGER_LPTIM2_CH2 (14U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ #define GPDMA1_TRIGGER_LPTIM4_OUT (15U) /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ #define GPDMA1_TRIGGER_COMP1_OUT (16U) /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#if defined(COMP2) #define GPDMA1_TRIGGER_COMP2_OUT (17U) /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ +#endif /* COMP2 */ #define GPDMA1_TRIGGER_RTC_ALRA_TRG (18U) /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ #define GPDMA1_TRIGGER_RTC_ALRB_TRG (19U) /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ #define GPDMA1_TRIGGER_RTC_WUT_TRG (20U) /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ @@ -328,8 +330,48 @@ typedef struct __DMA_QListTypeDef #define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ #define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ #define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#if defined (TIM3_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM3_TRGO (44U) /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* defined (TRIGGER_TIM3_TRGO_SUPPORT) */ +#if defined (TIM4_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM4_TRGO (45U) /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* defined (TRIGGER_TIM4_TRGO_SUPPORT) */ +#if defined (TIM5_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM5_TRGO (46U) /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* defined (TRIGGER_TIM5_TRGO_SUPPORT) */ +#if defined (LTDC) +#define GPDMA1_TRIGGER_LTDC_LI (47U) /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* defined (LTDC) */ +#if defined (DSI) +#define GPDMA1_TRIGGER_DSI_TE (48U) /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define GPDMA1_TRIGGER_DSI_ER (49U) /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* defined (DSI) */ +#if defined (DMA2D_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_DMA2D_TC (50U) /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define GPDMA1_TRIGGER_DMA2D_CTC (51U) /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define GPDMA1_TRIGGER_DMA2D_TW (52U) /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* defined (DMA2D_TRIGGER_SUPPORT) */ +#if defined (GPU2D) +#define GPDMA1_TRIGGER_GPU2D_FLAG0 (53U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG1 (54U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG2 (55U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG3 (56U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* defined (GPU2D) */ #define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ #define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ +#if defined (GFXTIM) +#define GPDMA1_TRIGGER_GFXTIM_EVT3 (59U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT2 (60U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT1 (61U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT0 (62U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ +#endif /* defined (GFXTIM) */ +#if defined (JPEG) +#define GPDMA1_TRIGGER_JPEG_EOC (63U) /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define GPDMA1_TRIGGER_JPEG_IFNF (64U) /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define GPDMA1_TRIGGER_JPEG_IFT (65U) /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define GPDMA1_TRIGGER_JPEG_OFNE (66U) /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define GPDMA1_TRIGGER_JPEG_OFT (67U) /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ +#endif /* defined (JPEG) */ /* LPDMA1 triggers */ #define LPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ @@ -345,7 +387,9 @@ typedef struct __DMA_QListTypeDef #define LPDMA1_TRIGGER_LPTIM3_CH1 (10U) /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ #define LPDMA1_TRIGGER_LPTIM4_OUT (11U) /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ #define LPDMA1_TRIGGER_COMP1_OUT (12U) /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ +#if defined(COMP2) #define LPDMA1_TRIGGER_COMP2_OUT (13U) /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ +#endif /* COMP2 */ #define LPDMA1_TRIGGER_RTC_ALRA_TRG (14U) /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ #define LPDMA1_TRIGGER_RTC_ALRB_TRG (15U) /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ #define LPDMA1_TRIGGER_RTC_WUT_TRG (16U) /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ @@ -419,8 +463,8 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); * @} */ -/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List I/O Operation Functions - * @brief Linked-List I/O Operation Functions +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions * @{ */ HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); @@ -564,6 +608,8 @@ typedef struct #define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ #define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ +#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ + #define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ #define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ @@ -646,8 +692,11 @@ typedef struct ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) -#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ - ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) +#if defined (GPDMA1_TRIGGER_JPEG_OFT) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_JPEG_OFT) +#else +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) +#endif /* GPDMA1_TRIGGER_JPEG_OFT */ #define IS_DMA_NODE_TYPE(TYPE) \ (((TYPE) == DMA_LPDMA_LINEAR_NODE) || \ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h index 752be3a5e3..2c80f85cd1 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -82,7 +82,7 @@ typedef struct uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, @@ -325,7 +325,7 @@ typedef struct #define OB_USER_NRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ #define OB_USER_NRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ #define OB_USER_NRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */ -#define OB_USER_SRAM134_RST 0x00000010U /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ +#define OB_USER_SRAM_RST 0x00000010U /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ #define OB_USER_IWDG_SW 0x00000020U /*!< Independent watchdog selection */ #define OB_USER_IWDG_STOP 0x00000040U /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STDBY 0x00000080U /*!< Independent watchdog counter freeze in standby mode */ @@ -333,7 +333,9 @@ typedef struct #define OB_USER_SWAP_BANK 0x00000200U /*!< Swap banks */ #define OB_USER_DUALBANK 0x00000400U /*!< Dual-Bank on 1MB/512kB Flash memory devices */ #define OB_USER_BKPRAM_ECC 0x00000800U /*!< Backup RAM ECC detection and correction enable */ +#if defined(SRAM3_BASE) #define OB_USER_SRAM3_ECC 0x00001000U /*!< SRAM3 ECC detection and correction enable */ +#endif /* SRAM3_BASE */ #define OB_USER_SRAM2_ECC 0x00002000U /*!< SRAM2 ECC detection and correction enable */ #define OB_USER_SRAM2_RST 0x00004000U /*!< SRAM2 Erase when system reset */ #define OB_USER_NSWBOOT0 0x00008000U /*!< Software BOOT0 */ @@ -390,13 +392,13 @@ typedef struct * @} */ -/** @defgroup FLASH_OB_USER_SRAM134_RST FLASH Option Bytes User SRAM134 Erase On Reset Type +/** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes User SRAM Erase On Reset Type * @{ */ -#define OB_SRAM134_RST_ERASE 0x00000000U /*!< SRAM1, SRAM3 and SRAM4 erased - when a system reset occurs */ -#define OB_SRAM134_RST_NOT_ERASE FLASH_OPTR_SRAM134_RST /*!< SRAM1, SRAM3 and SRAM4 are not erased - when a system reset occurs */ +#define OB_SRAM_RST_ERASE 0x00000000U /*!< All SRAMs (except SRAM2 and BKPSRAM) erased + when a system reset occurs */ +#define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< All SRAMs (except SRAM2 and BKPSRAM) not erased + when a system reset occurs */ /** * @} */ @@ -1021,7 +1023,7 @@ extern FLASH_ProcessTypeDef pFlash; #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) -#define IS_OB_USER_SRAM134_RST(VALUE) (((VALUE) == OB_SRAM134_RST_ERASE) || ((VALUE) == OB_SRAM134_RST_NOT_ERASE)) +#define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE)) #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h index 2324ab765f..879efc66f6 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h index 95ac2befef..6d9c0198e3 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -279,6 +279,9 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ @@ -340,8 +343,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); @@ -362,7 +366,8 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); /* IO attributes management functions *****************************************/ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes); /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h index 2b30d189df..e36532db91 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -51,7 +51,6 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ @@ -60,189 +59,18 @@ typedef struct * @{ */ -#if (defined(STM32U575xx) || defined(STM32U585xx)) -/*--------------STM32U575xx/STM32U585xx---------------------------*/ /** * @brief AF 0 selection */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ #define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ #define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ -#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ -#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ -#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */ -#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */ -#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ -#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */ -#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ -#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ -#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */ -#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /* LPGPIO Alternate Function mapping */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */ -#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */ -#define GPIO_AF14_SDMMC2 ((uint8_t)0x0E) /* SDMMC2 Alternate Function mapping */ - - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#elif (defined(STM32U599xx) || defined(STM32U5A9xx) || defined(STM32U595xx) || defined(STM32U5A5xx)) - -/*--------------STM32U5xxxx---*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ -#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ -#define GPIO_AF0_S2DSTOP ((uint8_t)0x00) /* S2DSTOP Alternate Function mapping */ #define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ +#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */ /** * @brief AF 1 selection @@ -265,8 +93,15 @@ typedef struct #define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */ #define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ -#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */ -#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C5 Alternate Function mapping */ +#endif /* I2C5 */ +#if defined(I2C6) +#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */ +#endif /* I2C6 */ +#if defined(GFXTIM) +#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 3 selection @@ -275,14 +110,19 @@ typedef struct #define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ #define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ #define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ #define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ +#if defined(USART2) #define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ +#endif /* USART2 */ #define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ +#if defined(USB_OTG_HS) #define GPIO_AF3_USB_HS ((uint8_t)0x03) /* USB_HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ /** * @brief AF 4 selection @@ -291,39 +131,56 @@ typedef struct #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ #define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ #define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ #define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ #define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */ +#if defined (I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5 */ /** * @brief AF 5 selection */ #define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ #define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) #define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ #define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ #define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */ +#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 6 selection */ -#define GPIO_AF6_I2C3 ((uint8_t)0x05) /* I2C3 Alternate Function mapping */ +#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) #define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOPSI2 */ #define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#if defined(USART2) #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#endif /* USART2 */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#if defined(USART6) #define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#endif /* USART6 */ +#if defined(LTDC) #define GPIO_AF7_LTDC ((uint8_t)0x07) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ /** * @brief AF 8 selection @@ -332,8 +189,15 @@ typedef struct #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(SDMMC2) +#define GPIO_AF8_SDMMC2 ((uint8_t)0x08) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#if defined(LTDC) #define GPIO_AF8_LTDC ((uint8_t)0x08) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ +#if defined(HSPI1) #define GPIO_AF8_HSPI1 ((uint8_t)0x08) /* HSPI1 Alternate Function mapping */ +#endif /* HSPI1 */ /** * @brief AF 9 selection @@ -348,38 +212,68 @@ typedef struct #define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */ #define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ #define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) #define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ #define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ +#if defined(USB_OTG_HS) #define GPIO_AF10_USB_HS ((uint8_t)0x0A) /* USB_HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ +#if defined(DSI) +#define GPIO_AF10_DSI ((uint8_t)0x0A) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(GFXTIM) +#define GPIO_AF10_GFXTIM ((uint8_t)0x0A) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 11 selection */ +#if defined(UCPD1) #define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */ -#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /* LPGPIO Alternate Function mapping */ +#endif /* UCPD1 */ +#if defined(SDMMC2) #define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#define GPIO_AF11_LPGPIO1 ((uint8_t)0x0B) /* LPGPIO1 Alternate Function mapping */ +#if defined(FMC_BASE) +#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ +#if defined(DSI) #define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(GFXTIM) +#define GPIO_AF11_GFXTIM ((uint8_t)0x0B) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 12 selection */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#if defined(FMC_BASE) #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ #define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ #define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ #define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#if defined(SDMMC2) #define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ /** * @brief AF 13 selection */ #define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ +#if defined(SAI2) #define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_RNG ((uint8_t)0x0D) /* RNG Alternate Function mapping */ +#endif /* SAI2 */ #define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */ #define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 14 selection @@ -393,7 +287,9 @@ typedef struct #define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */ #define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ #define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */ - +#if defined(FMC_BASE) +#define GPIO_AF14_FMC ((uint8_t)0x0E) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ /** * @brief AF 15 selection @@ -402,8 +298,6 @@ typedef struct #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) -#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */ - /** * @} */ @@ -420,12 +314,10 @@ typedef struct /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ -#if (defined(STM32U575xx) || defined(STM32U585xx)) /* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ #define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) -#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */ /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h index 6faf06d246..4e88ffd5d5 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -42,19 +42,25 @@ extern "C" { */ /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ -#define GTZC_MCPBB_NB_VCTR_REG_MAX (32U) -#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) +#if defined (SRAM5_BASE) +#define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */ +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */ +#else +#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */ +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */ +#endif /* SRAM5_BASE */ + typedef struct { - uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for + uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. Each bit corresponds to a block inside the super-block. 0 means non-secure, 1 means secure */ - uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for + uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. Each bit corresponds to a block inside the super-block. 0 means non-privilege, 1 means privilege */ - uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of + uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 0 means unlocked, 1 means locked */ } MPCBB_Attribute_ConfigTypeDef; @@ -191,7 +197,9 @@ typedef struct #define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) #define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) +#if defined (USART2) #define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) +#endif /* USART2 */ #define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) #define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) #define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) @@ -201,7 +209,18 @@ typedef struct #define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) #define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) #define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) +#if defined (UCPD1) #define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) +#endif /* UCPD1 */ +#if defined (USART6) +#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) +#endif /* USART6 */ +#if defined (I2C5) +#define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos) +#endif /* I2C5 */ +#if defined (I2C6) +#define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos) +#endif /* I2C6 */ #define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) @@ -210,47 +229,113 @@ typedef struct #define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) #define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) #define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) +#if defined (SAI2) #define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) +#endif /* SAI2 */ +#if defined (LTDC) || defined (USB_DRD_FS) +#define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos) +#endif /* LTDC || USB_DRD_FS */ +#if defined (DSI) +#define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos) +#endif /* DSI */ +#if defined (GFXTIM) +#define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos) +#endif /* GFXTIM */ #define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos) #define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) #define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) #define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) #define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) +#if defined (DMA2D) #define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos) +#endif /* DMA2D */ #define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) #define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) #define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) -#define GTZC_PERIPH_DCMI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) +#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) +#endif /* (USB_OTG_FS) || (USB_OTG_HS) */ +#if defined (AES) #define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) +#endif /* AES */ #define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) #define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) +#if defined (PKA) #define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) +#endif /* PKA */ +#if defined (SAES) #define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) +#endif /* SAES */ +#if defined (OCTOSPIM) #define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos) +#endif /* OCTOSPIM */ #define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) +#if defined (SDMMC2) #define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) +#endif /* SDMMC2 */ +#if defined (FMC_BASE) #define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos) +#endif /* FMC_BASE */ #define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) +#if defined (OCTOSPI2) #define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos) +#endif /* OCTOSPI2 */ #define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) +#if defined (GPU2D) +#define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos) +#endif /* GPU2D */ +#if defined (GFXMMU) +#define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos) +#define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos) +#endif /* GFXMMU */ +#if defined (HSPI1) +#define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos) +#endif /* HSPI1 */ +#if defined (DCACHE2) +#define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos) +#endif /* DCACHE2 */ +#if defined (JPEG) +#define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos) +#endif /* JPEG */ #define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) #define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) #define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) +#if defined (OTFDEC2) #define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) +#endif /* OTFDEC2 */ +#if defined (OTFDEC1) #define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) +#endif /* OTFDEC1 */ #define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos) #define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos) #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#if defined (FMC_BASE) #define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos) +#endif /* FMC_BASE */ #define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) +#if defined (OCTOSPI2) #define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos) +#endif /* OCTOSPI2 */ +#if defined (HSPI1) +#define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos) +#endif /* HSPI1 */ +#if defined (SRAM6_BASE) +#define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) +#define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) +#endif /* SRAM6_BASE */ #define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) #define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) +#if defined (SRAM3_BASE) #define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) +#endif /* SRAM3_BASE */ #define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) +#if defined (SRAM5_BASE) +#define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos) +#define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos) +#endif /* SRAM5_BASE */ /* GTZC2 */ #define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) @@ -366,17 +451,17 @@ typedef struct /* user-oriented definitions for MPCBB */ #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ -#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) -#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) +#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U) +#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U) -#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) -#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) -#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) -#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) +#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) +#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) +#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) +#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ -#define GTZC_MCPBB_LOCK_OFF (0U) -#define GTZC_MCPBB_LOCK_ON (1U) +#define GTZC_MPCBB_LOCK_OFF (0U) +#define GTZC_MPCBB_LOCK_ON (1U) /** * @} @@ -482,7 +567,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * @} */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup GTZC_Exported_Functions_Group2 * @brief MPCWM Initialization and Configuration functions @@ -490,7 +575,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, */ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc); + const MPCWM_ConfigTypeDef *pMPCWM_Desc); HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc); /** @@ -503,45 +588,45 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd */ void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); -uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance); +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); /** * @} */ -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @addtogroup GTZC_Exported_Functions_Group4 * @brief MPCBB Initialization and Configuration functions * @{ */ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, - MPCBB_ConfigTypeDef *pMPCBB_desc); + const MPCBB_ConfigTypeDef *pMPCBB_desc); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, MPCBB_ConfigTypeDef *pMPCBB_desc); HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, - uint32_t *pMemAttributes); + const uint32_t *pMemAttributes); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, uint32_t *pMemAttributes); -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, - uint32_t *pLockAttributes); + const uint32_t *pLockAttributes); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, uint32_t *pLockAttributes); HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, uint32_t *pLockState); -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup GTZC_Exported_Functions_Group5 * @brief TZIC functions @@ -569,7 +654,7 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); * @} */ -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h index 04478e7be4..cbc876b222 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -628,3 +628,4 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, #endif /* STM32U5xx_HAL_HASH_H */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h index 170d085aba..66b46107d2 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -173,3 +173,4 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 #endif /* STM32U5xx_HAL_HASH_EX_H */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h index 055e368631..7ebaa0c10b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -814,8 +814,8 @@ uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ - (~I2C_CR2_RD_WRN))) + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h index a07779e1e2..9ad1581afb 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h index 823ef792d3..fcaa3aea93 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h index 8d94c4b245..d90709b5fa 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -243,6 +243,7 @@ typedef struct This parameter can be any value between 0 and 0xFFFF */ } OSPI_MemoryMappedTypeDef; +#if defined (OCTOSPIM) /** * @brief HAL OSPI IO Manager Configuration structure definition */ @@ -262,6 +263,7 @@ typedef struct if some signals are multiplexed in the OSPI IO Manager with the other OSPI. This parameter can be a value between 1 and 256 */ } OSPIM_CfgTypeDef; +#endif /*(OCTOSPIM)*/ #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /** @@ -338,7 +340,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @{ */ #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ -#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ +#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DMM) /*!< Dual-Quad mode enabled */ /** * @} */ @@ -427,7 +429,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @{ */ #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ -#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ +#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_MSEL) /*!< FLASH 2 selected */ /** * @} */ @@ -654,6 +656,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @} */ +#if defined (OCTOSPIM) /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port * @{ */ @@ -677,6 +680,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** * @} */ +#endif /*(OCTOSPIM)*/ /** * @} */ @@ -749,7 +753,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR,(__INTERRUPT__)) \ +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ == (__INTERRUPT__)) /** @@ -865,15 +869,16 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi); HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold); -uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi); +uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi); HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout); -uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi); -uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi); +uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi); +uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); /** * @} */ +#if defined (OCTOSPIM) /* OSPI IO Manager configuration function ************************************/ /** @addtogroup OSPI_Exported_Functions_Group4 * @{ @@ -884,13 +889,14 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD * @} */ +#endif /*(OCTOSPIM)*/ /* OSPI Delay Block function ************************************/ /** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function * @{ */ HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); -HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); +HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); /** @@ -899,11 +905,6 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H /** * @} */ - -/** - * @} - */ - /* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -1048,6 +1049,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) +#if defined(OCTOSPIM) #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) @@ -1074,6 +1076,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H #if defined (OCTOSPIM_CR_MUXEN) #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) #endif /*(OCTOSPIM_CR_MUXEN)*/ +#endif /*(OCTOSPIM)*/ /** @endcond */ @@ -1095,4 +1098,3 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H #endif #endif /* STM32U5xx_HAL_OSPI_H */ - diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h index d90d3c4cce..fc7e844f15 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -627,8 +627,8 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka); -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka); +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka); /** * @} */ @@ -652,4 +652,3 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); #endif #endif /* STM32U5xx_HAL_PKA_H */ - diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h index aef40b9c76..99450cee42 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -138,6 +138,9 @@ typedef struct #define PWR_FLAG_TEMPH (0x0CU) /*!< Temperature level flag (versus high threshold) */ #define PWR_FLAG_TEMPL (0x0DU) /*!< Temperature level flag (versus low threshold) */ #define PWR_FLAG_VBATH (0x0EU) /*!< Backup domain voltage level flag (versus high threshold) */ +#if defined (PWR_VOSR_USBBOOSTRDY) +#define PWR_FLAG_USBBOOSTRDY (0x0FU) /*!< USB EPOD booster ready flag */ +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ /** * @} */ @@ -307,6 +310,11 @@ typedef struct * @arg @ref PWR_FLAG_BOOSTRDY : EPOD booster ready flag. * Indicates that EPOD booster ready, * frequency could be higher than 50 MHz. + * @arg @ref PWR_FLAG_USBBOOSTRDY : USB EPOD booster ready flag. + * Indicates that USB EPOD booster ready, + * frequency could be higher than 50 MHz. + * This flag is available only for STM32U59xxx and STM32U5Axxx + * devices. * @arg @ref PWR_FLAG_STOPF : Stop flag. * Indicates that the device was resumed from Stop mode. * @arg @ref PWR_FLAG_SBF : Standby flag. @@ -356,8 +364,35 @@ typedef struct * Indicates that a wakeup event was received from the WKUP line 8. * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) \ - ( \ +#if defined (PWR_FLAG_USBBOOSTRDY) +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + ( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == PWR_VOSR_USBBOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#else +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + ( \ ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ @@ -380,6 +415,7 @@ typedef struct ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#endif /* defined (PWR_FLAG_USBBOOSTRDY) */ /** @brief Clear PWR flags. * @param __FLAG__ : Specifies the flag to clear. diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h index 538d76cf92..d3e3a008a3 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -103,42 +103,117 @@ typedef struct * @{ */ /* SRAM1 pages retention defines */ -#define PWR_SRAM1_PAGE1_STOP_RETENTION (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE2_STOP_RETENTION (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE3_STOP_RETENTION (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_FULL_STOP_RETENTION (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE1_STOP (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE2_STOP (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE3_STOP (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define PWR_SRAM1_PAGE4_STOP (SRAM1_ID | PAGE04_ID) /*!< SRAM1 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE5_STOP (SRAM1_ID | PAGE05_ID) /*!< SRAM1 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE6_STOP (SRAM1_ID | PAGE06_ID) /*!< SRAM1 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE7_STOP (SRAM1_ID | PAGE07_ID) /*!< SRAM1 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE8_STOP (SRAM1_ID | PAGE08_ID) /*!< SRAM1 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE9_STOP (SRAM1_ID | PAGE09_ID) /*!< SRAM1 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE10_STOP (SRAM1_ID | PAGE10_ID) /*!< SRAM1 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE11_STOP (SRAM1_ID | PAGE11_ID) /*!< SRAM1 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE12_STOP (SRAM1_ID | PAGE12_ID) /*!< SRAM1 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x0FFFU) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ /* SRAM2 pages retention defines */ -#define PWR_SRAM2_PAGE1_STOP_RETENTION (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ -#define PWR_SRAM2_PAGE2_STOP_RETENTION (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ -#define PWR_SRAM2_FULL_STOP_RETENTION (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_PAGE1_STOP (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_PAGE2_STOP (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_FULL_STOP (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ +#if defined (PWR_CR2_SRAM3PDS1) /* SRAM3 pages retention defines */ -#define PWR_SRAM3_PAGE1_STOP_RETENTION (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE2_STOP_RETENTION (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE3_STOP_RETENTION (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE4_STOP_RETENTION (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE5_STOP_RETENTION (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE6_STOP_RETENTION (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE7_STOP_RETENTION (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE8_STOP_RETENTION (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_FULL_STOP_RETENTION (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE1_STOP (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE2_STOP (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE3_STOP (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE4_STOP (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE5_STOP (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE6_STOP (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE7_STOP (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE8_STOP (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define PWR_SRAM3_PAGE9_STOP (SRAM3_ID | PAGE09_ID) /*!< SRAM3 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE10_STOP (SRAM3_ID | PAGE10_ID) /*!< SRAM3 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE11_STOP (SRAM3_ID | PAGE11_ID) /*!< SRAM3 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE12_STOP (SRAM3_ID | PAGE12_ID) /*!< SRAM3 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE13_STOP (SRAM3_ID | PAGE13_ID) /*!< SRAM3 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0x1FFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +#endif /* PWR_CR2_SRAM3PDS1 */ /* SRAM4 page retention defines */ -#define PWR_SRAM4_FULL_STOP_RETENTION (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM4_FULL_STOP (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ + +#if defined (PWR_CR4_SRAM5PDS1) +/* SRAM5 pages retention defines */ +#define PWR_SRAM5_PAGE1_STOP (SRAM5_ID | PAGE01_ID) /*!< SRAM5 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE2_STOP (SRAM5_ID | PAGE02_ID) /*!< SRAM5 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE3_STOP (SRAM5_ID | PAGE03_ID) /*!< SRAM5 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE4_STOP (SRAM5_ID | PAGE04_ID) /*!< SRAM5 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE5_STOP (SRAM5_ID | PAGE05_ID) /*!< SRAM5 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE6_STOP (SRAM5_ID | PAGE06_ID) /*!< SRAM5 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE7_STOP (SRAM5_ID | PAGE07_ID) /*!< SRAM5 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE8_STOP (SRAM5_ID | PAGE08_ID) /*!< SRAM5 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE9_STOP (SRAM5_ID | PAGE09_ID) /*!< SRAM5 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE10_STOP (SRAM5_ID | PAGE10_ID) /*!< SRAM5 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE11_STOP (SRAM5_ID | PAGE11_ID) /*!< SRAM5 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE12_STOP (SRAM5_ID | PAGE12_ID) /*!< SRAM5 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE13_STOP (SRAM5_ID | PAGE13_ID) /*!< SRAM5 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_FULL_STOP (SRAM5_ID | 0x1FFFU) /*!< SRAM5 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/* SRAM5 pages retention defines */ +#define PWR_SRAM6_PAGE1_STOP (SRAM6_ID | PAGE01_ID) /*!< SRAM6 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE2_STOP (SRAM6_ID | PAGE02_ID) /*!< SRAM6 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE3_STOP (SRAM6_ID | PAGE03_ID) /*!< SRAM6 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE4_STOP (SRAM6_ID | PAGE04_ID) /*!< SRAM6 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE5_STOP (SRAM6_ID | PAGE05_ID) /*!< SRAM6 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE6_STOP (SRAM6_ID | PAGE06_ID) /*!< SRAM6 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE7_STOP (SRAM6_ID | PAGE07_ID) /*!< SRAM6 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE8_STOP (SRAM6_ID | PAGE08_ID) /*!< SRAM6 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_FULL_STOP (SRAM6_ID | 0xFFU) /*!< SRAM6 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR5_SRAM6PDS1) */ /* Cache RAMs retention defines */ -#define PWR_ICACHE_FULL_STOP_RETENTION (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_DCACHE1_FULL_STOP_RETENTION (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_ICACHE_FULL_STOP (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_DCACHE1_FULL_STOP (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR2_DC2RAMPDS) +#define PWR_DCACHE2_FULL_STOP (DCACHE2RAM_ID | PAGE01_ID) /*!< DCACHE2 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_DMA2DRAMPDS) /* DMA2D RAM retention defines */ -#define PWR_DMA2DRAM_FULL_STOP_RETENTION (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_DMA2DRAM_FULL_STOP (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* PWR_CR2_DMA2DRAMPDS */ /* FMAC, FDCAN and USB RAMs retention defines */ -#define PWR_PERIPHRAM_FULL_STOP_RETENTION (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_PERIPHRAM_FULL_STOP (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ /* PKA32 RAM retention defines */ -#define PWR_PKA32RAM_FULL_STOP_RETENTION (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_PKA32RAM_FULL_STOP (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ + +#if defined (PWR_CR2_GPRAMPDS) +/* Graphic peripherals RAM retention defines */ +#define PWR_GRAPHICPRAM_FULL_STOP (GRAPHIPRAM_ID | PAGE01_ID) /*!< LTDC, GFXMMU retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/* DSI RAM retention defines */ +#define PWR_DSIRAM_FULL_STOP (DSIRAM_ID | PAGE01_ID) /*!< DSI RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/* JPEG RAM retention defines */ +#define PWR_JPEGRAM_FULL_STOP (JPEGRAM_ID | PAGE01_ID) /*!< JPEG RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ /** * @} */ @@ -148,9 +223,9 @@ typedef struct * the SRAM2 content is preserved based on the same defines in Stop 3 mode. * @{ */ -#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ -#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ -#define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_PAGE1_STANDBY PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_PAGE2_STANDBY PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_FULL_STANDBY (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ /** * @} */ @@ -158,10 +233,18 @@ typedef struct /** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention * @{ */ -#define PWR_SRAM1_FULL_RUN_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ -#define PWR_SRAM2_FULL_RUN_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ -#define PWR_SRAM3_FULL_RUN_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ -#define PWR_SRAM4_FULL_RUN_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ +#define PWR_SRAM1_FULL_RUN PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ +#define PWR_SRAM2_FULL_RUN PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ +#if defined (PWR_CR1_SRAM3PD) +#define PWR_SRAM3_FULL_RUN PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ +#endif /* PWR_CR1_SRAM3PD */ +#define PWR_SRAM4_FULL_RUN PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ +#if defined (PWR_CR1_SRAM5PD) +#define PWR_SRAM5_FULL_RUN PWR_CR1_SRAM5PD /*!< SRAM5 full retention in Run mode */ +#endif /* defined (PWR_CR1_SRAM5PD) */ +#if defined (PWR_CR1_SRAM6PD) +#define PWR_SRAM6_FULL_RUN PWR_CR1_SRAM6PD /*!< SRAM6 full retention in Run mode */ +#endif /* defined (PWR_CR1_SRAM6PD) */ /** * @} */ @@ -195,15 +278,6 @@ typedef struct * @} */ -/** @defgroup PWREx_VBAT_Battery_Charging_State PWR Extended Battery Charging State - * @{ - */ -#define PWR_BATTERY_CHARGING_DISABLE (0U) /*!< Disable battery charging */ -#define PWR_BATTERY_CHARGING_ENABLE PWR_BDCR2_VBE /*!< Enable battery charging */ -/** - * @} - */ - /** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port * @{ */ @@ -212,10 +286,17 @@ typedef struct #define PWR_GPIO_C (0x02U) /*!< GPIO port C */ #define PWR_GPIO_D (0x03U) /*!< GPIO port D */ #define PWR_GPIO_E (0x04U) /*!< GPIO port E */ +#if defined (PWR_PUCRF_PU0) #define PWR_GPIO_F (0x05U) /*!< GPIO port F */ +#endif /* PWR_PUCRF_PU0 */ #define PWR_GPIO_G (0x06U) /*!< GPIO port G */ #define PWR_GPIO_H (0x07U) /*!< GPIO port H */ +#if defined (PWR_PUCRI_PU0) #define PWR_GPIO_I (0x08U) /*!< GPIO port I */ +#endif /* PWR_PUCRI_PU0 */ +#if defined (PWR_PUCRJ_PU0) +#define PWR_GPIO_J (0x09U) /*!< GPIO port J */ +#endif /* defined (PWR_PUCRJ_PU0) */ /** * @} */ @@ -674,13 +755,35 @@ typedef struct #define SRAM_ID_MASK (0xFFFFUL << 16U) #define SRAM1_ID (0x01UL << 16U) #define SRAM2_ID (0x01UL << 17U) +#if defined (PWR_CR2_SRAM3PDS1) #define SRAM3_ID (0x01UL << 18U) +#endif /* PWR_CR2_SRAM3PDS1 */ #define SRAM4_ID (0x01UL << 19U) #define ICACHERAM_ID (0x01UL << 20U) #define DCACHE1RAM_ID (0x01UL << 21U) +#if defined (PWR_CR2_DMA2DRAMPDS) #define DMA2DRAM_ID (0x01UL << 22U) +#endif /* PWR_CR2_DMA2DRAMPDS */ #define PERIPHRAM_ID (0x01UL << 23U) #define PKARAM_ID (0x01UL << 24U) +#if defined (PWR_CR2_DC2RAMPDS) +#define DCACHE2RAM_ID (0x01UL << 25U) +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_GPRAMPDS) +#define GRAPHIPRAM_ID (0x01UL << 26U) +#endif /* defined (PWR_CR2_GPRAMPDS) */ +#if defined (PWR_CR2_DSIRAMPDS) +#define DSIRAM_ID (0x01UL << 27U) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ +#if defined (PWR_CR4_SRAM5PDS1) +#define SRAM5_ID (0x01UL << 28U) +#endif /* defined (PWR_CR4_SRAM5PDS1) */ +#if defined (PWR_CR5_SRAM6PDS1) +#define SRAM6_ID (0x01UL << 29U) +#endif /* defined (PWR_CR5_SRAM6PDS1) */ +#if defined (PWR_CR2_JPEGRAMPDS) +#define JPEGRAM_ID (0x01UL << 30U) +#endif /* defined (PWR_CR2_JPEGRAMPDS)*/ /* SRAM page retention IDs */ #define PAGE01_ID (0x01UL << 0U) @@ -698,8 +801,21 @@ typedef struct #define PAGE13_ID (0x01UL << 12U) /* All available RAM retention in Run mode define */ -#define PWR_ALL_RAM_RUN_RETENTION_MASK (PWR_SRAM1_FULL_RUN_RETENTION | PWR_SRAM2_FULL_RUN_RETENTION | \ - PWR_SRAM3_FULL_RUN_RETENTION | PWR_SRAM4_FULL_RUN_RETENTION) +#if defined (PWR_CR1_SRAM6PD) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ + PWR_SRAM5_FULL_RUN | PWR_SRAM6_FULL_RUN) +#elif defined (PWR_CR1_SRAM5PD) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ + PWR_SRAM5_FULL_RUN) +#elif defined (PWR_CR2_SRAM3PDS1) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN) +#else +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM4_FULL_RUN) +#endif /* defined (PWR_CR1_SRAM5PD) */ /** * @} */ @@ -748,13 +864,21 @@ typedef struct (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) -/* Battery charging activation check macro */ -#define IS_PWR_BATTERY_CHARGING(CHARGING) \ - (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) - /* GPIO port check macro */ -#define IS_PWR_GPIO_PORT(GPIO_PORT) \ +#if defined (PWR_PUCRJ_PU0) +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_F) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H) ||\ + ((GPIO_PORT) == PWR_GPIO_I) ||\ + ((GPIO_PORT) == PWR_GPIO_J)) +#elif defined (PWR_PUCRF_PU0) && defined (PWR_PUCRI_PU0) +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ (((GPIO_PORT) == PWR_GPIO_A) ||\ ((GPIO_PORT) == PWR_GPIO_B) ||\ ((GPIO_PORT) == PWR_GPIO_C) ||\ @@ -764,6 +888,16 @@ typedef struct ((GPIO_PORT) == PWR_GPIO_G) ||\ ((GPIO_PORT) == PWR_GPIO_H) ||\ ((GPIO_PORT) == PWR_GPIO_I)) +#else +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#endif /* defined (PWR_PUCRJ_PU0) */ /* GPIO pin mask check macro */ #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \ @@ -771,41 +905,75 @@ typedef struct /* SRAM2 retention in Standby mode check macro */ #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \ - (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\ - ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\ - ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION)) + (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY) ||\ + ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY) ||\ + ((CONTENT) == PWR_SRAM2_FULL_STANDBY)) /* RAMs retention in Stop mode check macros */ #define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) #define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#if defined (PWR_CR2_SRAM3PDS1) #define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* PWR_CR2_SRAM3PDS1 */ #define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR4_SRAM5PDS1) +#define IS_PWR_SRAM5_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM5_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +#define IS_PWR_SRAM6_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM6_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR5_SRAM6PDS1) */ #define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) #define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_DC2RAMPDS) +#define IS_PWR_DCACHE2_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DCACHE2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_DMA2DRAMPDS) #define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* PWR_CR2_DMA2DRAMPDS */ #define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) #define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_GPRAMPDS) +#define IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_GRAPHICPRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +#define IS_PWR_DSIRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DSIRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +#define IS_PWR_JPEGRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_JPEGRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ /* RAMs retention in Run mode check macro */ #define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_RETENTION_MASK)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_MASK)) == 0U) && ((RAMCONTENT) != 0U)) /** * @} */ @@ -862,6 +1030,18 @@ void HAL_PWREx_EnableAVM1(void); void HAL_PWREx_DisableAVM1(void); void HAL_PWREx_EnableAVM2(void); void HAL_PWREx_DisableAVM2(void); +#if defined (PWR_VOSR_USBPWREN) +HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void); +void HAL_PWREx_DisableUSBHSTranceiverSupply(void); +#endif /* defined (PWR_VOSR_USBPWREN) */ +#if defined (PWR_CR1_FORCE_USBPWR) +void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void); +void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void); +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ +#if defined (PWR_VOSR_VDD11USBDIS) +void HAL_PWREx_EnableVDD11USB(void); +void HAL_PWREx_DisableVDD11USB(void); +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM); void HAL_PWREx_EnableMonitoring(void); void HAL_PWREx_DisableMonitoring(void); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h index 176ad633ba..f82be56665 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -61,21 +61,21 @@ typedef struct uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ - uint32_t PLLP; /*!< PLLP: Division factor for system clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 - odd division factors are not allowed */ + uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ + uint32_t PLLR; /*!< PLLR: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + Only division by 1 and even division factors are allowed */ uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range - This parameter must be a value of @ref RCC_PLL_VCI_Range */ + This parameter must be a value of @ref RCC_PLL_VCI_Range */ uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for - PLL1 VCO It should be a value between 0 and 32767 */ + PLL1 VCO It should be a value between 0 and 8191 */ } RCC_PLLInitTypeDef; @@ -116,7 +116,7 @@ typedef struct This parameter can be a value of @ref RCC_MSI_Clock_Range */ uint32_t MSIKClockRange; /*!< The MSIK frequency range. - This parameter can be a value of @ref RCC_MSIk_Clock_Range */ + This parameter can be a value of @ref RCC_MSIK_Clock_Range */ uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ @@ -324,12 +324,16 @@ typedef struct * @} */ + + + /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output * @{ */ #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN + /** * @} */ @@ -366,6 +370,7 @@ typedef struct #define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) + /** * @} */ @@ -395,26 +400,26 @@ typedef struct * @} */ -/** @defgroup RCC_MSIk_Clock_Range MSIK Clock Range +/** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range * @{ */ -#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIk = 48 MHz */ -#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIk = 24 MHz */ -#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIk = 16 MHz */ -#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIk = 12 MHz */ -#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIk = 4 MHz */ -#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 2 MHz */ -#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1.33 MHz */ -#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1 MHz */ -#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIk = 3.072 MHz */ -#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.536 MHz */ -#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.024 MHz */ -#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 768 KHz */ -#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 400 KHz */ -#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 200 KHz */ -#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 133 KHz */ +#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ +#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ +#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ +#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ +#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ +#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ +#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */ +#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ +#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ +#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ +#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ +#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ +#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ +#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ +#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */ #define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ - RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 100 KHz */ + RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ /** * @} */ @@ -575,7 +580,6 @@ typedef struct #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ - /* Flags in the CSR register */ #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ @@ -634,12 +638,12 @@ typedef struct #define RCC_PLL1 RCC_SECCFGR_PLL1SEC #define RCC_PLL2 RCC_SECCFGR_PLL2SEC #define RCC_PLL3 RCC_SECCFGR_PLL3SEC -#define RCC_CLK48M RCC_SECCFGR_CLK48MSEC +#define RCC_ICLK RCC_SECCFGR_ICLKSEC #define RCC_HSI48 RCC_SECCFGR_HSI48SEC #define RCC_RMVF RCC_SECCFGR_RMVFSEC #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ - RCC_PLL3|RCC_CLK48M|RCC_RMVF) + RCC_PLL3|RCC_ICLK|RCC_RMVF) /** * @} */ @@ -674,49 +678,60 @@ typedef struct #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ UNUSED(tmpreg); \ } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ UNUSED(tmpreg); \ } while(0) @@ -724,23 +739,55 @@ typedef struct #define __HAL_RCC_MDF1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ UNUSED(tmpreg); \ } while(0) @@ -748,7 +795,7 @@ typedef struct #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ UNUSED(tmpreg); \ } while(0) @@ -756,7 +803,7 @@ typedef struct #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ UNUSED(tmpreg); \ } while(0) @@ -764,12 +811,12 @@ typedef struct #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) +#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) @@ -781,11 +828,29 @@ typedef struct #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) +#endif /* JPEG */ + #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) @@ -808,7 +873,7 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ UNUSED(tmpreg); \ } while(0) @@ -816,7 +881,7 @@ typedef struct #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ UNUSED(tmpreg); \ } while(0) @@ -824,7 +889,7 @@ typedef struct #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ UNUSED(tmpreg); \ } while(0) @@ -832,7 +897,7 @@ typedef struct #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ UNUSED(tmpreg); \ } while(0) @@ -840,23 +905,25 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ UNUSED(tmpreg); \ } while(0) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ UNUSED(tmpreg); \ } while(0) @@ -864,48 +931,84 @@ typedef struct #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ UNUSED(tmpreg); \ } while(0) +#if defined (GPIOI) #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ - UNUSED(tmpreg); \ - } while(0) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ + UNUSED(tmpreg); \ + } while(0) + +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ UNUSED(tmpreg); \ } while(0) +#if defined (USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_OTG_HS */ +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ UNUSED(tmpreg); \ } while(0) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */ +#endif /* defined (USB_OTG_FS) */ + +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ + #if defined(AES) #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ UNUSED(tmpreg); \ } while(0) @@ -915,7 +1018,7 @@ typedef struct #define __HAL_RCC_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ UNUSED(tmpreg); \ } while(0) @@ -924,106 +1027,123 @@ typedef struct #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ UNUSED(tmpreg); \ } while(0) +#if defined(PKA) #define __HAL_RCC_PKA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* PKA */ +#if defined(SAES) #define __HAL_RCC_SAES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ UNUSED(tmpreg); \ } while(0) - +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OCTOSPI2 */ #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) @@ -1035,19 +1155,38 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) +#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN) +#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ #if defined(AES) #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) @@ -1059,29 +1198,89 @@ typedef struct #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) +#if defined(PKA) #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) +#endif /* PKA */ +#if defined(SAES) #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) +#endif /* SRAM3_BASE */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM5_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) +#endif /* SRAM5_BASE */ /** * @} */ @@ -1103,55 +1302,55 @@ typedef struct #define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); -#define __HAL_RCC_AHB1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_AHB3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_AHB1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_AHB3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ + UNUSED(tmpreg); \ + } while(0) /** * @} @@ -1164,10 +1363,11 @@ typedef struct * using it. * @{ */ + #define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1175,7 +1375,7 @@ typedef struct #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ UNUSED(tmpreg); \ } while(0) @@ -1183,7 +1383,7 @@ typedef struct #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1191,7 +1391,7 @@ typedef struct #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1199,7 +1399,7 @@ typedef struct #define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1207,7 +1407,7 @@ typedef struct #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1215,7 +1415,7 @@ typedef struct #define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ UNUSED(tmpreg); \ } while(0) @@ -1223,7 +1423,7 @@ typedef struct #define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1243,6 +1443,7 @@ typedef struct #define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) #define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) + /** * @} */ @@ -1254,10 +1455,11 @@ typedef struct * using it. * @{ */ + #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ UNUSED(tmpreg); \ } while(0) @@ -1265,7 +1467,7 @@ typedef struct #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1273,7 +1475,7 @@ typedef struct #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1281,7 +1483,7 @@ typedef struct #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ UNUSED(tmpreg); \ } while(0) @@ -1289,7 +1491,7 @@ typedef struct #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ UNUSED(tmpreg); \ } while(0) @@ -1297,7 +1499,7 @@ typedef struct #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0) @@ -1305,7 +1507,7 @@ typedef struct #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0) @@ -1313,23 +1515,25 @@ typedef struct #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1337,7 +1541,7 @@ typedef struct #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1345,7 +1549,7 @@ typedef struct #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ UNUSED(tmpreg); \ } while(0) @@ -1353,7 +1557,7 @@ typedef struct #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1361,7 +1565,7 @@ typedef struct #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ UNUSED(tmpreg); \ } while(0) @@ -1369,52 +1573,77 @@ typedef struct #define __HAL_RCC_CRS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* USART6 */ -#define __HAL_RCC_DTS_CLK_ENABLE() do { \ +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* UCPD1 */ -#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) @@ -1426,11 +1655,11 @@ typedef struct #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) -#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) - #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) @@ -1444,15 +1673,28 @@ typedef struct #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) -#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) +#endif /* USART6 */ -#define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2 , RCC_APB1ENR2_DTSEN) +#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) +#endif /* UCPD1 */ + /** * @} */ @@ -1464,78 +1706,120 @@ typedef struct * using it. * @{ */ -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined (SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DSI */ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1553,7 +1837,26 @@ typedef struct #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) +#if defined (SAI2) #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) +#endif /* DSI */ + /** * @} */ @@ -1568,7 +1871,7 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ UNUSED(tmpreg); \ } while(0) @@ -1576,7 +1879,7 @@ typedef struct #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1584,7 +1887,7 @@ typedef struct #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1592,7 +1895,7 @@ typedef struct #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1600,7 +1903,7 @@ typedef struct #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1608,7 +1911,7 @@ typedef struct #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1616,7 +1919,7 @@ typedef struct #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1624,7 +1927,7 @@ typedef struct #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ UNUSED(tmpreg); \ } while(0) @@ -1632,7 +1935,7 @@ typedef struct #define __HAL_RCC_COMP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ UNUSED(tmpreg); \ } while(0) @@ -1640,7 +1943,7 @@ typedef struct #define __HAL_RCC_VREF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ UNUSED(tmpreg); \ } while(0) @@ -1648,7 +1951,7 @@ typedef struct #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ UNUSED(tmpreg); \ } while(0) @@ -1697,11 +2000,29 @@ typedef struct #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) +#endif /* JPEG */ + #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) @@ -1711,7 +2032,7 @@ typedef struct #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) -#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) +#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) @@ -1723,11 +2044,29 @@ typedef struct #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) +#endif /* JPEG */ + #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) +#if defined (DMA2D) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) @@ -1757,19 +2096,34 @@ typedef struct #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) != 0U) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U) #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) @@ -1781,29 +2135,59 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) +#if defined(PKA) #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) +#endif /* PKA */ -#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) +#endif /* SDMMC2 */ -#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) +#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) -#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) +#if defined (SRAM3_BASE) +#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) +#endif /* FMC_BASE */ -#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) -#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U) +#endif /* SRAM5_BASE */ #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) @@ -1815,19 +2199,34 @@ typedef struct #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) == 0U) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U) #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) @@ -1839,29 +2238,59 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) +#if defined(PKA) #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) +#endif /* PKA */ +#if defined(SAES) #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) +#endif /* OTFDEC1 */ +#if defined (OTFDEC2) #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) +#if defined (SDMMC2) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) +#if defined (SRAM3_BASE) #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) +#endif /* SRAM3_BASE */ -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) +#endif /* FMC_BASE */ -#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) -#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) +#if defined (OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U) +#endif /* SRAM5_BASE */ /** * @} */ @@ -1904,6 +2333,7 @@ typedef struct #define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) #define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) + /** * @} */ @@ -1931,7 +2361,9 @@ typedef struct #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) +#if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) +#endif /* USART2 */ #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) @@ -1945,15 +2377,27 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U) +#endif /* USART6 */ -#define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) +#if defined (UCPD1) #define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) +#endif /* UCPD1 */ #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) @@ -1969,7 +2413,9 @@ typedef struct #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) +#if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) +#endif /* USART2 */ #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) @@ -1983,15 +2429,28 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U) +#endif /* USART6 */ -#define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) +#if defined(UCPD1) #define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) +#endif /* UCPD1 */ + /** * @} */ @@ -2003,6 +2462,7 @@ typedef struct * using it. * @{ */ + #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) @@ -2019,7 +2479,25 @@ typedef struct #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) +#if defined (SAI2) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U) +#endif /* DSI */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) @@ -2037,7 +2515,26 @@ typedef struct #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) +#if defined (SAI2) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U) +#endif /* DSI */ + /** * @} */ @@ -2102,7 +2599,7 @@ typedef struct */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) -#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) @@ -2112,15 +2609,29 @@ typedef struct #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) +#if defined(JPEG) +#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) +#endif /* GPU2D */ #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) -#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) @@ -2130,11 +2641,26 @@ typedef struct #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) +#if defined(JPEG) +#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) +#endif /* GPU2D */ + /** * @} */ @@ -2143,115 +2669,190 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() do{\ - WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ - WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ - }while(0) +#define __HAL_RCC_AHB2_FORCE_RESET() do{\ + WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ + WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ + }while(0) -#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) -#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) -#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) -#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) -#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) -#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#endif /* GPIOF */ -#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) -#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) +#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) -#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) +#endif /* GPIOJ */ -#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) +#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) -#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) -#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#endif /* USB_OTG_HS */ -#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ -#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#endif /* AES */ + +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) + +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) + +#if defined(PKA) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#endif /* SAES */ -#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#endif /* OCTOSPIM */ -#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#endif /* OTFDEC1 */ -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#endif /* OTFDEC2 */ -#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) -#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#endif /* SDMMC2 */ -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#endif /* FMC_BASE */ -#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) -#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#if defined (OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#endif /* OCTOSPI2 */ -#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) +#endif /* HSPI1 */ -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#define __HAL_RCC_AHB2_RELEASE_RESET() do{\ + WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ + WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ + }while(0) -#define __HAL_RCC_AHB2_RELEASE_RESET() do{\ - WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ - WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ - }while(0) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) -#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) -#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) -#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) -#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) -#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#endif /* GPIOF */ -#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) -#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) -#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#endif /* GPIOI */ -#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) +#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) -#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#endif /* AES */ -#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) -#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) -#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) +#if defined(PKA) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#endif /* PKA */ -#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) +#if defined(SAES) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#endif /* SAES */ -#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#endif /* OCTOSPIM */ -#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#endif /* OTFDEC1 */ -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#endif /* OTFDEC2 */ -#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) -#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#endif /* SDMMC2 */ -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#endif /* FMC_BASE */ -#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) -#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#endif /* OCTOSPI2 */ -#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) +#endif /* HSPI1 */ -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) /** * @} */ @@ -2283,13 +2884,16 @@ typedef struct #define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) + /** * @} */ + /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ + #define __HAL_RCC_APB1_FORCE_RESET() do { \ WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ @@ -2309,7 +2913,9 @@ typedef struct #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#if defined (USART2) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif /* USART2 */ #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) @@ -2323,13 +2929,27 @@ typedef struct #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) +#if defined(USART6) +#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) +#if defined(UCPD1) #define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#endif /* UCPD1 */ #define __HAL_RCC_APB1_RELEASE_RESET() do { \ WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ @@ -2350,7 +2970,9 @@ typedef struct #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#if defined(USART2) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif /* USART2 */ #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) @@ -2364,13 +2986,28 @@ typedef struct #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) +#if defined(USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) +#if defined(UCPD1) #define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#endif /* UCPD1 */ + /** * @} */ @@ -2397,7 +3034,25 @@ typedef struct #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) +#endif /* DSI */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) @@ -2417,7 +3072,26 @@ typedef struct #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) +#endif /* DSI */ + /** * @} */ @@ -2469,6 +3143,7 @@ typedef struct #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) + /** * @} */ @@ -2494,11 +3169,29 @@ typedef struct #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) +#endif /* JPEG */ + #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) @@ -2522,11 +3215,29 @@ typedef struct #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) +#endif /* JPEG */ + #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) @@ -2534,9 +3245,10 @@ typedef struct #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) -#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) +#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + /** * @} */ @@ -2560,22 +3272,41 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) +#define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) +#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ #if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) #endif /* AES */ #if defined(HASH) @@ -2584,29 +3315,59 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) +#if defined(PKA) #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) +#endif /* PKA */ +#if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) +#endif /* HSPI1 */ + +#if defined(SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) +#endif /* SRAM6_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) +#endif /* SRAM5_BASE */ #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) @@ -2618,22 +3379,41 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) +#define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) +#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ #if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) #endif /* AES */ #if defined(HASH) @@ -2642,29 +3422,60 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) +#if defined(PKA) #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) +#endif /* PKA */ +#if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) +#endif /* HSPI1 */ + +#if defined(SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) +#endif /* SRAM6_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) +#endif /* SRAM5_BASE */ + /** * @} */ @@ -2678,7 +3489,7 @@ typedef struct * is enabled only when a peripheral requests AHB clock. * @{ */ -#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) +#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) @@ -2686,7 +3497,7 @@ typedef struct #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) -#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) +#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) @@ -2694,7 +3505,7 @@ typedef struct #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) -#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) +#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) @@ -2702,13 +3513,14 @@ typedef struct #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) -#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) +#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) + /** * @} */ @@ -2738,7 +3550,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) @@ -2752,13 +3566,27 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) +#endif /* UCPD1 */ #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) @@ -2776,7 +3604,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) @@ -2790,13 +3620,28 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) +#endif /* UCPD1 */ + /** * @} */ @@ -2826,7 +3671,25 @@ typedef struct #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) +#endif /* DSI */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) @@ -2844,7 +3707,25 @@ typedef struct #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) +#endif /* DSI */ /** * @} @@ -2902,6 +3783,7 @@ typedef struct #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) + /** * @} */ @@ -2942,7 +3824,6 @@ typedef struct #define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) - #define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) #define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) @@ -2974,10 +3855,12 @@ typedef struct #define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) #define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) + /** * @} */ + /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset * @{ */ @@ -3047,7 +3930,6 @@ typedef struct #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) - /** * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. @@ -3131,6 +4013,7 @@ typedef struct SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ } while(0) + /** * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode * @note After restart from Reset , the MSIK clock is around 4 MHz. @@ -3185,14 +4068,15 @@ typedef struct #define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) #define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) + /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode - * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). + * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). * @param __MSIRANGEVALUE__: specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz * @retval None @@ -3204,21 +4088,22 @@ typedef struct } while(0) /** * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode - * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). + * @param __MSIKRANGEVALUE__: specifies the MSIK clock range. * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz + * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz * @retval None */ -#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ - (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ - RCC_CSR_MSISSRANGE_Pos));\ - } while(0) +#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) \ + do { \ + SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ + MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, \ + (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)); \ + } while(0) /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode * @retval MSI clock range. @@ -3326,6 +4211,7 @@ typedef struct { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ } \ } while(0) @@ -3340,7 +4226,6 @@ typedef struct #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) - /** @brief Macro to set Low-speed clock (LSI) divider. * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. @@ -3377,26 +4262,37 @@ typedef struct * is stable and can be used to clock the RTC. * @param __STATE__: specifies the new state of the LSE. * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. + * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral * @retval None */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ - if((__STATE__) == RCC_LSE_ON) \ + if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ { \ SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ + else if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ else \ { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) @@ -3516,9 +4412,9 @@ typedef struct * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 * @retval None */ -#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) +#define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) -#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) +#define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) /** * @brief Macro to configure the main PLL clock source, multiplication and division factors. @@ -3545,15 +4441,15 @@ typedef struct * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. * - * @param __PLL1P__: specifies the division factor for system clock. - * This parameter must be a number between 2 and 128 (where odd numbers not allowed) - * - * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks + * @param __PLL1P__: specifies the division factor for peripheral kernel clocks. * This parameter must be a number between 1 and 128 * - * @param __PLL1R__: specifies the division factor for peripheral kernel clocks + * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks. * This parameter must be a number between 1 and 128 * + * @param __PLL1R__: specifies the division factor for system clock. + * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed) + * * @retval None */ #define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ @@ -3591,7 +4487,7 @@ typedef struct * 150 to 420 MHz if PLL1VCOSEL = 1. * @retval None */ -#define __HAL_RCC_PLLFRACN_CONFIG(__PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN,\ +#define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ (uint32_t)(__PLL1FRACN__) << \ RCC_PLL1FRACR_PLL1FRACN_Pos) @@ -3688,7 +4584,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -3821,7 +4717,6 @@ typedef struct */ #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ ((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_NONE) || \ ((SOURCE) == RCC_PLLSOURCE_HSE)) #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) @@ -3873,6 +4768,13 @@ typedef struct ((__RANGE__) == RCC_MSIKRANGE_13) || \ ((__RANGE__) == RCC_MSIKRANGE_14) || \ ((__RANGE__) == RCC_MSIKRANGE_15)) + +#define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \ + ((__RANGE__) == RCC_MSIKRANGE_5) || \ + ((__RANGE__) == RCC_MSIKRANGE_6) || \ + ((__RANGE__) == RCC_MSIKRANGE_7) || \ + ((__RANGE__) == RCC_MSIKRANGE_8)) + /** * @} */ @@ -3891,7 +4793,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); /** diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h index db52909360..1498a1289e 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -47,7 +47,7 @@ extern "C" { typedef struct { uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ @@ -56,23 +56,22 @@ typedef struct This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 - odd division factors are not allowed */ + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - uint32_t PLL2RGE; /*!PLL3CFGR, (__PLL3_CLOCKOUT__)) -/** @brief Macro to configure the ADC1, ADC4 and DAC interface clock. +/** @brief Macro to configure the ADC1, ADC2, ADC4 and DAC interface clock. * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source. * This parameter can be one of the following values: - * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC2 ADC4 and DAC clock * @retval None */ #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ @@ -1187,12 +1431,12 @@ typedef struct /** @brief Macro to get the ADCDAC clock source. * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC2, ADC4 and DAC clock */ #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL))) @@ -1205,7 +1449,7 @@ typedef struct * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source */ #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__CLK48_SOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, (uint32_t)(__CLK48_SOURCE__)) /** @brief macro to get the CLK48 source. * @retval The clock source can be one of the following values: @@ -1214,7 +1458,7 @@ typedef struct * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source */ -#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) +#define __HAL_RCC_GET_ICLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL))) /** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. @@ -1442,6 +1686,54 @@ typedef struct */ #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL))) +#if defined(I2C5) +/** @brief Macro to configure the I2C5 clock (I2C5CLK). + * + * @param __I2C5_CLKSOURCE__ specifies the I2C5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock + * @retval None + */ +#define __HAL_RCC_I2C5_CONFIG(__I2C5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL, (uint32_t)(__I2C5_CLKSOURCE__)) + +/** @brief Macro to get the I2C5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock + */ +#define __HAL_RCC_GET_I2C5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL))) +#endif /* I2C5 */ + +#if defined(I2C6) +/** @brief Macro to configure the I2C6 clock (I2C6CLK). + * + * @param __I2C6_CLKSOURCE__ specifies the I2C6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock + * @retval None + */ +#define __HAL_RCC_I2C6_CONFIG(__I2C6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL, (uint32_t)(__I2C6_CLKSOURCE__)) + +/** @brief Macro to get the I2C6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock + */ +#define __HAL_RCC_GET_I2C6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL))) +#endif /* I2C6 */ + /** @brief Macro to configure the USART1 clock (USART1CLK). * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. * This parameter can be one of the following values: @@ -1463,6 +1755,7 @@ typedef struct */ #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) +#if defined(USART2) /** @brief Macro to configure the USART2 clock (USART2CLK). * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. * This parameter can be one of the following values: @@ -1483,6 +1776,7 @@ typedef struct * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) +#endif /* USART2 */ /** @brief Macro to configure the USART3 clock (USART3CLK). * @@ -1549,6 +1843,30 @@ typedef struct */ #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) +#if defined(USART6) +/** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * @retval None + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief Macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART6SEL))) +#endif /* USART6 */ + /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). * * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. @@ -1573,7 +1891,6 @@ typedef struct */ #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) - /** @brief Macro to configure the OctoSPI clock. * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. * This parameter can be one of the following values: @@ -1595,6 +1912,29 @@ typedef struct */ #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL))) +#if defined(HSPI1) +/** @brief Macro to configure the HexaSPI clock. + * @param __HSPI_CLKSOURCE__ specifies the HexaSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock + * @retval None + */ +#define __HAL_RCC_HSPI_CONFIG(__HSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, (uint32_t)(__HSPI_CLKSOURCE__)) + +/** @brief Macro to get the HexaSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock + */ +#define __HAL_RCC_GET_HSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_HSPISEL))) +#endif /* HSPI1 */ + /** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK). * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source. * This parameter can be one of the following values: @@ -1629,6 +1969,7 @@ typedef struct */ #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL))) +#if defined(SAES) /** @brief macro to configure the SAES clock (SAESCLK). * @param __SAES_CLKSource__: specifies the SAES clock source. * This parameter can be one of the following values: @@ -1644,6 +1985,7 @@ typedef struct * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock */ #define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL))) +#endif /* SAES */ /** * @brief Macro to configure the SAI1 clock source. @@ -1674,6 +2016,7 @@ typedef struct */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) +#if defined(SAI2) /** * @brief Macro to configure the SAI2 clock source. * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived @@ -1698,6 +2041,7 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) +#endif /* SAI2 */ /** @brief Macro to configure the MDF1 clock. * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. @@ -1762,6 +2106,101 @@ typedef struct */ #define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL))) +#if defined(LTDC) + +/** @brief Macro to configure the LTDC clock. + * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock + * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock + * @retval None + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, (__LTDC_CLKSOURCE__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock + * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL)) + +#endif /* LTDC */ + +#if defined(DSI) + +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) + * @retval None + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, (__DSI_CLKSOURCE__)) + +/** @brief Macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL)) + +#endif /* DSI */ + +#if defined(USB_OTG_HS) + +/** @brief Macro to configure the USB PHY clock. + * @param __USBPHY_CLKSOURCE__ specifies the USB PHY clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock + * @retval None + */ +#define __HAL_RCC_USBPHY_CONFIG(__USBPHY_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, (__USBPHY_CLKSOURCE__)) + +/** @brief Macro to get the USB PHY clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock + */ +#define __HAL_RCC_GET_USBPHY_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL)) + +#endif /* USB_OTG_HS */ + +#if defined(RCC_CFGR2_PPRE_DPHY) + +/** @brief Macro to configure the DPHY clock. + * @param __PRESCALER__ specifies the DPHY clock source prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock + * @retval None + */ +#define __HAL_RCC_DPHY_CONFIG(__PRESCALER__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, (__PRESCALER__) << 8UL) + +/** @brief Macro to get the DPHY clock prescaler configuration. + * @retval The clock source prescaler can be one of the following values: + * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock + * @retval None + */ +#define __HAL_RCC_GET_DPHY_CONFIG() (READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY) >> 8UL) + +#endif /* defined(RCC_CFGR2_PPRE_DPHY) */ + #if defined(CRS) /** @@ -1930,12 +2369,12 @@ typedef struct * @{ */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); -void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); -void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); /** * @} */ @@ -1944,9 +2383,9 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); * @{ */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); -HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init); +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void); HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void); @@ -1954,15 +2393,19 @@ HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelecti void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); +void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange); void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void); void HAL_RCCEx_LSECSS_IRQHandler(void); void HAL_RCCEx_LSECSS_Callback(void); +void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void); +void HAL_RCCEx_MSIPLLUNLCK_Callback(void); void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); void HAL_RCCEx_DisableLSCO(void); void HAL_RCCEx_EnableMSIPLLMode(void); void HAL_RCCEx_DisableMSIPLLMode(void); - /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h index df9b0d42d2..49dca859a6 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -331,8 +331,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ @@ -387,3 +387,4 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif /* STM32U5xx_HAL_RNG_H */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h index c261ecd99f..ca8bae8c67 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -35,19 +35,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNGEx RNGEx +/** @defgroup RNG_Ex RNG_Ex * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Types RNGEx Exported Types - * @brief RNGEx Exported types +/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types + * @brief RNG_Ex Exported types * @{ */ /** - * @brief RNGEX Configuration Structure definition + * @brief RNG_Ex Configuration Structure definition */ typedef struct @@ -56,11 +56,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNGEX_Clock_Divider_Factor */ + be a value of @ref RNG_Ex_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNGEX_NIST_Compliance */ + value of @ref RNG_Ex_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNGEX_Auto_Reset */ + value of @ref RNG_Ex_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ } RNG_ConfigTypeDef; @@ -70,11 +70,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants +/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants * @{ */ -/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -113,7 +113,7 @@ typedef struct * @} */ -/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration +/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -122,7 +122,7 @@ typedef struct /** * @} */ -/** @defgroup RNGEX_Auto_Reset Auto Reset configuration +/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -137,7 +137,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Types RNGEx Private Types +/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types * @{ */ @@ -146,7 +146,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Variables RNGEx Private Variables +/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables * @{ */ @@ -155,7 +155,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants * @{ */ @@ -164,7 +164,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Macros RNGEx Private Macros +/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros * @{ */ @@ -203,7 +203,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Functions RNGEx Private Functions +/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions * @{ */ @@ -212,14 +212,14 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions +/** @addtogroup RNG_Ex_Exported_Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @addtogroup RNG_Ex_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); @@ -227,7 +227,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @addtogroup RNG_Ex_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); @@ -260,4 +260,5 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif -#endif /* STM32U5xx_HAL_RNGEX_H */ +#endif /* STM32U5xx_HAL_RNG_EX_H */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h index 01f4c82c17..902b9e3867 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -289,7 +289,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 0x00000000u +#define RTC_HOURFORMAT_24 0U #define RTC_HOURFORMAT_12 RTC_CR_FMT /** * @} @@ -298,7 +298,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition * @{ */ -#define RTC_OUTPUT_DISABLE 0x00000000u +#define RTC_OUTPUT_DISABLE 0U #define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 #define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 #define RTC_OUTPUT_WAKEUP RTC_CR_OSEL @@ -310,7 +310,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u +#define RTC_OUTPUT_POLARITY_HIGH 0U #define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} @@ -319,7 +319,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u +#define RTC_OUTPUT_TYPE_PUSHPULL 0U #define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /** * @} @@ -328,7 +328,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT * @{ */ -#define RTC_OUTPUT_PULLUP_NONE 0x00000000u +#define RTC_OUTPUT_PULLUP_NONE 0U #define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU /** * @} @@ -337,7 +337,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_NONE 0U #define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN /** * @} @@ -346,8 +346,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM 0x0u -#define RTC_HOURFORMAT12_PM 0x1u +#define RTC_HOURFORMAT12_AM 0U +#define RTC_HOURFORMAT12_PM 1U /** * @} */ @@ -357,7 +357,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H #define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H -#define RTC_DAYLIGHTSAVING_NONE 0x00000000u +#define RTC_DAYLIGHTSAVING_NONE 0U /** * @} */ @@ -365,7 +365,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET 0x00000000u +#define RTC_STOREOPERATION_RESET 0U #define RTC_STOREOPERATION_SET RTC_CR_BKP /** * @} @@ -374,8 +374,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN 0x00000000u -#define RTC_FORMAT_BCD 0x00000001u +#define RTC_FORMAT_BIN 0U +#define RTC_FORMAT_BCD 1U /** * @} */ @@ -420,7 +420,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0U #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /** @@ -430,7 +430,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE 0x00000000u +#define RTC_ALARMMASK_NONE 0U #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 @@ -454,8 +454,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions * @{ */ -#define ALARM_FLAG_AUTOCLR_ENABLE 0x00000001u -#define ALARM_FLAG_AUTOCLR_DISABLE 0x00000000u +#define ALARM_FLAG_AUTOCLR_ENABLE 1U +#define ALARM_FLAG_AUTOCLR_DISABLE 0U /** * @} */ @@ -463,7 +463,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDMASK_ALL 0U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared. */ #define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared */ #define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared */ @@ -498,7 +498,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask * @{ */ -#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask */ +#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask */ /** * @} */ @@ -661,7 +661,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /* Dummy action because is an invalid parameter value */ /** * @brief Disable the RTC Alarm interrupt. @@ -672,7 +675,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /* Dummy action because is an invalid parameter value */ /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. @@ -681,10 +687,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_IT_ALRA Alarm A interrupt * @arg @ref RTC_IT_ALRB Alarm B interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) \ - ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -693,10 +701,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_IT_ALRA Alarm A interrupt * @arg @ref RTC_IT_ALRB Alarm B interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) \ - ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\ + (0U)) /* Return 0 because it is an invalid parameter value */ /** * @brief Get the selected RTC Alarms flag status. @@ -705,9 +715,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_FLAG_ALRAF * @arg @ref RTC_FLAG_ALRBF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ /** * @brief Clear the RTC Alarms pending flags. @@ -718,9 +731,17 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) \ - ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) :\ - (RTC->SCR = (RTC_CLEAR_ALRBF))) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRAF)):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRBF)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Check whether if the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval The state of RTC Calendar initialization (TRUE or FALSE). + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) /** * @} @@ -760,14 +781,14 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -779,10 +800,10 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); /** * @} @@ -801,7 +822,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -823,10 +844,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ RTC_DR_DU) -#define RTC_INIT_MASK 0xFFFFFFFFu +#define RTC_INIT_MASK 0xFFFFFFFFU #define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) -#define RTC_TIMEOUT_VALUE 1000u +#define RTC_TIMEOUT_VALUE 1000U /** * @} @@ -874,11 +895,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u)) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -888,7 +909,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -916,13 +937,13 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u)) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h index e46318e350..61e1e37e92 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -132,7 +132,7 @@ typedef struct uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32]; /*!< Specifies the RNG Seed value. - This parameter is an array of value from 0 to 0xFFFFFFFF. */ + This parameter is an array of value from 0 to 0xFFFFFFFF */ RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB]; /*!< Specifies configuration of all active tampers. @@ -172,12 +172,12 @@ typedef struct uint32_t rtcNonSecureFeatures; /*!< Specifies the non-secure features. This parameter is only relevant if RTC is not fully secure - (rtcSecureFull == RTC_SECURE_FULL_NO). + (rtcSecureFull == RTC_SECURE_FULL_NO). This parameter can be a combination of @ref RTCEx_RTC_NonSecure_Features. */ uint32_t tampSecureFull; /*!< Specifies If the TAMP is fully secure or not execpt monotonic counters - and BackUp registers. + and BackUp registers. This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */ uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2 @@ -195,7 +195,7 @@ typedef struct uint32_t MonotonicCounterSecure; /*!< Specifies If the monotonic counter is secure or not This parameter can be a value of - @ref RTCEx_TAMP_Monotonic_Counter_Secure */ + @ref RTCEx_TAMP_Monotonic_Counter_Secure */ } RTC_SecureStateTypeDef; /** * @} @@ -226,8 +226,8 @@ typedef struct disabled. */ uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2. - Zone 1 : read secure write secure. - Zone 2 : read non-secure write secure. + Zone 1 granted accesses : read secure, write secure. + Zone 2 granted accesses : read non-secure, write secure. This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register . Warning : this parameter is writable in secure mode or if trustzone is @@ -235,7 +235,7 @@ typedef struct Warning : this parameter is shared with RTC_SecureStateTypeDef */ uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3. - Zone 3 : read non-secure write non-secure. + Zone 3 granted accesses : read non-secure, write non-secure. This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register. Warning : this parameter is writable in secure mode or if trustzone is @@ -262,8 +262,8 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING 0x00000000u -#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE +#define RTC_TIMESTAMPEDGE_RISING 0U +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} */ @@ -271,7 +271,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u +#define RTC_TIMESTAMPPIN_DEFAULT 0U /** * @} */ @@ -279,12 +279,12 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) /** * @} */ @@ -292,12 +292,12 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK pulses */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK pulses */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0U /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 8s, else 2exp18 RTCCLK pulses */ /** * @} */ @@ -305,11 +305,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0U /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ /** * @} */ @@ -317,13 +317,10 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions * @{ */ -#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre, - which is the required configuration for - ultra-low consumption mode. */ -#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK, - which is a high-consumption mode. - This mode should be set only when less - than 32s calibration window is required. */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 2exp20 ck_apre, which is the required configuration for ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0U /*!< Calibration window is 2exp20 RTCCLK, which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ /** * @} */ @@ -331,9 +328,8 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ 0x00000000u -#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL - +#define RTC_CALIBOUTPUT_512HZ 0U +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL /** * @} */ @@ -342,8 +338,8 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions * @{ */ -#define RTC_SHIFTADD1S_RESET 0x00000000u -#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +#define RTC_SHIFTADD1S_RESET 0U +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S /** * @} */ @@ -401,10 +397,10 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 1U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 2U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 3U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ /** * @} */ @@ -421,8 +417,8 @@ typedef struct /** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp * @{ */ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u -#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0U +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 1U /** * @} */ @@ -430,7 +426,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter * @{ */ -#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE 0U /*!< Tamper filter is disabled */ #define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ #define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 @@ -444,7 +440,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ @@ -460,7 +456,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ @@ -471,7 +467,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_ENABLE 0U /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ /** * @} @@ -480,7 +476,7 @@ typedef struct /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions * @{ */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0U /*!< TimeStamp on Tamper Detection event is not saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ /** * @} @@ -534,9 +530,9 @@ typedef struct #define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F #define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F #define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F -#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\ - RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\ - RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8) +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\ + RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\ + RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8) #define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F @@ -564,8 +560,8 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions * @{ */ -#define RTC_ATAMP_ENABLE 1u -#define RTC_ATAMP_DISABLE 0u +#define RTC_ATAMP_ENABLE 1U +#define RTC_ATAMP_DISABLE 0U /** * @} */ @@ -573,8 +569,8 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions * @{ */ -#define RTC_ATAMP_INTERRUPT_ENABLE 1u -#define RTC_ATAMP_INTERRUPT_DISABLE 0u +#define RTC_ATAMP_INTERRUPT_ENABLE 1U +#define RTC_ATAMP_INTERRUPT_DISABLE 0U /** * @} */ @@ -583,7 +579,7 @@ typedef struct * @{ */ #define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN -#define RTC_ATAMP_FILTER_DISABLE 0u +#define RTC_ATAMP_FILTER_DISABLE 0U /** * @} */ @@ -591,14 +587,15 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions * @{ */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ /** * @} */ @@ -606,14 +603,14 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition * @{ */ -#define RTC_ATAMP_1 0u /*!< Tamper 1 */ -#define RTC_ATAMP_2 1u /*!< Tamper 2 */ -#define RTC_ATAMP_3 2u /*!< Tamper 3 */ -#define RTC_ATAMP_4 3u /*!< Tamper 4 */ -#define RTC_ATAMP_5 4u /*!< Tamper 5 */ -#define RTC_ATAMP_6 5u /*!< Tamper 6 */ -#define RTC_ATAMP_7 6u /*!< Tamper 7 */ -#define RTC_ATAMP_8 7u /*!< Tamper 8 */ +#define RTC_ATAMP_1 0U /*!< Tamper 1 */ +#define RTC_ATAMP_2 1U /*!< Tamper 2 */ +#define RTC_ATAMP_3 2U /*!< Tamper 3 */ +#define RTC_ATAMP_4 3U /*!< Tamper 4 */ +#define RTC_ATAMP_5 4U /*!< Tamper 5 */ +#define RTC_ATAMP_6 5U /*!< Tamper 6 */ +#define RTC_ATAMP_7 6U /*!< Tamper 7 */ +#define RTC_ATAMP_8 7U /*!< Tamper 8 */ /** * @} */ @@ -621,7 +618,7 @@ typedef struct /** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition * @{ */ -#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */ +#define RTC_MONOTONIC_COUNTER_1 0U /*!< Monotonic counter 1 */ /** * @} */ @@ -629,39 +626,39 @@ typedef struct /** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition * @{ */ -#define RTC_BKP_NUMBER RTC_BKP_NB -#define RTC_BKP_DR0 0x00u -#define RTC_BKP_DR1 0x01u -#define RTC_BKP_DR2 0x02u -#define RTC_BKP_DR3 0x03u -#define RTC_BKP_DR4 0x04u -#define RTC_BKP_DR5 0x05u -#define RTC_BKP_DR6 0x06u -#define RTC_BKP_DR7 0x07u -#define RTC_BKP_DR8 0x08u -#define RTC_BKP_DR9 0x09u -#define RTC_BKP_DR10 0x0Au -#define RTC_BKP_DR11 0x0Bu -#define RTC_BKP_DR12 0x0Cu -#define RTC_BKP_DR13 0x0Du -#define RTC_BKP_DR14 0x0Eu -#define RTC_BKP_DR15 0x0Fu -#define RTC_BKP_DR16 0x10u -#define RTC_BKP_DR17 0x11u -#define RTC_BKP_DR18 0x12u -#define RTC_BKP_DR19 0x13u -#define RTC_BKP_DR20 0x14u -#define RTC_BKP_DR21 0x15u -#define RTC_BKP_DR22 0x16u -#define RTC_BKP_DR23 0x17u -#define RTC_BKP_DR24 0x18u -#define RTC_BKP_DR25 0x19u -#define RTC_BKP_DR26 0x1Au -#define RTC_BKP_DR27 0x1Bu -#define RTC_BKP_DR28 0x1Cu -#define RTC_BKP_DR29 0x1Du -#define RTC_BKP_DR30 0x1Eu -#define RTC_BKP_DR31 0x1Fu +#define RTC_BKP_NUMBER RTC_BKP_NB +#define RTC_BKP_DR0 0x00U +#define RTC_BKP_DR1 0x01U +#define RTC_BKP_DR2 0x02U +#define RTC_BKP_DR3 0x03U +#define RTC_BKP_DR4 0x04U +#define RTC_BKP_DR5 0x05U +#define RTC_BKP_DR6 0x06U +#define RTC_BKP_DR7 0x07U +#define RTC_BKP_DR8 0x08U +#define RTC_BKP_DR9 0x09U +#define RTC_BKP_DR10 0x0AU +#define RTC_BKP_DR11 0x0BU +#define RTC_BKP_DR12 0x0CU +#define RTC_BKP_DR13 0x0DU +#define RTC_BKP_DR14 0x0EU +#define RTC_BKP_DR15 0x0FU +#define RTC_BKP_DR16 0x10U +#define RTC_BKP_DR17 0x11U +#define RTC_BKP_DR18 0x12U +#define RTC_BKP_DR19 0x13U +#define RTC_BKP_DR20 0x14U +#define RTC_BKP_DR21 0x15U +#define RTC_BKP_DR22 0x16U +#define RTC_BKP_DR23 0x17U +#define RTC_BKP_DR24 0x18U +#define RTC_BKP_DR25 0x19U +#define RTC_BKP_DR26 0x1AU +#define RTC_BKP_DR27 0x1BU +#define RTC_BKP_DR28 0x1CU +#define RTC_BKP_DR29 0x1DU +#define RTC_BKP_DR30 0x1EU +#define RTC_BKP_DR31 0x1FU /** * @} */ @@ -669,25 +666,25 @@ typedef struct * Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions. * @{ */ -#define RTC_BINARY_NONE 0x00000000u /*!< Free running BCD calendar mode (Binary mode disabled). */ -#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ -#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */ +#define RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */ +#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */ /** * @} */ /** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented - * using the SSR Least Significant Bits. + * using the SSR Least Significant Bits. * @{ */ -#define RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_0 0U /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ /** * @} */ @@ -695,7 +692,7 @@ typedef struct /** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary mode Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDBINMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDBINMASK_ALL 0U /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */ #define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared. */ #define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ #define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ @@ -746,7 +743,7 @@ typedef struct * @{ */ #define RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */ -#define RTC_SECURE_FULL_NO 0u /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */ +#define RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */ /** * @} */ @@ -764,7 +761,7 @@ typedef struct #define RTC_NONSECURE_FEATURE_WUT ~RTC_SECCFGR_WUTSEC /*!< Wake up timer */ #define RTC_NONSECURE_FEATURE_ALRA ~RTC_SECCFGR_ALRASEC /*!< Alarm A */ #define RTC_NONSECURE_FEATURE_ALRB ~RTC_SECCFGR_ALRBSEC /*!< Alarm B */ -#define RTC_NONSECURE_FEATURE_ALL 0u +#define RTC_NONSECURE_FEATURE_ALL 0U /** * @} */ @@ -773,7 +770,7 @@ typedef struct * @{ */ #define TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMPER full secure */ -#define TAMP_SECURE_FULL_NO 0u /*!< TAMPER is not secure */ +#define TAMP_SECURE_FULL_NO 0U /*!< TAMPER is not secure */ /** * @} */ @@ -782,7 +779,7 @@ typedef struct * @{ */ #define TAMP_MONOTONIC_CNT_SECURE_YES TAMP_SECCFGR_CNT1SEC /*!< TAMPER Monotonic Counter secure */ -#define TAMP_MONOTONIC_CNT_SECURE_NO 0u /*!< TAMPER Monotonic Counter is not secure */ +#define TAMP_MONOTONIC_CNT_SECURE_NO 0U /*!< TAMPER Monotonic Counter is not secure */ /** * @} */ @@ -790,7 +787,7 @@ typedef struct * @{ */ #define RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV -#define RTC_PRIVILEGE_FULL_NO 0u +#define RTC_PRIVILEGE_FULL_NO 0U /** * @} */ @@ -798,7 +795,7 @@ typedef struct /** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition * @{ */ -#define RTC_PRIVILEGE_FEATURE_NONE 0u +#define RTC_PRIVILEGE_FEATURE_NONE 0U #define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization */ #define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration */ #define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp */ @@ -816,7 +813,7 @@ typedef struct * @{ */ #define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV -#define TAMP_PRIVILEGE_FULL_NO 0u +#define TAMP_PRIVILEGE_FULL_NO 0U /** * @} */ @@ -825,7 +822,7 @@ typedef struct * @{ */ #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_ERCFGR0 -#define TAMP_SECRETDEVICE_ERASE_DISABLE 0u +#define TAMP_SECRETDEVICE_ERASE_DISABLE 0U /** * @} */ @@ -834,7 +831,7 @@ typedef struct * @{ */ #define TAMP_MONOTONIC_CNT_PRIVILEGE_YES TAMP_PRIVCFGR_CNT1PRIV -#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0u +#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0U /** * @} */ @@ -842,7 +839,7 @@ typedef struct /** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition * @{ */ -#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0u +#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0U #define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV #define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV #define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2) @@ -883,24 +880,48 @@ typedef struct * @arg @ref RTC_FLAG_INITS Initialization status flag * @arg @ref RTC_FLAG_SHPF Shift operation pending flag * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag - * @arg @ref RTC_FLAG_ALRAF Alarm A write flag - * @arg @ref RTC_FLAG_ALRBF Alarm B write flag * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag * @arg @ref RTC_FLAG_TSF Time-stamp flag * @arg @ref RTC_FLAG_WUTF Wakeup timer flag * @arg @ref RTC_FLAG_ALRBF Alarm B flag * @arg @ref RTC_FLAG_ALRAF Alarm A flag - * @retval None - */ -#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR &\ - (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ - (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK)))) + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_RECALPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \ + RTC_ICSR_RECALPF) : \ + ((__FLAG__) == RTC_FLAG_INITF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \ + RTC_ICSR_INITF) : \ + ((__FLAG__) == RTC_FLAG_RSF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \ + RTC_ICSR_RSF) : \ + ((__FLAG__) == RTC_FLAG_INITS) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \ + RTC_ICSR_INITS) : \ + ((__FLAG__) == RTC_FLAG_SHPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \ + RTC_ICSR_SHPF) : \ + ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \ + RTC_ICSR_WUTWF) : \ + ((__FLAG__) == RTC_FLAG_SSRUF) ? (READ_BIT(RTC->SR, RTC_SR_SSRUF) == \ + RTC_SR_SSRUF) : \ + ((__FLAG__) == RTC_FLAG_ITSF) ? (READ_BIT(RTC->SR, RTC_SR_ITSF) == \ + RTC_SR_ITSF) : \ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == \ + RTC_SR_TSOVF) : \ + ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == \ + RTC_SR_TSF): \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == \ + RTC_SR_WUTF): \ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == \ + RTC_SR_ALRBF) : \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == \ + RTC_SR_ALRAF) : \ + (0U)) /* Return 0 because it is an invalid parameter value */ /* ---------------------------------WAKEUPTIMER---------------------------------*/ /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer * @{ */ + /** * @brief Enable the RTC WakeUp Timer peripheral. * @param __HANDLE__ specifies the RTC handle. @@ -923,7 +944,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_WUTIE)) /** * @brief Disable the RTC WakeUpTimer interrupt. @@ -933,8 +954,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) - +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_WUTIE)) /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. @@ -942,20 +962,19 @@ typedef struct * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. * This parameter can be: * @arg @ref RTC_IT_WUT WakeUpTimer interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) !=\ - 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U) + /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_WUT WakeUpTimer interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != \ - 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_WUTIE)) != 0U) /** * @brief Get the selected RTC WakeUpTimers flag status. @@ -964,9 +983,12 @@ typedef struct * This parameter can be: * @arg @ref RTC_FLAG_WUTF * @arg @ref RTC_FLAG_WUTWF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\ + ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ /** * @brief Clear the RTC Wake Up timers pending flags. @@ -976,14 +998,17 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF)) + /** * @} */ + /* ---------------------------------TIMESTAMP---------------------------------*/ /** @defgroup RTCEx_Timestamp RTC Timestamp * @{ */ + /** * @brief Enable the RTC TimeStamp peripheral. * @param __HANDLE__ specifies the RTC handle. @@ -1006,7 +1031,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_TSIE)) /** * @brief Disable the RTC TimeStamp interrupt. @@ -1016,7 +1041,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_TSIE)) /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. @@ -1024,20 +1049,19 @@ typedef struct * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. * This parameter can be: * @arg @ref RTC_IT_TS TimeStamp interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != \ - 0U) ? 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U) + /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg @ref RTC_IT_TS TimeStamp interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ?\ - 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_TSIE)) != 0U) /** * @brief Get the selected RTC TimeStamps flag status. @@ -1046,9 +1070,12 @@ typedef struct * This parameter can be: * @arg @ref RTC_FLAG_TSF * @arg @ref RTC_FLAG_TSOVF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter. */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ /** * @brief Clear the RTC Time Stamps pending flags. @@ -1059,9 +1086,10 @@ typedef struct * @arg @ref RTC_FLAG_TSOVF * @retval None */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? \ - (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \ - (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF))) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\ + (0U)) /* Dummy action because is an invalid parameter value */ /** * @brief Enable the RTC internal TimeStamp peripheral. @@ -1085,8 +1113,7 @@ typedef struct * @arg @ref RTC_FLAG_ITSF * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),\ - (__FLAG__))) +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_ITSF) == RTC_SR_ITSF)) /** * @brief Clear the RTC Internal Time Stamps pending flags. @@ -1096,8 +1123,7 @@ typedef struct * @arg @ref RTC_FLAG_ITSF * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__),\ - RTC_CLEAR_ITSF)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CITSF)) /** * @brief Enable the RTC TimeStamp on Tamper detection. @@ -1173,9 +1199,9 @@ typedef struct * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg @ref RTC_FLAG_SHPF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF)) /** * @} */ @@ -1184,6 +1210,7 @@ typedef struct /** @defgroup RTCEx_Tamper RTCEx tamper * @{ */ + /** * @brief Enable the TAMP Tamper input detection. * @param __HANDLE__ specifies the RTC handle. @@ -1219,6 +1246,7 @@ typedef struct */ #define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) + /**************************************************************************************************/ /** * @brief Enable the TAMP Tamper interrupt. @@ -1256,6 +1284,7 @@ typedef struct */ #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__)) + /**************************************************************************************************/ /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. @@ -1283,7 +1312,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE) */ #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) @@ -1313,7 +1342,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE) */ #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != \ 0U) ? 1UL : 0UL) @@ -1343,7 +1372,7 @@ typedef struct * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag * @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag * @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) */ #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U) @@ -1394,7 +1423,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_SSRUIE)) /** * @brief Disable the RTC SSRU interrupt. @@ -1404,7 +1433,8 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_SSRUIE)) + /** * @brief Check whether the specified RTC SSRU interrupt has occurred or not. @@ -1412,19 +1442,18 @@ typedef struct * @param __INTERRUPT__ specifies the RTC SSRU interrupt to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE) */ -#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) \ - ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE) */ -#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (RTC_CR_SSRUIE)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC SSRU's flag status. @@ -1432,9 +1461,9 @@ typedef struct * @param __FLAG__ specifies the RTC SSRU Flag is pending or not. * This parameter can be: * @arg @ref RTC_FLAG_SSRUF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) */ -#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) /** * @brief Clear the RTC Wake Up timer's pending flags. @@ -1444,14 +1473,15 @@ typedef struct * @arg @ref RTC_FLAG_SSRUF * @retval None */ -#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF)) - +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF)) /** * @} */ + /** * @} */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ @@ -1526,7 +1556,7 @@ void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc); */ void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} */ @@ -1658,11 +1688,11 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil ((LPCAL) == RTC_LPCAL_RESET)) -#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ - (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0U)) -#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \ - (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U)) +#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0U) && \ + (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0U)) #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ @@ -1713,7 +1743,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \ ((__STATE__) == RTC_SECURE_FULL_NO)) -#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0u) +#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0U) #define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \ ((__STATE__) == TAMP_SECURE_FULL_NO)) @@ -1724,7 +1754,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \ ((__STATE__) == RTC_PRIVILEGE_FULL_NO)) -#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0u) +#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0U) #define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \ ((__STATE__) == TAMP_PRIVILEGE_FULL_NO)) @@ -1732,7 +1762,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \ ((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO)) -#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0u) +#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0U) #define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \ ((MODE) == RTC_BINARY_ONLY) || \ @@ -1747,7 +1777,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \ ((BDCU) == RTC_BINARY_MIX_BCDU_7)) -#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \ +#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0U) || \ (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\ ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h index e30334a0b2..b78526d48e 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -123,9 +123,11 @@ typedef struct uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. This parameter can be a value of @ref UART_Overrun_Disable. */ +#if defined(HAL_DMA_MODULE_ENABLED) uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ +#endif /* HAL_DMA_MODULE_ENABLED */ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ @@ -182,7 +184,7 @@ typedef uint32_t HAL_UART_StateTypeDef; /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TORTO = 0x02U, @@ -190,6 +192,17 @@ typedef uint32_t HAL_UART_StateTypeDef; */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -201,7 +214,7 @@ typedef struct __UART_HandleTypeDef UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -224,14 +237,18 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ +#endif /* HAL_DMA_MODULE_ENABLED */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management @@ -335,7 +352,9 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ #define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) #define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -475,6 +494,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +#if defined(HAL_DMA_MODULE_ENABLED) /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ @@ -492,6 +512,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** * @} */ +#endif /* HAL_DMA_MODULE_ENABLED */ /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ @@ -532,7 +553,9 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ #define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) #define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ #define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ /** @@ -593,6 +616,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +#if defined(HAL_DMA_MODULE_ENABLED) /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ @@ -601,6 +625,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** * @} */ +#endif /* HAL_DMA_MODULE_ENABLED */ /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ @@ -788,7 +813,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -799,6 +824,16 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + /** * @} */ @@ -1366,6 +1401,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Ensure that UART DMA TX state is valid. * @param __DMATX__ UART DMA TX state. @@ -1382,6 +1418,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ ((__DMARX__) == UART_DMA_RX_ENABLE)) +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Ensure that UART half-duplex state is valid. * @param __HDSEL__ UART half-duplex state. @@ -1414,6 +1451,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ +#if defined(HAL_DMA_MODULE_ENABLED) #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ UART_ADVFEATURE_TXINVERT_INIT | \ UART_ADVFEATURE_RXINVERT_INIT | \ @@ -1423,6 +1461,16 @@ typedef void (*pUART_RxEventCallbackTypeDef) UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Ensure that UART frame TX inversion setting is valid. @@ -1473,6 +1521,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. * @param __DMA__ UART DMA enabling or disabling on error setting. @@ -1480,6 +1529,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Ensure that UART frame MSB first setting is valid. @@ -1583,15 +1633,17 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Transfer Abort functions */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); @@ -1641,8 +1693,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); */ /* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} @@ -1665,7 +1717,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @} @@ -1695,3 +1749,4 @@ extern const uint16_t UARTPrescTable[12]; #endif #endif /* STM32U5xx_HAL_UART_H */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h index e4b8363d2c..436e171231 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -268,12 +268,16 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /* Autonomous Mode Control functions **********************************************/ HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, - UART_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart); @@ -297,72 +301,100 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart * @retval UART clocking source, written in __CLOCKSOURCE__. */ #if defined(USART6) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART6; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#elif defined(USART2) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ } while(0U) #else -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ } while(0U) #endif /* USART6 */ @@ -513,3 +545,4 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart #endif #endif /* STM32U5xx_HAL_UART_EX_H */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h index c8d92472bf..cc85ca14c2 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -32,14 +32,10 @@ extern "C" { * @{ */ -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED) - -/** @addtogroup DLYB - * @{ - */ +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) /* Exported types ------------------------------------------------------------*/ -/** @defgroup DLYB_LL_Exported_Types DLYB Exported Types +/** @defgroup DLYB_LL DLYB * @{ */ @@ -56,17 +52,17 @@ typedef struct This parameter can be a value between 0 and DLYB_MAX_SELECT */ } LL_DLYB_CfgTypeDef; -/** - * @} - */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup DLYB_Exported_Constants DLYB Exported Constants * @{ */ #define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */ -#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ +#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ + +/** + * @} + */ /** @defgroup DLYB_LL_Flags DLYB Flags * @{ @@ -74,10 +70,6 @@ typedef struct #define DLYB_FLAG_LNGF DLYB_CFGR_LNGF -/** - * @} - */ - /** * @} */ @@ -117,8 +109,7 @@ __STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx) * @} */ - -/** @addtogroup DLYB_Control_Functions DLYB Control functions +/** @defgroup DLYB_Control_Functions DLYB Control functions * @{ */ @@ -138,7 +129,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c * @} */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */ +#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c index ccc93a26c2..62a57cc90a 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c @@ -8,7 +8,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -17,7 +17,6 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - @verbatim ============================================================================== ##### How to use this driver ##### @@ -54,10 +53,10 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.0.0 + * @brief STM32U5xx HAL Driver version number 1.3.0 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ @@ -348,7 +347,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) /** * @brief Return tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { @@ -441,6 +441,33 @@ uint32_t HAL_GetDEVID(void) return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @} */ @@ -622,6 +649,98 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the Cacheability of internal SRAMx by DCACHE2 + * + * @retval None + */ +void HAL_SYSCFG_EnableSRAMCached(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the Cacheability of internal SRAMx by DCACHE2 + * + * @retval None + */ +void HAL_SYSCFG_DisableSRAMCached(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell + * @note The vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_EnableVddCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell + * @retval None + */ +void HAL_SYSCFG_EnableVddHSPICompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell + * @note The Vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_DisableVddCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell + * @retval None + */ +void HAL_SYSCFG_DisableVddHSPICompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ /** * @} */ @@ -781,6 +900,99 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri #endif /* __ARM_FEATURE_CMSE */ +#ifdef SYSCFG_OTGHSPHYCR_EN +/** + * @brief Enable the OTG PHY . + * @param OTGPHYConfig Defines the OTG PHY configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_Enable + * @retval None + */ + +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig); +} + +/** + * @brief Set the OTG PHY Power Down config. + * @param PowerDownConfig Defines the OTG PHY Power down configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig); +} + +/** + * @brief Set the OTG PHY reference clock selection. + * @param RefClkSelection Defines the OTG PHY reference clock selection. + This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection); +} + +/** + * @brief Set the OTG PHY Disconnect Threshold. + * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Adjust the voltage level for the threshold used to detect valid high speed data. + * @param SquelchThreshold Defines the voltage level. + This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold + + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Set the OTG PHY Current config. + * @param PreemphasisCurrent Defines the current configuration. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent + + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +#endif /* SYSCFG_OTGHSPHYCR_EN */ + /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c index 003041af80..2ece94128d 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c @@ -11,7 +11,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -471,6 +471,8 @@ __weak void HAL_SYSTICK_Callback(void) */ void HAL_MPU_Enable(uint32_t MPU_Control) { + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; @@ -478,9 +480,9 @@ void HAL_MPU_Enable(uint32_t MPU_Control) SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Follow ARM recommendation with */ - /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */ - __DMB(); /* Force memory writes before continuing */ - __ISB(); /* Flush and refill pipeline with updated permissions */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -497,6 +499,8 @@ void HAL_MPU_Enable(uint32_t MPU_Control) */ void HAL_MPU_Enable_NS(uint32_t MPU_Control) { + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + /* Enable the MPU */ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; @@ -504,9 +508,9 @@ void HAL_MPU_Enable_NS(uint32_t MPU_Control) SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Follow ARM recommendation with */ - /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */ - __DMB(); /* Force memory writes before continuing */ - __ISB(); /* Flush and refill pipeline with updated permissions */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #endif /* __ARM_FEATURE_CMSE */ @@ -518,8 +522,16 @@ void HAL_MPU_Disable(void) { __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + /* Disable the MPU */ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -531,8 +543,16 @@ void HAL_MPU_Disable_NS(void) { __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + /* Disable fault exceptions */ + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + /* Disable the MPU */ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #endif /* __ARM_FEATURE_CMSE */ @@ -628,8 +648,8 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const } else { - MPUx->RBAR = 0U; MPUx->RLAR = 0U; + MPUx->RBAR = 0U; } } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c index ab73a11659..c5f0f88e18 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -38,7 +38,7 @@ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA()) (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE() (+++) Configure and enable two DMA channels one for managing data transfer from - memory to peripheral (input channel) and another stream for managing data + memory to peripheral (input channel) and another channel for managing data transfer from peripheral to memory (output channel) (+++) Associate the initialized DMA handle to the CRYP DMA handle using __HAL_LINKDMA() @@ -82,7 +82,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -191,7 +191,7 @@ (##) To perform message payload encryption or decryption AES is configured in CTR mode. (##) For authentication two phases are performed : - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message - only cleartext payload (not the ciphertext payload) is used and no outpout. + only cleartext payload (not the ciphertext payload) is used and no output. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits @@ -306,10 +306,11 @@ /** @addtogroup CRYP_Private_Defines * @{ */ -#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey +#define CRYP_GENERAL_TIMEOUT 82U +#define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /*!< The latency of GCM/CCM header phase is 290 clock cycles.*/ #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */ @@ -421,6 +422,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); (+) Data Type : 32,16, 8 or 1bit (+) AlgoMode : ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef + (+) For interleave mode, API HAL_CRYP_SaveContext and HAL_CRYP_RestoreContext to be used to save then Restore CRYP + configuration and parameters. CRYP_IVCONFIG_ONCE should be selected for KeyIVConfigSkip parameter. + Only polling mode is supported, interleave mode should be used with HAL_CRYP_Encrypt and HAL_CRYP_Decrypt API. @endverbatim * @{ @@ -436,6 +440,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) { uint32_t cr_value; +#if defined(SAES) + uint32_t tickstart; +#endif /* SAES */ /* Check the CRYP handle allocation */ if (hcryp == NULL) @@ -487,6 +494,34 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } else { + /* SAES is initializing, fetching random number from the RNG */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + __HAL_CRYP_DISABLE(hcryp); + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + /* SAES is initializing, no random number fetching error flagged */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_SET(hcryp->Instance->ISR, CRYP_FLAG_RNGEIF)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + __HAL_CRYP_DISABLE(hcryp); + hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \ hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection); /* Set the key size, data type, algorithm, Key selection and key protection */ @@ -601,8 +636,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { - /* Set the key size(This bit field is do not care in the DES or TDES modes) - data type, AlgoMode and operating mode */ + /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); } @@ -614,14 +648,18 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD /* In case of HSW, HW or SW key selection, we should specify Key mode selection (SAES_CR_KMOD) */ if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED)) { + /* Disable AES to change key mode */ + __HAL_CRYP_DISABLE(hcryp); /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ - AES_CR_KEYSEL | AES_CR_KEYPROT, hcryp->Init.DataType | hcryp->Init.KeySize | \ - hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection); + AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ + hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection | hcryp->Init.KeyMode); + /* Set to 0 the number of non-valid bytes using NPBLB field of CR register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); } /* Clear error flags */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); @@ -756,7 +794,6 @@ HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_ return HAL_ERROR; } - __HAL_LOCK(hcryp); if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -818,8 +855,6 @@ HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_ status = HAL_ERROR; } - __HAL_UNLOCK(hcryp); - return status; } @@ -840,35 +875,34 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(hcryp); if (hcryp->State == HAL_CRYP_STATE_READY) { switch (CallbackID) { case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /*!< Legacy weak InCpltCallback */ break; case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /*!< Legacy weak OutCpltCallback */ break; case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /*!< Legacy weak ErrorCallback */ break; case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; + hcryp->MspInitCallback = HAL_CRYP_MspInit; /*!< Legacy weak MspInit */ break; case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /*!< Legacy weak MspDeInit */ break; default : /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;/*!< Legacy weak ERROR INVALID CALLBACK */ /* Return error status */ status = HAL_ERROR; break; @@ -902,8 +936,6 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY status = HAL_ERROR; } - __HAL_UNLOCK(hcryp); - return status; } #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ @@ -1087,6 +1119,120 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) } #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +/** + * @brief CRYP peripheral parameters storage when processing Interleaved mode . + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure where CRYP parameters will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Save CRYP handle parameters */ + pcont->DataType = (uint32_t)(hcryp->Init.DataType); + pcont->KeySize = (uint32_t)(hcryp->Init.KeySize); + pcont->pKey = hcryp->Init.pKey; + pcont->pInitVect = hcryp->Init.pInitVect; + pcont->Algorithm = (uint32_t)(hcryp->Init.Algorithm); + pcont->DataWidthUnit = (uint32_t)(hcryp->Init.DataWidthUnit); + pcont->KeyIVConfigSkip = (uint32_t)(hcryp->Init.KeyIVConfigSkip); + pcont->KeyMode = (uint32_t)(hcryp->Init.KeyMode); + pcont->Phase = (uint32_t)(hcryp->Phase); + pcont->KeyIVConfig = (uint32_t)(hcryp->KeyIVConfig); + + /* Save CRYP CR register content */ + pcont->CR_Reg = READ_REG(hcryp->Instance->CR); + + /* Save IER register content */ + pcont->IER_Reg = READ_BIT(hcryp->Instance->IER, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Save Initialisation Vector registers */ + pcont->IVR0_Reg = READ_REG(hcryp->Instance->IVR0); + pcont->IVR1_Reg = READ_REG(hcryp->Instance->IVR1); + pcont->IVR2_Reg = READ_REG(hcryp->Instance->IVR2); + pcont->IVR3_Reg = READ_REG(hcryp->Instance->IVR3); + } + + /* To load Key for next piece of message */ + hcryp->KeyIVConfig = 0; + + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + +} + +/** + * @brief Restore CRYP parameters needed for Interleaved mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure that contains CRYP parameters stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Restore CRYP handle parameters */ + hcryp->Init.DataType = pcont->DataType; + hcryp->Init.KeySize = pcont->KeySize; + hcryp->Init.pKey = pcont->pKey; + hcryp->Init.pInitVect = pcont->pInitVect; + hcryp->Init.Algorithm = pcont->Algorithm; + hcryp->Init.DataWidthUnit = pcont->DataWidthUnit; + hcryp->Init.KeyIVConfigSkip = pcont->KeyIVConfigSkip; + hcryp->Init.KeyMode = pcont->KeyMode; + hcryp->Phase = pcont->Phase; + hcryp->KeyIVConfig = pcont->KeyIVConfig; + + /* Restore CRYP CR register content */ + WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); + + /* Restore CRYP IER register content */ + WRITE_REG(hcryp->Instance->IER, (uint32_t)(pcont->IER_Reg)); + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Restore Initialisation Vector registers */ + WRITE_REG(hcryp->Instance->IVR0, (uint32_t)(pcont->IVR0_Reg)); + WRITE_REG(hcryp->Instance->IVR1, (uint32_t)(pcont->IVR1_Reg)); + WRITE_REG(hcryp->Instance->IVR2, (uint32_t)(pcont->IVR2_Reg)); + WRITE_REG(hcryp->Instance->IVR3, (uint32_t)(pcont->IVR3_Reg)); + } + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} + /** * @} */ @@ -1706,7 +1852,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp /* Peripheral Key configuration to not do, IV to configure for CBC */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) { - if (hcryp->Init.Algorithm == CRYP_AES_CBC) + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { /* Set the Initialization Vector */ CRYP_SetIV(hcryp); @@ -1921,7 +2067,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * the configuration information for the CRYP peripheral * @retval CRYP error code */ -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp) { return hcryp->ErrorCode; } @@ -1932,7 +2078,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module. * @retval HAL state */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp) { return hcryp->State; } @@ -1948,8 +2094,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } @@ -1964,8 +2110,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -1980,8 +2126,8 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file */ } /** @@ -2010,7 +2156,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t tickstart; - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { if (hcryp->KeyIVConfig == 1U) { @@ -2027,61 +2173,84 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } - if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)) + if (dokeyivconfig == 1U) { - if (hcryp->Instance == AES) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ + (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) { - /* Set the Key */ - if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) - { - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - else /* After sharing the key, AES should set KMOD[1:0] to 00.*/ - { - hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; - } - } - else - { - /* We should re-write Key, in the case where we change key after first operation */ - if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + if (hcryp->Instance == AES) { /* Set the Key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /* After sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } } - /* Get tick */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) + else { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } } + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector */ + CRYP_SetIV(hcryp); + } } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + /* key & IV configuration for CBC and CTR in interleave mode */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) { - /* Set the Initialization Vector */ - CRYP_SetIV(hcryp); + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } } } /* If (dokeyivconfig == 1U) */ - + else + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } /* Peripheral Key configuration to not do, IV to configure for CBC */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) { - if (hcryp->Init.Algorithm == CRYP_AES_CBC) + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { /* Set the Initialization Vector*/ CRYP_SetIV(hcryp); @@ -2190,7 +2359,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) /* Peripheral Key configuration to not do, IV to configure for CBC */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) { - if (hcryp->Init.Algorithm == CRYP_AES_CBC) + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { /* Set the Initialization Vector*/ CRYP_SetIV(hcryp); @@ -2202,10 +2371,6 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) if (hcryp->Size != 0U) { - - /* Enable computation complete flag and Key, Read and Write error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); - /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2218,6 +2383,9 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; + + /* Enable computation complete flag and Key, Read and Write error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); } else { @@ -2241,7 +2409,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { if (hcryp->KeyIVConfig == 1U) { @@ -2270,7 +2438,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); /* Set the Key */ - if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ + (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) { if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -2282,6 +2451,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } + /* interleave mode Key configuration */ + else if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else + { + /* Nothing to do */ + } + /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2314,32 +2494,35 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } else /*SAES*/ { - /* key preparation for decryption, operating mode 2*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* we should re-write Key, in the case where we change key after first operation*/ - if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ { - if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) { - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } } - } - /* Enable SAES */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); - /* End of Key preparation for ECB/CBC */ - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } } /* Set IV */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) @@ -2349,7 +2532,47 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } /* if (dokeyivconfig == 1U) */ + else /* if (dokeyivconfig == 0U) */ + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + if (hcryp->Instance == AES) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + } + + } /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2365,7 +2588,6 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; } - /* Disable CRYP */ __HAL_CRYP_DISABLE(hcryp); @@ -2445,7 +2667,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -2471,44 +2693,48 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) } else /*SAES*/ { - /* key preparation for decryption, operating mode 2*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* we should re-write Key, in the case where we change key after first operation*/ - if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) { - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } } - } - /* Enable SAES */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count--; - if (count == 0U) + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); - /* End of Key preparation for ECB/CBC */ - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } } /* Set IV */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) @@ -2522,9 +2748,6 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->Phase = CRYP_PHASE_PROCESS; if (hcryp->Size != 0U) { - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); - /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2537,6 +2760,9 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); } else { @@ -2619,7 +2845,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -2645,44 +2871,48 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) } else /*SAES*/ { - /* key preparation for decryption, operating mode 2*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* we should re-write Key, in the case where we change key after first operation*/ - if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) { - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } } - } - /* Enable SAES */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count--; - if (count == 0U) + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); - /* End of Key preparation for ECB/CBC */ - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } } if (hcryp->Init.Algorithm != CRYP_AES_ECB) @@ -2723,10 +2953,11 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + uint32_t algo; /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit in the DMACR register */ @@ -2796,14 +3027,30 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /* Initiate payload DMA IN and processed data DMA OUT transfers */ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); } - /* Call input data transfer complete callback */ + else + { + + /* ECB, CBC or CTR end of input data feeding or + end of GCM/CCM payload data feeding through DMA */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + /* Don't call input data transfer complete callback only if + it remains some input data to write to the peripheral. + This case can only occur for GCM and CCM with a payload length + not a multiple of 16 bytes */ + if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ + (((hcryp->Size) % 16U) != 0U))) + { + /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */ } /** @@ -2869,7 +3116,16 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) hcryp->Instance->DINR = 0x0U; count++; } + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /*Wait on CCF flag*/ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); /*Read the output block from the output FIFO */ @@ -3388,7 +3644,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /****************************** Init phase **********************************/ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the Key */ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -3398,7 +3653,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t { hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; } - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ CRYP_SetIV(hcryp); @@ -3549,10 +3803,10 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3605,7 +3859,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) /******************************* Init phase *********************************/ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the Key */ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -3615,7 +3868,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) { hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; } - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ CRYP_SetIV(hcryp); @@ -3638,7 +3890,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -3685,7 +3937,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3735,6 +3987,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } /* Enter header data */ @@ -3829,7 +4089,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3879,6 +4139,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3929,7 +4197,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /*************************** Init phase ************************************/ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the Key */ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -3939,7 +4206,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; } - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ CRYP_SetIV(hcryp); @@ -3962,7 +4228,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -4039,7 +4305,6 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /********************** Init phase ******************************************/ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the Key */ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -4049,7 +4314,6 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t { hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; } - /* Set the initialization vector (IV) with B0 */ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); @@ -4196,6 +4460,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t npblb; uint32_t mode; uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4237,7 +4507,6 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) /********************** Init phase ******************************************/ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the Key */ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -4247,7 +4516,6 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) { hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; } - /* Set the initialization vector (IV) with B0 */ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); @@ -4273,7 +4541,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -4289,7 +4557,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (headersize_in_bytes == 0U) /* Header phase is skipped */ { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4371,26 +4648,65 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ + /* Enter header data */ + /* Check first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + hcryp->CrypHeaderCount++; loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4399,7 +4715,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - } + }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, @@ -4474,6 +4790,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4525,7 +4849,6 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /********************** Init phase ******************************************/ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the Key */ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -4535,7 +4858,6 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; } - /* Set the initialization vector (IV) with B0 */ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); @@ -4561,7 +4883,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -4796,6 +5118,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr hcryp->Instance->DINR = 0U; index++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Wait for CCF flag to be raised */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do @@ -4814,7 +5144,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -4837,6 +5167,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /* Process unlocked */ __HAL_UNLOCK(hcryp); + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } return HAL_OK; @@ -4854,10 +5192,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4988,10 +5326,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -5110,10 +5448,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t mode; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { @@ -5208,6 +5546,14 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) @@ -5298,7 +5644,7 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /* Get timeout */ tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -5351,7 +5697,7 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -5658,7 +6004,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c index cc049743fb..d57627fd31 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -67,7 +67,6 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions * @{ @@ -101,7 +100,8 @@ static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize); * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout) { /* Assume first Init.HeaderSize is in words */ uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */ @@ -132,9 +132,6 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); - /* Set the encrypt operating mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /* Write into the AES_DINR register the number of bits in header (64 bits) followed by the number of bits in the payload */ hcryp->Instance->DINR = 0U; @@ -144,7 +141,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -215,7 +212,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout) { uint32_t tagaddr = (uint32_t)pAuthTag; uint32_t i; @@ -240,12 +238,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); - /* Set encrypt operating mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -323,7 +318,6 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u - Derived hardware unique key (DHUK) - XOR of DHUK and BHK - Boot hardware key (BHK) - - Key registers AES_KEYx @endverbatim * @{ @@ -333,8 +327,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @brief Wrap (encrypt) application keys. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInput Pointer to the Key buffer to encrypt - * @param pOutput Pointer to the Key buffer encrypted + * @param pInput Pointer to the Key buffer to encrypt in case of ECB or CBC + * @param pOutput Pointer to the Key buffer encrypted in case of ECB or CBC * @param Timeout Specify Timeout value * @retval HAL status */ @@ -360,6 +354,9 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput /* Set the operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + /* Encryption operating mode(Mode 0)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + status = CRYPEx_KeyEncrypt(hcryp, Timeout); } else @@ -376,7 +373,7 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput * @brief Unwrap (Decrypt) application keys. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInput Pointer to the Key buffer to decrypt + * @param pInput Pointer to the Key buffer to decrypt. * @param Timeout Specify Timeout value * @retval HAL status */ @@ -418,14 +415,14 @@ HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInp * @} */ -/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions - * @brief Encrypt/Decrypt Shared key functions. +/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions + * @brief Encrypt and Decrypt Shared key functions. * @verbatim ============================================================================== - ##### Encrypt/Decrypt Shared key functions ##### + ##### Encrypt and Decrypt Shared key functions ##### ============================================================================== - [..] This section provides API allowing to Encrypt/Decrypt Shared key + [..] This section provides API allowing to Encrypt and Decrypt Shared key @endverbatim * @{ @@ -464,6 +461,9 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); + /* Encryption operating mode(Mode 0)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + status = CRYPEx_KeyEncrypt(hcryp, Timeout); } else @@ -546,18 +546,12 @@ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t T /* key preparation for decryption, operating mode 2*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - /* It is strongly recommended to select hardware secret keys */ - if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) - { - /* Set the Key */ - CRYPEx_SetKey(hcryp, hcryp->Init.KeySize); - } /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -614,7 +608,7 @@ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t T } /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -659,8 +653,6 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T uint32_t tickstart; uint32_t temp; /* Temporary CrypOutBuff */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - if (hcryp->Init.Algorithm != CRYP_AES_ECB) { /* Set the Initialization Vector */ @@ -669,31 +661,6 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); } - /* It is strongly recommended to select hardware secret keys */ - if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) - { - /* Set the Key */ - CRYPEx_SetKey(hcryp, hcryp->Init.KeySize); - } - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for Valid KEY flag to set */ - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_KEYVALID)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -718,7 +685,7 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T } /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -759,41 +726,6 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T return HAL_OK; } -/** - * @brief Write Key in Key registers. - * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param KeySize Size of Key - * @note If pKey is NULL, the Key registers are not written. - * @retval None - */ -static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize) -{ - if (hcryp->Init.pKey != NULL) - { - switch (KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U); - hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U); - hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U); - hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U); - hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U); - hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U); - hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U); - hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U); - hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U); - break; - default: - break; - } - } -} /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c index 39b4429f35..daf3d32f3c 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c @@ -12,7 +12,7 @@ ********************************************************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -25,6 +25,7 @@ ====================================================================================================================== ############### How to use this driver ############### ====================================================================================================================== + [..] DMA transfer modes are divided to 2 major categories : (+) Normal transfers (legacy) @@ -59,28 +60,28 @@ (+) Request : Specifies the DMA channel request Request parameters : - (++) can be a value of @ref DMA_Request_Selection + (++) can be a value of DMA_Request_Selection (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel - (++) can be a value of @ref DMA_Block_Request + (++) can be a value of DMA_Block_Request (+) Direction : Specifies the transfer direction for DMA channel - (++) can be a value of @ref DMA_Transfer_Direction + (++) can be a value of DMA_Transfer_Direction (+) SrcInc : Specifies the source increment mode for the DMA channel - (++) can be a value of @ref DMA_Source_Increment_Mode + (++) can be a value of DMA_Source_Increment_Mode (+) DestInc : Specifies the destination increment mode for the DMA channel - (++) can be a value of @ref DMA_Destination_Increment_Mode + (++) can be a value of DMA_Destination_Increment_Mode (+) SrcDataWidth : Specifies the source data width for the DMA channel - (++) can be a value of @ref DMA_Source_Data_Width + (++) can be a value of DMA_Source_Data_Width (+) DestDataWidth : Specifies the destination data width for the DMA channel - (++) can be a value of @ref DMA_Destination_Data_Width + (++) can be a value of DMA_Destination_Data_Width (+) Priority : Specifies the priority for the DMA channel - (++) can be a value of @ref DMA_Priority_Level + (++) can be a value of DMA_Priority_Level (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel (++) can be a value of between 1 and 64 @@ -89,13 +90,13 @@ (++) can be a value of between 1 and 64 (+) TransferAllocatedPort : Specifies the source and destination allocated ports - (++) can be a value of @ref DMA_Transfer_Allocated_Port + (++) can be a value of DMA_Transfer_Allocated_Port (+) TransferEventMode : Specifies the transfer event mode for the DMA channel - (++) can be a value of @ref DMA_Transfer_Event_Mode + (++) can be a value of DMA_Transfer_Event_Mode (+) Mode : Specifies the transfer mode for the DMA channel - (++) can be a value of @ref DMA_Transfer_Mode + (++) can be a value of DMA_Transfer_Mode *** Polling mode IO operation *** @@ -156,8 +157,9 @@ (++) Privilege : at channel level. (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes - configuration. This API is called once after each system boot. - When this API is called, HAL_DMA_ConfigChannelAttributes() API cannot be used anymore. + configuration. This API can be called once after each system boot. + If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. + Unlock is done either by a system boot or a by an RCC reset. (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. @@ -318,7 +320,9 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) { + DMA_TypeDef *p_dma_instance; + uint32_t tickstart = HAL_GetTick(); /* Check the DMA peripheral handle parameter */ @@ -883,11 +887,19 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) { - DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); + const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Global Interrupt Flag management *********************************************************************************/ - if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) +#else + if (global_active_flag_ns == 0U) +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { return; /* the global interrupt flag for the current channel is down , nothing to do */ } @@ -984,6 +996,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; + /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */ + __NOP(); + if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) { /* Update the DMA channel state */ @@ -1000,6 +1015,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) { /* Update the linked-list queue state */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; } /* Process Unlocked */ @@ -1082,6 +1100,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; + /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */ + __NOP(); + if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) { /* Update the DMA channel state */ @@ -1114,6 +1135,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /** * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. @@ -1132,9 +1155,6 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdma); - /* Check DMA channel state */ if (hdma->State == HAL_DMA_STATE_READY) { @@ -1178,6 +1198,8 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, default: { + /* Update error status */ + status = HAL_ERROR; break; } } @@ -1188,14 +1210,13 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdma); - return status; } /** * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. @@ -1212,9 +1233,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdma); - /* Check DMA channel state */ if (hdma->State == HAL_DMA_STATE_READY) { @@ -1281,9 +1299,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdma); - return status; } /** @@ -1462,7 +1477,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pChannelAttributes) { - DMA_TypeDef *p_dma_instance; + const DMA_TypeDef *p_dma_instance; uint32_t attributes; uint32_t channel_idx; @@ -1498,6 +1513,7 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co return HAL_OK; } + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Lock the DMA channel security and privilege attribute(s). @@ -1543,7 +1559,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ - if (hdma == NULL) + if ((hdma == NULL) || (pLockState == NULL)) { return HAL_ERROR; } @@ -1619,7 +1635,6 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma) /* Write DMA Channel Control Register (CCR) */ MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); - /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; @@ -1663,19 +1678,16 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma) /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ WRITE_REG(hdma->Instance->CBR1, 0U); - /* If 2D Addressing is supported by current channel */ if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) { /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/ WRITE_REG(hdma->Instance->CTR3, 0U); - /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/ WRITE_REG(hdma->Instance->CBR2, 0U); } - /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ WRITE_REG(hdma->Instance->CLLR, 0U); } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c index fe9a019448..ded17ef88e 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c @@ -15,7 +15,7 @@ ********************************************************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -163,6 +163,8 @@ in memory. Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. This API can be used when need to change few parameter to build new node. @@ -377,8 +379,8 @@ In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to FIFO capabilities titled data handling. (++) Padding pattern - Padding selected patter (zero padding or sign extension) when the source data width is smaller than - the destination data width at single level. + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) (Source : 0xFABA ------> Destination : 0xFFFFFABA) @@ -394,16 +396,17 @@ UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) (++) Exchange : Exchange data at byte and half-word on the destination and at byte level on the source. - Source byte exchange (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) - Destination byte exchange (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) - Destination half-word exchange (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) + Considering source and destination are both word type. Exchange operation can be as follows. + In examples below, one exchange setting is enabled at a time. + Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) + Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) + Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained can be combined according to application needs. (++) This API is complementary of normal transfers. (++) This API must not be called for linked-list transfers as data handling information are configured at node level. - (++) This API must be called only for DMA channel that supports data handling feature. *** User sequence *** [..] @@ -535,18 +538,12 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, DMA_NodeTypeDef *const pNode); static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); -#if (__GNUC__ == 11) || (__GNUC__ == 12) -static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, -#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, -#endif DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4); + DMA_NodeTypeDef const *const pNode3); static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4); + DMA_NodeTypeDef const *const pNode3); static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, uint32_t *const cllr_mask, uint32_t *const cllr_offset); @@ -676,8 +673,11 @@ HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) */ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) { + /* Get DMA instance */ DMA_TypeDef *p_dma_instance; + + /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -690,9 +690,11 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); + /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -729,9 +731,11 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) hdma->Instance->CBR2 = 0U; } + /* Clear privilege attribute */ CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); @@ -748,9 +752,10 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) hdma->XferAbortCallback = NULL; hdma->XferSuspendCallback = NULL; - /* Update the queue state and error code */ - if(hdma->LinkedListQueue != NULL) + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) { + /* Update the queue state and error code */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; @@ -786,7 +791,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List I/O Operation Functions ############### + ############### Linked-List IO Operation Functions ############### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1036,6 +1041,8 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) * specified DMA linked-list Node. * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. * @retval HAL status. */ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, @@ -1060,6 +1067,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); + assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); /* Check DMA channel parameters */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) @@ -1160,7 +1168,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1169,7 +1177,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1288,7 +1296,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1297,7 +1305,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1368,7 +1376,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1377,7 +1385,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1798,7 +1806,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1807,7 +1815,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1960,7 +1968,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1969,7 +1977,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2240,7 +2248,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2252,7 +2260,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2438,7 +2446,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2450,7 +2458,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2575,7 +2583,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2587,7 +2595,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -3500,7 +3508,7 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) hdma->Instance->CCR |= DMA_CCR_SUSP; /* Check if the DMA channel is suspended */ - while ((hdma->Instance->CSR & DMA_CSR_SUSPF) != 0U) + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) { /* Check for the timeout */ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) @@ -3516,10 +3524,10 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) return HAL_ERROR; } - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_SUSPEND; } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; } return HAL_OK; @@ -3655,7 +3663,13 @@ static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) uint32_t tmpreg; /* Prepare DMA Channel Control Register (CCR) value */ - tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode | hdma->InitLinkedList.LinkAllocatedPort; + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } /* Write DMA Channel Control Register (CCR) */ MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); @@ -3834,7 +3848,6 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; /*********************************************************************************** CDAR register value is updated */ - /* Check if the selected channel is 2D addressing */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) { @@ -4075,19 +4088,13 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ -#if (__GNUC__ == 11) || (__GNUC__ == 12) -static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, -#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, -#endif DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4) + DMA_NodeTypeDef const *const pNode3) { - uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3 | (uint32_t)pNode4) & DMA_CLBAR_LBA); + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); uint32_t ref = 0U; /* Check node 1 address */ @@ -4105,11 +4112,6 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN { ref = (uint32_t)pNode3; } - /* Check node 4 address */ - else if ((uint32_t)pNode4 != 0U) - { - ref = (uint32_t)pNode4; - } else { /* Prevent MISRA-C2012-Rule-15.7 */ @@ -4129,13 +4131,11 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. */ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4) + DMA_NodeTypeDef const *const pNode3) { uint32_t ref = 0U; @@ -4154,26 +4154,11 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, { ref = pNode3->NodeInfo & NODE_TYPE_MASK; } - /* Check node 4 parameter */ - else if (pNode4 != NULL) - { - ref = pNode4->NodeInfo & NODE_TYPE_MASK; - } else { /* Prevent MISRA-C2012-Rule-15.7 */ } - /* Check node 1 parameter */ - if (pNode1 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode1->NodeInfo & NODE_TYPE_MASK)) - { - return 1U; - } - } - /* Check node 2 parameter */ if (pNode2 != NULL) { @@ -4194,16 +4179,6 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, } } - /* Check node 4 parameter */ - if (pNode4 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode4->NodeInfo & NODE_TYPE_MASK)) - { - return 4U; - } - } - return 0U; } @@ -4398,7 +4373,7 @@ static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, DMA_NodeTypeDef *const pDestNode) { /* Repeat for all register nodes */ - for (uint32_t reg_idx = 0U; reg_idx < NODE_CLLR_IDX_POS; reg_idx++) + for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) { pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; } @@ -4423,12 +4398,12 @@ static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, uint32_t cllr_idx = RegisterNumber - 1U; DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; - uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL }; /* Update ULL position according to register number */ - update_link[cllr_idx] = update_link[NODE_CLLR_IDX_POS - 1U]; + update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; /* Repeat for all node registers */ while (contextnode_reg_counter != RegisterNumber) @@ -4488,12 +4463,12 @@ static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, uint32_t cllr_mask; DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; - uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL }; /* Update ULL position according to register number */ - update_link[RegisterNumber - 1U] = update_link[NODE_CLLR_IDX_POS - 1U]; + update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; /* Get context node CLLR information */ cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; @@ -4563,7 +4538,7 @@ static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, uint32_t FirstUnusedField) { /* Repeat for all unused fields */ - for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_CLLR_IDX_POS; reg_idx++) + for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) { pNode->LinkRegisters[reg_idx] = 0U; } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c index b52314f1a8..20fda2d087 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c index a18e039f39..d6d910c1c9 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c @@ -10,7 +10,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -1082,7 +1082,7 @@ static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_ * @param UserConfig The selected User Option Bytes values. * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, + * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, @@ -1141,14 +1141,14 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_mask |= FLASH_OPTR_nRST_SHDW; } - if ((UserType & OB_USER_SRAM134_RST) != 0U) + if ((UserType & OB_USER_SRAM_RST) != 0U) { - /* SRAM134_RST option byte should be modified */ - assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST)); + /* SRAM_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST)); - /* Set value and mask for SRAM134_RST option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST); - optr_reg_mask |= FLASH_OPTR_SRAM134_RST; + /* Set value and mask for SRAM_RST option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST); + optr_reg_mask |= FLASH_OPTR_SRAM_RST; } if ((UserType & OB_USER_IWDG_SW) != 0U) @@ -1220,7 +1220,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC); optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC; } - +#if defined(SRAM3_BASE) if ((UserType & OB_USER_SRAM3_ECC) != 0U) { /* SRAM3_ECC option byte should be modified */ @@ -1230,7 +1230,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC); optr_reg_mask |= FLASH_OPTR_SRAM3_ECC; } - +#endif /* SRAM3_BASE */ if ((UserType & OB_USER_SRAM2_ECC) != 0U) { /* SRAM2_ECC option byte should be modified */ @@ -1551,7 +1551,7 @@ static uint32_t FLASH_OB_GetRDP(void) * @retval The FLASH User Option Bytes values. * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, + * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c index c3bb932955..dcfcfb7574 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c @@ -10,7 +10,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -84,7 +84,10 @@ (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG @@ -239,7 +242,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure Alternate function mapped with the current IO */ tmp = p_gpio->AFR[(pin_position) >> 3U]; tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U)); - tmp |= ((GPIO_AF11_LPGPIO & 0x0FUL) << (((pin_position) & 0x07U) * 4U)); + tmp |= ((GPIO_AF11_LPGPIO1 & 0x0FUL) << (((pin_position) & 0x07U) * 4U)); p_gpio->AFR[(pin_position) >> 3U] = tmp; /* Configure IO Direction mode (Alternate) */ @@ -320,39 +323,39 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))); EXTI->EXTICR[position >> 2U] = tmp; - /* Clear EXTI line configuration */ - tmp = EXTI->IMR1; + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { tmp |= iocurrent; } - EXTI->IMR1 = tmp; + EXTI->RTSR1 = tmp; - tmp = EXTI->EMR1; + tmp = EXTI->FTSR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { tmp |= iocurrent; } - EXTI->EMR1 = tmp; + EXTI->FTSR1 = tmp; - /* Clear Rising Falling edge configuration */ - tmp = EXTI->RTSR1; + /* Clear EXTI line configuration */ + tmp = EXTI->EMR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { tmp |= iocurrent; } - EXTI->RTSR1 = tmp; + EXTI->EMR1 = tmp; - tmp = EXTI->FTSR1; + tmp = EXTI->IMR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { tmp |= iocurrent; } - EXTI->FTSR1 = tmp; + EXTI->IMR1 = tmp; } } position++; @@ -469,7 +472,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; @@ -519,6 +522,34 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin } } +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + /** * @brief Toggle the specified GPIO pin. * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding @@ -876,12 +907,13 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32 * @param pPinAttributes: pointer to return the pin attributes. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes) +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes) { uint32_t iocurrent; uint32_t pin_position; uint32_t position = 0U; - GPIO_TypeDef *p_gpio; + const GPIO_TypeDef *p_gpio; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c index 090f9478b6..53e805a31b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -124,26 +124,68 @@ #define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */ #define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */ #define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */ +#if defined (HSPI1) +#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */ +#endif /* HSPI1 */ /* Definitions for GTZC TZSC & TZIC ALL register values */ /* TZSC1 / TZIC1 instances */ -#define TZSC1_SECCFGR1_ALL (0x001FFFFFUL) +#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx) +#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x000007FFUL) +#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL) +#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL) + +#define TZIC1_IER1_ALL (0x00EFFFFFUL) +#define TZIC1_IER2_ALL (0x000007FFUL) +#define TZIC1_IER3_ALL (0x0FFFFFFFUL) +#define TZIC1_IER4_ALL (0xFF1FC01FUL) + +#define TZIC1_FCR1_ALL (0x00EFFFFFUL) +#define TZIC1_FCR2_ALL (0x000007FFUL) +#define TZIC1_FCR3_ALL (0x0FFFFFFFUL) +#define TZIC1_FCR4_ALL (0xFF1FC01FUL) + +#elif defined(STM32U5F9xx) || defined(STM32U5G9xx) +#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x00000FFFUL) +#define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL) +#define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL) + +#define TZIC1_IER1_ALL (0x00EFFFFFUL) +#define TZIC1_IER2_ALL (0x00000FFFUL) +#define TZIC1_IER3_ALL (0x1FFFFFFFUL) +#define TZIC1_IER4_ALL (0xFFDFC01FUL) + +#define TZIC1_FCR1_ALL (0x00EFFFFFUL) +#define TZIC1_FCR2_ALL (0x00000FFFUL) +#define TZIC1_FCR3_ALL (0x1FFFFFFFUL) +#define TZIC1_FCR4_ALL (0xFFDFC01FUL) +#else +#define TZSC1_SECCFGR1_ALL (0x000FFFFFUL) #define TZSC1_SECCFGR2_ALL (0x000001FFUL) #define TZSC1_SECCFGR3_ALL (0x007FFFFFUL) -#define TZSC1_PRIVCFGR1_ALL (0x001FFFFFUL) +#define TZSC1_PRIVCFGR1_ALL (0x000FFFFFUL) #define TZSC1_PRIVCFGR2_ALL (0x000001FFUL) #define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL) -#define TZIC1_IER1_ALL (0x001FFFFFUL) +#define TZIC1_IER1_ALL (0x000FFFFFUL) #define TZIC1_IER2_ALL (0x000001FFUL) #define TZIC1_IER3_ALL (0x007FFFFFUL) #define TZIC1_IER4_ALL (0x3F0FC01FUL) -#define TZIC1_FCR1_ALL (0x001FFFFFUL) +#define TZIC1_FCR1_ALL (0x000FFFFFUL) #define TZIC1_FCR2_ALL (0x000001FFUL) #define TZIC1_FCR3_ALL (0x007FFFFFUL) #define TZIC1_FCR4_ALL (0x3F0FC01FUL) +#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */ /* TZSC2 / TZIC2 instances */ #define TZSC2_SECCFGR1_ALL (0x00001BFFUL) @@ -156,6 +198,7 @@ #define TZIC2_FCR1_ALL (0x00001BFFUL) #define TZIC2_FCR2_ALL (0x0300C07FUL) +#define REG_SIZE 32U /** * @} */ @@ -166,18 +209,18 @@ * @{ */ -#define IS_ADDRESS_IN(mem, address)\ - ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ - || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ +#define IS_ADDRESS_IN(mem, address) \ + ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ + || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) ) -#define IS_ADDRESS_IN_S(mem, address)\ - ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ +#define IS_ADDRESS_IN_S(mem, address) \ + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) -#define IS_ADDRESS_IN_NS(mem, address)\ - ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ +#define IS_ADDRESS_IN_NS(mem, address) \ + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) #define GTZC_BASE_ADDRESS(mem)\ @@ -527,9 +570,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * The structure description is available in @ref GTZC_Exported_Types. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, + const MPCWM_ConfigTypeDef *pMPCWM_Desc) { uint32_t register_address; uint32_t reg_value; @@ -539,11 +581,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; /* check entry parameters */ - if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) - || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE)) - && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) - || ((pMPCWM_Desc->Offset % granularity) != 0U) - || ((pMPCWM_Desc->Length % granularity) != 0U)) + if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) || +#if defined (FMC_BANK3) + (((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) && +#else + ((MemBaseAddress == BKPSRAM_BASE) && +#endif /* FMC_BANK3 */ + (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) || + ((pMPCWM_Desc->Offset % granularity) != 0U) || + ((pMPCWM_Desc->Length % granularity) != 0U)) { return HAL_ERROR; } @@ -565,6 +611,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); } break; +#if defined (FMC_BANK1) case FMC_BANK1: size = TZSC_MPCWM1_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) @@ -579,6 +626,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); } break; +#endif /* FMC_BANK1 */ +#if defined (FMC_BANK3) case FMC_BANK3: /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 * (Parameter already checked) @@ -586,6 +635,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( size = TZSC_MPCWM3_MEM_SIZE; register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); break; +#endif /* FMC_BANK3 */ case BKPSRAM_BASE: /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 * (Parameter already checked) @@ -593,6 +643,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( size = TZSC_MPCWM4_MEM_SIZE; register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); break; +#if defined (OCTOSPI2_BASE) case OCTOSPI2_BASE: size = TZSC_MPCWM5_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) @@ -607,15 +658,30 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); } break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + size = TZSC_MPCWM6_MEM_SIZE; + if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) + { + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); + } + else + { + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); + } + break; +#endif /* HSPI1 */ default: return HAL_ERROR; break; } - if ((pMPCWM_Desc->Offset > size) - || ((pMPCWM_Desc->Offset - + pMPCWM_Desc->Length) - > size)) + if ((pMPCWM_Desc->Offset > size) || + ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size)) { return HAL_ERROR; } @@ -643,43 +709,60 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( * @brief Get a TZSC-MPCWM area configuration. * @param MemBaseAddress WM identifier. * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor. + * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of + * two MPCWM_ConfigTypeDef structures. * The structure description is available in @ref GTZC_Exported_Types. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc) { - uint32_t register_address; + uint32_t register_address_regionA; + uint32_t register_address_regionB = 0U; uint32_t reg_value; uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \ GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; - /* firstly take care of the first area, present on all MPCWM sub-blocks */ + /* Loading the subregion A & B addresses into their specific variables */ switch (MemBaseAddress) { case OCTOSPI1_BASE: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); break; +#if defined (FMC_BANK1) case FMC_BANK1: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); break; +#endif /* FMC_BANK1 */ +#if defined (FMC_BANK3) case FMC_BANK3: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); break; +#endif /* FMC_BANK3 */ case BKPSRAM_BASE: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); break; +#if defined (OCTOSPI2_BASE) case OCTOSPI2_BASE: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); + break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); break; +#endif /* HSPI1 */ default: return HAL_ERROR; break; } /* read register and update the descriptor for first area*/ - reg_value = READ_REG(*(__IO uint32_t *)register_address); + reg_value = READ_REG(*(__IO uint32_t *)register_address_regionA); pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1; pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk) >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity; @@ -687,36 +770,16 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity; /* read configuration register and update the descriptor for first area*/ - reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U)); + reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionA - 4U)); pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; - if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE)) + if (register_address_regionB != 0U) { - /* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE - * or FMC_BANK1 (already checked) - * Now take care of the second area, present on these sub-blocks - */ - switch (MemBaseAddress) - { - case OCTOSPI1_BASE: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); - break; - case FMC_BANK1: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); - break; - case OCTOSPI2_BASE: - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); - break; - default: - return HAL_ERROR; - break; - } - /* read register and update the descriptor for second area*/ - reg_value = READ_REG(*(__IO uint32_t *)register_address); + reg_value = READ_REG(*(__IO uint32_t *)register_address_regionB); pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2; pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk) >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity; @@ -724,9 +787,9 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity; /* read configuration register and update the descriptor for second area*/ - reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U)); - pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ - GTZC_TZSC_MPCWM_CFGR_SEC); + reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionB - 4U)); + pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ + GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; } @@ -768,7 +831,7 @@ void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance) * @param TZSC_Instance TZSC sub-block instance. * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON) */ -uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance) +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance) { return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); } @@ -800,10 +863,9 @@ uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance) * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, - MPCBB_ConfigTypeDef *pMPCBB_desc) + const MPCBB_ConfigTypeDef *pMPCBB_desc) { GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t reg_value; uint32_t mem_size; uint32_t size_in_superblocks; uint32_t i; @@ -811,24 +873,25 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, /* check entry parameters */ if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) +#if defined (SRAM3_BASE) && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))) - || ((pMPCBB_desc->SecureRWIllegalMode - != GTZC_MPCBB_SRWILADIS_ENABLE) - && (pMPCBB_desc->SecureRWIllegalMode - != GTZC_MPCBB_SRWILADIS_DISABLE)) - || ((pMPCBB_desc->InvertSecureState - != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) - && (pMPCBB_desc->InvertSecureState - != GTZC_MPCBB_INVSECSTATE_INVERTED))) +#endif /* SRAM3_BASE */ + && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) +#if defined (SRAM5_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) +#endif /* SRAM6_BASE */ + ) + || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) + && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) + || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) + && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) { return HAL_ERROR; } - /* write InvertSecureState and SecureRWIllegalMode properties */ - /* assume their Position/Mask is identical for all sub-blocks */ - reg_value = pMPCBB_desc->InvertSecureState; - reg_value |= pMPCBB_desc->SecureRWIllegalMode; if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB1; @@ -839,52 +902,80 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB3; mem_size = GTZC_MEM_SIZE(SRAM3); } - else +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { - /* Here MemBaseAddress is inside SRAM4 (parameter already checked) */ mpcbb_ptr = GTZC_MPCBB4; mem_size = GTZC_MEM_SIZE(SRAM4); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB5; + mem_size = GTZC_MEM_SIZE(SRAM5); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + /* write PRIVCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->PRIVCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); + } + #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t size_mask; + uint32_t reg_value; - /* write configuration and lock register information */ - MODIFY_REG(mpcbb_ptr->CR, - GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); - if (size_in_superblocks == 32U) + /* write SECCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->SECCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if (size_in_superblocks >= 32U) { size_mask = 0xFFFFFFFFU; + MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]); } else +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ { - size_mask = (1UL << size_in_superblocks) - 1U; + size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U; } /* limitation: code not portable with memory > 512K */ MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]); - /* write SECCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->SECCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); - } -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /* write InvertSecureState and SecureRWIllegalMode properties */ + reg_value = pMPCBB_desc->InvertSecureState; + reg_value |= pMPCBB_desc->SecureRWIllegalMode; - /* write PRIVCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->PRIVCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); - } + /* write configuration and lock register information */ + MODIFY_REG(mpcbb_ptr->CR, + GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } @@ -907,8 +998,17 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, /* check entry parameters */ if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) +#if defined (SRAM3_BASE) && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))) +#endif /* SRAM3_BASE */ + && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) +#if defined (SRAM5_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) +#endif /* SRAM6_BASE */ + ) { return HAL_ERROR; } @@ -925,39 +1025,55 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB3; mem_size = GTZC_MEM_SIZE(SRAM3); } - else +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB4; mem_size = GTZC_MEM_SIZE(SRAM4); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB5; + mem_size = GTZC_MEM_SIZE(SRAM5); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t reg_value; - uint32_t size_mask; /* read configuration and lock register information */ reg_value = READ_REG(mpcbb_ptr->CR); pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk); pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk); - if (size_in_superblocks == 32U) - { - size_mask = 0xFFFFFFFFU; - } - else - { - size_mask = (1UL << size_in_superblocks) - 1U; - } + /* limitation: code not portable with memory > 512K */ - pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1) - & size_mask; + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1); + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2); +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* read SECCFGR / PRIVCFGR registers information */ @@ -978,13 +1094,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, * @param NbBlocks Number of blocks to configure * (Block size is 512 Bytes). * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), - * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC, - * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV. + * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, + * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, - uint32_t *pMemAttributes) + const uint32_t *pMemAttributes) { GTZC_MPCBB_TypeDef *mpcbb_ptr; uint32_t base_address; @@ -1027,6 +1143,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB2; base_address = SRAM2_BASE_S; } +#if defined (SRAM3_BASE) else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U) { @@ -1039,6 +1156,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB3; base_address = SRAM3_BASE_S; } +#endif /* SRAM3_BASE */ else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U) { @@ -1051,6 +1169,34 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB4; base_address = SRAM4_BASE_S; } +#if defined (SRAM5_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB5; + base_address = SRAM5_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB5; + base_address = SRAM5_BASE_S; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_S; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1068,13 +1214,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* secure configuration */ - if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC) + if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC) { SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); do_attr_change = 1U; } - else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC) + else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC) { CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); @@ -1087,12 +1233,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* privilege configuration */ - if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV) + if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV) { SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); } - else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV) + else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV) { CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); @@ -1130,8 +1276,8 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, * (must be 512 Bytes aligned). * @param NbBlocks Number of blocks to get configuration. * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), - * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC, - * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV. + * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, + * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, @@ -1178,6 +1324,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB2_S; base_address = SRAM2_BASE_S; } +#if defined (SRAM3_BASE) else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM3, end_address))) { @@ -1190,6 +1337,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB3_S; base_address = SRAM3_BASE_S; } +#endif /* SRAM3_BASE */ else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM4, end_address))) { @@ -1202,6 +1350,34 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB4_S; base_address = SRAM4_BASE_S; } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM5, end_address))) + { + mpcbb_ptr = GTZC_MPCBB5_NS; + base_address = SRAM5_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM5, end_address))) + { + mpcbb_ptr = GTZC_MPCBB5_S; + base_address = SRAM5_BASE_S; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_NS; + base_address = SRAM6_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_S; + base_address = SRAM6_BASE_S; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1217,9 +1393,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)) >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK; - pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)) - >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK; + pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) + >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK; offset_bit_start++; if (offset_bit_start == 32U) @@ -1241,19 +1417,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), * with for each element: * value 0 super-block is unlocked, value 1 super-block is locked - * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and - * GTZC_MCPBB_SUPERBLOCK_LOCKED values). + * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and + * GTZC_MPCBB_SUPERBLOCK_LOCKED values). * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, - uint32_t *pLockAttributes) + const uint32_t *pLockAttributes) { __IO uint32_t *reg_mpcbb; uint32_t base_address; uint32_t superblock_start; uint32_t offset_bit_start; - uint32_t i; + uint32_t i = 0U; /* firstly check that MemAddress is well 16KBytes aligned */ if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) @@ -1268,7 +1444,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM1); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; } else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) @@ -1277,28 +1452,46 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM2); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; } +#if defined (SRAM3_BASE) else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) && (IS_ADDRESS_IN(SRAM3, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM3); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; } - +#endif /* SRAM3_BASE */ else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) && (IS_ADDRESS_IN(SRAM4, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM4); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) + && (IS_ADDRESS_IN(SRAM5, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM5); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1308,13 +1501,14 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; offset_bit_start = superblock_start % 32U; - for (i = 0U; i < NbSuperBlocks; i++) + /* First 32 super-blocks */ + while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) { - if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED) + if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) { SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); } - else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED) + else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) { CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); } @@ -1324,8 +1518,36 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, } offset_bit_start++; + i++; } +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) + { + /* Point to second configuration lock register */ + reg_mpcbb++; + + /* Remaining super-blocks */ + for (; i < NbSuperBlocks; i++) + { + if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) + { + SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) + { + CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else + { + break; + } + + offset_bit_start++; + } + } +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + /* an unexpected value in pLockAttributes array leads to an error status */ if (i != NbSuperBlocks) { @@ -1343,19 +1565,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), * with for each element: * value 0 super-block is unlocked, value 1 super-block is locked - * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and - * GTZC_MCPBB_SUPERBLOCK_LOCKED values). + * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and + * GTZC_MPCBB_SUPERBLOCK_LOCKED values). * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, uint32_t *pLockAttributes) { - uint32_t reg_mpcbb; + __IO uint32_t *reg_mpcbb; uint32_t base_address; uint32_t superblock_start; uint32_t offset_bit_start; - uint32_t i; + uint32_t i = 0U; /* firstly check that MemAddress is well 16KBytes aligned */ if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) @@ -1370,8 +1592,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM1); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; } else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) && (IS_ADDRESS_IN(SRAM2, (MemAddress @@ -1380,9 +1601,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM2); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; } +#if defined (SRAM3_BASE) else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) && (IS_ADDRESS_IN(SRAM3, (MemAddress + (NbSuperBlocks @@ -1390,9 +1611,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM3); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; } +#endif /* SRAM3_BASE */ else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) && (IS_ADDRESS_IN(SRAM4, (MemAddress + (NbSuperBlocks @@ -1400,25 +1621,64 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM4); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB4_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) + && (IS_ADDRESS_IN(SRAM5, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM5); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; + } +#endif /* SRAM5_BASE */ + +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; } - /* get start coordinates of the configuration */ + /* Get start coordinates of the configuration */ superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; offset_bit_start = superblock_start % 32U; - for (i = 0U; i < NbSuperBlocks; i++) + while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) { - pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U))) + pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) >> (offset_bit_start % 32U); offset_bit_start++; + i++; } +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) + { + /* Point to second configuration lock register */ + reg_mpcbb++; + + /* Remaining super-blocks */ + for (; i < NbSuperBlocks; i++) + { + pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) + >> (offset_bit_start % 32U); + offset_bit_start++; + } + } +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + return HAL_OK; } @@ -1439,14 +1699,28 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) { SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* SRAM3_BASE*/ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1458,7 +1732,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) /** * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter. * @param MemBaseAddress MPCBB identifier. - * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON). + * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON). * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, @@ -1473,14 +1747,28 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, { *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* SRAM3_BASE */ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1618,37 +1906,37 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) { /* special case where it is applied to all peripherals */ reg_value = READ_REG(GTZC_TZIC1->SR1); - for (i = 0U; i < 32U; i++) + for (i = 0U; i < REG_SIZE; i++) { pFlag[i] = (reg_value & (1UL << i)) >> i; } reg_value = READ_REG(GTZC_TZIC1->SR2); - for (i = 32U; i < 64U; i++) + for (i = REG_SIZE; i < (2U * REG_SIZE); i++) { pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U); } reg_value = READ_REG(GTZC_TZIC1->SR3); - for (i = 64; i < 96U; i++) + for (i = 2U * REG_SIZE; i < (3U * REG_SIZE); i++) { pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U); } reg_value = READ_REG(GTZC_TZIC1->SR4); - for (i = 96U; i < 128U; i++) + for (i = 3U * REG_SIZE; i < (4U * REG_SIZE); i++) { pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); } reg_value = READ_REG(GTZC_TZIC2->SR1); - for (i = 128U; i < 160U; i++) + for (i = 4U * REG_SIZE; i < (5U * REG_SIZE); i++) { pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U); } reg_value = READ_REG(GTZC_TZIC2->SR2); - for (i = 160U; i < GTZC_TZIC_PERIPH_NUMBER; i++) + for (i = 5U * REG_SIZE; i < GTZC_TZIC_PERIPH_NUMBER; i++) { pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U); } @@ -1921,4 +2209,3 @@ __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId) /** * @} */ - diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c index 24f611829b..6f92988d5d 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c @@ -15,7 +15,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -124,7 +124,7 @@ (#) HAL in interruption mode (interruptions driven) (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. - This is why, for driver implementation simplicity’s sake, user is requested to enter a message the + This is why, for driver implementation simplicity's sake, user is requested to enter a message the length of which is a multiple of 4 bytes. (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR @@ -159,9 +159,9 @@ [..] (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + Use function HAL_HASH_RegisterCallback() to register a user callback. - (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : callback for input completion. (+) DgstCpltCallback : callback for digest computation completion. (+) ErrorCallback : callback for error. @@ -170,9 +170,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : callback for input completion. @@ -181,13 +181,13 @@ (+) MspInitCallback : HASH MspInit. (+) MspDeInitCallback : HASH MspDeInit. - (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init - and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + reset to the legacy weak (surcharged) functions in the HAL_HASH_Init + and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -195,8 +195,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit - or @ref HAL_HASH_Init function. + using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit + or HAL_HASH_Init function. When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -2942,6 +2942,14 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u return HAL_OK; } } /* if (polling_step == 1) */ + else + { + /* otherwise, carry on in interrupt-mode */ + hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data + to be fed to the Peripheral */ + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at + the next interruption */ + } /* Process Unlock */ @@ -3557,3 +3565,4 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c index 7cb325fa57..32a20b5912 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c @@ -17,7 +17,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -1038,3 +1038,4 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c index af27d758c2..250041e110 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -615,7 +615,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); @@ -2269,11 +2274,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -3028,11 +3033,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -4114,11 +4119,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -4899,7 +4904,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA * the configuration information for the specified I2C. * @retval None */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); @@ -5435,6 +5440,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5802,6 +5813,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); @@ -5844,6 +5858,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -6531,7 +6551,8 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_LISTEN)) { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; @@ -7561,19 +7582,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7601,13 +7622,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7623,7 +7644,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -7637,7 +7658,6 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) __HAL_I2C_ENABLE_IT(hi2c, tmpisr); } - /** * @brief Manage the disabling of Interrupts. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c index 39d2f3fe15..ae5e0e179c 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c index 3560393083..36b790e594 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -35,7 +35,7 @@ cache invalidate maintenance operation, error management and TrustZone security support. - (+) The ICACHE provides additionnaly the possibility to remap input address + (+) The ICACHE provides additionally the possibility to remap input address falling into up to four memory regions (used to remap aliased code in external memories to the internal Code region, for execution) @@ -45,10 +45,13 @@ [..] The ICACHE HAL driver can be used as follows: - (#) Enable and disable the Instruction Cache with respectively - @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable() + (#) Optionally configure the Instruction Cache mode with + @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration + does not suit the application requirements. - (#) Configure the Instruction Cache mode with @ref HAL_ICACHE_ConfigAssociativityMode() + (#) Enable and disable the Instruction Cache with respectively + @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable(). + Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status. (#) Initiate the cache maintenance invalidation procedure with either @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT() @@ -234,9 +237,9 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void) HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; - /* Reset BSYENDF before to disable the instruction cache */ - /* that starts a cache invalidation procedure */ - CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + /* Make sure BSYENDF is reset before to disable the instruction cache */ + /* as it automatically starts a cache invalidation procedure */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); @@ -287,7 +290,7 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) else { /* Make sure BSYENDF is reset before to start cache invalidation */ - CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); /* Launch cache invalidation */ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); @@ -317,7 +320,7 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) } else { - /* Make sure BSYENDF is reset */ + /* Make sure BSYENDF is reset before to start cache invalidation */ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); /* Enable end of cache invalidation interrupt */ @@ -485,7 +488,7 @@ void HAL_ICACHE_IRQHandler(void) /* Disable error interrupt */ CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); - /* Clear ICACHE error pending flag */ + /* Clear ERR pending flag */ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); /* Instruction cache error interrupt user callback */ @@ -498,7 +501,7 @@ void HAL_ICACHE_IRQHandler(void) /* Disable end of cache invalidation interrupt */ CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - /* Clear ICACHE busyend pending flag */ + /* Clear BSYENDF pending flag */ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); /* Instruction cache busyend interrupt user callback */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c index b4284d40bc..d888e2adfc 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c @@ -14,16 +14,18 @@ + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration + ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause + * ****************************************************************************** @verbatim =============================================================================== @@ -51,7 +53,7 @@ and the CS boundary using the HAL_OSPI_Init() function. [..] When using Hyperbus, configure the RW recovery time, the access time, - the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + the write latency and the latency mode using the HAL_OSPI_HyperbusCfg() function. *** Indirect functional mode *** @@ -189,7 +191,7 @@ [..] Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. (+) FifoThresholdCallback : callback when the fifo threshold is reached. @@ -207,9 +209,9 @@ [..] By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init() + reset to the legacy weak (overridden) functions in the HAL_OSPI_Init() and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -226,7 +228,7 @@ [..] When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -282,7 +284,9 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +#if defined (OCTOSPIM) static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); +#endif /* OCTOSPIM */ /** @endcond */ @@ -410,7 +414,7 @@ HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi) ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); /* Configure Dual Quad mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DMM, hospi->Init.DualQuad); /* Configure sample shifting and delay hold quarter cycle */ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), @@ -2128,7 +2132,7 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /** * @brief Register a User OSPI Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hospi : OSPI handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: @@ -2238,7 +2242,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_ /** * @brief Unregister a User OSPI Callback - * OSPI Callback is redirected to the weak (surcharged) predefined callback + * OSPI Callback is redirected to the weak predefined callback * @param hospi : OSPI handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -2540,7 +2544,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t * @param hospi : OSPI handle. * @retval Fifo threshold */ -uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi) +uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi) { return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U); } @@ -2561,7 +2565,7 @@ HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeou * @param hospi : OSPI handle * @retval OSPI Error Code */ -uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi) +uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi) { return hospi->ErrorCode; } @@ -2571,7 +2575,7 @@ uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi) * @param hospi : OSPI handle * @retval HAL state */ -uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) +uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi) { /* Return OSPI handle state */ return hospi->State; @@ -2581,6 +2585,7 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) * @} */ +#if defined (OCTOSPIM) /** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function * @brief OSPI IO Manager configuration function * @@ -2622,7 +2627,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); - if (hospi->Instance == OCTOSPI1) + if (hospi->Instance == (OCTOSPI_TypeDef *)OCTOSPI1) { instance = 0U; other_instance = 1U; @@ -2673,12 +2678,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) { - SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], \ OCTOSPIM_PCR_IOLSRC_1); } if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) { - SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], \ OCTOSPIM_PCR_IOHSRC_1); } } @@ -2854,6 +2859,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * /** * @} */ +#endif /* OCTOSPIM */ /** @cond 0 @@ -3045,7 +3051,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the flash ID */ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_MSEL, cmd->FlashId); } if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) @@ -3179,8 +3185,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), - (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | - cmd->DataMode | cmd->DataDtrMode)); + (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | cmd->DataMode | + cmd->DataDtrMode)); } else { @@ -3206,6 +3212,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC return status; } +#if defined (OCTOSPIM) /** * @brief Get the current IOM configuration for an OctoSPI instance. * @param instance_nb : number of the instance @@ -3320,6 +3327,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * /* Return function status */ return status; } +#endif /* OCTOSPIM */ /** @defgroup OSPI_Exported_Functions_Group5 Delay Block function @@ -3346,11 +3354,13 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart; /* Enable OCTOSPI Free Running Clock (mandatory) */ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + /* Update OCTOSPI state */ + hospi->State = HAL_OSPI_STATE_BUSY_CMD; + if (hospi->Instance == OCTOSPI1) { /* Enable the DelayBlock */ @@ -3361,6 +3371,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL status = HAL_OK; } +#if defined (OCTOSPI2) else if (hospi->Instance == OCTOSPI2) { /* Enable the DelayBlock */ @@ -3370,33 +3381,19 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg); status = HAL_OK; } +#endif /* OCTOSPI2 */ else { /* Nothing to do */ } - /* Disable OCTOSPI */ - __HAL_OSPI_DISABLE(hospi); - - /* Wait till OSPI Disabled or if Time out is reached, exit */ - tickstart = HAL_GetTick(); - while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET) - { - if ((HAL_GetTick() - tickstart) > hospi->Timeout) - { - hospi->State = HAL_OSPI_STATE_ERROR; - hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - return HAL_TIMEOUT; - } - } + /* Abort the current OCTOSPI operation if exist */ + (void)HAL_OSPI_Abort(hospi); /* Disable Free Running Clock */ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - /* Re-Enable OCTOSPI */ - __HAL_OSPI_ENABLE(hospi); - /* Return function status */ return status; } @@ -3407,7 +3404,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL * @param pdlyb_cfg: Pointer to DLYB configuration structure. * @retval HAL status. */ -HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) +HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; @@ -3416,11 +3413,13 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg); status = HAL_OK; } +#if defined (OCTOSPI2) else if (hospi->Instance == OCTOSPI2) { LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg); status = HAL_OK; } +#endif /* OCTOSPI2 */ else { @@ -3439,11 +3438,13 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart; /* Enable OCTOSPI Free Running Clock (mandatory) */ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + /* Update OCTOSPI state */ + hospi->State = HAL_OSPI_STATE_BUSY_CMD; + if (hospi->Instance == OCTOSPI1) { /* Enable the DelayBlock */ @@ -3456,9 +3457,10 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OS } /* Disable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI1); + LL_DLYB_Disable(DLYB_OCTOSPI1); } +#if defined (OCTOSPI2) else if (hospi->Instance == OCTOSPI2) { /* Enable the DelayBlock */ @@ -3471,35 +3473,21 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OS } /* Disable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI2); + LL_DLYB_Disable(DLYB_OCTOSPI2); } +#endif /* OCTOSPI2 */ else { /* Nothing to do */ } - /* Disable OCTOSPI */ - __HAL_OSPI_DISABLE(hospi); - - /* Wait till OSPI Disabled or if Time out is reached, exit */ - tickstart = HAL_GetTick(); - while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET) - { - if ((HAL_GetTick() - tickstart) > hospi->Timeout) - { - hospi->State = HAL_OSPI_STATE_ERROR; - hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - return HAL_TIMEOUT; - } - } + /* Abort the current OctoSPI operation if exist */ + (void)HAL_OSPI_Abort(hospi); /* Disable Free Running Clock */ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - /* Re-Enable OCTOSPI */ - __HAL_OSPI_ENABLE(hospi); - /* Return function status */ return status; } @@ -3511,10 +3499,6 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OS * @} */ -/** - * @} - */ - #endif /* HAL_OSPI_MODULE_ENABLED */ /** diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c index b80d4a0851..eab1bf3c65 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -200,11 +200,11 @@ The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_PKA_RegisterCallback() + Use Functions HAL_PKA_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks: + Function HAL_PKA_RegisterCallback() allows to register following callbacks: (+) OperationCpltCallback : callback for End of operation. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. @@ -213,11 +213,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default + Use function HAL_PKA_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) OperationCpltCallback : callback for End of operation. @@ -226,27 +226,27 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET + By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback(). + examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when + reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() + If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state, + in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit() - or @ref HAL_PKA_Init() function. + using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit() + or HAL_PKA_Init() function. [..] When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or @@ -288,13 +288,16 @@ */ /* Private variables ---------------------------------------------------------*/ +static uint32_t primeordersize; +static uint32_t opsize; +static uint32_t modulussize; /* Private function prototypes -----------------------------------------------*/ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ */ -uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka); -HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); -uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode); +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode); uint32_t PKA_GetBitSize_u8(uint32_t byteNumber); uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb); uint32_t PKA_GetBitSize_u32(uint32_t wordNumber); @@ -322,7 +325,7 @@ void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2Aff void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in); HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); /** * @} */ @@ -807,6 +810,8 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -822,6 +827,8 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -838,6 +845,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -853,6 +862,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -871,6 +882,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); + opsize = in->OpSize; + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -886,6 +899,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); + opsize = in->OpSize; + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } @@ -900,7 +915,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) uint32_t size; /* Get output result size */ - size = PKA_Result_GetSize(hpka, PKA_MODULAR_EXP_OUT_RESULT, 130UL); + size = opsize; /* Move the result to appropriate location (indicated in out parameter) */ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); @@ -918,6 +933,8 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); + primeordersize = in->primeOrderSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -933,6 +950,8 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); + primeordersize = in->primeOrderSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -949,7 +968,8 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe uint32_t size; /* Get output result size */ - size = PKA_Result_GetSize(hpka, PKA_ECDSA_SIGN_OUT_SIGNATURE_R, 20UL); + size = primeordersize; + if (out != NULL) { @@ -1110,6 +1130,8 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); + modulussize = in->modulusSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1125,6 +1147,8 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); + modulussize = in->modulusSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1139,7 +1163,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out uint32_t size; /* Get output result size */ - size = PKA_Result_GetSize(hpka, PKA_ECC_SCALAR_MUL_OUT_RESULT_X, 20UL); + size = modulussize; /* If a destination buffer is provided */ if (out != NULL) @@ -1838,7 +1862,7 @@ __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval HAL status */ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka) { /* Return PKA handle state */ return hpka->State; @@ -1849,7 +1873,7 @@ HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval PKA error code */ -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka) { /* Return PKA handle error code */ return hpka->ErrorCode; @@ -1872,7 +1896,7 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval Return the current mode */ -uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka) +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka) { /* return the shifted PKA_CR_MODE value */ return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); @@ -1885,7 +1909,7 @@ uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka) * @param Tickstart Tick start value * @retval HAL status */ -HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) { /* Wait for the end of operation or timeout */ while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL) @@ -1908,7 +1932,7 @@ HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeo * @param mode PKA operating mode * @retval error code */ -uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode) +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode) { uint32_t err = HAL_PKA_ERROR_NONE; @@ -2264,15 +2288,15 @@ void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in) /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); } /** @@ -2340,6 +2364,8 @@ void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInT * @brief Set input parameters. * @param hpka PKA handle * @param in Input information + * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash + * for example)the hash value should be written at the end of the buffer with zeros padding at beginning. */ void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) { @@ -2544,7 +2570,7 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) /* Move the input parameters coefficient b to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); /* Move the input parameters modulus value p to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); @@ -2564,7 +2590,7 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) /* Move the input parameters curve prime order N to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); } @@ -2606,7 +2632,7 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) /* Move the input parameters modulus value n to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL)); } /** @@ -2907,7 +2933,7 @@ HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t F * @param Maxsize Specifies the possible max size of the result in words * @retval size */ -uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize) +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize) { uint32_t size; uint32_t current_index = Maxsize - 1UL; @@ -2936,4 +2962,3 @@ uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32 /** * @} */ - diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c index 5acfe511d8..069dad242b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -644,11 +644,6 @@ void HAL_PWR_EnterSTANDBYMode(void) /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif /*( __CC_ARM)*/ - /* Wait For Interrupt Request */ __WFI(); } @@ -870,6 +865,9 @@ void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) } } #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + /* NSecure item management (TZEN = 0) */ if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) { diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c index 1f0375868c..37265e420b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -84,7 +84,7 @@ (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA electrical and logical isolation. - It is recommanded to disable VDDUSB, VDDIO2 and VDDA electrical and + It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and logical isolation through HAL_PWREx_DisableVddUSB(), HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA(). @@ -101,6 +101,23 @@ (++) VDDA versus 1V6 (++) VDDA versus 1V8 + (#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and + HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal + USB HS transceiver supply. + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableOTGHSPHYLowPowerRetention() and + HAL_PWREx_DisableOTGHSPHYLowPowerRetention() to enable / disable OTG_HS PHY power during + low power modes (Stop2, Stop3 and Standby). + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableVDD11USB() and + HAL_PWREx_DisableVDD11USB() to enable/ disable the VDD11USB. + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to enable / disable the VBAT and temperature monitoring. @@ -126,15 +143,29 @@ (+) Retained RAM can be one of the following RAMs : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 + (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) (++) ICACHE - (++) DMA2DRAM + (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) PKA32RAM (++) DCACHE1 (++) FMAC (++) FDCAN (++) USB + (++) DCACHE2 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) LTDC (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) GFXMMU (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) DSI (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) JPEG (available only for STM32U5Fxxx and STM32U5Gxxx devices) (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and HAL_PWREx_DisableRAMsContentRunRetention() to @@ -142,8 +173,12 @@ (+) Retained RAM can be one of the following RAMs : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 + (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) (#) Call HAL_PWREx_EnableFlashFastWakeUp() and HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory @@ -162,9 +197,9 @@ and pull-down configuration. (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to - apply repectively pull-up and pull-down to selected I/O. + apply respectively pull-up and pull-down to selected I/O. Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to - disable applied repectively pull-up and pull-down to selected I/O. + disable applied respectively pull-up and pull-down to selected I/O. @endverbatim ****************************************************************************** @@ -190,9 +225,17 @@ /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ -/*!< PORTI pins mask */ -#define PWR_PORTI_AVAILABLE_PINS (0xFFU) -/*!< Time out value of flags setting */ +#if defined (PWR_PUCRJ_PU0) +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0xFFFFU) +/* PORTJ pins mask */ +#define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU) +#else +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0x00FFU) +#endif /* defined (PWR_PUCRJ_PU0) */ + +/* Time out value of flags setting */ #define PWR_FLAG_SETTING_DELAY (0x32U) /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask @@ -309,6 +352,13 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No change, nothing to do */ if (vos_old == VoltageScaling) { + /* Enable USB BOOST after wake up from Stop mode */ + if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3) + { + /* Enable USB BOOST */ + SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); + } + return HAL_OK; } @@ -326,7 +376,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling); } - /* Wait until VOSRDY is rised */ + /* Wait until VOSRDY is raised */ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U)) { @@ -336,7 +386,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* Check time out */ if (timeout != 0U) { - /* Wait until ACTVOSRDY is rised */ + /* Wait until ACTVOSRDY is raised */ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U)) { @@ -538,7 +588,7 @@ void HAL_PWREx_DisableFastSoftStart(void) *** Stop 3 mode *** =================== [..] - The Stop 3 mode is based on the Cortex�-M33 Deepsleep mode combined with + The Stop 3 mode is based on the Cortex-M33 Deepsleep mode combined with peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain are stopped. The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. @@ -1005,7 +1055,7 @@ __weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin) The switch to the VBAT supply is controlled by the power down reset embedded in the Reset block. - (+) After exiting reset, the USB Type-C �dead battery� behavior is enabled, + (+) After exiting reset, the USB Type-C (dead battery) behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized @@ -1331,6 +1381,86 @@ void HAL_PWREx_DisableMonitoring(void) CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); } +#if defined (PWR_VOSR_USBPWREN) +/** + * @brief Enable the internal USB HS transceiver supply. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void) +{ + uint32_t vos; + + /* Get the system applied voltage scaling range */ + vos = HAL_PWREx_GetVoltageRange(); + + /* Check the system applied voltage scaling range */ + if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2)) + { + SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the internal USB HS transceiver supply. + * @retval HAL status. + */ +void HAL_PWREx_DisableUSBHSTranceiverSupply(void) +{ + CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); +} +#endif /* defined (PWR_VOSR_USBPWREN) */ + +#if defined (PWR_CR1_FORCE_USBPWR) +/** + * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). + * @retval None. + */ +void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void) +{ + /* Set FORCE_USBPWR bit */ + SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). + * @retval None. + */ +void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void) +{ + /* Clear FORCE_USBPWR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ + +#if defined (PWR_VOSR_VDD11USBDIS) +/** + * @brief Enable the VDD11USB. + * @retval None. + */ +void HAL_PWREx_EnableVDD11USB(void) +{ + /* Clear VDD11USBDIS bit */ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Disable the VDD11USB. + * @retval None. + */ +void HAL_PWREx_DisableVDD11USB(void) +{ + /* Set VDD11USBDIS bit */ + SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ + +#ifdef UCPD1 /** * @brief Enable UCPD configuration memorization in Standby mode. * @retval None. @@ -1353,7 +1483,7 @@ void HAL_PWREx_DisableUCPDStandbyMode(void) /** * @brief Enable dead battery behavior. - * @note After exiting reset, the USB Type-C �dead battery� behavior is + * @note After exiting reset, the USB Type-C (dead battery) behavior is * enabled, which may have a pull-down effect on CC1 and CC2 pins. * It is recommended to disable it in all cases, either to stop this * pull-down or to handover control to the UCPD (the UCPD must be @@ -1367,7 +1497,7 @@ void HAL_PWREx_EnableUCPDDeadBattery(void) /** * @brief Disable dead battery behavior. - * @note After exiting reset, the USB Type-C �dead battery� behavior is + * @note After exiting reset, the USB Type-C (dead battery) behavior is * enabled, which may have a pull-down effect on CC1 and CC2 pins. * It is recommended to disable it in all cases, either to stop this * pull-down or to handover control to the UCPD (the UCPD must be @@ -1378,6 +1508,7 @@ void HAL_PWREx_DisableUCPDDeadBattery(void) { SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); } +#endif /* UCPD1 */ /** * @brief Enable the Battery charging. @@ -1540,10 +1671,12 @@ __weak void HAL_PWREx_AVM2Callback(void) (+) Retained content RAMs in Stop modes are : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 (++) ICACHE - (++) DMA2DRAM + (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) PKA32RAM (++) DCACHE (++) FMAC @@ -1556,7 +1689,8 @@ __weak void HAL_PWREx_AVM2Callback(void) (+) Retained content RAMs in Run modes are : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 [..] @@ -1577,9 +1711,9 @@ __weak void HAL_PWREx_AVM2Callback(void) * Stop 3 and Standby mode and its content is kept. * @param SRAM2Pages : Specifies the SRAM2 pages. * This parameter can be one of the following values : - * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention. - * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention. - * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention. + * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. + * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. + * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. * @retval None. */ void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) @@ -1597,9 +1731,9 @@ void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) * mode and its content is lost. * @param SRAM2Pages : Specifies the SRAM2 pages. * This parameter can be one of the following values : - * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention. - * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention. - * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention. + * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. + * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. + * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. * @retval None. */ void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) @@ -1637,6 +1771,12 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); CLEAR_BIT(PWR->CR2, dummy); +#if defined (PWR_CR4_SRAM1PDS4) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; + CLEAR_BIT(PWR->CR4, dummy); +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + break; } @@ -1647,12 +1787,13 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); break; } +#if defined (PWR_CR2_SRAM3PDS1) /* SRAM 3 Stop retention */ case SRAM3_ID: { @@ -1664,8 +1805,16 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); +#if defined (PWR_CR4_SRAM3PDS9) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; + CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + break; } +#endif /* PWR_CR2_SRAM3PDS1 */ /* SRAM 4 Stop retention */ case SRAM4_ID: @@ -1674,7 +1823,7 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); break; @@ -1687,7 +1836,7 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos); break; @@ -1700,12 +1849,13 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos); break; } +#if defined (PWR_CR2_DMA2DRAMPDS) /* DMA2D RAM Stop retention */ case DMA2DRAM_ID: { @@ -1713,11 +1863,12 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); break; } +#endif /* PWR_CR2_DMA2DRAMPDS */ /* FMAC, FDCAN and USB RAM Stop retention */ case PERIPHRAM_ID: @@ -1726,12 +1877,13 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); break; } +#if defined (PWR_CR2_PKARAMPDS) /* PKA32 RAM Stop retention */ case PKARAM_ID: { @@ -1739,11 +1891,102 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); break; } +#endif /* PWR_CR2_PKARAMPDS */ + +#if defined (PWR_CR2_DC2RAMPDS) + /* DCACHE2 RAM Stop retention */ + case DCACHE2RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) + /* LTDC and GFXMMU RAM Stop retention */ + case GRAPHIPRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) + /* DSI RAM Stop retention */ + case DSIRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) + /* JPEG RAM Stop retention */ + case JPEGRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR4_SRAM5PDS1) + /* SRAM 5 Stop retention */ + case SRAM5_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); + CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) + /* SRAM 6 Stop retention */ + case SRAM6_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); + CLEAR_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR5_SRAM6PDS1) */ default: { @@ -1778,6 +2021,11 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) /* Calculate pages mask */ dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); SET_BIT(PWR->CR2, dummy); +#if defined (PWR_CR4_SRAM1PDS4) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; + SET_BIT(PWR->CR4, dummy); +#endif /* defined (PWR_CR4_SRAM1PDS4) */ break; } @@ -1789,12 +2037,13 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); break; } +#if defined (PWR_CR2_SRAM3PDS1) /* SRAM 3 Stop retention */ case SRAM3_ID: { @@ -1806,8 +2055,16 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); +#if defined (PWR_CR4_SRAM3PDS9) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; + SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + break; } +#endif /* PWR_CR2_SRAM3PDS1 */ /* SRAM 4 Stop retention */ case SRAM4_ID: @@ -1816,7 +2073,7 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); break; @@ -1829,7 +2086,7 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos)); break; @@ -1842,12 +2099,13 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos)); break; } +#if defined (PWR_CR2_DMA2DRAMPDS) /* DMA2D RAM Stop retention */ case DMA2DRAM_ID: { @@ -1855,11 +2113,12 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); break; } +#endif /* PWR_CR2_DMA2DRAMPDS */ /* FMAC, FDCAN and USB RAM Stop retention */ case PERIPHRAM_ID: @@ -1868,12 +2127,13 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); break; } +#if defined (PWR_CR2_PKARAMPDS) /* PKA32 RAM Stop retention */ case PKARAM_ID: { @@ -1881,11 +2141,102 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); break; } +#endif /* PWR_CR2_PKARAMPDS */ + +#if defined (PWR_CR2_DC2RAMPDS) + /* DCACHE2 RAM Stop retention */ + case DCACHE2RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) + /* LTDC and GFXMMU RAM Stop retention */ + case GRAPHIPRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) + /* DSI RAM Stop retention */ + case DSIRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) + /* JPEG RAM Stop retention */ + case JPEGRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR4_SRAM5PDS1) + /* SRAM 5 Stop retention */ + case SRAM5_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); + SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) + /* SRAM 6 Stop retention */ + case SRAM6_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); + SET_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR5_SRAM6PDS1) */ default: { @@ -1899,10 +2250,17 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) * @brief Enable RAMs full content retention in Run mode. * @param RAMSelection : Specifies the SRAM content to be retained in Run mode. * This parameter can be one or a combination of the following values : - * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content retention. - * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content retention. - * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content retention. - * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content retention. + * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention. + * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention. + * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention (available only for STM32U575xx, + * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices). + * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention. + * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for + * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + * and STM32U5Gxxx devices). + * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for + * STM32U5Fxxx and STM32U5Gxxx devices). * @retval None. */ void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection) @@ -1918,10 +2276,17 @@ void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection) * @brief Disable RAMs full content retention in Run mode. * @param RAMSelection : Specifies the SRAM content to be lost in Run mode. * This parameter can be one or a combination of the following values : - * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content lost. - * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content lost. - * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content lost. - * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content lost. + * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost. + * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost. + * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost (available only for STM32U575xx, + * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices). + * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost. + * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for + * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + * and STM32U5Gxxx devices). + * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for + * STM32U5Fxxx and STM32U5Gxxx devices). * @retval None. */ void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection) @@ -2035,15 +2400,17 @@ void HAL_PWREx_DisableSRAM4FastWakeUp(void) * @verbatim =============================================================================== - ##### Voltage monitoring Functions ##### + ##### I/O Pull-Up Pull-Down Configuration Functions ##### =============================================================================== [..] In Standby and Shutdown mode, pull up and pull down can be configured to maintain an I/O in the selected state. If the APC bit in the PWR_APCR register is set, the I/Os can be configured either with a pull-up through - PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I), or with a pull-down through - PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I)), or can be kept in analog state + PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through + PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state if none of the PWR_PUCRx or PWR_PDCRx register is set. + (+) Port J is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices. [..] The pull-down configuration has highest priority over pull-up @@ -2140,10 +2507,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_P CLEAR_BIT(PWR->PDCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */ SET_BIT(PWR->PUCRF, GPIO_Pin); CLEAR_BIT(PWR->PDCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */ SET_BIT(PWR->PUCRG, GPIO_Pin); @@ -2155,10 +2524,19 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_P CLEAR_BIT(PWR->PDCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */ SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */ + SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; @@ -2211,9 +2589,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_ CLEAR_BIT(PWR->PUCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */ CLEAR_BIT(PWR->PUCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */ CLEAR_BIT(PWR->PUCRG, GPIO_Pin); @@ -2223,9 +2603,17 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_ CLEAR_BIT(PWR->PUCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */ CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */ + CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; @@ -2290,10 +2678,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO CLEAR_BIT(PWR->PUCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */ SET_BIT(PWR->PDCRF, GPIO_Pin); CLEAR_BIT(PWR->PUCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */ SET_BIT(PWR->PDCRG, GPIO_Pin); @@ -2305,10 +2695,19 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO CLEAR_BIT(PWR->PUCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */ SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */ + SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; @@ -2361,9 +2760,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPI CLEAR_BIT(PWR->PDCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */ CLEAR_BIT(PWR->PDCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */ CLEAR_BIT(PWR->PDCRG, GPIO_Pin); @@ -2373,9 +2774,17 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPI CLEAR_BIT(PWR->PDCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */ CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */ + CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c index 0c6d5dbb60..edff155664 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c @@ -11,7 +11,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -44,7 +44,7 @@ (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/SDMMC1/RNG) + derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/USB FS/SDMMC1/RNG) @endverbatim ****************************************************************************** @@ -70,6 +70,7 @@ * @{ */ #define PLLDIVR_RESET_VALUE (0x01010280U) +#define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ /** * @} */ @@ -84,6 +85,7 @@ ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) @@ -125,7 +127,7 @@ #define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \ ((VALUE) == RCC_PLLVCIRANGE_1)) -#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) +#define IS_RCC_PLL_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) @@ -184,7 +186,8 @@ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ -#define LSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 5UL /* 5 ms (LSI maximum timeout is LSI startup time + LSI_VALUE/128 when + LSI prediv is used) */ #define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ @@ -246,7 +249,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); the PLL as System clock source. (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. - It can be used to generate the clock for the USB OTG FS (48 MHz). + It can be used to generate the clock for the USB FS or USB OTG FS (48 MHz). The number of flash wait states is automatically adjusted when MSI range is updated with HAL_RCC_OscConfig() and the MSI is used as System clock source. @@ -260,14 +263,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: (++) The first output is used to generate the high speed system clock (up to 80MHz). - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + (++) The second output is used to generate the clock for the USB FS or USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). (++) The third output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks: (++) The first output is used to generate SAR ADC1 clock. - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + (++) The second output is used to generate the clock for the USB Fs or USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). (++) The Third output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. @@ -305,7 +308,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); divided by 2 to 31. You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz + (+@) USB FS, USB OTG FS, SDMMC1 and RNG: USB OTG FS or USB FS requires a frequency equal to 48 MHz to work correctly, while the SDMMC1 and RNG peripherals require a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2 through PLLQ divider. You have to enable the peripheral clock and use @@ -354,6 +357,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); * - LSI, LSE and RTC clocks * @retval HAL status */ + HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; @@ -370,6 +374,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { return HAL_ERROR; } + } tickstart = HAL_GetTick(); @@ -535,13 +540,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * first and then HSE On or HSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct) { uint32_t tickstart; HAL_StatusTypeDef status; uint32_t sysclk_source; uint32_t pll_config; FlagStatus pwrboosten = RESET; + uint32_t temp1_pllckcfg; + uint32_t temp2_pllckcfg; /* Check Null pointer */ if (pRCC_OscInitStruct == NULL) @@ -568,7 +575,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) { - if ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) && (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF) { return HAL_ERROR; } @@ -581,10 +588,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) (HCLK) and the supply voltage of the device */ if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) { - /* First increase number of wait states update if necessary */ - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + /* Decrease number of wait states update if necessary */ + /* Only possible when MSI is the System clock source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) { - return HAL_ERROR; + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } } /* Selects the Multiple Speed oscillator (MSI) clock range */ @@ -602,10 +613,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ (pRCC_OscInitStruct->MSIClockRange)); - /* Decrease number of wait states update if necessary */ - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) { - return HAL_ERROR; + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } } } @@ -672,7 +685,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) { - if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF) { return HAL_ERROR; } @@ -723,7 +736,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not be disabled */ - if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF) { return HAL_ERROR; } @@ -1149,6 +1162,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { + FlagStatus pwrclkchanged = RESET; + /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { @@ -1168,7 +1183,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) @@ -1177,8 +1192,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) } } - /* Enable PWR CLK */ - __HAL_RCC_PWR_CLK_ENABLE(); + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } /*Disable EPOD to configure PLL1MBOOST*/ if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN) @@ -1196,16 +1215,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) pRCC_OscInitStruct->PLL.PLLQ, pRCC_OscInitStruct->PLL.PLLR); - assert_param(IS_RCC_PLLFRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); + assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACN */ - __HAL_RCC_PLLFRACN_DISABLE(); + __HAL_RCC_PLL_FRACN_DISABLE(); /* Configure PLL PLL1FRACN */ - __HAL_RCC_PLLFRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); + __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); /* Enable PLL1FRACN */ - __HAL_RCC_PLLFRACN_ENABLE(); + __HAL_RCC_PLL_FRACN_ENABLE(); assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE)); @@ -1218,8 +1237,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); } - /*Disable PWR clk */ - __HAL_RCC_PWR_CLK_DISABLE(); + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } /* Enable PLL System Clock output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); @@ -1243,9 +1265,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) /* Disable the main PLL */ __HAL_RCC_PLL_DISABLE(); - /* Disable main PLL outputs to save power if no PLLs on */ - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR); - tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ @@ -1256,11 +1275,57 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) return HAL_TIMEOUT; } } + + /* Unselect main PLL clock source and disable main PLL outputs to save power */ + RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); + } } else { - return HAL_ERROR; + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLL1CFGR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pRCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ + RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1MBOOST) != pRCC_OscInitStruct->PLL.PLLMBOOST) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pRCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \ + RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \ + RCC_PLL1DIVR_PLL1Q_Pos) != (pRCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \ + RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + + /* FRACN1 on-the-fly value update */ + if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos) != (pRCC_OscInitStruct->PLL.PLLFRACN)) + { + assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable PLL1FRACN. */ + __HAL_RCC_PLL_FRACN_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait at least 2 CK_REF (PLL1 input source divided by M) period to make sure next latched value + will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE) + { + } + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); + + /* Enable PLL1FRACN to latch the new value. */ + __HAL_RCC_PLL_FRACN_ENABLE(); + } } } return HAL_OK; @@ -1334,15 +1399,60 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk } } + /* Increasing the BUS frequency divider */ + /*-------------------------- PCLK3 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) + { + if ((pRCC_ClkInitStruct->APB3CLKDivider) > (RCC->CFGR3 & RCC_CFGR3_PPRE3)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider); + } + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + /*------------------------- SYSCLK Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource)); + FlagStatus pwrclkchanged = RESET; /* PLL is selected as System Clock Source */ if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - __HAL_RCC_PWR_CLK_ENABLE(); + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } tickstart = HAL_GetTick(); /* Check if EPOD is enabled */ if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U) @@ -1357,7 +1467,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk } } - __HAL_RCC_PWR_CLK_DISABLE(); + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) @@ -1445,45 +1559,58 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk } } + /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { - assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + if ((pRCC_ClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + } } /*-------------------------- PCLK3 Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) + if ((pRCC_ClkInitStruct->APB3CLKDivider) < (RCC->CFGR3 & RCC_CFGR3_PPRE3)) { - return HAL_ERROR; + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, (pRCC_ClkInitStruct->APB3CLKDivider)); } } @@ -1530,7 +1657,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -1661,34 +1788,27 @@ uint32_t HAL_RCC_GetSysClockFreq(void) fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); - if (pllm != 0U) - { - switch (pllsource) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1U); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1U); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1U); - break; - } - - pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); - sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr); - } - else + switch (pllsource) { - sysclockfreq = 0; + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1U); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1U); + break; + + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1U); + break; } + + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr); } return sysclockfreq; @@ -1752,6 +1872,10 @@ uint32_t HAL_RCC_GetPCLK3Freq(void) */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) { + uint32_t regval; + uint32_t reg1val; + uint32_t reg2val; + /* Check the parameters */ assert_param(pRCC_OscInitStruct != (void *)NULL); @@ -1759,104 +1883,62 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + /* Get Control register */ + regval = RCC->CR; + /* Get the HSE configuration -----------------------------------------------*/ - if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) - { - pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) - { - pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; - } - else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) - { - pRCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - pRCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } + pRCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT)); /* Get the MSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_MSISON) == RCC_CR_MSISON) - { - pRCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - pRCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } + pRCC_OscInitStruct->MSIState = regval & RCC_CR_MSISON; - pRCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_ICSCR1_MSISRANGE)); + reg1val = RCC->ICSCR1; + reg2val = RCC->ICSCR2; + + pRCC_OscInitStruct->MSIClockRange = (uint32_t)((reg1val & RCC_ICSCR1_MSISRANGE)); if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12) { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM3) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM3) >> \ RCC_ICSCR2_MSITRIM3_Pos); } else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8) { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM2) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM2) >> \ RCC_ICSCR2_MSITRIM2_Pos); } else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4) { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM1) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM1) >> \ RCC_ICSCR2_MSITRIM1_Pos); } else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/ { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM0) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM0) >> \ RCC_ICSCR2_MSITRIM0_Pos); } - /* Get the HSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) - { - pRCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - pRCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } + /* Get the HSI configuration -----------------------------------------------*/ + pRCC_OscInitStruct->HSIState = regval & RCC_CR_HSION; pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); + /* Get BDCR register */ + regval = RCC->BDCR; + /* Get the LSE configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - pRCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - pRCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } + pRCC_OscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN)); /* Get the LSI configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSION) == RCC_BDCR_LSION) - { - pRCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - pRCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } + pRCC_OscInitStruct->LSIState = regval & RCC_BDCR_LSION; + + /* Get Control register */ + regval = RCC->CR; /* Get the HSI48 configuration ---------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) - { - pRCC_OscInitStruct->HSI48State = RCC_HSI48_ON; - } - else - { - pRCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; - } + pRCC_OscInitStruct->HSI48State = regval & RCC_CR_HSI48ON; /* Get the PLL configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) + if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) { pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1864,17 +1946,21 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) { pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } - pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); - pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1RGE)); + + reg1val = RCC->PLL1CFGR; + reg2val = RCC->PLL1DIVR; + + pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC); + pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE)); pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); - pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1MBOOST) >> \ - RCC_PLL1CFGR_PLL1MBOOST_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1MBOOST) >> \ + RCC_PLL1CFGR_PLL1MBOOST_Pos)); } /** @@ -2153,7 +2239,6 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) else { if (msirange > RCC_MSIRANGE_2) - { if (vos == PWR_REGULATOR_VOLTAGE_SCALE4) { @@ -2174,7 +2259,6 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) else { if (msirange == RCC_MSIRANGE_1) - { if (vos == PWR_REGULATOR_VOLTAGE_SCALE3) { diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c index f28c27f868..ab25e158ba 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -46,11 +46,15 @@ #define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ +#if defined (STM32U585xx) || defined (STM32U575xx) +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */ +#else +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */ +#endif /* STM32U585xx || STM32U575xx */ -#define LSCO_GPIO_PORT GPIOA - -#define LSCO_PIN GPIO_PIN_2 +/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ +#define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */ /** * @} @@ -80,11 +84,13 @@ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) +#if defined(USART2) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) +#endif /* USART2 */ #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ @@ -104,6 +110,14 @@ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) +#if defined(USART6) +#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) +#endif /* USART6 */ + #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ @@ -135,6 +149,22 @@ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \ ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK)) +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK)) +#endif /* I2C5 */ + +#if defined(I2C6) +#define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK)) +#endif /* I2C6 */ + #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ @@ -142,12 +172,14 @@ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) +#if defined(SAI2) #define IS_RCC_SAI2CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) +#endif /* SAI2 */ #define IS_RCC_LPTIM1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \ @@ -181,9 +213,11 @@ ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI)) +#if defined(SAES) #define IS_RCC_SAESCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \ ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2)) +#endif /* SAES */ #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ @@ -213,11 +247,19 @@ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)) -#define IS_RCC_CLK48CLKSOURCE(__SOURCE__)\ - (((__SOURCE__) == RCC_CLK48CLKSOURCE_HSI48)|| \ - ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_CLK48CLKSOURCE_MSIK)) +#if defined(HSPI1) +#define IS_RCC_HSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3)) +#endif /* HSPI1 */ + +#define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\ + (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK)) #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ @@ -245,6 +287,33 @@ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#if defined(LTDC) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2)) + +#endif /* LTDC */ + +#if defined(DSI) + +#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY)) + +#endif /* DSI */ + +#if defined(USB_OTG_HS) + +#define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2)) + +#endif /* USB_OTG_HS */ + #if defined(CRS) #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ @@ -270,14 +339,18 @@ #endif /* CRS */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2); -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); /** * @} */ @@ -317,36 +390,45 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3); * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock + * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*) * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4,DAC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock - * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock + * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock + * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock + * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status + * + * (*) value not defined in all devices. */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { uint32_t tmpregister; uint32_t tickstart; @@ -366,6 +448,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection); } +#if defined(USART2) /*-------------------------- USART2 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) { @@ -375,6 +458,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection); } +#endif /* USART2 */ /*-------------------------- USART3 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) @@ -405,6 +489,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection); } +#if defined(USART6) + /*-------------------------- USART6 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection); + } +#endif /* USART6 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) @@ -456,6 +551,30 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection); } +#if defined(I2C5) + /*-------------------------- I2C5 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection)); + + /* Configure the I2C5 clock source */ + __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection); + } +#endif /* I2C5 */ + +#if defined(I2C6) + /*-------------------------- I2C6 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection)); + + /* Configure the I2C6 clock source */ + __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection); + } +#endif /* I2C6 */ + /*-------------------------- LPTIM1 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) { @@ -528,6 +647,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } } +#if defined(SAI2) /*-------------------------- SAI2 clock source configuration ---------------------*/ if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) { @@ -577,6 +697,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl status = ret; } } +#endif /* SAI2 */ /*-------------------------- ADCDAC clock source configuration ----------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC) @@ -640,7 +761,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Configure the MDF1 interface clock source */ @@ -658,7 +778,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl { /* Check the parameters */ assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection)); - switch (pPeriphClkInit->Adf1ClockSelection) { case RCC_ADF1CLKSOURCE_PLL1: @@ -679,7 +798,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Configure the ADF1 interface clock source */ @@ -698,7 +816,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl FlagStatus pwrclkchanged = RESET; /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection)); - /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -777,25 +894,25 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } } - /*-------------------------------------- CK48 Configuration -----------------------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + /*-------------------------------------- ICLK Configuration -----------------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK) { /* Check the parameters */ - assert_param(IS_RCC_CLK48CLKSOURCE(pPeriphClkInit->Clk48ClockSelection)); + assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection)); - switch (pPeriphClkInit->Clk48ClockSelection) + switch (pPeriphClkInit->IclkClockSelection) { - case RCC_CLK48CLKSOURCE_PLL2: + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); break; - case RCC_CLK48CLKSOURCE_PLL1: - /* Enable CLK48 Clock output generated from System PLL */ + case RCC_ICLK_CLKSOURCE_PLL1: + /* Enable ICLK Clock output generated from System PLL */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); break; - case RCC_CLK48CLKSOURCE_HSI48: + case RCC_ICLK_CLKSOURCE_HSI48: break; - case RCC_CLK48CLKSOURCE_MSIK: + case RCC_ICLK_CLKSOURCE_MSIK: break; default: ret = HAL_ERROR; @@ -804,7 +921,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl if (ret == HAL_OK) { /* Configure the CLK48 source */ - __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->Clk48ClockSelection); + __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection); } else { @@ -836,7 +953,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Set the source of RNG clock*/ @@ -849,6 +965,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } } +#if defined(SAES) /*-------------------------- SAES clock source configuration ----------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES) { @@ -858,6 +975,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /* Configure the SAES clock source */ __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection); } +#endif /* SAES */ /*-------------------------- SDMMC1/2 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC)) @@ -918,12 +1036,70 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2) { - /* Enable PLL2 Q CLK output */ - __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + } + if (ret == HAL_OK) + { + /* Configure the OctoSPI clock source */ + __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(HSPI1) + /*-------------------------- HSPIx kernel clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI) + { + + /* Check the parameters */ + assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection)); + + switch (pPeriphClkInit->HspiClockSelection) + { + case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/ + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/ + /* Enable 48M2 Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/ + /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of HSPI kernel clock*/ + __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; } - /* Configure the OctoSPI clock source */ - __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); } +#endif /* defined(HSPI1) */ /*-------------------------- FDCAN1 kernel clock source configuration -------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1)) @@ -964,6 +1140,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /*-------------------------- DAC1 clock source configuration ----------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1) { + /* Check the parameters */ assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection)); @@ -971,31 +1148,189 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection); } +#if defined(LTDC) + + /*-------------------------- LTDC clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection)); + + switch (pPeriphClkInit->LtdcClockSelection) + { + case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/ + /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LTDC clock source config set later after clock selection check */ + break; + + case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/ + /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LTDC clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LTDC clock*/ + __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(LTDC) */ + +#if defined(DSI) + + /*-------------------------- DSI clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + + /* Check the parameters */ + assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection)); + + if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3) + { + /* PLL3 is used as clock source for DSI clock*/ + /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(DSI) */ + +#if defined(USB_OTG_HS) + + /*-------------------------- USB PHY clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) + { + + /* Check the parameters */ + assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection)); + + switch (pPeriphClkInit->UsbPhyClockSelection) + { + case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/ + case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/ + /* USB-PHY clock source config set later after clock selection check */ + break; + + case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */ + case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */ + /* Enable P Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + /* USB-PHY clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USBPHY clock*/ + __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(USB_OTG_HS) */ + return status; } + + /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2, - * SAES, ADC1, ADC4, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1). + * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ +#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY; +#elif (defined(STM32U595xx) || defined(STM32U5A5xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY; +#elif (defined(STM32U585xx) || defined(STM32U575xx)) pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \ RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; +#else + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ + RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \ + RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; +#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ + +#if defined(SAES) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAES; +#endif /* SAES */ + /* Get the PLL2 Clock configuration -----------------------------------------------*/ pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos); pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; @@ -1021,8 +1356,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the USART1 clock source ---------------------------------------------*/ pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#if defined(USART2) /* Get the USART2 clock source ---------------------------------------------*/ pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* USART2 */ /* Get the USART3 clock source ---------------------------------------------*/ pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); @@ -1036,6 +1373,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the LPUART1 clock source --------------------------------------------*/ pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(USART6) + /* Get the UART6 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); +#endif /* defined(USART6) */ + /* Get the I2C1 clock source -----------------------------------------------*/ pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); @@ -1048,6 +1390,16 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the I2C4 clock source -----------------------------------------------*/ pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); +#if defined(I2C5) + /* Get the clock source ---------------------------------------------*/ + pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE(); +#endif /* defined(I2C5) */ + +#if defined(I2C6) + /* Get the clock source ---------------------------------------------*/ + pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE(); +#endif /* defined(I2C6) */ + /* Get the LPTIM1 clock source ---------------------------------------------*/ pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); @@ -1066,17 +1418,21 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the ADF1 clock source -----------------------------------------------*/ pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); +#if defined(SAES) /* Get the SAES clock source -----------------------------------------------*/ pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE(); +#endif /* SAES */ /* Get the SAI1 clock source -----------------------------------------------*/ pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI2) /* Get the SAI2 clock source -----------------------------------------------*/ pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); +#endif /* SAI2 */ /* Get the CLK48 clock source ----------------------------------------------*/ - pPeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE(); /* Get the SDMMC clock source ----------------------------------------------*/ pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); @@ -1104,6 +1460,26 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the RNG clock source ------------------------------------------------*/ pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + +#if defined(HSPI1) + /* Get the HSPI kernel clock source ------------------------------------------------*/ + pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE(); +#endif /* defined(HSPI1) */ + +#if defined(LTDC) + /* Get the LTDC clock source ------------------------------------------------*/ + pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* defined(LTDC) */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /* defined(DSI) */ + +#if defined(USB_OTG_HS) + /* Get the USB PHY clock source ------------------------------------------------*/ + pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE(); +#endif /* defined(USB_OTG_HS) */ } /** @@ -1133,73 +1509,64 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; - pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN; + pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); - if (pll1m != 0U) + switch (pll1source) { - switch (pll1source) - { - - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ - ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); - break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - default: - pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ - ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); - break; - } - - if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U) - { - PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ - RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \ - (float_t)1)); - } - else - { - PLL1_Clocks->PLL1_P_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U) - { - PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ - RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \ - (float_t)1)); - } - else - { - PLL1_Clocks->PLL1_Q_Frequency = 0U; - } - if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U) - { - PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ - RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \ - (float_t)1)); - } - else - { - PLL1_Clocks->PLL1_R_Frequency = 0U; - } + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ + ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + default: + pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ + ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U) + { + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \ + (float_t)1)); } else { PLL1_Clocks->PLL1_P_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U) + { + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \ + (float_t)1)); + } + else + { PLL1_Clocks->PLL1_Q_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U) + { + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \ + (float_t)1)); + } + else + { PLL1_Clocks->PLL1_R_Frequency = 0U; } + } /** @@ -1231,69 +1598,60 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; - pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN; + pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ RCC_PLL2FRACR_PLL2FRACN_Pos)); - if (pll2m != 0U) + switch (pll2source) { - switch (pll2source) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ - (fracn2 / (float_t)0x2000) + (float_t)1); - break; + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ + (fracn2 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \ - ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); - break; + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \ + ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ - (fracn2 / (float_t)0x2000) + (float_t)1); - break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ + (fracn2 / (float_t)0x2000) + (float_t)1); + break; - default: - pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \ - * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); - break; - } - if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) - { - PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ - RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \ - (float_t)1)); - } - else - { - PLL2_Clocks->PLL2_P_Frequency = 0U; - } - if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U) - { - PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ - RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \ - (float_t)1)); - } - else - { - PLL2_Clocks->PLL2_Q_Frequency = 0U; - } - if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U) - { - PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ - RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \ - (float_t)1)); - } - else - { - PLL2_Clocks->PLL2_R_Frequency = 0U; - } + default: + pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \ + * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + } + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) + { + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \ + (float_t)1)); } else { PLL2_Clocks->PLL2_P_Frequency = 0U; + } + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U) + { + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \ + (float_t)1)); + } + else + { PLL2_Clocks->PLL2_Q_Frequency = 0U; + } + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U) + { + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \ + (float_t)1)); + } + else + { PLL2_Clocks->PLL2_R_Frequency = 0U; } } @@ -1329,75 +1687,66 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U; - pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN; + pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ RCC_PLL3FRACR_PLL3FRACN_Pos)); - if (pll3m != 0U) + switch (pll3source) { - switch (pll3source) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ - (fracn3 / (float_t)0x2000) + (float_t)1); + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ + (fracn3 / (float_t)0x2000) + (float_t)1); - break; - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ - ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); - break; + break; + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ + ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ - (fracn3 / (float_t)0x2000) + (float_t)1); - break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ + (fracn3 / (float_t)0x2000) + (float_t)1); + break; - default: - pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ - ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); - break; - } - - if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U) - { - PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ - RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \ - (float_t)1)); - } - else - { - PLL3_Clocks->PLL3_P_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U) - { - PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ - RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \ - (float_t)1)); - } - else - { - PLL3_Clocks->PLL3_Q_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U) - { - PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ - RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \ - (float_t)1)); - } - else - { - PLL3_Clocks->PLL3_R_Frequency = 0U; - } + default: + pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ + ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + } + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U) + { + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \ + (float_t)1)); } else { PLL3_Clocks->PLL3_P_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U) + { + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \ + (float_t)1)); + } + else + { PLL3_Clocks->PLL3_Q_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U) + { + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \ + (float_t)1)); + } + else + { PLL3_Clocks->PLL3_R_Frequency = 0U; } + } /** @@ -1410,31 +1759,41 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock + * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4, DAC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*) * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock - * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock + * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @retval Frequency in Hz + * + * (*) value not defined in all devices. */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { PLL1_ClocksTypeDef pll1_clocks; PLL2_ClocksTypeDef pll2_clocks; @@ -1479,912 +1838,1238 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = 0U; } } - else + else if (PeriphClk == RCC_PERIPHCLK_SAI1) { - /* Other external peripheral clock source than RTC */ - switch (PeriphClk) - { - case RCC_PERIPHCLK_SAI1: - - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - - switch (srcclk) - { - case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PIN: - - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + switch (srcclk) + { + case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - default : - { - frequency = 0U; - break; - } - } + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; break; - case RCC_PERIPHCLK_SAI2: - - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - - switch (srcclk) - { - case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PIN: + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; - - case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - default : + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; - frequency = 0U; - break; + case RCC_SAI1CLKSOURCE_PIN: - } + frequency = EXTERNAL_SAI1_CLOCK_VALUE; break; - case RCC_PERIPHCLK_SAES: - /* Get the current SAES source */ - srcclk = __HAL_RCC_GET_SAES_SOURCE(); - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI)) + case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2)) - { - frequency = HSI_VALUE >> 1U; - } - /* Clock not enabled for SAES */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_CLK48: - - srcclk = __HAL_RCC_GET_CLK48_SOURCE(); - - switch (srcclk) - { - case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - - case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - - case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */ + default : + { + frequency = 0U; + break; + } + } + } +#if defined(SAI2) + else if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; + switch (srcclk) + { + case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - default : + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; - frequency = 0U; - break; + case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - } + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; break; - case RCC_PERIPHCLK_SDMMC: - srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); - if (srcclk == RCC_SDMMCCLKSOURCE_CLK48) - { - srcclk = __HAL_RCC_GET_CLK48_SOURCE(); + case RCC_SAI2CLKSOURCE_PIN: - switch (srcclk) - { - case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - } - case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */ - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - } - case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */ - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; - } - case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; - } - default : - { - frequency = 0U; - break; - } - } - break; - } - else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1) - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - } - else - { - frequency = 0U; - } + frequency = EXTERNAL_SAI1_CLOCK_VALUE; break; - case RCC_PERIPHCLK_USART1: - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); + case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ - if (srcclk == RCC_USART1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_USART2: - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); + default : - if (srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART2 */ - else - { - frequency = 0U; - } + frequency = 0U; break; + } + } +#endif /* SAI2 */ +#if defined(SAES) + else if (PeriphClk == RCC_PERIPHCLK_SAES) + { + /* Get the current SAES source */ + srcclk = __HAL_RCC_GET_SAES_SOURCE(); - case RCC_PERIPHCLK_USART3: - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI)) + { + frequency = HSI_VALUE; + } + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2)) + { + frequency = HSI_VALUE >> 1U; + } + /* Clock not enabled for SAES */ + else + { + frequency = 0U; + } + } +#endif /* SAES */ + else if (PeriphClk == RCC_PERIPHCLK_ICLK) + { + srcclk = __HAL_RCC_GET_ICLK_SOURCE(); - if (srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } + switch (srcclk) + { + case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; break; - case RCC_PERIPHCLK_UART4: - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ - if (srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; break; - case RCC_PERIPHCLK_UART5: - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); + case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ - if (srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) { - frequency = LSE_VALUE; + frequency = HSI48_VALUE; } - /* Clock not enabled for UART5 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPUART1: - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ - if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) - { - frequency = HAL_RCC_GetPCLK3Freq(); - } - else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK)) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for LPUART1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_ADCDAC: + default : - srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + if (srcclk == RCC_SDMMCCLKSOURCE_CLK48) + { + srcclk = __HAL_RCC_GET_ICLK_SOURCE(); - if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) + switch (srcclk) + { + case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ { - frequency = HAL_RCC_GetSysClockFreq(); + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; } - else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2) + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_R_Frequency; - } - else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) - { - frequency = HAL_RCC_GetHCLKFreq(); + frequency = pll2_clocks.PLL2_Q_Frequency; break; } - else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK) + case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)]; + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) + { + frequency = HSI48_VALUE; + } + else + { + frequency = 0U; + } break; } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) + case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ { - frequency = HSI_VALUE; + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; } - /* Clock not enabled for ADC */ - else + default : { frequency = 0U; + break; } - break; - - case RCC_PERIPHCLK_MDF1: - /* Get the current MDF1 source */ - srcclk = __HAL_RCC_GET_MDF1_SOURCE(); - - switch (srcclk) - { - case RCC_MDF1CLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_MDF1CLKSOURCE_PLL3: - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_Q_Frequency; - break; + } + } + else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + } + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_USART1) + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); - case RCC_MDF1CLKSOURCE_HCLK: + if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + frequency = 0U; + } + } +#if defined(USART2) + else if (PeriphClk == RCC_PERIPHCLK_USART2) + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); - frequency = HAL_RCC_GetHCLKFreq(); - break; + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2 */ + else + { + frequency = 0U; + } + } +#endif /* USART2 */ + else if (PeriphClk == RCC_PERIPHCLK_USART3) + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); - case RCC_MDF1CLKSOURCE_PIN: + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_UART4) + { + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + if (srcclk == RCC_UART4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART4 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_UART5) + { + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); - case RCC_MDF1CLKSOURCE_MSIK: + if (srcclk == RCC_UART5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + } +#if defined(USART6) + else if (PeriphClk == RCC_PERIPHCLK_USART6) + { + /* Get the current USART6 source */ + srcclk = __HAL_RCC_GET_USART6_SOURCE(); - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + if (srcclk == RCC_USART6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + } +#endif /* USART6 */ + else if (PeriphClk == RCC_PERIPHCLK_LPUART1) + { + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - default: + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for LPUART1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADCDAC) + { + srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); - frequency = 0U; - break; + if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) + { + frequency = HAL_RCC_GetHCLKFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for ADC */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_MDF1) + { + /* Get the current MDF1 source */ + srcclk = __HAL_RCC_GET_MDF1_SOURCE(); - } + switch (srcclk) + { + case RCC_MDF1CLKSOURCE_PLL1: + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; break; - case RCC_PERIPHCLK_ADF1: - /* Get the current ADF1 source */ - srcclk = __HAL_RCC_GET_ADF1_SOURCE(); + case RCC_MDF1CLKSOURCE_PLL3: - switch (srcclk) - { - case RCC_ADF1CLKSOURCE_PLL1: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + break; - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; + case RCC_MDF1CLKSOURCE_HCLK: - case RCC_ADF1CLKSOURCE_PLL3: + frequency = HAL_RCC_GetHCLKFreq(); + break; - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_Q_Frequency; - break; + case RCC_MDF1CLKSOURCE_PIN: - case RCC_ADF1CLKSOURCE_HCLK: + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; - frequency = HAL_RCC_GetHCLKFreq(); - break; + case RCC_MDF1CLKSOURCE_MSIK: - case RCC_ADF1CLKSOURCE_PIN: + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADF1) + { + /* Get the current ADF1 source */ + srcclk = __HAL_RCC_GET_ADF1_SOURCE(); - case RCC_ADF1CLKSOURCE_MSIK: + switch (srcclk) + { + case RCC_ADF1CLKSOURCE_PLL1: - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; - default: + case RCC_ADF1CLKSOURCE_PLL3: - frequency = 0U; - break; - } + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; break; - case RCC_PERIPHCLK_I2C1: - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + case RCC_ADF1CLKSOURCE_HCLK: - if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + frequency = HAL_RCC_GetHCLKFreq(); + break; + + case RCC_ADF1CLKSOURCE_PIN: + + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case RCC_ADF1CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - frequency = HSI_VALUE; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for I2C1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_I2C2: - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + default: - if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C1) + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C2) + { + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C2 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C3) + { + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + + switch (srcclk) + { + case RCC_I2C3CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_I2C3CLKSOURCE_HSI: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - frequency = HAL_RCC_GetPCLK1Freq(); + frequency = HSI_VALUE; } - else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + else { - frequency = HAL_RCC_GetSysClockFreq(); + frequency = 0U; } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + break; + } + case RCC_I2C3CLKSOURCE_SYSCLK: + { + frequency = HAL_RCC_GetSysClockFreq(); + break; + } + case RCC_I2C3CLKSOURCE_MSIK: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - frequency = HSI_VALUE; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for I2C2 */ else { frequency = 0U; } break; + } + default: + { + frequency = 0U; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C4) + { + /* Get the current I2C4 source */ + srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - case RCC_PERIPHCLK_I2C3: - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C4 */ + else + { + frequency = 0U; + } + } +#if defined (I2C5) + else if (PeriphClk == RCC_PERIPHCLK_I2C5) + { + /* Get the current I2C5 source */ + srcclk = __HAL_RCC_GET_I2C5_SOURCE(); - switch (srcclk) - { - case RCC_I2C3CLKSOURCE_PCLK3: - { - frequency = HAL_RCC_GetPCLK3Freq(); - break; - } - case RCC_I2C3CLKSOURCE_HSI: - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - } - case RCC_I2C3CLKSOURCE_SYSCLK: - { - frequency = HAL_RCC_GetSysClockFreq(); - break; - } - case RCC_I2C3CLKSOURCE_MSIK: - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)]; - break; - } - default: - { - frequency = 0U; - break; - } - } + if (srcclk == RCC_I2C5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C5 */ + else + { + frequency = 0U; + } + } +#endif /* I2C5 */ +#if defined (I2C6) + else if (PeriphClk == RCC_PERIPHCLK_I2C6) + { + /* Get the current I2C6 source */ + srcclk = __HAL_RCC_GET_I2C6_SOURCE(); + + if (srcclk == RCC_I2C6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C6 */ + else + { + frequency = 0U; + } + } +#endif /* I2C6 */ + else if (PeriphClk == RCC_PERIPHCLK_LPTIM34) + { + /* Get the current LPTIM34 source */ + srcclk = __HAL_RCC_GET_LPTIM34_SOURCE(); + + if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM34 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) + { + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) + { + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM2 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN1) + { + /* Get the current FDCAN1 kernel source */ + srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + /* Clock not enabled for FDCAN1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI1) + { + /* Get the current SPI1 kernel source */ + srcclk = __HAL_RCC_GET_SPI1_SOURCE(); + switch (srcclk) + { + case RCC_SPI1CLKSOURCE_PCLK2: + + frequency = HAL_RCC_GetPCLK2Freq(); + break; + + case RCC_SPI1CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); break; - case RCC_PERIPHCLK_I2C4: - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); + case RCC_SPI1CLKSOURCE_HSI: - if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - /* Clock not enabled for I2C4 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPTIM34: - /* Get the current LPTIM34 source */ - srcclk = __HAL_RCC_GET_LPTIM34_SOURCE(); + case RCC_SPI1CLKSOURCE_MSIK: - if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI)) + else { - frequency = LSI_VALUE; + frequency = 0U; } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI)) + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI2) + { + /* Get the current SPI2 kernel source */ + srcclk = __HAL_RCC_GET_SPI2_SOURCE(); + switch (srcclk) + { + case RCC_SPI2CLKSOURCE_PCLK1: + + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_SPI2CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI2CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM34 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPTIM1: - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + case RCC_SPI2CLKSOURCE_MSIK: - if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) - { - frequency = LSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPTIM2: - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI3) + { + /* Get the current SPI3 kernel source */ + srcclk = __HAL_RCC_GET_SPI3_SOURCE(); + switch (srcclk) + { + case RCC_SPI3CLKSOURCE_PCLK3: + + frequency = HAL_RCC_GetPCLK3Freq(); + break; + + case RCC_SPI3CLKSOURCE_SYSCLK: - if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) - { - frequency = LSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI3CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM2 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_FDCAN1: - /* Get the current FDCAN1 kernel source */ - srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + case RCC_SPI3CLKSOURCE_MSIK: - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - } - else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for FDCAN1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_SPI1: - /* Get the current SPI1 kernel source */ - srcclk = __HAL_RCC_GET_SPI1_SOURCE(); - switch (srcclk) - { - case RCC_SPI1CLKSOURCE_PCLK2: - - frequency = HAL_RCC_GetPCLK2Freq(); - break; + default: - case RCC_SPI1CLKSOURCE_SYSCLK: + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_OSPI) + { + /* Get the current OSPI kernel source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - frequency = HAL_RCC_GetSysClockFreq(); - break; + switch (srcclk) + { + case RCC_OSPICLKSOURCE_PLL2: - case RCC_SPI1CLKSOURCE_HSI: + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case RCC_OSPICLKSOURCE_PLL1: - case RCC_SPI1CLKSOURCE_MSIK: + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + case RCC_OSPICLKSOURCE_SYSCLK: - default: + frequency = HAL_RCC_GetSysClockFreq(); + break; - frequency = 0U; - break; + case RCC_OSPICLKSOURCE_MSIK: + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - break; - - case RCC_PERIPHCLK_SPI2: - /* Get the current SPI2 kernel source */ - srcclk = __HAL_RCC_GET_SPI2_SOURCE(); - switch (srcclk) + else { - case RCC_SPI2CLKSOURCE_PCLK1: - - frequency = HAL_RCC_GetPCLK1Freq(); - break; - - case RCC_SPI2CLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_SPI2CLKSOURCE_HSI: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_SPI2CLKSOURCE_MSIK: - - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; - - default: - - frequency = 0U; - break; - + frequency = 0U; } break; - case RCC_PERIPHCLK_SPI3: - /* Get the current SPI3 kernel source */ - srcclk = __HAL_RCC_GET_SPI3_SOURCE(); - switch (srcclk) - { - case RCC_SPI3CLKSOURCE_PCLK3: - - frequency = HAL_RCC_GetPCLK3Freq(); - break; + default: - case RCC_SPI3CLKSOURCE_SYSCLK: + frequency = 0U; + break; + } + } +#if defined(HSPI1) - frequency = HAL_RCC_GetSysClockFreq(); - break; + else if (PeriphClk == RCC_PERIPHCLK_HSPI) + { + /* Get the current HSPI kernel source */ + srcclk = __HAL_RCC_GET_HSPI_SOURCE(); - case RCC_SPI3CLKSOURCE_HSI: + switch (srcclk) + { + case RCC_HSPICLKSOURCE_SYSCLK: - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + frequency = HAL_RCC_GetSysClockFreq(); + break; - case RCC_SPI3CLKSOURCE_MSIK: + case RCC_HSPICLKSOURCE_PLL1: - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; - default: + case RCC_HSPICLKSOURCE_PLL2: - frequency = 0U; - break; - } + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; break; + case RCC_HSPICLKSOURCE_PLL3: - case RCC_PERIPHCLK_OSPI: - /* Get the current OSPI kernel source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - - switch (srcclk) - { - case RCC_OSPICLKSOURCE_PLL2: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; + default: - case RCC_OSPICLKSOURCE_PLL1: + frequency = 0U; + break; + } + } +#endif /* defined(HSPI1) */ + else if (PeriphClk == RCC_PERIPHCLK_DAC1) + { + /* Get the current DAC1 kernel source */ + srcclk = __HAL_RCC_GET_DAC1_SOURCE(); - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; + /* Check if LSE is ready and if DAC1 clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if DAC1 clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + /* Clock not enabled for DAC1*/ + else + { + frequency = 0U; + } - case RCC_OSPICLKSOURCE_SYSCLK: + } + else if (PeriphClk == RCC_PERIPHCLK_RNG) + { + /* Get the current RNG kernel source */ + srcclk = __HAL_RCC_GET_RNG_SOURCE(); - frequency = HAL_RCC_GetSysClockFreq(); - break; + /* Check if HSI48 is ready and if RNG clock selection is HSI48 */ + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } - case RCC_OSPICLKSOURCE_MSIK: + /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2)) + { + frequency = HSI48_VALUE >> 1U ; + } - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + /* Check if HSI is ready and if RNG clock selection is HSI */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for RNG */ + else + { + frequency = 0U; + } + } +#if defined(LTDC) + else if (PeriphClk == RCC_PERIPHCLK_LTDC) + { + /* Get the current LTDC kernel source */ + srcclk = __HAL_RCC_GET_LTDC_SOURCE(); - default: + switch (srcclk) + { + case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */ - frequency = 0U; - break; - } + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; break; - case RCC_PERIPHCLK_DAC1: - /* Get the current DAC1 kernel source */ - srcclk = __HAL_RCC_GET_DAC1_SOURCE(); - /* Check if LSE is ready and if DAC1 clock selection is LSE */ - if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if DAC1 clock selection is LSI */ - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI)) - { - frequency = LSI_VALUE; - } - /* Clock not enabled for DAC1*/ - else - { - frequency = 0U; - } + case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */ + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; break; default: - frequency = 0U; + + frequency = 0U; break; } } +#endif /* defined(LTDC) */ + +#if defined(USB_OTG_HS) + + else if (PeriphClk == RCC_PERIPHCLK_USBPHY) + { + /* Get the current USB_OTG_HS kernel source */ + srcclk = __HAL_RCC_GET_USBPHY_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2)) + { + frequency = HSE_VALUE >> 1U ; + } + else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + } + else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = (pll1_clocks.PLL1_P_Frequency) / 2U; + } + /* Clock not enabled for USB_OTG_HS */ + else + { + frequency = 0U; + } + } +#endif /* defined(USB_OTG_HS) */ + + else + { + frequency = 0; + } return (frequency); } -/** - * @} - */ /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions @@ -2407,7 +3092,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) * contains the configuration information for the PLL2 * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; @@ -2481,6 +3166,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) } } } + return status; } @@ -2522,7 +3208,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) * contains the configuration information for the PLL3 * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init) +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; @@ -2594,6 +3280,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init) } } } + return status; } @@ -2740,7 +3427,7 @@ void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) * This parameter can be one of the following values: * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value) * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz - * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.5 MHz + * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz * @retval None @@ -2752,6 +3439,25 @@ void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); } +/** + * @brief Configure the MSIK range after standby mode. + * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz). + * @param MSIKRange MSIK range + * This parameter can be one of the following values: + * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value) + * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz + * @retval None + */ +void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange) +{ + assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange)); + + __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange); +} + /** * @brief Enable the LSE Clock Security System. * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled @@ -2774,15 +3480,57 @@ void HAL_RCCEx_DisableLSECSS(void) CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); } +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line + * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable IT on LSECSS EXTI Line */ + SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS); + /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */ + SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS); +} + /** * @brief Handle the RCC LSE Clock Security System interrupt request. + * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. * @retval None */ void HAL_RCCEx_LSECSS_IRQHandler(void) { + uint32_t falling_edge_flag; + uint32_t rising_edge_flag; + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U) { - /* RCC LSE Clock Security System interrupt user callback */ + /* Read Falling Edge flag on LSECSS EXTI interrupt */ + falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); + + /* Read Rising Edge flag on LSECSS EXTI interrupt */ + rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); + + /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */ + if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \ + (rising_edge_flag == RCC_EXTI_LINE_LSECSS)) + { + if (rising_edge_flag == RCC_EXTI_LINE_LSECSS) + { + /* Clear the RCC LSECSS EXTI Rising Edge flag */ + WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); + } + if (falling_edge_flag == RCC_EXTI_LINE_LSECSS) + { + /* Clear the RCC LSECSS EXTI Falling Edge flag */ + WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); + } + } + /* RCC LSECSS interrupt user callback */ HAL_RCCEx_LSECSS_Callback(); } } @@ -2798,6 +3546,61 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) */ } +/** + * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line. + * @note MSI PLL Unlock Interrupt is mapped on EXTI line + * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void) +{ + /* Enable IT on MSI PLL Unlock EXTI Line */ + SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK); + /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */ + SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK); +} + +/** + * @brief Handle the RCC MSI PLL Unlock interrupt request. + * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void) +{ + uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + + /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */ + if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \ + (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)) + { + if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) + { + /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */ + WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + } + if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) + { + /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */ + WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + } + /* RCC MSI PLL Unlock interrupt user callback */ + HAL_RCCEx_MSIPLLUNLCK_Callback(); + } +} + +/** + * @brief RCCEx RCC MSI PLL Unlock interrupt callback. + * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval none + */ +__weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file + */ +} + /** * @brief Select the Low Speed clock source to output on LSCO pin (PA2). * @param LSCOSource specifies the Low Speed clock source to output. @@ -2808,23 +3611,12 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { - GPIO_InitTypeDef gpio_initstruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); - /* LSCO Pin Clock Enable */ - LSCO_CLK_ENABLE(); - - /* Configure the LSCO pin in analog mode */ - gpio_initstruct.Pin = LSCO_PIN; - gpio_initstruct.Mode = GPIO_MODE_ANALOG; - gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH; - gpio_initstruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(LSCO_GPIO_PORT, &gpio_initstruct); - /* Update LSCOSEL clock source in Backup Domain control register */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -2905,7 +3697,6 @@ void HAL_RCCEx_DisableMSIPLLMode(void) { CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); } - /** * @} */ @@ -2931,7 +3722,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and sychronization frequencies values + directly reload value with target and synchronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration @@ -3370,11 +4161,11 @@ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that * contains the configuration parameters as well as VCI clock ranges. - * @note PLL2 is temporary disable to apply new parameters + * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2) +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2) { uint32_t tickstart; @@ -3442,13 +4233,13 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2) } /** - * @brief Configure the parameters N & P & optionally M of PLL3 and enable PLL3 output clock(s). - * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that - * contains the configuration parameters N & P & optionally M as well as PLL3 output clock(s) - * @note PLL3 is temporary disable to apply new parameters + * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI clock ranges. + * @note PLL3 is temporary disabled to apply new parameters * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3) +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3) { uint32_t tickstart; assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source)); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c index 6a033c47ab..b8546c5bc2 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -43,8 +43,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. - Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : RNG Error Callback. (+) MspInitCallback : RNG MspInit. (+) MspDeInitCallback : RNG MspDeInit. @@ -52,9 +52,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : RNG Error Callback. @@ -63,16 +63,16 @@ [..] For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). [..] - By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: - example @ref HAL_RNG_ErrorCallback(). + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (overridden) functions: + example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() - and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -81,13 +81,13 @@ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() - or @ref HAL_RNG_Init() function. + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -201,7 +201,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); - /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -387,8 +386,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -442,14 +439,12 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -462,8 +457,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -517,8 +510,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -681,8 +672,9 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t be used as it may not have enough entropy */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { - /* Update the error code */ + /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; + status = HAL_ERROR; /* Clear bit DRDY */ CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } @@ -762,18 +754,19 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Check if Seed Error Current Status (SECS) is set */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS) { /* RNG IP performed the reset automatically (auto-reset) */ /* Clear bit SEIS */ @@ -813,7 +806,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -845,7 +838,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -912,7 +905,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -922,7 +915,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; @@ -1032,3 +1025,4 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c index cc787144fc..f5a72796af 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c @@ -11,7 +11,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -31,7 +31,7 @@ #if defined(RNG) -/** @addtogroup RNGEx +/** @addtogroup RNG_Ex * @brief RNG Extended HAL module driver. * @{ */ @@ -42,7 +42,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @addtogroup RNG_Ex_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -54,11 +54,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNGEx_Exported_Functions +/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -78,12 +78,12 @@ * RNG_ConfigTypeDef. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains * the configuration information for RNG module * @retval HAL status */ -HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf) { uint32_t tickstart; uint32_t cr_value; @@ -124,7 +124,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos)); MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 - | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3, + | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS, (uint32_t)(RNG_CR_CONDRST | cr_value)); /* RNG health test control in accordance with NIST */ @@ -174,7 +174,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef * RNG_ConfigTypeDef. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains * the configuration information for RNG module * @retval HAL status @@ -270,12 +270,12 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim =============================================================================== - ##### Configuration and lock functions ##### + ##### Recover from seed error function ##### =============================================================================== [..] This section provide function allowing to: (+) Recover from a seed error @@ -337,3 +337,4 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c index 062162fbb6..7edd7bed06 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c @@ -18,7 +18,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -26,7 +26,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ******************************************************************************* + ****************************************************************************** @verbatim =============================================================================== ##### RTC Operating Condition ##### @@ -363,39 +363,50 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check if the calendar has been not initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); - - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* Calendar is already initialized */ + /* Set flag to OK */ + status = HAL_OK; + } if (status == HAL_OK) { + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } } @@ -1057,7 +1068,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1071,7 +1082,7 @@ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1085,12 +1096,10 @@ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); SET_BIT(RTC->CR, RTC_CR_BKP); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** @@ -1098,12 +1107,10 @@ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); CLEAR_BIT(RTC->CR, RTC_CR_BKP); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** @@ -1111,7 +1118,7 @@ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval operation see RTC_StoreOperation_Definitions */ -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); return READ_BIT(RTC->CR, RTC_CR_BKP); @@ -1142,20 +1149,21 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; UNUSED(hrtc); - /* Get subseconds structure field from the corresponding register*/ + /* Get subseconds structure field from the corresponding register */ sTime->SubSeconds = READ_REG(RTC->SSR); + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) { /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Get SecondFraction structure field from the corresponding register field*/ + /* Get SecondFraction structure field from the corresponding register field */ sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S); /* Get the TR register */ @@ -1176,6 +1184,15 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); } } + else + { + /* Initialize structure fields */ + sTime->Hours = 0U; + sTime->Minutes = 0U; + sTime->Seconds = 0U; + sTime->TimeFormat = 0U; + sTime->SecondFraction = 0U; + } return HAL_OK; } @@ -1274,7 +1291,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1446,8 +1463,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } } - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) @@ -1516,8 +1531,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA SET_BIT(RTC->CR, RTC_CR_ALRBE); } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1656,8 +1669,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } } - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm registers */ if (sAlarm->Alarm == RTC_ALARM_A) @@ -1728,8 +1739,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; @@ -1758,8 +1767,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ if (Alarm == RTC_ALARM_A) @@ -1775,8 +1782,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; @@ -1800,7 +1805,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, + uint32_t Format) { uint32_t tmpreg; uint32_t subsecondtmpreg; @@ -1868,7 +1874,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) /* Get interrupt status */ uint32_t tmp = READ_REG(RTC->SMISR); - if ((tmp & RTC_SMISR_ALRAMF) != 0u) + if ((tmp & RTC_SMISR_ALRAMF) != 0U) { /* Clear the AlarmA interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); @@ -1880,7 +1886,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } - if ((tmp & RTC_SMISR_ALRBMF) != 0u) + if ((tmp & RTC_SMISR_ALRBMF) != 0U) { /* Clear the AlarmB interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); @@ -1961,8 +1967,11 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) @@ -1971,8 +1980,15 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -1980,9 +1996,6 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T /* Clear the Alarm interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - return HAL_OK; } @@ -2023,7 +2036,6 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart; - UNUSED(hrtc); /* Clear RSF flag */ CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); @@ -2034,7 +2046,17 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -2064,7 +2086,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) { /* Return RTC handle state */ return hrtc->State; @@ -2092,7 +2114,6 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; - UNUSED(hrtc); /* Check if the Initialization mode is set */ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { @@ -2105,8 +2126,18 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + status = HAL_TIMEOUT; + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + else + { + break; + } } } } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c index 8d450bb2fc..83335c2fe3 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -186,14 +186,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /* Get the RTC_CR register and clear the bits to be configured */ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Time Stamp TSEDGE and Enable bits */ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -237,8 +233,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Get the RTC_CR register and clear the bits to be configured */ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); @@ -246,8 +240,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Enable timestamp and IT */ SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; @@ -269,14 +261,10 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; @@ -299,14 +287,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the internal Time Stamp Enable bits */ SET_BIT(RTC->CR, RTC_CR_ITSE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -327,16 +311,13 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the internal Time Stamp Enable bits */ CLEAR_BIT(RTC->CR, RTC_CR_ITSE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; @@ -361,8 +342,9 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe RTC_DateTypeDef *sTimeStampDate, uint32_t Format) { uint32_t tmptime; - uint32_t tmpdate; + uint32_t tmpdate; + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -404,41 +386,19 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe return HAL_OK; } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** - * @brief Handle TimeStamp secure interrupt request. + * @brief Handle TimeStamp interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Get the pending status of the TimeStamp Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call TimeStampEvent registered Callback */ - hrtc->TimeStampEventCallback(hrtc); #else - HAL_RTCEx_TimeStampEventCallback(hrtc); -#endif /*(USE_HAL_RTC_REGISTER_CALLBACKS == 1)*/ - /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when - TSF bit is reset.*/ - WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Handle TimeStamp non-secure interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U) +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call TimeStampEvent registered Callback */ @@ -447,14 +407,13 @@ void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_TimeStampEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when - TSF bit is reset.*/ + TSF bit is reset.*/ WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); } /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief TimeStamp callback. @@ -479,6 +438,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) @@ -488,9 +450,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /* Clear the TIMESTAMP OverRun Flag */ WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - return HAL_ERROR; } @@ -498,15 +457,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - return HAL_OK; } @@ -546,10 +509,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Clear WUTE in RTC_CR to disable the wakeup timer */ CLEAR_BIT(RTC->CR, RTC_CR_WUTE); @@ -560,19 +522,27 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -586,9 +556,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Enable the Wakeup Timer */ SET_BIT(RTC->CR, RTC_CR_WUTE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -622,10 +591,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Clear WUTE in RTC_CR to disable the wakeup timer */ CLEAR_BIT(RTC->CR, RTC_CR_WUTE); @@ -643,15 +611,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -665,9 +640,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -688,36 +662,44 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Disable the Wakeup Timer */ /* In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -733,46 +715,25 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Get the counter value */ return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** - * @brief Handle Wake Up Timer secure interrupt request. + * @brief Handle Wake Up Timer interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - if ((RTC->SMISR & RTC_SMISR_WUTMF) != 0u) - { - /* Immediately clear flags */ - WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call wake up timer registered Callback */ - hrtc->WakeUpTimerEventCallback(hrtc); + /* Get the pending status of the Wake-Up Timer Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_WUTMF) != 0U) #else - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Handle Wake Up Timer non-secure interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get the pending status of the WAKEUPTIMER Interrupt */ if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { /* Clear the WAKEUPTIMER interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); @@ -789,7 +750,6 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Wake Up Timer callback. @@ -806,7 +766,6 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) */ } - /** * @brief Handle Wake Up Timer Polling. * @param hrtc RTC handle @@ -815,6 +774,9 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) @@ -823,8 +785,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -870,8 +839,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @{ */ - - /** * @brief Set the Smooth calibration parameters. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses @@ -879,7 +846,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * SmoothCalibMinusPulsesValue must be equal to 0. * @param hrtc RTC handle * @param SmoothCalibPeriod Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : + * This parameter can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. @@ -904,23 +871,20 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* check if a calibration is pending*/ - if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) - { - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); - /* check if a calibration is pending*/ - while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + /* check if a calibration is pending */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -930,8 +894,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo return HAL_TIMEOUT; } + else + { + break; + } } } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Smooth calibration settings */ MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), @@ -966,6 +936,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t L /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1009,30 +980,39 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); tickstart = HAL_GetTick(); - /* Wait until the shift is completed*/ + /* Wait until the shift is completed */ while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } } } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Check if the reference clock detection is disabled */ if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) { @@ -1047,6 +1027,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; /* Process Unlocked */ @@ -1099,10 +1080,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32 /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the RTC_CR register */ MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput); @@ -1110,8 +1090,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32 /* Enable calibration output */ SET_BIT(RTC->CR, RTC_CR_COE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1132,16 +1110,13 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Disable calibration output */ CLEAR_BIT(RTC->CR, RTC_CR_COE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1164,6 +1139,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1185,6 +1161,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) if (status == HAL_OK) { + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1206,6 +1183,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1227,6 +1205,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) if (status == HAL_OK) { + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1248,16 +1227,13 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ SET_BIT(RTC->CR, RTC_CR_BYPSHAD); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1280,16 +1256,13 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1310,6 +1283,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); UNUSED(Instance); /* This register is read-only only and is incremented by one when a write access is done to this @@ -1330,6 +1304,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, u */ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); UNUSED(Instance); @@ -1350,17 +1325,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Enable IT SSRU */ __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1379,17 +1352,15 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_TS); + __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1398,7 +1369,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) return HAL_OK; } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Handle SSR underflow interrupt request. * @param hrtc RTC handle @@ -1406,10 +1376,15 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) { - if ((RTC->SMISR & RTC_SMISR_SSRUMF) != 0u) + /* Get the pending status of the SSR Underflow Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_SSRUMF) != 0U) +#else + if (READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) != 0U) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { - /* Immediately clear flags */ - RTC->SCR = RTC_SCR_CSSRUF; + /* Immediately clear SSR underflow flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); /* SSRU callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -1424,32 +1399,7 @@ void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#else -/** - * @brief Handle SSR underflow interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) - { - /* Immediately clear flags */ - RTC->SCR = RTC_SCR_CSSRUF; - /* SSRU callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call SSRUEvent registered Callback */ - hrtc->SSRUEventCallback(hrtc); -#else - HAL_RTCEx_SSRUEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief SSR underflow callback. * @param hrtc RTC handle @@ -1505,8 +1455,11 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) @@ -1515,8 +1468,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -1524,9 +1484,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /* Clear the Alarm Flag */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - return HAL_OK; } @@ -1623,9 +1580,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /* Timestamp on tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) { - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* Control register 1 */ @@ -1695,9 +1650,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Timestamp on tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) { - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* Interrupt enable register */ @@ -1785,9 +1738,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active CR = READ_REG(RTC->CR); if ((CR & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection)) { - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } CR1 = READ_REG(TAMP->CR1); @@ -1824,7 +1775,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active } /* Configure ATOSELx[] in case of output sharing */ - ATCR2 |= sAllTamper->TampInput[i].Output << ((3u * i) + TAMP_ATCR2_ATOSEL1_Pos); + ATCR2 |= sAllTamper->TampInput[i].Output << ((3U * i) + TAMP_ATCR2_ATOSEL1_Pos); if (i != sAllTamper->TampInput[i].Output) { @@ -1846,14 +1797,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]); } - /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ tickstart = HAL_GetTick(); - while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0u) + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -1907,14 +1868,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe WRITE_REG(TAMP->ATSEEDR, pSeed[i]); } - /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ tickstart = HAL_GetTick(); while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -1930,6 +1901,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe */ HAL_StatusTypeDef HAL_RTCEx_SetBoothardwareKey(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK); @@ -1987,7 +1959,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); uint32_t tickstart = HAL_GetTick(); @@ -1999,7 +1973,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -2030,11 +2012,11 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_Inter /* timestamp on internal tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) { - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + /* No Erase Backup register enable for Internal Tamper */ if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { /* Control register 3 */ @@ -2089,9 +2071,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_In /* timestamp on internal tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) { - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* Interrupt enable register */ @@ -2121,7 +2101,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_In */ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); /* Disable the selected Tamper pin */ @@ -2147,7 +2129,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui */ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); uint32_t tickstart = HAL_GetTick(); @@ -2159,7 +2143,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -2170,22 +2162,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, return HAL_OK; } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @brief Handle Tamper secure interrupt request. +/** + * @brief Handle Tamper interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) { - uint32_t tmp; - - /* Get secure interrupt status */ - tmp = READ_REG(TAMP->SMISR); - - /* Immediately clear flags */ - WRITE_REG(TAMP->SCR, tmp); + /* Get the pending status of the Tampers Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t tmp = READ_REG(TAMP->SMISR); +#else + uint32_t tmp = READ_REG(TAMP->MISR); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Check Tamper1 status */ if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) @@ -2413,247 +2402,10 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_InternalTamper13EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -} - - -#else -/** - * @brief Handle Tamper non-secure interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get interrupt status */ - uint32_t tmp = READ_REG(TAMP->MISR); - /* Immediately clear flags */ + /* Clear flags after treatment to allow the potential tamper feature */ WRITE_REG(TAMP->SCR, tmp); - - /* Check Tamper1 status */ - if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 1 Event registered Callback */ - hrtc->Tamper1EventCallback(hrtc); -#else - /* Tamper1 callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper2 status */ - if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 2 Event registered Callback */ - hrtc->Tamper2EventCallback(hrtc); -#else - /* Tamper2 callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper3 status */ - if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 3 Event registered Callback */ - hrtc->Tamper3EventCallback(hrtc); -#else - /* Tamper3 callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper4 status */ - if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 4 Event registered Callback */ - hrtc->Tamper4EventCallback(hrtc); -#else - /* Tamper4 callback */ - HAL_RTCEx_Tamper4EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper5 status */ - if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 5 Event registered Callback */ - hrtc->Tamper5EventCallback(hrtc); -#else - /* Tamper5 callback */ - HAL_RTCEx_Tamper5EventCallback(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ - } - - /* Check Tamper6 status */ - if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 6 Event registered Callback */ - hrtc->Tamper6EventCallback(hrtc); -#else - /* Tamper6 callback */ - HAL_RTCEx_Tamper6EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper7 status */ - if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 7 Event registered Callback */ - hrtc->Tamper7EventCallback(hrtc); -#else - /* Tamper7 callback */ - HAL_RTCEx_Tamper7EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper8 status */ - if ((tmp & RTC_TAMPER_8) == RTC_TAMPER_8) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 8 Event registered Callback */ - hrtc->Tamper8EventCallback(hrtc); -#else - /* Tamper8 callback */ - HAL_RTCEx_Tamper8EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper1 status */ - if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 1 Event registered Callback */ - hrtc->InternalTamper1EventCallback(hrtc); -#else - /* Internal Tamper1 callback */ - HAL_RTCEx_InternalTamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper2 status */ - if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 2 Event registered Callback */ - hrtc->InternalTamper2EventCallback(hrtc); -#else - /* Internal Tamper2 callback */ - HAL_RTCEx_InternalTamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper3 status */ - if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 3 Event registered Callback */ - hrtc->InternalTamper3EventCallback(hrtc); -#else - /* Internal Tamper3 callback */ - HAL_RTCEx_InternalTamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper5 status */ - if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 5 Event registered Callback */ - hrtc->InternalTamper5EventCallback(hrtc); -#else - /* Internal Tamper5 callback */ - HAL_RTCEx_InternalTamper5EventCallback(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ - } - /* Check Internal Tamper6 status */ - if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 6 Event registered Callback */ - hrtc->InternalTamper6EventCallback(hrtc); -#else - /* Internal Tamper6 callback */ - HAL_RTCEx_InternalTamper6EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper7 status */ - if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 7 Event registered Callback */ - hrtc->InternalTamper7EventCallback(hrtc); -#else - /* Internal Tamper7 callback */ - HAL_RTCEx_InternalTamper7EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper8 status */ - if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 8 Event registered Callback */ - hrtc->InternalTamper8EventCallback(hrtc); -#else - /* Internal Tamper8 callback */ - HAL_RTCEx_InternalTamper8EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper9 status */ - if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 9 Event registered Callback */ - hrtc->InternalTamper9EventCallback(hrtc); -#else - /* Internal Tamper9 callback */ - HAL_RTCEx_InternalTamper9EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper11 status */ - if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 11 Event registered Callback */ - hrtc->InternalTamper11EventCallback(hrtc); -#else - /* Internal Tamper11 callback */ - HAL_RTCEx_InternalTamper11EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper12 status */ - if ((tmp & RTC_INT_TAMPER_12) == RTC_INT_TAMPER_12) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 12 Event registered Callback */ - hrtc->InternalTamper12EventCallback(hrtc); -#else - /* Internal Tamper12 callback */ - HAL_RTCEx_InternalTamper12EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper13 status */ - if ((tmp & RTC_INT_TAMPER_13) == RTC_INT_TAMPER_13) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 13 Event registered Callback */ - hrtc->InternalTamper13EventCallback(hrtc); -#else - /* Internal Tamper13 callback */ - HAL_RTCEx_InternalTamper13EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Tamper 1 callback. @@ -2670,7 +2422,6 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) */ } - /** * @brief Tamper 2 callback. * @param hrtc RTC handle @@ -2956,7 +2707,7 @@ __weak void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc) [..] (+) Before calling any tamper or internal tamper function, you have to call first HAL_RTC_Init() function. - (+) In that ine you can select to output tamper event on RTC pin. + (+) In that one you can select to output tamper event on RTC pin. [..] This subsection provides functions allowing to (+) Write a data in a specified RTC Backup data register @@ -2978,7 +2729,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 { uint32_t tmp; + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); @@ -3001,6 +2754,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) { uint32_t tmp; + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); @@ -3114,6 +2868,7 @@ uint32_t HAL_RTCEx_Get_Erase_SecretDev_Conf(void) */ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Read registers */ uint32_t rtc_seccfgr = READ_REG(RTC->SECCFGR); @@ -3123,7 +2878,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureSta secureState->rtcSecureFull = READ_BIT(rtc_seccfgr, RTC_SECCFGR_SEC); /* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */ - secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_ALL); + secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_NONE); /* TAMP */ secureState->tampSecureFull = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_TAMPSEC); @@ -3150,6 +2905,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureSta */ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull)); assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures)); @@ -3202,6 +2958,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureSta */ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull)); assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures)); @@ -3243,12 +3000,14 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_Privil */ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* Read registers */ uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR); uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR); uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR); - UNUSED(hrtc); /* RTC privilege configuration */ privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c index ab262704a4..9eb4e1b19c 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -88,8 +88,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -107,9 +107,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -128,16 +128,16 @@ [..] For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -146,16 +146,17 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -197,8 +198,9 @@ /** @addtogroup UART_Private_Functions * @{ */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); @@ -209,6 +211,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); @@ -348,15 +351,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In asynchronous mode, the following bits must be kept cleared: @@ -413,15 +418,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In half-duplex mode, the following bits must be kept cleared: @@ -499,15 +506,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In LIN mode, the following bits must be kept cleared: @@ -583,15 +592,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In multiprocessor mode, the following bits must be kept cleared: @@ -656,6 +667,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -695,7 +707,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief Register a User UART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -727,8 +742,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_READY) { switch (CallbackID) @@ -814,14 +827,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -844,8 +858,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -933,8 +945,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } @@ -1110,10 +1120,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -1124,8 +1134,14 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u return HAL_ERROR; } - __HAL_LOCK(huart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1139,7 +1155,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1147,12 +1163,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1170,6 +1187,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1214,8 +1233,14 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - __HAL_LOCK(huart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1242,13 +1267,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* as long as data have to be received */ while (huart->RxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1285,7 +1310,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1295,8 +1320,14 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - __HAL_LOCK(huart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1318,8 +1349,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } @@ -1335,8 +1364,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } @@ -1369,11 +1396,17 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ if (!(IS_LPUART_INSTANCE(huart->Instance))) { /* Check that USART RTOEN bit is set */ @@ -1392,6 +1425,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Send an amount of data in DMA mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), @@ -1402,7 +1436,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef status; uint16_t nbByte = Size; @@ -1415,8 +1449,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat return HAL_ERROR; } - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1480,8 +1512,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; @@ -1491,8 +1521,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1527,8 +1555,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1560,26 +1586,54 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - __HAL_LOCK(huart); - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - /* Disable the UART DMA Tx request */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } } if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Disable the UART DMA Rx request */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; - __HAL_UNLOCK(huart); + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } return HAL_OK; } @@ -1591,12 +1645,19 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_BUSY_TX) { - /* Enable the UART DMA Tx request */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } } if (huart->RxState == HAL_UART_STATE_BUSY_RX) { @@ -1604,14 +1665,24 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Enable the UART DMA Rx request */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); + return HAL_ERROR; + } + } + } return HAL_OK; } @@ -1683,6 +1754,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) return HAL_OK; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Abort ongoing transfers (blocking mode). @@ -1709,11 +1781,15 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) { @@ -1734,11 +1810,14 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) { @@ -1758,6 +1837,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0U; @@ -1803,11 +1883,15 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) { @@ -1827,6 +1911,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx transfer counter */ huart->TxXferCount = 0U; @@ -1867,11 +1952,15 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) { @@ -1891,6 +1980,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Rx transfer counter */ huart->RxXferCount = 0U; @@ -1937,6 +2027,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } +#if defined(HAL_DMA_MODULE_ENABLED) /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -1968,12 +2059,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) { @@ -1992,11 +2085,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) { @@ -2015,6 +2111,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) @@ -2080,11 +2177,15 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) { @@ -2121,6 +2222,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Tx transfer counter */ huart->TxXferCount = 0U; @@ -2176,11 +2278,15 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) { @@ -2224,6 +2330,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Rx transfer counter */ huart->RxXferCount = 0U; @@ -2357,11 +2464,15 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - /* Disable the UART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) { @@ -2390,6 +2501,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Call user error callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2427,6 +2539,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); +#if defined(HAL_DMA_MODULE_ENABLED) /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -2448,10 +2561,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -2461,6 +2576,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); @@ -2473,6 +2593,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } else { +#endif /* HAL_DMA_MODULE_ENABLED */ /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ @@ -2494,6 +2615,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxISR = NULL; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2503,7 +2629,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; +#if defined(HAL_DMA_MODULE_ENABLED) } +#endif /* HAL_DMA_MODULE_ENABLED */ } /* UART in mode Transmitter ------------------------------------------------*/ @@ -2960,7 +3088,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1; uint32_t temp2; @@ -2976,7 +3104,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3130,7 +3258,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); @@ -3150,10 +3278,10 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) if (pclk != 0U) { /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { - huart->Instance->BRR = usartdiv; + huart->Instance->BRR = (uint16_t)usartdiv; } else { @@ -3183,6 +3311,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { @@ -3204,13 +3339,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { @@ -3218,12 +3346,14 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } +#if defined(HAL_DMA_MODULE_ENABLED) /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) @@ -3268,6 +3398,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3279,6 +3416,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3288,6 +3434,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -3295,10 +3442,11 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /** - * @brief Handle UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart UART handle. * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -3314,35 +3462,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); return HAL_TIMEOUT; } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; /* Process Unlocked */ @@ -3396,10 +3548,11 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -3414,14 +3567,20 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } return HAL_OK; } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Start Receive operation in DMA mode. * @note This function could be called by all HAL UART API providing reception in DMA mode. @@ -3500,18 +3659,18 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } } - __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3538,6 +3697,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** @@ -3566,6 +3726,7 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA UART transmit process complete callback. * @param hdma DMA handle. @@ -3580,10 +3741,12 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { huart->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } @@ -3636,10 +3799,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3650,6 +3815,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3684,6 +3853,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3942,6 +4115,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) HAL_UART_AbortReceiveCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief TX interrupt handler for 7 or 8 bits data word length . @@ -3981,7 +4155,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -3996,7 +4170,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } else { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4053,7 +4227,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -4073,7 +4247,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4144,6 +4318,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4159,6 +4346,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4223,6 +4411,19 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4238,6 +4439,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4353,6 +4555,19 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4368,6 +4583,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4503,6 +4719,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4518,6 +4747,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4576,3 +4806,4 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /** * @} */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c index 9ddf46c2ac..a8395d4a75 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -38,6 +38,7 @@ configured prior starting RX/TX transfers. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -211,15 +212,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ @@ -703,11 +706,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -731,8 +733,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -749,6 +749,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -814,7 +815,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -824,29 +825,24 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; - status = UART_Start_Receive_IT(huart, pData, Size); + (void)UART_Start_Receive_IT(huart, pData, Size); - /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status; @@ -857,6 +853,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Receive an amount of data in DMA mode till either the expected number * of data is received or an IDLE event occurs. @@ -886,10 +883,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -918,6 +914,37 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} /** * @brief Set autonomous mode Configuration. @@ -925,7 +952,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * @param sConfig Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig) { uint32_t tmpreg; @@ -987,7 +1015,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, * @param sConfig Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, + UART_AutonomousModeConfTypeDef *sConfig) { uint32_t tmpreg; @@ -1114,3 +1143,4 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) /** * @} */ + diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c index aa0bc97c1c..ff5b4ea9dd 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c @@ -11,14 +11,15 @@ * ****************************************************************************** * @attention - * - * Copyright (c) 2021 STMicroelectronics. + * + * Copyright (c) 2021 - 2025 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause + * ****************************************************************************** @verbatim ============================================================================== @@ -55,12 +56,12 @@ * @{ */ -/** @defgroup DLYB DLYB +/** @defgroup DLYB_LL DLYB * @brief DLYB LL module driver. * @{ */ -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED) +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) /** @cond 0 @@ -230,7 +231,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c /** * @} */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */ +#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** * @} From f247241badd3cd80ab47475578c3d2a7dbc7999c Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Mon, 30 Jun 2025 17:00:27 +0200 Subject: [PATCH 079/133] [zep fromtree] STM32U5 : update HAL on U5 to version 1.6.1 Change-Id: I54cae301cd6cabc23a7fc047442a4962b972c5e7 Signed-off-by: Ahmad EL JOUAID (cherry picked from commit f8744e5d8e8d612b18b2de9c22dd0938446b942a) --- .../b_u585i_iot02a/partition/flash_layout.h | 2 +- .../Components/mx25lm51245g/mx25lm51245g.h | 2 +- .../stm32u5xx/Device/Include/stm32u585xx.h | 10757 ++++++++-------- .../stm32u5xx/Device/Include/stm32u5xx.h | 16 +- .../Device/Include/system_stm32u5xx.h | 1 + .../hal/Inc/Legacy/stm32_hal_legacy.h | 143 +- .../common/stm32u5xx/hal/Inc/stm32u5xx_hal.h | 61 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h | 75 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h | 28 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_def.h | 4 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h | 307 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h | 274 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h | 17 + .../stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h | 60 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h | 64 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h | 2 - .../stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h | 48 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h | 30 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h | 2 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h | 20 + .../stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h | 20 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h | 10 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h | 4 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h | 1 + .../stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h | 40 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h | 7 + .../stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h | 15 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h | 14 +- .../stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h | 6 +- .../stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h | 6 +- .../common/stm32u5xx/hal/Src/stm32u5xx_hal.c | 146 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c | 198 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c | 144 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c | 70 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_dma.c | 85 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c | 43 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_flash.c | 4 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c | 41 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c | 2 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_hash.c | 139 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c | 64 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c | 294 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_icache.c | 80 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c | 11 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_pka.c | 233 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c | 66 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c | 18 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c | 67 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c | 3 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rng.c | 20 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c | 18 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c | 85 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c | 44 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_uart.c | 178 +- .../stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c | 67 +- .../stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c | 10 +- 56 files changed, 7581 insertions(+), 6585 deletions(-) diff --git a/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h b/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h index f75c161ab2..06a0ac2451 100644 --- a/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h +++ b/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h @@ -83,7 +83,7 @@ /* area for BL2 code protected by hdp */ #define FLASH_AREA_BL2_OFFSET (FLASH_AREA_PERSO_OFFSET+FLASH_AREA_PERSO_SIZE ) -#define FLASH_AREA_BL2_SIZE (0x20000) +#define FLASH_AREA_BL2_SIZE (0x22000) /* HDP area end at this address */ #define FLASH_BL2_HDP_END (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE-1) /* area for BL2 code not protected by hdp */ diff --git a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h index f65b2268ef..3134ac49fb 100644 --- a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h +++ b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h @@ -124,7 +124,7 @@ extern "C" { #define MX25LM51245G_READ_CFG_REG_CMD 0x15U /*!< Read configuration Register */ #define MX25LM51245G_WRITE_STATUS_REG_CMD 0x01U /*!< Write Status Register */ #define MX25LM51245G_READ_CFG_REG2_CMD 0x71U /*!< Read configuration Register2 */ -#define MX25LM51245G_WRITE_CFG_REG2_CMD 0x72U /*!< Write configuration Register2 */ +#define MX25LM51245G_WRITE_CFG_REG2_CMD 0x72U /*!< Write configuration Register2 */ #define MX25LM51245G_READ_FAST_BOOT_REG_CMD 0x16U /*!< Read fast boot Register */ #define MX25LM51245G_WRITE_FAST_BOOT_REG_CMD 0x17U /*!< Write fast boot Register */ #define MX25LM51245G_ERASE_FAST_BOOT_REG_CMD 0x18U /*!< Erase fast boot Register */ diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h index a0ffef9155..9a20646eb0 100644 --- a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h +++ b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h @@ -233,7 +233,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -257,11 +257,6 @@ typedef struct uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ - uint32_t RESERVED3[246]; /*!< Reserved, */ - __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ - __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ } CRC_TypeDef; /** @@ -389,7 +384,7 @@ typedef struct __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - uint32_t RESERVED; + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; @@ -681,11 +676,6 @@ typedef struct __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ - __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ } ICACHE_TypeDef; /** @@ -1242,20 +1232,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ - uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */ - __IO uint32_t UCPD; /*!< SYSCFG USB Type C and Power delivery register Address offset: 0x70 */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -2143,11 +2131,11 @@ typedef struct #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Pos (0UL) #define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Pos (0UL) #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Pos (1UL) #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) /** @@ -3511,164 +3499,164 @@ typedef struct /******************************* ADC VERSION ********************************/ #define ADC_VER_V5_X /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5UL) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6UL) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10UL) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ -#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Pos (11UL) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ -#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Pos (12UL) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ /******************** Bit definition for ADC_IER register ********************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5UL) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6UL) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10UL) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ -#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Pos (11UL) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ -#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Pos (12UL) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3UL) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5UL) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ -#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Pos (16UL) #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ -#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Pos (24UL) #define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ #define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ -#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Pos (24UL) #define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ #define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ -#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Pos (25UL) #define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ #define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ -#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Pos (26UL) #define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ #define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ -#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Pos (27UL) #define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ #define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29UL) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ /******************** Bit definition for ADC_CFGR register ********************/ -#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Pos (0UL) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ -#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Pos (2UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ -#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Pos (0UL) #define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Pos (1UL) #define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Pos (4UL) #define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ -#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Pos (5UL) #define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ -#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Pos (5UL) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ @@ -3677,68 +3665,68 @@ typedef struct #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ -#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Pos (14UL) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ -#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Pos (14UL) #define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ -#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Pos (17UL) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Pos (20UL) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ -#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Pos (24UL) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ -#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Pos (25UL) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ /* Specific ADC4 */ -#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Pos (6UL) #define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -3748,14 +3736,14 @@ typedef struct #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_CFGR2 register ********************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0UL) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1UL) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -3763,14 +3751,14 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9UL) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10UL) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ -#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Pos (16UL) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ @@ -3784,23 +3772,23 @@ typedef struct #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ -#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Pos (13UL) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ -#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Pos (14UL) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ -#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Pos (15UL) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ -#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Pos (27UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ -#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Pos (28UL) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ @@ -3809,243 +3797,243 @@ typedef struct #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /* Specific ADC4 */ -#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Pos (2UL) #define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Pos (29UL) #define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ /******************** Bit definition for ADC_SMPR1 register ********************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0UL) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3UL) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6UL) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9UL) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12UL) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15UL) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18UL) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21UL) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24UL) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27UL) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ -#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Pos (0UL) #define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ -#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Pos (4UL) #define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ -#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Pos (8UL) #define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ #define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ -#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Pos (8UL) #define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ -#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Pos (9UL) #define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ -#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Pos (10UL) #define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ -#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Pos (11UL) #define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ -#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Pos (12UL) #define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ -#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Pos (13UL) #define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ -#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Pos (14UL) #define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ -#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Pos (15UL) #define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ -#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Pos (16UL) #define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ -#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Pos (17UL) #define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ -#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Pos (18UL) #define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ -#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Pos (19UL) #define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ -#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Pos (20UL) #define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ -#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Pos (21UL) #define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ -#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Pos (22UL) #define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ -#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Pos (23UL) #define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ -#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Pos (24UL) #define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ -#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Pos (25UL) #define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ -#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Pos (26UL) #define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ #define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ -#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Pos (27UL) #define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ #define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ -#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Pos (26UL) #define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ #define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ -#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Pos (26UL) #define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ #define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ -#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Pos (30UL) #define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ #define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ -#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Pos (31UL) #define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ #define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ /******************** Bit definition for ADC_SMPR2 register ********************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0UL) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3UL) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6UL) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9UL) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12UL) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15UL) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18UL) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21UL) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24UL) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Pos (27UL) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ @@ -4053,7 +4041,7 @@ typedef struct #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register ********************/ -#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Pos (0UL) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ @@ -4078,16 +4066,16 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ -#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Pos (0UL) #define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ -#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Pos (0UL) #define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ -#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Pos (29UL) #define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ #define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ #define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ @@ -4095,7 +4083,7 @@ typedef struct #define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0UL) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -4103,7 +4091,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6UL) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -4112,7 +4100,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12UL) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -4121,7 +4109,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18UL) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -4130,7 +4118,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24UL) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -4140,7 +4128,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ********************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0UL) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -4149,7 +4137,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6UL) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -4158,7 +4146,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12UL) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -4167,7 +4155,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18UL) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -4176,7 +4164,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24UL) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -4186,7 +4174,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ********************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0UL) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -4195,7 +4183,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6UL) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -4204,7 +4192,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12UL) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -4213,7 +4201,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18UL) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -4222,7 +4210,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24UL) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -4232,7 +4220,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ********************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0UL) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -4241,7 +4229,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6UL) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -4250,21 +4238,21 @@ typedef struct #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0UL) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ /******************** Bit definition for ADC_PW register ********************/ -#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Pos (0UL) #define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ #define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ -#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Pos (1UL) #define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ #define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ -#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Pos (2UL) #define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ #define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ -#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) #define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ #define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ @@ -4283,13 +4271,13 @@ typedef struct #define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP /******************** Bit definition for ADC_JSQR register ********************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0UL) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2UL) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -4298,13 +4286,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Pos (7UL) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Pos (9UL) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ @@ -4313,7 +4301,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Pos (15UL) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ @@ -4322,7 +4310,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Pos (21UL) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ @@ -4331,7 +4319,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ -#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Pos (27UL) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ @@ -4341,7 +4329,7 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ********************/ -#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Pos (0UL) #define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ @@ -4369,18 +4357,18 @@ typedef struct #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ -#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Pos (24UL) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Pos (25UL) #define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Pos (26UL) #define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ @@ -4390,7 +4378,7 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR2 register ********************/ -#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Pos (0UL) #define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ @@ -4418,18 +4406,18 @@ typedef struct #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ -#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Pos (24UL) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Pos (25UL) #define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Pos (26UL) #define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ @@ -4439,7 +4427,7 @@ typedef struct #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR3 register ********************/ -#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Pos (0UL) #define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ @@ -4467,18 +4455,18 @@ typedef struct #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ -#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Pos (24UL) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Pos (25UL) #define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Pos (26UL) #define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ @@ -4488,7 +4476,7 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR4 register ********************/ -#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Pos (0UL) #define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ @@ -4516,18 +4504,18 @@ typedef struct #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ -#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Pos (24UL) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Pos (25UL) #define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Pos (26UL) #define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ @@ -4537,15 +4525,15 @@ typedef struct #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_GCOMP register ********************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ -#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Pos (31UL) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ /******************** Bit definition for ADC_JDR1 register ********************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0UL) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -4582,7 +4570,7 @@ typedef struct #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0UL) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -4619,7 +4607,7 @@ typedef struct #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0UL) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -4656,7 +4644,7 @@ typedef struct #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0UL) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -4693,7 +4681,7 @@ typedef struct #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ********************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -4722,7 +4710,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_AWD1TR register *******************/ -#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Pos (0UL) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ @@ -4738,7 +4726,7 @@ typedef struct #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ -#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Pos (16UL) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ @@ -4755,7 +4743,7 @@ typedef struct #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWDTR2 register *******************/ -#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Pos (0UL) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ @@ -4771,7 +4759,7 @@ typedef struct #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ -#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Pos (16UL) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ @@ -4788,88 +4776,88 @@ typedef struct #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_CHSELR register ****************/ -#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Pos (0UL) #define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Pos (0UL) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Pos (1UL) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Pos (2UL) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Pos (3UL) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Pos (4UL) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Pos (5UL) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Pos (6UL) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Pos (7UL) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Pos (8UL) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Pos (9UL) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Pos (10UL) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Pos (11UL) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Pos (12UL) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Pos (13UL) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Pos (14UL) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Pos (15UL) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Pos (16UL) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Pos (17UL) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Pos (18UL) #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Pos (19UL) #define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Pos (20UL) #define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Pos (21UL) #define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Pos (22UL) #define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Pos (23UL) #define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Pos (0UL) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Pos (0UL) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ @@ -4877,7 +4865,7 @@ typedef struct #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ -#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Pos (4UL) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ @@ -4885,7 +4873,7 @@ typedef struct #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Pos (8UL) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ @@ -4893,7 +4881,7 @@ typedef struct #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Pos (12UL) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ @@ -4901,7 +4889,7 @@ typedef struct #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Pos (16UL) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ @@ -4909,7 +4897,7 @@ typedef struct #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ -#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Pos (20UL) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ @@ -4917,7 +4905,7 @@ typedef struct #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ -#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Pos (24UL) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ @@ -4925,7 +4913,7 @@ typedef struct #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ -#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Pos (28UL) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ @@ -4934,7 +4922,7 @@ typedef struct #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD3TR register *******************/ -#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Pos (0UL) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ @@ -4950,7 +4938,7 @@ typedef struct #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ -#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Pos (16UL) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ @@ -4967,7 +4955,7 @@ typedef struct #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWD3CR register ********************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -4996,7 +4984,7 @@ typedef struct #define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_DIFSEL register ********************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Pos (0UL) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ @@ -5021,7 +5009,7 @@ typedef struct #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) #define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ #define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ #define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ @@ -5033,7 +5021,7 @@ typedef struct #define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ -#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) #define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ #define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ @@ -5045,17 +5033,17 @@ typedef struct #define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ #define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ -#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Pos (16UL) #define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) #define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) #define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ -#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Pos (0UL) #define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -5067,7 +5055,7 @@ typedef struct #define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ /******************** Bit definition for ADC_CALFACT2 register ********************/ -#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Pos (0UL) #define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ #define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ @@ -5104,13 +5092,13 @@ typedef struct #define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OR register ********************/ -#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Pos (0UL) #define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ #define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ /************************* ADC Common registers *****************************/ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -5118,19 +5106,19 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Pos (23UL) #define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ -#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Pos (25UL) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ -#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Pos (26UL) #define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ #define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ @@ -5141,58 +5129,58 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CORDIC_CSR register *****************/ -#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Pos (0UL) #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ -#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Pos (4UL) #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ -#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Pos (8UL) #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ -#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Pos (16UL) #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ -#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Pos (17UL) #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ -#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Pos (18UL) #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ -#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Pos (19UL) #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ -#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Pos (20UL) #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ -#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Pos (21UL) #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ -#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Pos (22UL) #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ -#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Pos (31UL) #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ /******************* Bit definition for CORDIC_WDATA register ***************/ -#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Pos (0UL) #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ /******************* Bit definition for CORDIC_RDATA register ***************/ -#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Pos (0UL) #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ @@ -5202,40 +5190,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ @@ -5244,93 +5232,93 @@ typedef struct /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Pos (0UL) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Pos (1UL) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Pos (2UL) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Pos (3UL) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Pos (5UL) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Pos (6UL) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Pos (7UL) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8U) -#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Pos (0UL) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Pos (16UL) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Pos (24UL) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Pos (28UL) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Pos (31UL) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Pos (0UL) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Pos (1UL) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Pos (2UL) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Pos (3UL) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Pos (8UL) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Pos (9UL) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Pos (10UL) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Pos (15UL) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Pos (16UL) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Pos (0UL) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Pos (1UL) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Pos (2UL) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Pos (3UL) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ @@ -5340,65 +5328,89 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk -#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk -#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk -#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Pos (7UL) #define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) #define RNG_CR_ARDIS RNG_CR_ARDIS_Msk -#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Pos (8UL) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk -#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Pos (12UL) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) #define RNG_CR_NISTC RNG_CR_NISTC_Msk -#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Pos (13UL) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk -#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Pos (16UL) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ -#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Pos (20UL) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk -#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Pos (30UL) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk -#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Pos (31UL) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Pos (0UL) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk -#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Pos (1UL) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk -#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Pos (2UL) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk -#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk -#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Pos (6UL) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + /******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Pos (0UL) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -5408,277 +5420,277 @@ typedef struct #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -18140,257 +18154,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -18401,57 +18415,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -18459,7 +18473,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -18470,10 +18484,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -18484,489 +18498,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -18976,44 +18990,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!Instance->SR \ - & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ - ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ - ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ - ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ - (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + (CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h index d724710854..7b4e96dc95 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h @@ -175,7 +175,7 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler ------------ @@ -208,7 +208,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM & GNUCompiler ---------------- */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h index e62dff3ec9..68129223cf 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h @@ -252,174 +252,174 @@ typedef struct __DMA_HandleTypeDef * @{ */ /* GPDMA1 requests */ -#define GPDMA1_REQUEST_ADC1 (0U) /*!< GPDMA1 HW request is ADC1 */ -#define GPDMA1_REQUEST_ADC4 (1U) /*!< GPDMA1 HW request is ADC4 */ -#define GPDMA1_REQUEST_DAC1_CH1 (2U) /*!< GPDMA1 HW request is DAC1_CH1 */ -#define GPDMA1_REQUEST_DAC1_CH2 (3U) /*!< GPDMA1 HW request is DAC1_CH2 */ -#define GPDMA1_REQUEST_TIM6_UP (4U) /*!< GPDMA1 HW request is TIM6_UP */ -#define GPDMA1_REQUEST_TIM7_UP (5U) /*!< GPDMA1 HW request is TIM7_UP */ -#define GPDMA1_REQUEST_SPI1_RX (6U) /*!< GPDMA1 HW request is SPI1_RX */ -#define GPDMA1_REQUEST_SPI1_TX (7U) /*!< GPDMA1 HW request is SPI1_TX */ -#define GPDMA1_REQUEST_SPI2_RX (8U) /*!< GPDMA1 HW request is SPI2_RX */ -#define GPDMA1_REQUEST_SPI2_TX (9U) /*!< GPDMA1 HW request is SPI2_TX */ -#define GPDMA1_REQUEST_SPI3_RX (10U) /*!< GPDMA1 HW request is SPI3_RX */ -#define GPDMA1_REQUEST_SPI3_TX (11U) /*!< GPDMA1 HW request is SPI3_TX */ -#define GPDMA1_REQUEST_I2C1_RX (12U) /*!< GPDMA1 HW request is I2C1_RX */ -#define GPDMA1_REQUEST_I2C1_TX (13U) /*!< GPDMA1 HW request is I2C1_TX */ -#define GPDMA1_REQUEST_I2C1_EVC (14U) /*!< GPDMA1 HW request is I2C1_EVC */ -#define GPDMA1_REQUEST_I2C2_RX (15U) /*!< GPDMA1 HW request is I2C2_RX */ -#define GPDMA1_REQUEST_I2C2_TX (16U) /*!< GPDMA1 HW request is I2C2_TX */ -#define GPDMA1_REQUEST_I2C2_EVC (17U) /*!< GPDMA1 HW request is I2C2_EVC */ -#define GPDMA1_REQUEST_I2C3_RX (18U) /*!< GPDMA1 HW request is I2C3_RX */ -#define GPDMA1_REQUEST_I2C3_TX (19U) /*!< GPDMA1 HW request is I2C3_TX */ -#define GPDMA1_REQUEST_I2C3_EVC (20U) /*!< GPDMA1 HW request is I2C3_EVC */ -#define GPDMA1_REQUEST_I2C4_RX (21U) /*!< GPDMA1 HW request is I2C4_RX */ -#define GPDMA1_REQUEST_I2C4_TX (22U) /*!< GPDMA1 HW request is I2C4_TX */ -#define GPDMA1_REQUEST_I2C4_EVC (23U) /*!< GPDMA1 HW request is I2C4_EVC */ -#define GPDMA1_REQUEST_USART1_RX (24U) /*!< GPDMA1 HW request is USART1_RX */ -#define GPDMA1_REQUEST_USART1_TX (25U) /*!< GPDMA1 HW request is USART1_TX */ +#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#define GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW request is ADC4 */ +#define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ +#define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ +#define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ +#define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ +#define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ +#define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ +#define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW request is I2C1_EVC */ +#define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ +#define GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW request is I2C2_EVC */ +#define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ +#define GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW request is I2C3_EVC */ +#define GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW request is I2C4_RX */ +#define GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW request is I2C4_TX */ +#define GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW request is I2C4_EVC */ +#define GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW request is USART1_TX */ #if defined(USART2) -#define GPDMA1_REQUEST_USART2_RX (26U) /*!< GPDMA1 HW request is USART2_RX */ -#define GPDMA1_REQUEST_USART2_TX (27U) /*!< GPDMA1 HW request is USART2_TX */ +#define GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW request is USART2_TX */ #endif /* USART2 */ -#define GPDMA1_REQUEST_USART3_RX (28U) /*!< GPDMA1 HW request is USART3_RX */ -#define GPDMA1_REQUEST_USART3_TX (29U) /*!< GPDMA1 HW request is USART3_TX */ -#define GPDMA1_REQUEST_UART4_RX (30U) /*!< GPDMA1 HW request is UART4_RX */ -#define GPDMA1_REQUEST_UART4_TX (31U) /*!< GPDMA1 HW request is UART4_TX */ -#define GPDMA1_REQUEST_UART5_RX (32U) /*!< GPDMA1 HW request is UART5_RX */ -#define GPDMA1_REQUEST_UART5_TX (33U) /*!< GPDMA1 HW request is UART5_TX */ -#define GPDMA1_REQUEST_LPUART1_RX (34U) /*!< GPDMA1 HW request is LPUART1_RX */ -#define GPDMA1_REQUEST_LPUART1_TX (35U) /*!< GPDMA1 HW request is LPUART1_TX */ -#define GPDMA1_REQUEST_SAI1_A (36U) /*!< GPDMA1 HW request is SAI1_A */ -#define GPDMA1_REQUEST_SAI1_B (37U) /*!< GPDMA1 HW request is SAI1_B */ +#define GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW request is USART3_TX */ +#define GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW request is UART4_RX */ +#define GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW request is UART4_TX */ +#define GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW request is UART5_RX */ +#define GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW request is UART5_TX */ +#define GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW request is LPUART1_TX */ +#define GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW request is SAI1_B */ #if defined(SAI2) -#define GPDMA1_REQUEST_SAI2_A (38U) /*!< GPDMA1 HW request is SAI2_A */ -#define GPDMA1_REQUEST_SAI2_B (39U) /*!< GPDMA1 HW request is SAI2_B */ +#define GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW request is SAI2_A */ +#define GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW request is SAI2_B */ #endif /* SAI2 */ -#define GPDMA1_REQUEST_OCTOSPI1 (40U) /*!< GPDMA1 HW request is OCTOSPI1 */ +#define GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW request is OCTOSPI1 */ #if defined(OCTOSPI2) -#define GPDMA1_REQUEST_OCTOSPI2 (41U) /*!< GPDMA1 HW request is OCTOSPI2 */ +#define GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW request is OCTOSPI2 */ #endif /* OCTOSPI2 */ -#define GPDMA1_REQUEST_TIM1_CH1 (42U) /*!< GPDMA1 HW request is TIM1_CH1 */ -#define GPDMA1_REQUEST_TIM1_CH2 (43U) /*!< GPDMA1 HW request is TIM1_CH2 */ -#define GPDMA1_REQUEST_TIM1_CH3 (44U) /*!< GPDMA1 HW request is TIM1_CH3 */ -#define GPDMA1_REQUEST_TIM1_CH4 (45U) /*!< GPDMA1 HW request is TIM1_CH4 */ -#define GPDMA1_REQUEST_TIM1_UP (46U) /*!< GPDMA1 HW request is TIM1_UP */ -#define GPDMA1_REQUEST_TIM1_TRIG (47U) /*!< GPDMA1 HW request is TIM1_TRIG */ -#define GPDMA1_REQUEST_TIM1_COM (48U) /*!< GPDMA1 HW request is TIM1_COM */ -#define GPDMA1_REQUEST_TIM8_CH1 (49U) /*!< GPDMA1 HW request is TIM8_CH1 */ -#define GPDMA1_REQUEST_TIM8_CH2 (50U) /*!< GPDMA1 HW request is TIM8_CH2 */ -#define GPDMA1_REQUEST_TIM8_CH3 (51U) /*!< GPDMA1 HW request is TIM8_CH3 */ -#define GPDMA1_REQUEST_TIM8_CH4 (52U) /*!< GPDMA1 HW request is TIM8_CH4 */ -#define GPDMA1_REQUEST_TIM8_UP (53U) /*!< GPDMA1 HW request is TIM8_UP */ -#define GPDMA1_REQUEST_TIM8_TRIG (54U) /*!< GPDMA1 HW request is TIM8_TRIG */ -#define GPDMA1_REQUEST_TIM8_COM (55U) /*!< GPDMA1 HW request is TIM8_COM */ -#define GPDMA1_REQUEST_TIM2_CH1 (56U) /*!< GPDMA1 HW request is TIM2_CH1 */ -#define GPDMA1_REQUEST_TIM2_CH2 (57U) /*!< GPDMA1 HW request is TIM2_CH2 */ -#define GPDMA1_REQUEST_TIM2_CH3 (58U) /*!< GPDMA1 HW request is TIM2_CH3 */ -#define GPDMA1_REQUEST_TIM2_CH4 (59U) /*!< GPDMA1 HW request is TIM2_CH4 */ -#define GPDMA1_REQUEST_TIM2_UP (60U) /*!< GPDMA1 HW request is TIM2_UP */ -#define GPDMA1_REQUEST_TIM3_CH1 (61U) /*!< GPDMA1 HW request is TIM3_CH1 */ -#define GPDMA1_REQUEST_TIM3_CH2 (62U) /*!< GPDMA1 HW request is TIM3_CH2 */ -#define GPDMA1_REQUEST_TIM3_CH3 (63U) /*!< GPDMA1 HW request is TIM3_CH3 */ -#define GPDMA1_REQUEST_TIM3_CH4 (64U) /*!< GPDMA1 HW request is TIM3_CH4 */ -#define GPDMA1_REQUEST_TIM3_UP (65U) /*!< GPDMA1 HW request is TIM3_UP */ -#define GPDMA1_REQUEST_TIM3_TRIG (66U) /*!< GPDMA1 HW request is TIM3_TRIG */ -#define GPDMA1_REQUEST_TIM4_CH1 (67U) /*!< GPDMA1 HW request is TIM4_CH1 */ -#define GPDMA1_REQUEST_TIM4_CH2 (68U) /*!< GPDMA1 HW request is TIM4_CH2 */ -#define GPDMA1_REQUEST_TIM4_CH3 (69U) /*!< GPDMA1 HW request is TIM4_CH3 */ -#define GPDMA1_REQUEST_TIM4_CH4 (70U) /*!< GPDMA1 HW request is TIM4_CH4 */ -#define GPDMA1_REQUEST_TIM4_UP (71U) /*!< GPDMA1 HW request is TIM4_UP */ -#define GPDMA1_REQUEST_TIM5_CH1 (72U) /*!< GPDMA1 HW request is TIM5_CH1 */ -#define GPDMA1_REQUEST_TIM5_CH2 (73U) /*!< GPDMA1 HW request is TIM5_CH2 */ -#define GPDMA1_REQUEST_TIM5_CH3 (74U) /*!< GPDMA1 HW request is TIM5_CH3 */ -#define GPDMA1_REQUEST_TIM5_CH4 (75U) /*!< GPDMA1 HW request is TIM5_CH4 */ -#define GPDMA1_REQUEST_TIM5_UP (76U) /*!< GPDMA1 HW request is TIM5_UP */ -#define GPDMA1_REQUEST_TIM5_TRIG (77U) /*!< GPDMA1 HW request is TIM5_TRIG */ -#define GPDMA1_REQUEST_TIM15_CH1 (78U) /*!< GPDMA1 HW request is TIM15_CH1 */ -#define GPDMA1_REQUEST_TIM15_UP (79U) /*!< GPDMA1 HW request is TIM15_UP */ -#define GPDMA1_REQUEST_TIM15_TRIG (80U) /*!< GPDMA1 HW request is TIM15_TRIG */ -#define GPDMA1_REQUEST_TIM15_COM (81U) /*!< GPDMA1 HW request is TIM15_COM */ -#define GPDMA1_REQUEST_TIM16_CH1 (82U) /*!< GPDMA1 HW request is TIM16_CH1 */ -#define GPDMA1_REQUEST_TIM16_UP (83U) /*!< GPDMA1 HW request is TIM16_UP */ -#define GPDMA1_REQUEST_TIM17_CH1 (84U) /*!< GPDMA1 HW request is TIM17_CH1 */ -#define GPDMA1_REQUEST_TIM17_UP (85U) /*!< GPDMA1 HW request is TIM17_UP */ -#define GPDMA1_REQUEST_DCMI_PSSI (86U) /*!< GPDMA1 HW request is DCMI_PSSI */ -#define GPDMA1_REQUEST_AES_IN (87U) /*!< GPDMA1 HW request is AES_IN */ -#define GPDMA1_REQUEST_AES_OUT (88U) /*!< GPDMA1 HW request is AES_OUT */ -#define GPDMA1_REQUEST_HASH_IN (89U) /*!< GPDMA1 HW request is HASH_IN */ +#define GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW request is TIM1_COM */ +#define GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW request is TIM8_UP */ +#define GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW request is TIM8_COM */ +#define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW request is TIM2_UP */ +#define GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW request is TIM3_TRIG */ +#define GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW request is TIM4_UP */ +#define GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW request is TIM5_UP */ +#define GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW request is TIM5_TRIG */ +#define GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW request is TIM15_UP */ +#define GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW request is TIM15_COM */ +#define GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW request is TIM16_UP */ +#define GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW request is TIM17_UP */ +#define GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW request is DCMI_PSSI */ +#define GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW request is AES_IN */ +#define GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW request is AES_OUT */ +#define GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW request is HASH_IN */ #if defined(UCPD1) -#define GPDMA1_REQUEST_UCPD1_TX (90U) /*!< GPDMA1 HW request is UCPD1_TX */ -#define GPDMA1_REQUEST_UCPD1_RX (91U) /*!< GPDMA1 HW request is UCPD1_RX */ +#define GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW request is UCPD1_TX */ +#define GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW request is UCPD1_RX */ #endif /* UCPD1 */ -#define GPDMA1_REQUEST_MDF1_FLT0 (92U) /*!< GPDMA1 HW request is MDF1_FLT0 */ -#define GPDMA1_REQUEST_MDF1_FLT1 (93U) /*!< GPDMA1 HW request is MDF1_FLT1 */ -#define GPDMA1_REQUEST_MDF1_FLT2 (94U) /*!< GPDMA1 HW request is MDF1_FLT2 */ -#define GPDMA1_REQUEST_MDF1_FLT3 (95U) /*!< GPDMA1 HW request is MDF1_FLT3 */ -#define GPDMA1_REQUEST_MDF1_FLT4 (96U) /*!< GPDMA1 HW request is MDF1_FLT4 */ -#define GPDMA1_REQUEST_MDF1_FLT5 (97U) /*!< GPDMA1 HW request is MDF1_FLT5 */ -#define GPDMA1_REQUEST_ADF1_FLT0 (98U) /*!< GPDMA1 HW request is ADF1_FLT0 */ -#define GPDMA1_REQUEST_FMAC_READ (99U) /*!< GPDMA1 HW request is FMAC_READ */ -#define GPDMA1_REQUEST_FMAC_WRITE (100U) /*!< GPDMA1 HW request is FMAC_WRITE */ -#define GPDMA1_REQUEST_CORDIC_READ (101U) /*!< GPDMA1 HW request is CORDIC_READ */ -#define GPDMA1_REQUEST_CORDIC_WRITE (102U) /*!< GPDMA1 HW request is CORDIC_WRITE */ -#define GPDMA1_REQUEST_SAES_IN (103U) /*!< GPDMA1 HW request is SAES_IN */ -#define GPDMA1_REQUEST_SAES_OUT (104U) /*!< GPDMA1 HW request is SAES_OUT */ -#define GPDMA1_REQUEST_LPTIM1_IC1 (105U) /*!< GPDMA1 HW request is LPTIM1_IC1 */ -#define GPDMA1_REQUEST_LPTIM1_IC2 (106U) /*!< GPDMA1 HW request is LPTIM1_IC2 */ -#define GPDMA1_REQUEST_LPTIM1_UE (107U) /*!< GPDMA1 HW request is LPTIM1_UE */ -#define GPDMA1_REQUEST_LPTIM2_IC1 (108U) /*!< GPDMA1 HW request is LPTIM2_IC1 */ -#define GPDMA1_REQUEST_LPTIM2_IC2 (109U) /*!< GPDMA1 HW request is LPTIM2_IC2 */ -#define GPDMA1_REQUEST_LPTIM2_UE (110U) /*!< GPDMA1 HW request is LPTIM2_UE */ -#define GPDMA1_REQUEST_LPTIM3_IC1 (111U) /*!< GPDMA1 HW request is LPTIM3_IC1 */ -#define GPDMA1_REQUEST_LPTIM3_IC2 (112U) /*!< GPDMA1 HW request is LPTIM3_IC2 */ -#define GPDMA1_REQUEST_LPTIM3_UE (113U) /*!< GPDMA1 HW request is LPTIM3_UE */ +#define GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW request is MDF1_FLT5 */ +#define GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#define GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW request is FMAC_READ */ +#define GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW request is FMAC_WRITE */ +#define GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW request is CORDIC_READ */ +#define GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#define GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW request is SAES_IN */ +#define GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW request is SAES_OUT */ +#define GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW request is LPTIM3_UE */ #if defined (HSPI1_BASE) -#define GPDMA1_REQUEST_HSPI1 (114U) /*!< GPDMA1 HW request is HSPI1 */ -#endif /* defined (HSPI1_BASE) */ +#define GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ +#endif /* HSPI1_BASE */ #if defined (I2C5) -#define GPDMA1_REQUEST_I2C5_RX (115U) /*!< GPDMA1 HW request is I2C5_RX */ -#define GPDMA1_REQUEST_I2C5_TX (116U) /*!< GPDMA1 HW request is I2C5_TX */ -#define GPDMA1_REQUEST_I2C5_EVC (117U) /*!< GPDMA1 HW request is I2C5_EVC */ -#endif /* defined (I2C5) */ +#define GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ +#define GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ +#define GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* I2C5 */ #if defined (I2C6) -#define GPDMA1_REQUEST_I2C6_RX (118U) /*!< GPDMA1 HW request is I2C6_RX */ -#define GPDMA1_REQUEST_I2C6_TX (119U) /*!< GPDMA1 HW request is I2C6_TX */ -#define GPDMA1_REQUEST_I2C6_EVC (120U) /*!< GPDMA1 HW request is I2C6_EVC */ -#endif /* defined (I2C6) */ +#define GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ +#define GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ +#define GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* I2C6 */ #if defined (USART6) -#define GPDMA1_REQUEST_USART6_RX (121U) /*!< GPDMA1 HW request is USART6_RX */ -#define GPDMA1_REQUEST_USART6_TX (122U) /*!< GPDMA1 HW request is USART6_TX */ -#endif /* defined (USART6) */ +#define GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ +#define GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ #if defined (ADC2) -#define GPDMA1_REQUEST_ADC2 (123U) /*!< GPDMA1 HW request is ADC2 */ -#endif /* defined (ADC2) */ +#define GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ #if defined (JPEG) -#define GPDMA1_REQUEST_JPEG_RX (124U) /*!< GPDMA1 HW request is JPEG_TX */ -#define GPDMA1_REQUEST_JPEG_TX (125U) /*!< GPDMA1 HW request is JPEG_RX */ -#endif /* defined (JPEG) */ +#define GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ +#define GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ +#endif /* JPEG */ /* LPDMA1 requests */ -#define LPDMA1_REQUEST_LPUART1_RX (0U) /*!< LPDMA1 HW request is LPUART1_RX */ -#define LPDMA1_REQUEST_LPUART1_TX (1U) /*!< LPDMA1 HW request is LPUART1_TX */ -#define LPDMA1_REQUEST_SPI3_RX (2U) /*!< LPDMA1 HW request is SPI3_RX */ -#define LPDMA1_REQUEST_SPI3_TX (3U) /*!< LPDMA1 HW request is SPI3_TX */ -#define LPDMA1_REQUEST_I2C3_RX (4U) /*!< LPDMA1 HW request is I2C3_RX */ -#define LPDMA1_REQUEST_I2C3_TX (5U) /*!< LPDMA1 HW request is I2C3_TX */ -#define LPDMA1_REQUEST_I2C3_EVC (6U) /*!< LPDMA1 HW request is I2C3_EVC */ -#define LPDMA1_REQUEST_ADC4 (7U) /*!< LPDMA1 HW request is ADC4 */ -#define LPDMA1_REQUEST_DAC1_CH1 (8U) /*!< LPDMA1 HW request is DAC1_CH1 */ -#define LPDMA1_REQUEST_DAC1_CH2 (9U) /*!< LPDMA1 HW request is DAC1_CH2 */ -#define LPDMA1_REQUEST_ADF1_FLT0 (10U) /*!< LPDMA1 HW request is ADF1_FLT0 */ -#define LPDMA1_REQUEST_LPTIM1_IC1 (11U) /*!< LPDMA1 HW request is LPTIM1_IC1 */ -#define LPDMA1_REQUEST_LPTIM1_IC2 (12U) /*!< LPDMA1 HW request is LPTIM1_IC2 */ -#define LPDMA1_REQUEST_LPTIM1_UE (13U) /*!< LPDMA1 HW request is LPTIM1_UE */ -#define LPDMA1_REQUEST_LPTIM3_IC1 (14U) /*!< LPDMA1 HW request is LPTIM3_IC1 */ -#define LPDMA1_REQUEST_LPTIM3_IC2 (15U) /*!< LPDMA1 HW request is LPTIM3_IC2 */ -#define LPDMA1_REQUEST_LPTIM3_UE (16U) /*!< LPDMA1 HW request is LPTIM3_UE */ +#define LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW request is LPUART1_RX */ +#define LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW request is LPUART1_TX */ +#define LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW request is SPI3_RX */ +#define LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW request is SPI3_TX */ +#define LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW request is I2C3_RX */ +#define LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW request is I2C3_TX */ +#define LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW request is I2C3_EVC */ +#define LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW request is ADC4 */ +#define LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW request is DAC1_CH1 */ +#define LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW request is DAC1_CH2 */ +#define LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW request is ADF1_FLT0 */ +#define LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW request is LPTIM1_IC1 */ +#define LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW request is LPTIM1_IC2 */ +#define LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW request is LPTIM1_UE */ +#define LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW request is LPTIM3_IC1 */ +#define LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW request is LPTIM3_IC2 */ +#define LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW request is LPTIM3_UE */ /* Software request */ -#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ /** * @} */ @@ -562,7 +562,6 @@ typedef struct __DMA_HandleTypeDef */ - /** * @} */ @@ -771,7 +770,7 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState); @@ -891,12 +890,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->MISR & (GLOBAL_FLAG))) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h index df9b9246f9..f0a04eabcd 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h @@ -151,7 +151,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< Specifies the source security attribute */ uint32_t DestSecure; /*!< Specifies the destination security attribute */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } DMA_NodeConfTypeDef; @@ -237,10 +237,10 @@ typedef struct __DMA_QListTypeDef destination data width */ #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width => Packed at the destination data width - (Available only for GPDMA) */ + (Not available on LPDMA) */ #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width => Unpacked at the destination data width - (Available only for GPDMA) */ + (Not available on LPDMA) */ /** * @} */ @@ -285,129 +285,129 @@ typedef struct __DMA_QListTypeDef * @{ */ /* GPDMA1 triggers */ -#define GPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ -#define GPDMA1_TRIGGER_EXTI_LINE1 (1U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ -#define GPDMA1_TRIGGER_EXTI_LINE2 (2U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ -#define GPDMA1_TRIGGER_EXTI_LINE3 (3U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ -#define GPDMA1_TRIGGER_EXTI_LINE4 (4U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ -#define GPDMA1_TRIGGER_EXTI_LINE5 (5U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ -#define GPDMA1_TRIGGER_EXTI_LINE6 (6U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ -#define GPDMA1_TRIGGER_EXTI_LINE7 (7U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ -#define GPDMA1_TRIGGER_TAMP_TRG1 (8U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ -#define GPDMA1_TRIGGER_TAMP_TRG2 (9U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ -#define GPDMA1_TRIGGER_TAMP_TRG3 (10U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ -#define GPDMA1_TRIGGER_LPTIM1_CH1 (11U) /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ -#define GPDMA1_TRIGGER_LPTIM1_CH2 (12U) /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ -#define GPDMA1_TRIGGER_LPTIM2_CH1 (13U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ -#define GPDMA1_TRIGGER_LPTIM2_CH2 (14U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ -#define GPDMA1_TRIGGER_LPTIM4_OUT (15U) /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ -#define GPDMA1_TRIGGER_COMP1_OUT (16U) /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ #if defined(COMP2) -#define GPDMA1_TRIGGER_COMP2_OUT (17U) /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ +#define GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ #endif /* COMP2 */ -#define GPDMA1_TRIGGER_RTC_ALRA_TRG (18U) /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ -#define GPDMA1_TRIGGER_RTC_ALRB_TRG (19U) /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ -#define GPDMA1_TRIGGER_RTC_WUT_TRG (20U) /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ -#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF (22U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF (23U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF (24U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF (25U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF (26U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF (27U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF (28U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF (29U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF (30U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF (31U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF (32U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF (33U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF (34U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF (35U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF (36U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF (37U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF (38U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF (39U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF (40U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ -#define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ -#define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#define GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ #if defined (TIM3_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM3_TRGO (44U) /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* defined (TRIGGER_TIM3_TRGO_SUPPORT) */ +#define GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ #if defined (TIM4_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM4_TRGO (45U) /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ -#endif /* defined (TRIGGER_TIM4_TRGO_SUPPORT) */ +#define GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ #if defined (TIM5_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM5_TRGO (46U) /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ -#endif /* defined (TRIGGER_TIM5_TRGO_SUPPORT) */ +#define GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ #if defined (LTDC) -#define GPDMA1_TRIGGER_LTDC_LI (47U) /*!< GPDMA1 HW Trigger signal is LTDC_LI */ -#endif /* defined (LTDC) */ +#define GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* LTDC */ #if defined (DSI) -#define GPDMA1_TRIGGER_DSI_TE (48U) /*!< GPDMA1 HW Trigger signal is DSI_TE */ -#define GPDMA1_TRIGGER_DSI_ER (49U) /*!< GPDMA1 HW Trigger signal is DSI_ER */ -#endif /* defined (DSI) */ +#define GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* DSI */ #if defined (DMA2D_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_DMA2D_TC (50U) /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ -#define GPDMA1_TRIGGER_DMA2D_CTC (51U) /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ -#define GPDMA1_TRIGGER_DMA2D_TW (52U) /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ -#endif /* defined (DMA2D_TRIGGER_SUPPORT) */ +#define GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* DMA2D_TRIGGER_SUPPORT */ #if defined (GPU2D) -#define GPDMA1_TRIGGER_GPU2D_FLAG0 (53U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG1 (54U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG2 (55U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG3 (56U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ -#endif /* defined (GPU2D) */ -#define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ -#define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* GPU2D */ +#define GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ +#define GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ #if defined (GFXTIM) -#define GPDMA1_TRIGGER_GFXTIM_EVT3 (59U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT2 (60U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT1 (61U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT0 (62U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ -#endif /* defined (GFXTIM) */ +#define GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ +#endif /* GFXTIM */ #if defined (JPEG) -#define GPDMA1_TRIGGER_JPEG_EOC (63U) /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ -#define GPDMA1_TRIGGER_JPEG_IFNF (64U) /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ -#define GPDMA1_TRIGGER_JPEG_IFT (65U) /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ -#define GPDMA1_TRIGGER_JPEG_OFNE (66U) /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ -#define GPDMA1_TRIGGER_JPEG_OFT (67U) /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ -#endif /* defined (JPEG) */ +#define GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ +#endif /* JPEG */ /* LPDMA1 triggers */ -#define LPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ -#define LPDMA1_TRIGGER_EXTI_LINE1 (1U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ -#define LPDMA1_TRIGGER_EXTI_LINE2 (2U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ -#define LPDMA1_TRIGGER_EXTI_LINE3 (3U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ -#define LPDMA1_TRIGGER_EXTI_LINE4 (4U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ -#define LPDMA1_TRIGGER_TAMP_TRG1 (5U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ -#define LPDMA1_TRIGGER_TAMP_TRG2 (6U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ -#define LPDMA1_TRIGGER_TAMP_TRG3 (7U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ -#define LPDMA1_TRIGGER_LPTIM1_CH1 (8U) /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ -#define LPDMA1_TRIGGER_LPTIM1_CH2 (9U) /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ -#define LPDMA1_TRIGGER_LPTIM3_CH1 (10U) /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ -#define LPDMA1_TRIGGER_LPTIM4_OUT (11U) /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ -#define LPDMA1_TRIGGER_COMP1_OUT (12U) /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ +#define LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ #if defined(COMP2) -#define LPDMA1_TRIGGER_COMP2_OUT (13U) /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ +#define LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ #endif /* COMP2 */ -#define LPDMA1_TRIGGER_RTC_ALRA_TRG (14U) /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ -#define LPDMA1_TRIGGER_RTC_ALRB_TRG (15U) /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ -#define LPDMA1_TRIGGER_RTC_WUT_TRG (16U) /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ -#define LPDMA1_TRIGGER_ADC4_AWD1 (17U) /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ -#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF (18U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF (19U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF (20U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF (21U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF (22U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF (23U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF (24U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF (25U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF (26U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF (27U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF (28U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF (29U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ -#define LPDMA1_TRIGGER_TIM2_TRGO (30U) /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ -#define LPDMA1_TRIGGER_TIM15_TRGO (31U) /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ +#define LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ +#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ /** * @} */ @@ -597,40 +597,40 @@ typedef struct * @brief DMAEx Private Constants * @{ */ -#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ +#define DMA_LINKEDLIST (0x0080UL) /* DMA channel linked-list mode */ -#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ -#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ -#define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */ -#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001UL) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002UL) /* DMA channel 2D addressing mode */ +#define DMA_CHANNEL_TYPE_LPDMA (0x0010UL) /* LPDMA channel node */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020UL) /* GPDMA channel node */ -#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ -#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ -#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ +#define NODE_TYPE_MASK (0x00FFUL) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700UL) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008UL) /* DMA channel node CLLR index position */ -#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ +#define NODE_MAXIMUM_SIZE (0x0008UL) /* Amount of registers of the node */ -#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ -#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ +#define NODE_STATIC_FORMAT (0x0000UL) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001UL) /* DMA channel node dynamic format */ -#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ -#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ +#define UPDATE_CLLR_POSITION (0x0000UL) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001UL) /* DMA channel update CLLR value */ -#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ -#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ +#define LASTNODE_ISNOT_CIRCULAR (0x0000UL) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001UL) /* Last node is first circular node */ -#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ -#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ +#define QUEUE_TYPE_STATIC (0x0000UL) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001UL) /* DMA channel dynamic queue */ -#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ -#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ -#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ -#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ -#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ -#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ -#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ -#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ -#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ +#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */ +#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */ +#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h index 6d9c0198e3..e13dc2732d 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h @@ -279,6 +279,23 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + #define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h index cbc876b222..110b835f14 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h @@ -118,13 +118,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -477,15 +477,15 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -498,15 +498,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -518,9 +518,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -532,9 +532,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -545,9 +545,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -559,8 +559,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -595,19 +595,19 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h index 66b46107d2..f98b72ecfa 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h @@ -51,15 +51,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -70,15 +70,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -88,9 +88,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -100,9 +100,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -112,9 +112,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -125,8 +125,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -136,20 +136,20 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h index 7ebaa0c10b..f76f875478 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h @@ -119,8 +119,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h index 9ad1581afb..c080ddc1dd 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h @@ -103,54 +103,54 @@ typedef struct #define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ #define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ -#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) +#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000UL)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ -#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ -#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ -#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ -#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) +#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000UL)) /*!< HW Trigger signal is LPDMA_CH0_TRG */ -#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH1_TRG */ -#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH2_TRG */ -#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH3_TRG */ -#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM3_CH1_TRG */ -#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ -#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ -#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h index fcaa3aea93..e9dcf7ec7a 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h @@ -28,6 +28,7 @@ extern "C" { /* Includes -----------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" +#if defined(ICACHE) /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -71,7 +72,7 @@ typedef struct /** @defgroup ICACHE_WaysSelection Ways selection * @{ */ -#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */ #define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ /** * @} @@ -90,10 +91,10 @@ typedef struct /** @defgroup ICACHE_Region Remapped Region number * @{ */ -#define ICACHE_REGION_0 0U /*!< Region 0 */ -#define ICACHE_REGION_1 1U /*!< Region 1 */ -#define ICACHE_REGION_2 2U /*!< Region 2 */ -#define ICACHE_REGION_3 3U /*!< Region 3 */ +#define ICACHE_REGION_0 0UL /*!< Region 0 */ +#define ICACHE_REGION_1 1UL /*!< Region 1 */ +#define ICACHE_REGION_2 2UL /*!< Region 2 */ +#define ICACHE_REGION_3 3UL /*!< Region 3 */ /** * @} */ @@ -101,13 +102,13 @@ typedef struct /** @defgroup ICACHE_Region_Size Remapped Region size * @{ */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ /** * @} */ @@ -115,7 +116,7 @@ typedef struct /** @defgroup ICACHE_Traffic_Route Remapped Traffic route * @{ */ -#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */ #define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ /** * @} @@ -124,7 +125,7 @@ typedef struct /** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type * @{ */ -#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */ #define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ /** * @} @@ -285,6 +286,7 @@ HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); /** * @} */ +#endif /* ICACHE */ #ifdef __cplusplus } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h index d90709b5fa..9b7dd5c599 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h @@ -924,7 +924,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) -#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h index fc7e844f15..939df94afb 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h @@ -108,6 +108,9 @@ typedef struct PKA_TypeDef *Instance; /*!< Register base address */ __IO HAL_PKA_StateTypeDef State; /*!< PKA state */ __IO uint32_t ErrorCode; /*!< PKA Error code */ + __IO uint32_t primeordersize; /*!< Elliptic curve prime order length */ + __IO uint32_t opsize; /*!< Modular exponentiation operand length */ + __IO uint32_t modulussize; /*!< Elliptic curve modulus length */ #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */ void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */ @@ -148,6 +151,21 @@ typedef struct const uint8_t *primeOrder; /*!< pointer to order of the curve */ } PKA_ECCMulInTypeDef; +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulExInTypeDef; + typedef struct { uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */ @@ -573,6 +591,8 @@ uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka); HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout); HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out); HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h index 99450cee42..0586ab0d40 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h @@ -106,8 +106,9 @@ typedef struct /** @defgroup PWR_Sleep_Mode_Entry PWR Sleep Mode Entry * @{ */ -#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ -#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (0x03U) /** * @} */ @@ -115,8 +116,9 @@ typedef struct /** @defgroup PWR_Stop_Mode_Entry PWR Stop Mode Entry * @{ */ -#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ -#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (0x03U) /** * @} */ @@ -703,12 +705,14 @@ typedef struct ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) /* Sleep mode entry check macro */ -#define IS_PWR_SLEEP_ENTRY(ENTRY) \ - (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) /* Stop mode entry check macro */ -#define IS_PWR_STOP_ENTRY(ENTRY) \ - (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) /* PWR items check macro */ #define IS_PWR_ITEMS_ATTRIBUTES(ITEM) \ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h index f82be56665..f2d8cee0fc 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h @@ -325,8 +325,6 @@ typedef struct */ - - /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output * @{ */ @@ -4708,10 +4706,10 @@ typedef struct * @arg @ref RCC_FLAG_LPWRRST Low Power reset * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) +#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5UL) == 1UL) ? RCC->CR : \ + ((((__FLAG__) >> 5UL) == 2UL) ? RCC->BDCR : \ + ((((__FLAG__) >> 5UL) == 3UL) ? RCC->CSR : RCC->CIFR)))) & \ + (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0UL) ? 1U : 0U) /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h index 1498a1289e..5f0cd89b11 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h @@ -312,7 +312,7 @@ typedef struct @ref RCCEx_CRS_ErrorLimitDefault */ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of + This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ } RCC_CRSInitTypeDef; @@ -1030,7 +1030,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h index 49dca859a6..3688ac6951 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h @@ -179,6 +179,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h index ca8bae8c67..4c1c21ffe5 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h @@ -35,19 +35,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -56,13 +56,15 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ + uint32_t NoiseSource; /*!< RNG noise source control(Oscillator Enable signals) + must be a value between 0x0 and 0x0003FFFF */ } RNG_ConfigTypeDef; /** @@ -70,11 +72,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -113,7 +115,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -122,7 +124,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -137,7 +139,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -146,7 +148,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -155,7 +157,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -164,7 +166,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -203,7 +205,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -212,11 +214,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -227,7 +229,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h index 902b9e3867..fedd50e3f3 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h @@ -743,6 +743,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) +/** + * @brief Get RTC Binary mode. + * @param __HANDLE__ specifies the RTC handle. + * @retval The selected RTC Binary mode (RTC_BINARY_NONE, RTC_BINARY_ONLY, or RTC_BINARY_MIX). + */ +#define __HAL_RTC_GET_BINARY_MODE(__HANDLE__) (READ_REG(RTC->ICSR & RTC_ICSR_BIN)) + /** * @} */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h index 61e1e37e92..2c15c2e47e 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h @@ -998,7 +998,7 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CWUTF)) /** * @} @@ -1087,8 +1087,8 @@ typedef struct * @retval None */ #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ - ((__FLAG__) == RTC_FLAG_TSF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\ - ((__FLAG__) == RTC_FLAG_TSOVF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\ + ((__FLAG__) == RTC_FLAG_TSF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF)):\ (0U)) /* Dummy action because is an invalid parameter value */ /** @@ -1446,9 +1446,9 @@ typedef struct */ #define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U) /** - * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @brief Check whether the specified RTC SSRU interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval The state of __INTERRUPT__ (TRUE or FALSE) @@ -1466,14 +1466,14 @@ typedef struct #define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) /** - * @brief Clear the RTC Wake Up timer's pending flags. + * @brief Clear the RTC SSRU's pending flags. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC SSRU Flag to clear. * This parameter can be: * @arg @ref RTC_FLAG_SSRUF * @retval None */ -#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF)) +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF)) /** * @} */ @@ -1659,7 +1659,6 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) - #define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h index b78526d48e..67105dd018 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h @@ -48,12 +48,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -293,7 +291,6 @@ typedef enum HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ @@ -1218,7 +1215,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1233,8 +1230,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h index 436e171231..a4b1fd5728 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h @@ -67,7 +67,7 @@ typedef struct uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection - or @ref LPUARTEx_Autonomous_Trigger_selection.*/ + or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ @@ -194,7 +194,7 @@ typedef struct * @} */ -/** @defgroup LPUARTEx_Autonomous_Trigger_selection LPUARTEx Autonomous trigger selection +/** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection * @brief LPUART Autonomous Trigger selection * @{ */ @@ -240,8 +240,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h index cc85ca14c2..718016b8ca 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h @@ -33,6 +33,7 @@ extern "C" { */ #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) /* Exported types ------------------------------------------------------------*/ /** @defgroup DLYB_LL DLYB @@ -113,8 +114,8 @@ __STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx) * @{ */ -void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); -void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); +void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef *pdlyb_cfg); +void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); /** @@ -129,6 +130,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c * @} */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ #endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c index 62a57cc90a..8fcd85a4b6 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c @@ -53,12 +53,12 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.3.0 + * @brief STM32U5xx HAL Driver version number 1.6.2 */ -#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32U5xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x02UL) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32U5xx_HAL_VERSION_SUB2 << 8U )\ @@ -89,7 +89,7 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @{ */ -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim @@ -130,8 +130,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on MSI clock, as MSI is the clock + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on MSI clock, as MSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. @@ -151,6 +151,9 @@ HAL_StatusTypeDef HAL_Init(void) /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { @@ -234,29 +237,57 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + uint32_t ticknumber = 0U; + uint32_t systicksel; + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if ((uint32_t)uwTickFreq == 0UL) { return HAL_ERROR; } - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + /* Check Clock source to calculate the tickNumber */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) { - return HAL_ERROR; + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + else { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; + systicksel = HAL_SYSTICK_GetCLKSourceConfig(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + /* LSI selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + /* LSE selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + default: + /* Nothing to do */ + break; + } } - else + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(ticknumber) > 0U) { return HAL_ERROR; } + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + /* Return function status */ return HAL_OK; } @@ -265,7 +296,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Group2 HAL Control functions +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim @@ -292,7 +323,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None @@ -329,16 +360,25 @@ uint32_t HAL_GetTickPrio(void) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); - - if (status == HAL_OK) + if (status != HAL_OK) { - uwTickFreq = Freq; + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; } } @@ -634,7 +674,7 @@ void HAL_SYSCFG_DisableVREFBUF(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_EnableIOAnalogBooster(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -644,11 +684,65 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_DisableIOAnalogBooster(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +/** + * @brief Enable the I/O analog switch voltage selection + * + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable the I/O analog switch voltage selection + * + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DECOUPLING_CAPACITANCE(Capacitance)); + + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + */ +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + #if defined(SYSCFG_CFGR1_SRAMCACHED) /** * @brief Enable the Cacheability of internal SRAMx by DCACHE2 @@ -706,6 +800,7 @@ void HAL_SYSCFG_EnableVddHSPICompensationCell(void) SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); } #endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Disable the Compensation Cell of GPIO supplied by VDD * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell @@ -815,8 +910,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions * @brief SYSCFG attributes management functions. * @@ -907,7 +1000,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri This parameter can be one of @ref SYSCFG_OTG_PHY_Enable * @retval None */ - void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) { /* Check the parameter */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c index 2ece94128d..8dd0ec3b79 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c @@ -75,19 +75,23 @@ (++) Reload Value should not exceed 0xFFFFFF [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** + *** How to configure MPU using CORTEX HAL driver *** =========================================================== [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. + This section provides functions allowing to configure the Memory Protection Unit (MPU). + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. @endverbatim ****************************************************************************** @@ -274,7 +278,23 @@ void HAL_NVIC_SystemReset(void) */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - return SysTick_Config(TicksNumb); + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); } /** * @} @@ -437,6 +457,52 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) } } +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + uint32_t systick_rcc_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + systick_rcc_source = READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL); + + switch (systick_rcc_source) + { + case (0x00000000U): + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + + case (RCC_CCIPR1_SYSTICKSEL_0): + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case (RCC_CCIPR1_SYSTICKSEL_1): + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + /** * @brief Handle SYSTICK interrupt request. * @retval None @@ -556,6 +622,82 @@ void HAL_MPU_Disable_NS(void) } #endif /* __ARM_FEATURE_CMSE */ +/** + * @brief Enable the MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the non-secure MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /*__ARM_FEATURE_CMSE*/ + +/** + * @brief Disable the MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /*__ARM_FEATURE_CMSE*/ + /** * @brief Initialize and configure the Region and the memory to be protected. * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains @@ -623,6 +765,9 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const #endif /* __ARM_FEATURE_CMSE */ assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ __DMB(); @@ -630,29 +775,20 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const /* Set the Region number */ MPUx->RNR = pMPU_RegionInit->Number; - if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); - assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); - - MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | - ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | - ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); - - MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | - ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); - } - else - { - MPUx->RLAR = 0U; - MPUx->RBAR = 0U; - } + /* Disable the Region */ + CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk); + + MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); } + static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) { __IO uint32_t *p_mair; diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c index c5f0f88e18..59e214eaeb 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c @@ -364,6 +364,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -636,6 +637,13 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -650,10 +658,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1207,7 +1228,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1380,11 +1405,25 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1475,10 +1514,22 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1585,7 +1636,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1614,6 +1671,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1688,7 +1746,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1716,6 +1780,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1773,7 +1838,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1879,6 +1950,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1935,7 +2007,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1963,6 +2041,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -2006,26 +2085,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->IER; + uint32_t itflagsr = hcryp->Instance->SR; + uint32_t itflagisr = hcryp->Instance->ISR; + /* Check if Read or write error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + if ((itsource & CRYP_IT_RWEIE) != 0U) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + if ((itflagsr & CRYP_FLAG_WRERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + if ((itflagsr & CRYP_FLAG_RDERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } } /* Check if Key error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + if ((itsource & CRYP_IT_KEIE) != 0U) { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + if ((itflagisr & CRYP_FLAG_KEIF) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); @@ -2034,9 +2117,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + if ((itflagisr & CRYP_FLAG_CCF) != 0U) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) != 0U) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -3537,7 +3620,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3611,7 +3718,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -5762,7 +5868,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c index d57627fd31..0d126caaa4 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c @@ -40,7 +40,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -67,6 +67,7 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions * @{ @@ -126,6 +127,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -144,19 +152,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -460,7 +465,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -505,7 +516,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } status = CRYPEx_KeyDecrypt(hcryp, Timeout); } else @@ -725,6 +742,31 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c index daf3d32f3c..6e9299ecc7 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c @@ -23,7 +23,7 @@ ********************************************************************************************************************** @verbatim ====================================================================================================================== - ############### How to use this driver ############### + ##### How to use this driver ##### ====================================================================================================================== [..] @@ -96,8 +96,7 @@ (++) can be a value of DMA_Transfer_Event_Mode (+) Mode : Specifies the transfer mode for the DMA channel - (++) can be a value of DMA_Transfer_Mode - + (++) can be DMA_NORMAL *** Polling mode IO operation *** ================================= @@ -218,7 +217,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma); * @verbatim ====================================================================================================================== - ############### Initialization and de-initialization functions ############### + ##### Initialization and de-initialization functions ##### ====================================================================================================================== [..] This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. @@ -252,7 +251,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - if ((hdma->Init.Direction == DMA_MEMORY_TO_PERIPH) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)) + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) { assert_param(IS_DMA_REQUEST(hdma->Init.Request)); } @@ -275,6 +274,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Allocate lock resource */ __HAL_UNLOCK(hdma); + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -379,7 +389,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -423,7 +433,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### IO operation functions ############### + ##### IO operation functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -892,20 +902,20 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Global Interrupt Flag management *********************************************************************************/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) #else if (global_active_flag_ns == 0U) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { return; /* the global interrupt flag for the current channel is down , nothing to do */ } /* Data Transfer Error Interrupt management *************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) @@ -919,7 +929,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Update Linked-list Error Interrupt management ********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) @@ -933,7 +943,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* User Setting Error Interrupt management **************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) @@ -947,7 +957,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Trigger Overrun Interrupt management *****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) @@ -961,7 +971,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Half Transfer Complete Interrupt management **********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) @@ -979,7 +989,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Suspend Transfer Interrupt management ****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) @@ -996,19 +1006,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */ - __NOP(); - - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1048,7 +1047,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Transfer Complete Interrupt management ***************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) @@ -1100,19 +1099,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */ - __NOP(); - - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1309,7 +1297,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, * @verbatim ====================================================================================================================== - ############### State and Errors functions ############### + ##### State and Errors functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1355,7 +1343,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) * @verbatim ====================================================================================================================== - ############### DMA Attributes functions ############### + ##### DMA Attributes functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1462,7 +1450,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); } } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } @@ -1496,7 +1484,6 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel privilege attribute */ attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Get DMA channel security attribute */ attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; @@ -1506,14 +1493,12 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel destination security attribute */ attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* return value */ *pChannelAttributes = attributes; return HAL_OK; } - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Lock the DMA channel security and privilege attribute(s). @@ -1543,7 +1528,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h return HAL_OK; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Get the security and privilege attribute lock state of a DMA channel. @@ -1555,7 +1540,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) { - DMA_TypeDef *p_dma_instance; + const DMA_TypeDef *p_dma_instance; uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c index ded17ef88e..c60e908201 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c @@ -26,7 +26,7 @@ ********************************************************************************************************************** @verbatim ====================================================================================================================== - ############### How to use this driver ############### + ##### How to use this driver ##### ====================================================================================================================== [..] Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as @@ -538,9 +538,15 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, DMA_NodeTypeDef *const pNode); static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3); +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3); +#endif /* __GNUC__ && !__CC_ARM */ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3); @@ -582,7 +588,7 @@ static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); * @verbatim ====================================================================================================================== - ############### Linked-List Initialization and De-Initialization Functions ############### + ##### Linked-List Initialization and De-Initialization Functions ##### ====================================================================================================================== [..] This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. @@ -677,7 +683,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ DMA_TypeDef *p_dma_instance; - /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -694,7 +699,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); - /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -739,7 +743,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -791,7 +795,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List IO Operation Functions ############### + ##### Linked-List IO Operation Functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -957,7 +961,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List Management Functions ############### + ##### Linked-List Management Functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1094,17 +1098,13 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); } /* Check DMA channel security and privilege attributes parameters */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Build the DMA channel node */ DMA_List_BuildNode(pNodeConfig, pNode); @@ -3224,7 +3224,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Data handling, repeated block and trigger configuration functions ############### + ##### Data handling, repeated block and trigger configuration functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -3451,7 +3451,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, * @verbatim ====================================================================================================================== - ############### Suspend and resume operation functions ############### + ##### Suspend and resume operation functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -3614,7 +3614,7 @@ HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Fifo status function ############### + ##### Fifo status function ##### ====================================================================================================================== [..] This section provides function allowing to get DMA channel FIFO level. @@ -3736,7 +3736,7 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, { pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Add parameters related to DMA configuration */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) @@ -3906,7 +3906,6 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, /********************************************************************************* CBR2 register value is updated */ } - /* Update node information value ************************************************************************************/ /* Set node information */ pNode->NodeInfo = pNodeConfig->NodeType; @@ -3971,7 +3970,7 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, { pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*********************************************************************************** CTR1 fields values are updated */ @@ -4090,9 +4089,15 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3) +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3) +#endif /* __GNUC__ && !__CC_ARM */ { uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); uint32_t ref = 0U; @@ -4461,7 +4466,7 @@ static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, uint32_t contextnode_reg_counter = 0U; uint32_t cllr_idx; uint32_t cllr_mask; - DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c index 20fda2d087..ec02b6b508 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c @@ -627,7 +627,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset. Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t tickstart = HAL_GetTick(); uint32_t error; __IO uint32_t *reg_sr; @@ -638,7 +638,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if (Timeout != HAL_MAX_DELAY) { - if (HAL_GetTick() >= timeout) + if(((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c index dcfcfb7574..1de1e4a9c5 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c @@ -247,8 +247,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure IO Direction mode (Alternate) */ tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U)); - tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * GPIO_MODER_MODE1_Pos)); p_gpio->MODER = tmp; } else if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -260,14 +260,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure Alternate function mapped with the current IO */ tmp = GPIOx->AFR[position >> 3U]; - tmp &= ~(0x0FUL << ((position & 0x07U) * 4U)); - tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U)); + tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); GPIOx->AFR[position >> 3U] = tmp; /* Configure IO Direction mode (Alternate) */ tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); p_gpio->MODER = tmp; } else @@ -277,8 +277,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); p_gpio->MODER = tmp; } @@ -291,8 +291,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure the IO Speed */ tmp = p_gpio->OSPEEDR; - tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U)); - tmp |= (pGPIO_Init->Speed << (pin_position * 2U)); + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); + tmp |= (pGPIO_Init->Speed << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); p_gpio->OSPEEDR = tmp; /* Configure the IO Output Type */ @@ -302,15 +302,16 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) p_gpio->OTYPER = tmp; } - if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) + if ((pGPIO_Init->Mode != GPIO_MODE_ANALOG) || + ((pGPIO_Init->Mode == GPIO_MODE_ANALOG) && (pGPIO_Init->Pull != GPIO_PULLUP))) { /* Check the Pull parameters */ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ tmp = p_gpio->PUPDR; - tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U)); - tmp |= ((pGPIO_Init->Pull) << (pin_position * 2U)); + tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); + tmp |= ((pGPIO_Init->Pull) << (pin_position * GPIO_PUPDR_PUPD1_Pos)); p_gpio->PUPDR = tmp; } @@ -319,8 +320,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { tmp = EXTI->EXTICR[position >> 2U]; - tmp &= ~((0x0FUL) << (8U * (position & 0x03U))); - tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))); + tmp &= ~((0x0FUL) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); + tmp |= (GPIO_GET_INDEX(GPIOx) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); EXTI->EXTICR[position >> 2U] = tmp; /* Clear Rising Falling edge configuration */ @@ -429,19 +430,19 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * 2U)); + p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); /* Configure the default Alternate Function in current IO */ - p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * 4U)); + p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); /* Configure the default value for IO Speed */ - p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U)); + p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); /* Configure the default value IO Output Type */ p_gpio->OTYPER &= ~(GPIO_OTYPER_OT0 << pin_position); /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U)); + p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); } position++; @@ -917,7 +918,7 @@ HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uin /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_ALL)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); /* Check null pointer */ if (pPinAttributes == NULL) diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c index 53e805a31b..f22c3d5e0b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c @@ -613,7 +613,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres break; #if defined (FMC_BANK1) case FMC_BANK1: - size = TZSC_MPCWM1_MEM_SIZE; + size = TZSC_MPCWM2_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) { register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c index 6f92988d5d..43fb5161aa 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c @@ -273,10 +273,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -765,7 +765,7 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -806,7 +806,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -823,7 +823,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -864,7 +864,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -912,7 +912,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -936,7 +936,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -950,7 +950,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -966,7 +966,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -991,7 +991,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1005,7 +1005,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1078,7 +1078,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1108,7 +1108,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1165,7 +1165,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1184,7 +1184,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1226,7 +1226,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1244,7 +1244,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1298,7 +1298,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1323,7 +1323,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1833,12 +1833,15 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint8_t tmp1; + uint8_t tmp2; + uint8_t tmp3; - for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U) + for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++) { /* Write input data 4 bytes at a time */ HASH->DIN = *(uint32_t *)inputaddr; @@ -1846,10 +1849,10 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size)) { /* wait for flag BUSY not set before Wait for DINIS = 1*/ - if (buffercounter >= 64U) + if ((buffercounter * 4U) >= 64U) { if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { @@ -1870,14 +1873,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter + 4U); + hhash->HashInCount = Size - ((buffercounter * 4U) + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter + 4U); + hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U); } else { @@ -1896,6 +1899,50 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ /* At this point, all the data have been entered to the Peripheral: exit */ + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_DATATYPE_16B) + { + /* Write remaining input data */ + + if ((Size % 4U) <= 2U) + { + HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + HASH->DIN = *(uint32_t *)inputaddr; + } + + } + else if ((hhash->Init.DataType == HASH_DATATYPE_8B) + || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + HASH->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp1 = *(uint8_t *)inputaddr; + tmp2 = *(((uint8_t *)inputaddr) + 1U); + tmp3 = *(((uint8_t *)inputaddr) + 2U); + HASH->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U); + } + } + else + { + HASH->DIN = *(uint32_t *)inputaddr; + } + } + + return HAL_OK; } @@ -1905,7 +1952,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2456,10 +2503,10 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2491,7 +2538,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2507,7 +2554,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2515,7 +2562,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2593,9 +2640,9 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2627,7 +2674,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2638,7 +2685,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2696,7 +2743,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2818,7 +2865,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2943,13 +2990,13 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u } } /* if (polling_step == 1) */ else - { + { /* otherwise, carry on in interrupt-mode */ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data to be fed to the Peripheral */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at the next interruption */ - } + } /* Process Unlock */ @@ -2984,7 +3031,7 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3189,7 +3236,7 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3267,7 +3314,7 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3378,7 +3425,7 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c index 32a20b5912..7f38dad076 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c @@ -149,7 +149,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -175,7 +175,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -190,7 +190,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -207,7 +207,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -248,7 +248,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -291,7 +291,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -329,7 +329,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -345,7 +345,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -369,7 +369,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -383,7 +383,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -435,7 +435,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -465,7 +465,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -522,7 +522,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -541,7 +541,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -584,7 +584,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -602,7 +602,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -660,7 +660,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -684,7 +684,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -760,7 +760,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -781,7 +781,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -807,7 +807,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -830,7 +830,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -877,7 +877,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -899,7 +899,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -920,7 +920,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -946,7 +946,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -968,7 +968,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -989,7 +989,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1015,7 +1015,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c index 250041e110..3f23b88cf2 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c @@ -91,7 +91,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -157,7 +157,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -215,7 +215,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1364,6 +1364,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1390,14 +1392,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1411,6 +1405,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1422,6 +1428,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1434,6 +1444,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1457,31 +1471,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -2912,6 +2943,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -3427,6 +3459,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3484,53 +3518,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -4835,7 +4880,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4844,7 +4889,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -5510,9 +5557,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5941,9 +5987,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6545,14 +6590,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (tmpstate == HAL_I2C_STATE_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; @@ -6562,6 +6607,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -6616,7 +6666,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6630,6 +6680,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -6721,7 +6822,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -7218,12 +7319,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7263,7 +7370,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7302,7 +7409,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7329,16 +7436,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -7346,19 +7455,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -7372,14 +7476,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7387,11 +7495,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** @@ -7546,15 +7654,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c index 36b790e594..38383d3018 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c @@ -46,30 +46,35 @@ The ICACHE HAL driver can be used as follows: (#) Optionally configure the Instruction Cache mode with - @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration + HAL_ICACHE_ConfigAssociativityMode() if the default configuration does not suit the application requirements. (#) Enable and disable the Instruction Cache with respectively - @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable(). - Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). + Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. (#) Initiate the cache maintenance invalidation procedure with either - @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT() + HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() (interrupt mode). When interrupt mode is used, the callback function - @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate - procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete() + HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate + procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() may be called to wait for the end of the invalidate procedure automatically - initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable(). + initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). The cache operation is bypassed during the invalidation procedure. (#) Use the performance monitoring counters for Hit and Miss with the following - functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(), - @ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and - @ref HAL_ICACHE_Monitor_GetMissValue() + functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), + HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and + HAL_ICACHE_Monitor_GetMissValue() (#) Enable and disable up to four regions to remap input address from external memories to the internal Code region for execution with - @ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion() + HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() @endverbatim */ @@ -85,7 +90,7 @@ * @brief HAL ICACHE module driver * @{ */ -#ifdef HAL_ICACHE_MODULE_ENABLED +#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -184,32 +189,32 @@ HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) /** * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) + * @retval HAL status (HAL_OK) */ HAL_StatusTypeDef HAL_ICACHE_DeInit(void) { - HAL_StatusTypeDef status; + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); - /* Disable cache with reset value for 2-ways set associative mode */ + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); /* Stop monitor and reset monitor values */ - (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS); - (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS); + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - /* No remapped regions */ - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3); + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - /* Wait for end of invalidate cache procedure */ - status = HAL_ICACHE_WaitForInvalidateComplete(); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - return status; + return HAL_OK; } /** @@ -282,22 +287,15 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) { HAL_StatusTypeDef status; - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - /* Launch cache invalidation */ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - - status = HAL_ICACHE_WaitForInvalidateComplete(); } + status = HAL_ICACHE_WaitForInvalidateComplete(); + return status; } @@ -643,7 +641,7 @@ HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) * @} */ -#endif /* HAL_ICACHE_MODULE_ENABLED */ +#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ /** * @} diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c index d888e2adfc..1829f1c906 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c @@ -1149,7 +1149,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1242,7 +1243,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -2709,8 +2711,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c index eab1bf3c65..c4c487476b 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c @@ -277,6 +277,7 @@ * @{ */ #define PKA_RAM_SIZE 1334U +#define PKA_RAM_ERASE_TIMEOUT 1000U /* Private macro -------------------------------------------------------------*/ #define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ @@ -288,9 +289,6 @@ */ /* Private variables ---------------------------------------------------------*/ -static uint32_t primeordersize; -static uint32_t opsize; -static uint32_t modulussize; /* Private function prototypes -----------------------------------------------*/ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ @@ -310,6 +308,7 @@ HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode); void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); @@ -399,8 +398,22 @@ HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) /* Set the state to busy */ hpka->State = HAL_PKA_STATE_BUSY; - /* Reset the control register and enable the PKA */ - hpka->Instance->CR = PKA_CR_EN; + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ + while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* Set timeout status */ + err = HAL_TIMEOUT; + break; + } + } /* Get current tick */ tickstart = HAL_GetTick(); @@ -502,12 +515,50 @@ __weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka) */ __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpka); - - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, the HAL_PKA_MspDeInit can be implemented in the user file + user should take into consideration PKA RAM erase when resetting PKA */ + uint32_t tickstart = HAL_GetTick(); + + /* Enable PKA reset state */ + __HAL_RCC_PKA_FORCE_RESET(); + + /* Release PKA from reset state */ + __HAL_RCC_PKA_RELEASE_RESET(); + + /* Wait the INITOK flag Setting */ + while (hpka->Instance->CR != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + } + + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Wait the INITOK flag Setting */ + if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, PKA_RAM_ERASE_TIMEOUT) != HAL_OK) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* PKA Periph clock disable */ + hpka->Instance->CR = 0; + __HAL_RCC_PKA_CLK_DISABLE(); + + /* PKA Periph IRQ disable */ + HAL_NVIC_DisableIRQ(PKA_IRQn); } #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) @@ -728,6 +779,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode() (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx() (++) HAL_PKA_ECCDoubleBaseLadder() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine() @@ -772,6 +824,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode_IT(); (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx_IT(); (++) HAL_PKA_ECCDoubleBaseLadder_IT() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine_IT() @@ -809,9 +862,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -826,9 +877,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -844,9 +893,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -861,9 +908,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -881,9 +926,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -898,12 +941,11 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } + /** * @brief Retrieve operation result. * @param hpka PKA handle @@ -915,7 +957,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) uint32_t size; /* Get output result size */ - size = opsize; + size = hpka->opsize; /* Move the result to appropriate location (indicated in out parameter) */ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); @@ -932,9 +974,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - - primeordersize = in->primeOrderSize; - + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -949,9 +989,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - - primeordersize = in->primeOrderSize; - + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -968,7 +1006,7 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe uint32_t size; /* Get output result size */ - size = primeordersize; + size = hpka->primeordersize; if (out != NULL) @@ -1084,11 +1122,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1099,11 +1144,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** @@ -1129,9 +1181,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - - modulussize = in->modulusSize; - + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1146,9 +1196,37 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); + hpka->modulussize = in->modulusSize; + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} +/** + * @brief ECC scalar multiplication extended in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + hpka->modulussize = in->modulusSize; + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} - modulussize = in->modulusSize; - +/** + * @brief ECC scalar multiplication extended in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1163,7 +1241,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out uint32_t size; /* Get output result size */ - size = modulussize; + size = hpka->modulussize; /* If a destination buffer is provided */ if (out != NULL) @@ -1705,13 +1783,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) { uint32_t mode = PKA_GetMode(hpka); - FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR); - FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR); - FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND); - FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); /* Address error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET)) + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; @@ -1720,7 +1796,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* RAM access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET)) + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; @@ -1729,7 +1805,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* OPERATION access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET)) + if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; @@ -1793,7 +1869,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* End Of Operation interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET)) + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) { /* Clear PROCEND flag */ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); @@ -2592,7 +2668,50 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); } +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} /** * @brief Set input parameters. diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c index 069dad242b..b22827af06 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c @@ -298,8 +298,11 @@ void HAL_PWR_DisableBkUpAccess(void) The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode() function. - (++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction. - (++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction. + (++) PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + clear of pending events before. + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. -@@- The Regulator parameter is not used for the STM32U5 family and is kept as parameter just to maintain compatibility with other families. @@ -327,8 +330,11 @@ void HAL_PWR_DisableBkUpAccess(void) with : (++) StopEntry: - (+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction. - (+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction. + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: Enter STOP mode with WFE instruction and + no clear of pending event before. -@@- The Regulator parameter is not used for the STM32U5 family and is kept as parameter just to maintain compatibility with other families. @@ -523,13 +529,11 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * products. * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE * instruction. - * This parameter can be one of the following values : - * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait - * For Interrupt request. - * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait - * For Event request. - * @note When WFI entry is used, ticks interrupt must be disabled to avoid - * unexpected CPU wake up. + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. * @retval None. */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) @@ -550,9 +554,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) } else { - /* Wait For Event Request */ - __SEV(); - __WFE(); + if (SleepEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ __WFE(); } } @@ -581,10 +590,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE * instruction. * This parameter can be one of the following values : - * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait - * For Interrupt request. - * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait - * For Event request. + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. * @retval None. */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) @@ -608,9 +618,14 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) } else { - /* Wait For Event Request */ - __SEV(); - __WFE(); + if (StopEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ __WFE(); } @@ -821,6 +836,13 @@ __weak void HAL_PWR_PVDCallback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of @ref PWR_Items. * @param Attributes : Specifies the available attribute(s). @@ -918,6 +940,8 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; } #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); /* Get Non-Secure privileges attribute */ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; #endif /* __ARM_FEATURE_CMSE */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c index 37265e420b..d16da4bad7 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c @@ -865,7 +865,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN1); } } @@ -878,7 +878,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN2); } } @@ -891,7 +891,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN3); } } @@ -904,7 +904,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN4); } } @@ -917,7 +917,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN5); } } @@ -930,7 +930,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN6); } } @@ -943,7 +943,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN7); } } @@ -956,7 +956,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN8); } } } @@ -2400,7 +2400,7 @@ void HAL_PWREx_DisableSRAM4FastWakeUp(void) * @verbatim =============================================================================== - ##### I/O Pull-Up Pull-Down Configuration Functions ##### + ##### IO Pull-Up Pull-Down Configuration Functions ##### =============================================================================== [..] In Standby and Shutdown mode, pull up and pull down can be configured to diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c index edff155664..eddb2dbe3c 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c @@ -362,21 +362,6 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; - /* Increasing the CPU frequency */ - if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) - { - return HAL_ERROR; - } - - } - tickstart = HAL_GetTick(); /* Set MSION bit */ @@ -508,17 +493,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = MSI_VALUE; /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) - { - return HAL_ERROR; - } + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; } /* Adapt Systick interrupt period */ @@ -1243,9 +1226,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruc __HAL_RCC_PWR_CLK_DISABLE(); } - /* Enable PLL System Clock output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); - /* Enable the main PLL */ __HAL_RCC_PLL_ENABLE(); @@ -1259,6 +1239,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruc return HAL_TIMEOUT; } } + + /* Enable PLL System Clock output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + } else { @@ -1674,6 +1658,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio_initstruct; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); @@ -2044,11 +2032,11 @@ void HAL_RCC_NMI_IRQHandler(void) /* Check RCC CSSF interrupt flag */ if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); } } @@ -2079,6 +2067,14 @@ __weak void HAL_RCC_CSSCallback(void) /** * @brief Configure the RCC item attribute(s). * @note Available attributes are to secure items and set RCC as privileged. + * @note As the privileged attributes concern either all secure or all + * non-secure RCC resources accesses and not each RCC individual items + * access attribute, the application must ensure that the privilege + * access attribute configurations are coherent amongst the security + * level set on RCC individual items so not to overwrite a previous + * more restricted access rule (consider either all secure and/or all + * non-secure RCC resources accesses by privileged-only transactions or + * privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items * @param Attributes specifies the RCC secure/privilege attributes. @@ -2114,14 +2110,18 @@ void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) CLEAR_BIT(RCC->SECCFGR, Item); CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); break; -#else +#else /* Non-secure Privilege attribute */ case RCC_NSEC_PRIV: SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; /* Non-secure Non-Privilege attribute */ case RCC_NSEC_NPRIV: CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; #endif /* __ARM_FEATURE_CMSE */ default: @@ -2171,6 +2171,9 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut #else /* Get Non-Secure privileges attribute */ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + #endif /* __ARM_FEATURE_CMSE */ /* return value */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c index ab25e158ba..b08f34f360 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c @@ -332,7 +332,7 @@ #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) -#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) @@ -1266,7 +1266,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe } - /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c index b8546c5bc2..1ad42fb4da 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c @@ -198,8 +198,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR_NIST_VALUE */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -234,12 +246,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -642,6 +654,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } @@ -675,8 +689,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; status = HAL_ERROR; - /* Clear bit DRDY */ - CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } else /* No seed error */ { diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c index f5a72796af..9a98e9c36c 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c @@ -31,7 +31,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -42,7 +42,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -54,11 +54,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -130,6 +130,9 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT /* RNG health test control in accordance with NIST */ WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); + /* RNG noise source control in accordance with NIST */ + WRITE_REG(hrng->Instance->NSCR, pConf->NoiseSource); + /* Writing bit CONDRST=0*/ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); /* Get tick */ @@ -270,7 +273,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -307,6 +310,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c index 7edd7bed06..e3c01161e6 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c @@ -67,8 +67,10 @@ =================================================================== [..] (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. + (+) Configure the RTC prescalers (asynchronous and synchronous), the RTC mode + (binary, BCD or mix) and the RTC hour format using the HAL_RTC_Init() function. + (+) In order to reconfigure the RTC peripheral, it is necessary to use HAL_RTC_DeInit() + first, then use HAL_RTC_Init() again. *** Time and Date configuration *** =================================== @@ -363,44 +365,54 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Check if the calendar has been not initialized */ + /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar does not need to be initialized as the 'binary only' mode is selected */ + status = HAL_OK; + } } else { - /* Calendar is already initialized */ - /* Set flag to OK */ + /* The calendar is already initialized */ status = HAL_OK; } @@ -1488,12 +1500,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm A output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRAOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); } else { /* Disable the Alarm A output clear */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRAOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); } /* Configure the Alarm state: Enable Alarm */ SET_BIT(RTC->CR, RTC_CR_ALRAE); @@ -1520,12 +1532,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm B output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRBOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); } else { /* Disable the Alarm B output clear */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRBOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); } /* Configure the Alarm state: Enable Alarm */ SET_BIT(RTC->CR, RTC_CR_ALRBE); @@ -1693,12 +1705,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm A output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRAOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); } else { /* Disable the Alarm A output clear*/ - CLEAR_BIT(RTC->CR, RTC_CR_ALRAOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); } /* Configure the Alarm interrupt */ @@ -1726,12 +1738,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm B Output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRBOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); } else { /* Disable the Alarm B Output clear */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRBOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); } /* Configure the Alarm interrupt */ @@ -1739,7 +1751,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } - hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c index 83335c2fe3..c448a76ec0 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c @@ -29,8 +29,10 @@ ============================================================================== [..] (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. + (+) Configure the RTC prescalers (asynchronous and synchronous), the RTC mode + (binary, BCD or mix) and the RTC hour format using the HAL_RTC_Init() function. + (+) In order to reconfigure the RTC peripheral, it is necessary to use HAL_RTC_DeInit() + first, then use HAL_RTC_Init() again. *** RTC Wakeup configuration *** ================================ @@ -88,10 +90,6 @@ with interrupt mode using HAL_RTCEx_SetTamper_IT() function. (+) The default configuration of the Tamper erases the backup registers. To avoid erase, enable the NoErase field on the RTC_TAMPCR register. - (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to - perform TAMP base address offset calculation. - (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization - by setting ClockEnable inti field to RTC_CLOCK_DISABLE. (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using setting Interrupt field. @@ -657,7 +655,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t */ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart; /* Process Locked */ __HAL_LOCK(hrtc); @@ -670,32 +667,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) - { - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - else - { - break; - } - } - } - /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -901,7 +872,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo } } /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Smooth calibration settings */ MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), @@ -1012,7 +983,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - + /* Check if the reference clock detection is disabled */ if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) { @@ -1619,7 +1590,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | \ (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); - if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) { tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); } @@ -1784,7 +1755,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active } } - WRITE_REG(TAMP->IER, IER); WRITE_REG(TAMP->IER, IER); WRITE_REG(TAMP->ATCR1, ATCR1); WRITE_REG(TAMP->ATCR2, ATCR2); diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c index 9eb4e1b19c..8d09892627 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c @@ -722,7 +722,6 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -847,7 +846,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -966,10 +964,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -980,9 +975,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -996,10 +988,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1010,8 +999,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -1028,75 +1015,76 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1456,6 +1444,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ if (huart->hdmatx != NULL) { /* Set the UART DMA transfer complete callback */ @@ -1518,9 +1511,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } } +#if !defined(USART_DMAREQUESTS_SW_WA) /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -2589,6 +2584,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3466,7 +3483,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { @@ -3823,12 +3840,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3861,12 +3890,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3931,7 +3970,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4603,6 +4641,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4767,6 +4806,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c index a8395d4a75..2953fad1e1 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c @@ -25,7 +25,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -254,12 +254,11 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -324,19 +323,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -344,13 +343,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -556,7 +555,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -706,6 +705,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; @@ -825,6 +832,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; @@ -924,17 +939,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c index ff5b4ea9dd..1ee2afc6f4 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c @@ -62,6 +62,7 @@ */ #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) /** @cond 0 @@ -107,7 +108,7 @@ * - SUCCESS: the Delay value is set. * - ERROR: the Delay value is not set. */ -void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef *pdlyb_cfg) { /* Check the DelayBlock instance */ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); @@ -130,7 +131,7 @@ void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) * - SUCCESS: the Delay value is received. * - ERROR: the Delay value is not received. */ -void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) { /* Check the DelayBlock instance */ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); @@ -207,14 +208,14 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c pdlyb_cfg->Units = i ; /* Disable the length sampling */ - DLYBx->CR = DLYB_CR_SEN; + CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); return (uint32_t)SUCCESS; } } /* Disable the length sampling */ - DLYBx->CR = DLYB_CR_SEN; + CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); return (uint32_t)ERROR; @@ -231,6 +232,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c /** * @} */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ #endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** From 2cee3967efa9d3681ce050e9328d2f2b8ea78858 Mon Sep 17 00:00:00 2001 From: BUDKE Gerson Fernando Date: Fri, 25 Jul 2025 10:13:14 +0200 Subject: [PATCH 080/133] [zep fromtree] platform: stm: b_u585i_iot02a: Change flash layout The b_u585i_iot02a board have an external flash memory which is already enabled inside tf-m. This proposes a new layout to increase the space for bootloader, S and NS firmware to allow bigger applications to be developed. The firmware upgrade then will use the first sectors from external NOR memory as the secundary slots. With this change the bootloader still have 16k available to handle future needs but keeps the applications partitions the same. Change-Id: Ibb1b12cfbd2eca60736fb2d45f7dbea79807381f Signed-off-by: BUDKE Gerson Fernando (cherry picked from commit 6aa16b2f9f834466b60b452a27f2476c4d69c87c) --- .../b_u585i_iot02a/partition/flash_layout.h | 92 +++++++++++-------- 1 file changed, 55 insertions(+), 37 deletions(-) diff --git a/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h b/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h index 06a0ac2451..026df06591 100644 --- a/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h +++ b/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h @@ -29,27 +29,32 @@ */ /* Flash layout for b_u585i_iot02a with BL2 (multiple image boot): * + * Boot partition (384 KB): * 0x0000_0000 SCRATCH (64KB) * 0x0001_0000 BL2 - counters(16 KB) - * 0x0001_4000 BL2 - MCUBoot (84 KB) - * 0x0002_7000 OTP Write Protect (4KB) - * 0x0002_8000 NV counters area (16 KB) - * 0x0002_c000 Secure Storage Area (16 KB) - * 0x0003_0000 Internal Trusted Storage Area (16 KB) - * 0x0003_8000 Secure image primary slot (384 KB) - * 0x0009_8000 Non-secure image primary slot (512 KB) - * 0x0011_8000 Secure image secondary slot (384 KB) - * 0x0017_8000 Non-secure image secondary slot (512 KB) + * 0x0001_4000 BL2 - MCUBoot protected (136 KB) + * 0x0003_6000 BL2 - MCUBoot unprotected (4 KB) + * 0x0003_7000 OTP Write Protect (4KB) + * 0x0003_8000 NV counters area (16 KB) + * 0x0003_c000 Secure Storage Area (64 KB) + * 0x0004_c000 Internal Trusted Storage Area (64 KB) + * 0x0005_c000 > reserved for bootloader purposes (16k) + * 0x0006_0000 Secure image primary slot (512 KB) Internal flash + * 0x000f_0000 Non-secure image primary slot (1024 KB) Internal flash + * 0x001f_0000 User Defined primary slot (128 KB) Internal flash (ex. Zephyr storage) + * 0x0000_0000 Secure image secondary slot (512 KB) External flash + * 0x0008_0000 Non-secure image secondary slot (3072 KB) External flash + * 0x0018_0000 > User Defined External flash * * Bl2 binary is written at 0x1_2000: * it contains bl2_counter init value, OTP write protect, NV counters area init. */ /* Flash layout info for BL2 bootloader */ -#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x2000) /* 8 KB */ -#define FLASH_B_SIZE (0x100000) /* 1 MBytes*/ -#define FLASH_TOTAL_SIZE (FLASH_B_SIZE+FLASH_B_SIZE) /* 2 MBytes */ -#define FLASH_BASE_ADDRESS (0x0c000000) /* same as FLASH0_BASE_S */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x2000) /* 8 KB */ +#define FLASH_B_SIZE (0x100000) /* 1 MBytes*/ +#define FLASH_TOTAL_SIZE (FLASH_B_SIZE+FLASH_B_SIZE) /* 2 MBytes */ +#define FLASH_BASE_ADDRESS (0x0c000000) /* same as FLASH0_BASE_S */ /* Flash device ID */ @@ -61,7 +66,7 @@ /* scratch area */ #define FLASH_AREA_SCRATCH_OFFSET (0x0) -#define FLASH_AREA_SCRATCH_SIZE (0x10000) /* 64 KB */ +#define FLASH_AREA_SCRATCH_SIZE (0x10000) /* 64 KB */ /* control scratch area */ #if (FLASH_AREA_SCRATCH_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 @@ -69,12 +74,12 @@ #endif /* (FLASH_AREA_SCRATCH_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0*/ /* area for bl2 anti roll back counter */ -#define FLASH_BL2_NVCNT_AREA_OFFSET (FLASH_AREA_SCRATCH_SIZE) -#define FLASH_BL2_NVCNT_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE+FLASH_AREA_IMAGE_SECTOR_SIZE) +#define FLASH_BL2_NVCNT_AREA_OFFSET (FLASH_AREA_SCRATCH_SIZE) /* @64 KB 0x10000 */ +#define FLASH_BL2_NVCNT_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE+FLASH_AREA_IMAGE_SECTOR_SIZE) /* 16 KB */ /* Area for downloading bl2 image */ -#define FLASH_AREA_BL2_BIN_OFFSET (FLASH_BL2_NVCNT_AREA_OFFSET +FLASH_AREA_IMAGE_SECTOR_SIZE) +#define FLASH_AREA_BL2_BIN_OFFSET (FLASH_BL2_NVCNT_AREA_OFFSET +FLASH_AREA_IMAGE_SECTOR_SIZE) /* @72 KB 0x12000 */ /* personal Area Not used */ -#define FLASH_AREA_PERSO_OFFSET (FLASH_BL2_NVCNT_AREA_OFFSET +FLASH_BL2_NVCNT_AREA_SIZE) +#define FLASH_AREA_PERSO_OFFSET (FLASH_BL2_NVCNT_AREA_OFFSET +FLASH_BL2_NVCNT_AREA_SIZE) /* @80 KB 0x14000 */ #define FLASH_AREA_PERSO_SIZE (0x0) /* control personal area */ #if (FLASH_AREA_PERSO_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 @@ -82,32 +87,32 @@ #endif /* FLASH_AREA_PERSO_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ /* area for BL2 code protected by hdp */ -#define FLASH_AREA_BL2_OFFSET (FLASH_AREA_PERSO_OFFSET+FLASH_AREA_PERSO_SIZE ) -#define FLASH_AREA_BL2_SIZE (0x22000) +#define FLASH_AREA_BL2_OFFSET (FLASH_AREA_PERSO_OFFSET+FLASH_AREA_PERSO_SIZE ) /* @80 KB 0x14000 */ +#define FLASH_AREA_BL2_SIZE (0x22000) /* 136 KB */ /* HDP area end at this address */ -#define FLASH_BL2_HDP_END (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE-1) +#define FLASH_BL2_HDP_END (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE-1) /* @216 KB - 1 */ /* area for BL2 code not protected by hdp */ -#define FLASH_AREA_BL2_NOHDP_OFFSET (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE) -#define FLASH_AREA_BL2_NOHDP_CODE_SIZE (0x1000) -#define FLASH_AREA_OTP_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET+FLASH_AREA_BL2_NOHDP_CODE_SIZE) -#define FLASH_AREA_OTP_SIZE (0x1000) -#define FLASH_AREA_BL2_NOHDP_SIZE (FLASH_AREA_OTP_SIZE+FLASH_AREA_BL2_NOHDP_CODE_SIZE) +#define FLASH_AREA_BL2_NOHDP_OFFSET (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE) /* @216 KB 0x36000 */ +#define FLASH_AREA_BL2_NOHDP_CODE_SIZE (0x1000) /* 4 KB */ +#define FLASH_AREA_OTP_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET+FLASH_AREA_BL2_NOHDP_CODE_SIZE)/* @220 KB 0x37000 */ +#define FLASH_AREA_OTP_SIZE (0x1000) /* 4 KB */ +#define FLASH_AREA_BL2_NOHDP_SIZE (FLASH_AREA_OTP_SIZE+FLASH_AREA_BL2_NOHDP_CODE_SIZE) /* 4 KB */ /* control area for BL2 code protected by hdp */ #if (FLASH_AREA_BL2_NOHDP_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 #error "HDP area must be aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" #endif /* (FLASH_AREA_BL2_NOHDP_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ /* Non Volatile Counters definitions */ -#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE+FLASH_AREA_IMAGE_SECTOR_SIZE) -#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET+FLASH_AREA_BL2_NOHDP_SIZE) +#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE+FLASH_AREA_IMAGE_SECTOR_SIZE)/* 16 KB */ +#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET+FLASH_AREA_BL2_NOHDP_SIZE) /* @224 kB 0x38000 */ /* Control Non Volatile Counters definitions */ #if (FLASH_NV_COUNTER_AREA_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 #error "FLASH_NV_COUNTER_AREA_SIZE not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" #endif /* (FLASH_NV_COUNTER_AREA_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ /* Secure Storage (PS) Service definitions */ -#define FLASH_PS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE+FLASH_AREA_IMAGE_SECTOR_SIZE) -#define FLASH_PS_AREA_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET+FLASH_NV_COUNTERS_AREA_SIZE) +#define FLASH_PS_AREA_SIZE (8 * FLASH_AREA_IMAGE_SECTOR_SIZE) /* 64 KB */ +#define FLASH_PS_AREA_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET+FLASH_NV_COUNTERS_AREA_SIZE) /* @240 KB 0x3c000 */ /* Control Secure Storage (PS) Service definitions*/ #if (FLASH_PS_AREA_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 @@ -115,18 +120,18 @@ #endif /* (FLASH_PS_AREA_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ /* Internal Trusted Storage (ITS) Service definitions */ -#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET+FLASH_PS_AREA_SIZE) -#define FLASH_ITS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE+FLASH_AREA_IMAGE_SECTOR_SIZE) +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET+FLASH_PS_AREA_SIZE) /* @304 KB 0x4c000 */ +#define FLASH_ITS_AREA_SIZE (8 * FLASH_AREA_IMAGE_SECTOR_SIZE) /* 64 KB */ /*Control Internal Trusted Storage (ITS) Service definitions */ #if (FLASH_ITS_AREA_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 #error "FLASH_ITS_AREA_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" #endif /* (FLASH_ITS_AREA_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ -#define FLASH_S_PARTITION_SIZE (0x60000) /* 384 KB for S partition */ -#define FLASH_NS_PARTITION_SIZE (0x80000) /* 512 KB for NS partition */ +#define FLASH_S_PARTITION_SIZE (0x80000) /* 512 KB for S partition */ +#define FLASH_NS_PARTITION_SIZE (0x100000) /* 1024 KB for NS partition */ -#define FLASH_PARTITION_SIZE (FLASH_S_PARTITION_SIZE+FLASH_NS_PARTITION_SIZE) +#define FLASH_PARTITION_SIZE (FLASH_S_PARTITION_SIZE+FLASH_NS_PARTITION_SIZE) /* 1536 KB */ #if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) #define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE @@ -136,7 +141,20 @@ /* Secure image primary slot */ #define FLASH_AREA_0_ID (1) #define FLASH_AREA_0_DEVICE_ID (FLASH_DEVICE_ID-FLASH_DEVICE_ID) -#define FLASH_AREA_0_OFFSET (FLASH_ITS_AREA_OFFSET+FLASH_ITS_AREA_SIZE) + +/* + To merge regions + #define FLASH_AREA_0_OFFSET (FLASH_ITS_AREA_OFFSET+FLASH_ITS_AREA_SIZE) + + Use fixed position offset to start S firmware to keep unsused area betwwen + bootloader and S fimware. This allows bootloader to be increased and have + application code compatible between different bootloader regions. + + The S firmware offset is now: 2MiB - Reserved (128k) - NS (1MiB) - S (512k) => + 0x200000 - 0x20000 - 0x100000 - 0x80000 => 0x60000 +*/ +#define FLASH_AREA_0_OFFSET (0x60000) /* @384 KB 0x60000 */ + /* Control Secure image primary slot */ #if (FLASH_AREA_0_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 #error "FLASH_AREA_0_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" @@ -282,7 +300,7 @@ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) -#define BOOT_TFM_SHARED_DATA_BASE (0x3003fc00) +#define BOOT_TFM_SHARED_DATA_BASE (_SRAM3_BASE_S-BOOT_TFM_SHARED_DATA_SIZE) #define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE #define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE #endif /* __FLASH_LAYOUT_H__ */ From 29ea877d1037d03298fd6faf576550c6e3c3ef42 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Fri, 8 Aug 2025 10:08:22 +0200 Subject: [PATCH 081/133] [zep fromtree] platform: stm32wba65i_dk: Fix install for STM32_FLASH_LAYOUT_BEGIN_OFFSET Install a flash_layout.h header file that consider the value of build directive STM32_FLASH_LAYOUT_BEGIN_OFFSET passed when building TF-M. Without this change, generic code building non-secure application, like when Zephyr builds TF-M regression test non-secure application, do not consider this directive and use flash_layout.h as if STM32_FLASH_LAYOUT_BEGIN_OFFSET was 0. Signed-off-by: Ahmad EL JOUAID Change-Id: Icc20b09041f7bcb0287c932e6a2a13f6fa73e268 (cherry picked from commit eed47eff0e5ab8cac2126e24cb4e84e1148a9f68) --- .../ext/target/stm/stm32wba65i_dk/CMakeLists.txt | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt index 72801ad0f4..46049b8ad2 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt +++ b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt @@ -63,11 +63,22 @@ install(DIRECTORY ${STM_COMMON_DIR}/hal/accelerator/ FILES_MATCHING PATTERN "*.h") install(FILES - ${STM32WBA65I_DK_DIR}/partition/flash_layout.h ${STM32WBA65I_DK_DIR}/partition/region_defs.h DESTINATION ${INSTALL_PLATFORM_NS_DIR}/partition ) +# Install a flash_layout.h header file that consider STM32_FLASH_LAYOUT_BEGIN_OFFSET +# TF-M was built with. +install(FILES + ${STM32WBA65I_DK_DIR}/partition/flash_layout.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/partition/gen_layout +) + +file(WRITE ${INSTALL_PLATFORM_NS_DIR}/partition/flash_layout.h + "#define STM32_FLASH_LAYOUT_BEGIN_OFFSET ${STM32_FLASH_LAYOUT_BEGIN_OFFSET}\n" + "#include \"gen_layout/flash_layout.h\"\n" +) + install(DIRECTORY ${PLATFORM_DIR}/ext/common ${PLATFORM_DIR}/ext/driver DESTINATION ${INSTALL_PLATFORM_NS_DIR}/ext) From ab4bfe863745b83ded4d84b0a3e294dff025d924 Mon Sep 17 00:00:00 2001 From: Ahmad EL JOUAID Date: Fri, 8 Aug 2025 10:49:24 +0200 Subject: [PATCH 082/133] [zep fromtree] STM32 : update Readme file Merged README files to centralize documentation and avoid duplication. Signed-off-by: Ahmad EL JOUAID Change-Id: I4e313797144aa13ec5d2d55187b8e2d967c3cb95 (cherry picked from commit 5bd762ff21232b47a28b1a4a4842f0d8b7648eb8) --- docs/platform/stm/b_u585i_iot02a/readme.rst | 54 +++++++++++++++ docs/platform/stm/common/stm32h5xx/readme.rst | 66 ------------------- docs/platform/stm/common/stm32l5xx/readme.rst | 64 ------------------ docs/platform/stm/common/stm32u5xx/readme.rst | 58 ---------------- .../platform/stm/common/stm32wbaxx/readme.rst | 47 ------------- docs/platform/stm/index.rst | 18 ++--- docs/platform/stm/nucleo_l552ze_q/readme.rst | 65 +++++++++++++++++- docs/platform/stm/stm32h573i_dk/readme.rst | 63 ++++++++++++++++++ docs/platform/stm/stm32l562e_dk/readme.rst | 40 +++++++++++ docs/platform/stm/stm32wba65i-dk/readme.rst | 44 +++++++++++++ 10 files changed, 271 insertions(+), 248 deletions(-) delete mode 100644 docs/platform/stm/common/stm32h5xx/readme.rst delete mode 100644 docs/platform/stm/common/stm32l5xx/readme.rst delete mode 100644 docs/platform/stm/common/stm32u5xx/readme.rst delete mode 100644 docs/platform/stm/common/stm32wbaxx/readme.rst diff --git a/docs/platform/stm/b_u585i_iot02a/readme.rst b/docs/platform/stm/b_u585i_iot02a/readme.rst index 8bbd0cefab..e0d3d384b0 100644 --- a/docs/platform/stm/b_u585i_iot02a/readme.rst +++ b/docs/platform/stm/b_u585i_iot02a/readme.rst @@ -1,3 +1,38 @@ +------- +STM32U5 +------- + +TF-M is supported on STM32U5 family + +https://www.st.com/en/microcontrollers-microprocessors/stm32u5-series.html + + +Directory content +^^^^^^^^^^^^^^^^^ + +- stm/common/stm32u5xx/stm32u5xx_hal: + Content from https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git + +- stm/common/stm32u5xx/Device: + Content from https://github.com/STMicroelectronics/cmsis_device_u5.git + +- stm/common/stm32u5xx/bl2: + stm32l5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeU5.git (Projects/B-U585I-IOT02A/Applications/TFM) + +- stm/common/stm32u5xx/secure: + stm32l5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeU5.git (Projects/B-U585I-IOT02A/Applications/TFM) + +- stm/common/stm32u5xx/boards: + Adaptation for stm32 board using stm32l5xx soc from https://github.com/STMicroelectronics/STM32CubeU5.git (Projects/B-U585I-IOT02A/Applications/TFM) + + +Specific Software Requirements +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) + + + B_U585I_IOT02A ^^^^^^^^^^^^^^^ @@ -75,6 +110,25 @@ the attestation service in Isolation Level 1 on Linux. ninja -C . -j 8 +Write software on target +^^^^^^^^^^^^^^^^^^^^^^^^ +In secure build folder directory api_ns: + + - ``postbuild.sh``: Updates regression.sh and TFM_UPDATE.sh scripts according to flash_layout.h + - ``regression.sh``: Sets platform option bytes config and erase platform + - ``TFM_UPDATE.sh``: Writes bl2, secure, and non secure image in target + + +Connect board to USB and Execute the 3 scripts in following order to update platform: +postbuild.sh, regression.sh, TFM_UPDATE.sh + +The virtual com port from STLINK is used for TFM log and serial port configuration should be: + + - Baud rate = 115200 + - Data = 8 bits + - Parity = none + - Stop = 1 bit + - Flow control = none ------------- diff --git a/docs/platform/stm/common/stm32h5xx/readme.rst b/docs/platform/stm/common/stm32h5xx/readme.rst deleted file mode 100644 index 416fe3fa34..0000000000 --- a/docs/platform/stm/common/stm32h5xx/readme.rst +++ /dev/null @@ -1,66 +0,0 @@ -------- -STM32H5 -------- - -TF-M is supported on STM32H5 family - -https://www.st.com/en/microcontrollers-microprocessors/stm32h5-series.html - - -Directory content -^^^^^^^^^^^^^^^^^ - -- stm/common/stm32h5xx/stm32h5xx_hal: - Content from https://github.com/STMicroelectronics/stm32h5xx_hal_driver - -- stm/common/stm32h5xx/Device: - Content from https://github.com/STMicroelectronics/cmsis_device_h5 - -- stm/common/stm32h5xx/bl2: - stm32h5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeH5.git (Projects/STM32H573I_DK/Applications/TFM) - -- stm/common/stm32h5xx/secure: - stm32h5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeH5.git (Projects/STM32H573I_DK/Applications/TFM) - -- stm/common/stm32h5xx/boards: - Adaptation and tools specific to stm32 board using stm32h5xx soc from https://github.com/STMicroelectronics/STM32CubeH5.git (Projects/STM32H573I_DK/Applications/TFM) - -- stm/common/stm32h5xx/CMSIS_Driver: - Flash and uart driver for stm32h5xx platform - -- stm/common/stm32h5xx/Native_Driver: - Random generator and tickless implementation - -Specific Software Requirements -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) - -Limitations to Consider When Using the Platform -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -MPU and ICACHE disabled in bl2 boot stage - -Write software on target -^^^^^^^^^^^^^^^^^^^^^^^^ -In build folder: - - - ``postbuild.sh``: Updates regression.sh and TFM_UPDATE.sh scripts according to flash_layout.h - - ``regression.sh``: Sets platform option bytes config and erase platform - - ``TFM_UPDATE.sh``: Writes bl2, secure, and non secure image in target - - -Connect board to USB and Execute the 3 scripts in following order to update platform: -postbuild.sh, regression.sh, TFM_UPDATE.sh - -The virtual com port from STLINK is used for TFM log and serial port configuration should be: - - - Baud rate = 115200 - - Data = 8 bits - - Parity = none - - Stop = 1 bit - - Flow control = none - -------------- - -*Copyright (c) 2023 STMicroelectronics. All rights reserved.* -*SPDX-License-Identifier: BSD-3-Clause* \ No newline at end of file diff --git a/docs/platform/stm/common/stm32l5xx/readme.rst b/docs/platform/stm/common/stm32l5xx/readme.rst deleted file mode 100644 index 3250705884..0000000000 --- a/docs/platform/stm/common/stm32l5xx/readme.rst +++ /dev/null @@ -1,64 +0,0 @@ -------- -STM32L5 -------- - -TF-M is supported on STM32L5 family - -https://www.st.com/en/microcontrollers-microprocessors/stm32l5-series.html - -https://www.st.com/resource/en/user_manual/dm00678763-getting-started-with-stm32cubel5-tfm-application-stmicroelectronics.pdf - -Directory content -^^^^^^^^^^^^^^^^^ - -- stm/common/stm32l5xx/stm32l5xx_hal: - Content from https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git - -- stm/common/stm32l5xx/Device: - Content from https://github.com/STMicroelectronics/cmsis_device_l5.git - -- stm/common/stm32l5xx/bl2: - stm32l5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) - -- stm/common/stm32l5xx/secure: - stm32l5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) - -- stm/common/stm32l5xx/boards: - Adaptation and tools specific to stm32 board using stm32l5xx soc from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) - -- stm/common/stm32l5xx/CMSIS_Driver: - Flash and uart driver for stm32l5xx platform - -- stm/common/stm32l5xx/Native_Driver: - Random generator and tickless implementation - -Specific Software Requirements -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) - - -Write software on target -^^^^^^^^^^^^^^^^^^^^^^^^ -In secure build folder directory api_ns: - - - ``postbuild.sh``: Updates regression.sh and TFM_UPDATE.sh scripts according to flash_layout.h - - ``regression.sh``: Sets platform option bytes config and erase platform - - ``TFM_UPDATE.sh``: Writes bl2, secure, and non secure image in target - - -Connect board to USB and Execute the 3 scripts in following order to update platform: -postbuild.sh, regression.sh, TFM_UPDATE.sh - -The virtual com port from STLINK is used for TFM log and serial port configuration should be: - - - Baud rate = 115200 - - Data = 8 bits - - Parity = none - - Stop = 1 bit - - Flow control = none - -------------- - -*Copyright (c) 2019 STMicroelectronics. All rights reserved.* -*SPDX-License-Identifier: BSD-3-Clause* diff --git a/docs/platform/stm/common/stm32u5xx/readme.rst b/docs/platform/stm/common/stm32u5xx/readme.rst deleted file mode 100644 index 9db6e52f2a..0000000000 --- a/docs/platform/stm/common/stm32u5xx/readme.rst +++ /dev/null @@ -1,58 +0,0 @@ -------- -STM32U5 -------- - -TF-M is supported on STM32U5 family - -https://www.st.com/en/microcontrollers-microprocessors/stm32u5-series.html - - -Directory content -^^^^^^^^^^^^^^^^^ - -- stm/common/stm32u5xx/stm32u5xx_hal: - Content from https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git - -- stm/common/stm32u5xx/Device: - Content from https://github.com/STMicroelectronics/cmsis_device_u5.git - -- stm/common/stm32u5xx/bl2: - stm32l5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeU5.git (Projects/B-U585I-IOT02A/Applications/TFM) - -- stm/common/stm32u5xx/secure: - stm32l5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeU5.git (Projects/B-U585I-IOT02A/Applications/TFM) - -- stm/common/stm32u5xx/boards: - Adaptation for stm32 board using stm32l5xx soc from https://github.com/STMicroelectronics/STM32CubeU5.git (Projects/B-U585I-IOT02A/Applications/TFM) - - -Specific Software Requirements -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) - - -Write software on target -^^^^^^^^^^^^^^^^^^^^^^^^ -In secure build folder directory api_ns: - - - ``postbuild.sh``: Updates regression.sh and TFM_UPDATE.sh scripts according to flash_layout.h - - ``regression.sh``: Sets platform option bytes config and erase platform - - ``TFM_UPDATE.sh``: Writes bl2, secure, and non secure image in target - - -Connect board to USB and Execute the 3 scripts in following order to update platform: -postbuild.sh, regression.sh, TFM_UPDATE.sh - -The virtual com port from STLINK is used for TFM log and serial port configuration should be: - - - Baud rate = 115200 - - Data = 8 bits - - Parity = none - - Stop = 1 bit - - Flow control = none - -------------- - -*Copyright (c) 2021 STMicroelectronics. All rights reserved.* -*SPDX-License-Identifier: BSD-3-Clause* diff --git a/docs/platform/stm/common/stm32wbaxx/readme.rst b/docs/platform/stm/common/stm32wbaxx/readme.rst deleted file mode 100644 index 7fa855a918..0000000000 --- a/docs/platform/stm/common/stm32wbaxx/readme.rst +++ /dev/null @@ -1,47 +0,0 @@ --------- -STM32WBA --------- - -TF-M is supported on STM32WBA series - -https://www.st.com/en/microcontrollers-microprocessors/stm32wba-series.html - -Directory content -^^^^^^^^^^^^^^^^^ - -- stm/common/stm32wbaxx/stm32wbaxx_hal: - Content from https://github.com/STMicroelectronics/stm32wbaxx_hal_driver (HAL version - Tags V1.6.0 ) - -- stm/common/stm32wbaxx/Device: - Content from https://github.com/STMicroelectronics/cmsis_device_wba - -- stm/common/stm32wbaxx/secure: - stm32wbaxx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeWBA.git - -- stm/common/stm32wbaxx/boards: - Adaptation and tools specific to stm32 board using stm32wbaxx device from https://github.com/STMicroelectronics/STM32CubeWBA.git - -- stm/common/stm32wbaxx/CMSIS_Driver: - Flash and uart driver for stm32wbaxx platform - -- stm/common/stm32wbaxx/Native_Driver: - Random generator and tickless implementation - -Specific Software Requirements -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -STM32CubeProgrammer is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) - - -Limitations to Consider When Using the Platform -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -TF-M Supported without BL1/BL2. - -By default, TFM_OTP_DEFAULT_PROVISIONING and DEFAULT_SHARED_DATA switches are enabled in TF-M, -to use dummy data in OTP and SRAM shared_data areas as BL2 not supported. - -------------- - -*Copyright (c) 2024 STMicroelectronics. All rights reserved.* -*SPDX-License-Identifier: BSD-3-Clause* \ No newline at end of file diff --git a/docs/platform/stm/index.rst b/docs/platform/stm/index.rst index cb1c853b56..95d26381da 100644 --- a/docs/platform/stm/index.rst +++ b/docs/platform/stm/index.rst @@ -6,20 +6,16 @@ This document contains SOC and boards supported by stm32. .. toctree:: :maxdepth: 1 - :caption: SOC + :caption: SOC and Boards :glob: - common/stm*/** + b_u585i_iot02a/readme.rst + nucleo_l552ze_q/readme.rst + stm32l562e_dk/readme.rst + stm32h573i_dk/readme.rst + stm32wba65i-dk/readme.rst -.. toctree:: - :maxdepth: 1 - :caption: Boards - :glob: - - nucleo*/** - stm32*/** - b_*/** -------------- -*Copyright (c) 2021, stmicroelectronics All rights reserved.* +*Copyright (c) 2021 - 2025, stmicroelectronics All rights reserved.* diff --git a/docs/platform/stm/nucleo_l552ze_q/readme.rst b/docs/platform/stm/nucleo_l552ze_q/readme.rst index d57b420cca..3dfea5a2eb 100644 --- a/docs/platform/stm/nucleo_l552ze_q/readme.rst +++ b/docs/platform/stm/nucleo_l552ze_q/readme.rst @@ -1,5 +1,45 @@ -`NUCLEO_L552ZE_Q`_ -^^^^^^^^^^^^^^^^^^ +------- +STM32L5 +------- + +TF-M is supported on STM32L5 family + +https://www.st.com/en/microcontrollers-microprocessors/stm32l5-series.html + +https://www.st.com/resource/en/user_manual/dm00678763-getting-started-with-stm32cubel5-tfm-application-stmicroelectronics.pdf + +Directory content +^^^^^^^^^^^^^^^^^ + +- stm/common/stm32l5xx/stm32l5xx_hal: + Content from https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git + +- stm/common/stm32l5xx/Device: + Content from https://github.com/STMicroelectronics/cmsis_device_l5.git + +- stm/common/stm32l5xx/bl2: + stm32l5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) + +- stm/common/stm32l5xx/secure: + stm32l5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) + +- stm/common/stm32l5xx/boards: + Adaptation and tools specific to stm32 board using stm32l5xx soc from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) + +- stm/common/stm32l5xx/CMSIS_Driver: + Flash and uart driver for stm32l5xx platform + +- stm/common/stm32l5xx/Native_Driver: + Random generator and tickless implementation + +Specific Software Requirements +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) + + +NUCLEO_L552ZE_Q +^^^^^^^^^^^^^^^ STM32 Nucleo-144 development board with STM32L552ZE MCU, SMPS, supports Arduino, ST Zio and morpho connectivity @@ -74,6 +114,27 @@ the attestation service in Isolation Level 1 on Linux. ninja -C . -j 8 +Write software on target +^^^^^^^^^^^^^^^^^^^^^^^^ +In secure build folder directory api_ns: + + - ``postbuild.sh``: Updates regression.sh and TFM_UPDATE.sh scripts according to flash_layout.h + - ``regression.sh``: Sets platform option bytes config and erase platform + - ``TFM_UPDATE.sh``: Writes bl2, secure, and non secure image in target + + +Connect board to USB and Execute the 3 scripts in following order to update platform: +postbuild.sh, regression.sh, TFM_UPDATE.sh + +The virtual com port from STLINK is used for TFM log and serial port configuration should be: + + - Baud rate = 115200 + - Data = 8 bits + - Parity = none + - Stop = 1 bit + - Flow control = none + + .. _NUCLEO_L552ZE_Q: https://www.st.com/en/evaluation-tools/nucleo-l552ze-q.html ------------- diff --git a/docs/platform/stm/stm32h573i_dk/readme.rst b/docs/platform/stm/stm32h573i_dk/readme.rst index 7c8868fd76..b97fe007a2 100644 --- a/docs/platform/stm/stm32h573i_dk/readme.rst +++ b/docs/platform/stm/stm32h573i_dk/readme.rst @@ -1,3 +1,46 @@ +------- +STM32H5 +------- + +TF-M is supported on STM32H5 family + +https://www.st.com/en/microcontrollers-microprocessors/stm32h5-series.html + + +Directory content +^^^^^^^^^^^^^^^^^ + +- stm/common/stm32h5xx/stm32h5xx_hal: + Content from https://github.com/STMicroelectronics/stm32h5xx_hal_driver + +- stm/common/stm32h5xx/Device: + Content from https://github.com/STMicroelectronics/cmsis_device_h5 + +- stm/common/stm32h5xx/bl2: + stm32h5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeH5.git (Projects/STM32H573I_DK/Applications/TFM) + +- stm/common/stm32h5xx/secure: + stm32h5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeH5.git (Projects/STM32H573I_DK/Applications/TFM) + +- stm/common/stm32h5xx/boards: + Adaptation and tools specific to stm32 board using stm32h5xx soc from https://github.com/STMicroelectronics/STM32CubeH5.git (Projects/STM32H573I_DK/Applications/TFM) + +- stm/common/stm32h5xx/CMSIS_Driver: + Flash and uart driver for stm32h5xx platform + +- stm/common/stm32h5xx/Native_Driver: + Random generator and tickless implementation + +Specific Software Requirements +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) + +Limitations to Consider When Using the Platform +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +MPU and ICACHE disabled in bl2 boot stage + + STM32H573I_DK ^^^^^^^^^^^^^^^ @@ -75,6 +118,26 @@ the attestation service in Isolation Level 1 on Linux. ninja -C . -j 8 +Write software on target +^^^^^^^^^^^^^^^^^^^^^^^^ +In build folder: + + - ``postbuild.sh``: Updates regression.sh and TFM_UPDATE.sh scripts according to flash_layout.h + - ``regression.sh``: Sets platform option bytes config and erase platform + - ``TFM_UPDATE.sh``: Writes bl2, secure, and non secure image in target + + +Connect board to USB and Execute the 3 scripts in following order to update platform: +postbuild.sh, regression.sh, TFM_UPDATE.sh + +The virtual com port from STLINK is used for TFM log and serial port configuration should be: + + - Baud rate = 115200 + - Data = 8 bits + - Parity = none + - Stop = 1 bit + - Flow control = none + ------------- *Copyright (c) 2023, STMicroelectronics. All rights reserved.* diff --git a/docs/platform/stm/stm32l562e_dk/readme.rst b/docs/platform/stm/stm32l562e_dk/readme.rst index c8b42c73c7..b5136efa07 100644 --- a/docs/platform/stm/stm32l562e_dk/readme.rst +++ b/docs/platform/stm/stm32l562e_dk/readme.rst @@ -1,3 +1,43 @@ +------- +STM32L5 +------- + +TF-M is supported on STM32L5 family + +https://www.st.com/en/microcontrollers-microprocessors/stm32l5-series.html + +https://www.st.com/resource/en/user_manual/dm00678763-getting-started-with-stm32cubel5-tfm-application-stmicroelectronics.pdf + +Directory content +^^^^^^^^^^^^^^^^^ + +- stm/common/stm32l5xx/stm32l5xx_hal: + Content from https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git + +- stm/common/stm32l5xx/Device: + Content from https://github.com/STMicroelectronics/cmsis_device_l5.git + +- stm/common/stm32l5xx/bl2: + stm32l5xx bl2 code specific from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) + +- stm/common/stm32l5xx/secure: + stm32l5xx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) + +- stm/common/stm32l5xx/boards: + Adaptation and tools specific to stm32 board using stm32l5xx soc from https://github.com/STMicroelectronics/STM32CubeL5.git (Projects/STM32L562E-DK/Applications/TFM) + +- stm/common/stm32l5xx/CMSIS_Driver: + Flash and uart driver for stm32l5xx platform + +- stm/common/stm32l5xx/Native_Driver: + Random generator and tickless implementation + +Specific Software Requirements +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +STM32_Programmer_CLI is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) + + STM32L562E_DK ^^^^^^^^^^^^^ diff --git a/docs/platform/stm/stm32wba65i-dk/readme.rst b/docs/platform/stm/stm32wba65i-dk/readme.rst index 9c4abea168..97c12d9441 100644 --- a/docs/platform/stm/stm32wba65i-dk/readme.rst +++ b/docs/platform/stm/stm32wba65i-dk/readme.rst @@ -1,3 +1,47 @@ +-------- +STM32WBA +-------- + +TF-M is supported on STM32WBA series + +https://www.st.com/en/microcontrollers-microprocessors/stm32wba-series.html + +Directory content +^^^^^^^^^^^^^^^^^ + +- stm/common/stm32wbaxx/stm32wbaxx_hal: + Content from https://github.com/STMicroelectronics/stm32wbaxx_hal_driver (HAL version - Tags V1.6.0 ) + +- stm/common/stm32wbaxx/Device: + Content from https://github.com/STMicroelectronics/cmsis_device_wba + +- stm/common/stm32wbaxx/secure: + stm32wbaxx Secure porting adaptation from https://github.com/STMicroelectronics/STM32CubeWBA.git + +- stm/common/stm32wbaxx/boards: + Adaptation and tools specific to stm32 board using stm32wbaxx device from https://github.com/STMicroelectronics/STM32CubeWBA.git + +- stm/common/stm32wbaxx/CMSIS_Driver: + Flash and uart driver for stm32wbaxx platform + +- stm/common/stm32wbaxx/Native_Driver: + Random generator and tickless implementation + +Specific Software Requirements +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +STM32CubeProgrammer is required.(see https://www.st.com/en/development-tools/stm32cubeprog.html) + + +Limitations to Consider When Using the Platform +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +TF-M Supported without BL1/BL2. + +By default, TFM_OTP_DEFAULT_PROVISIONING and DEFAULT_SHARED_DATA switches are enabled in TF-M, +to use dummy data in OTP and SRAM shared_data areas as BL2 not supported. + + STM32WBA65_DK ^^^^^^^^^^^^^^^ From c373bba91de5267fa34870ba919d41fd6d435b3e Mon Sep 17 00:00:00 2001 From: BUDKE Gerson Fernando Date: Fri, 25 Jul 2025 08:18:53 +0200 Subject: [PATCH 083/133] [zep fromtree] platform: stm32u5xx: Add missing stm32u5a5xx.h The file stm32u5a5xx.h is part of the stm hal to enable support to stm32u5a5xx mcu. For some unknown reason this file still missing and code do not compile. Add the missing file to fully support out of tree tf-m to this plaform. Change-Id: Ib1971a9231af90b4877d45801afc5accea2484cb Signed-off-by: BUDKE Gerson Fernando Signed-off-by: Ahmad EL JOUAID (cherry picked from commit 3376880113cb75ce82d4fd05a02775ff1e9ee6b9) --- .../stm32u5xx/Device/Include/stm32u5a5xx.h | 26565 ++++++++++++++++ 1 file changed, 26565 insertions(+) create mode 100644 platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5a5xx.h diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5a5xx.h b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5a5xx.h new file mode 100644 index 0000000000..018b8ac5e9 --- /dev/null +++ b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5a5xx.h @@ -0,0 +1,26565 @@ +/** + ****************************************************************************** + * @file stm32u5a5xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5A5xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 - 2025 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +#ifndef STM32U5A5xx_H +#define STM32U5A5xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U5A5xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U5A5xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_2_IRQn = 37, /*!< ADC1_2 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_HS_IRQn = 73, /*!< USB OTG HS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 93, /*!< AES global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + PKA_IRQn = 97, /*!< PKA global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + OTFDEC1_IRQn = 108, /*!< OTFDEC1 global interrupt */ + OTFDEC2_IRQn = 109, /*!< OTFDEC2 global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ + USART6_IRQn = 126, /*!< USART6 global interrupt */ + I2C5_ER_IRQn = 127, /*!< I2C5 Error interrupt */ + I2C5_EV_IRQn = 128, /*!< I2C5 Event interrupt */ + I2C6_ER_IRQn = 129, /*!< I2C6 Error interrupt */ + I2C6_EV_IRQn = 130, /*!< I2C6 Error interrupt */ + HSPI1_IRQn = 131, /*!< HSPI1 global interrupt */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5A5xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5A5xx_H */ + From 3432079c41474d527a45d9f3bf4661376053805e Mon Sep 17 00:00:00 2001 From: BUDKE Gerson Fernando Date: Mon, 11 Aug 2025 17:29:10 +0200 Subject: [PATCH 084/133] [zep fromtree] platform: stm32u5xx: Move provision files The provision files are board dependent but are defined inside common CMakeLists.txt. This means that the current behaviour do not allow customize this values for Out of Tree buildings. This moves the definition to the board CMakeLists.txt to solve the issue. Change-Id: I6654fa7f61a3f7f33e65ac9b979e9224e009e8e9 Signed-off-by: BUDKE Gerson Fernando (cherry picked from commit 845319f646659104524c840e76e398150f60ed60) --- platform/ext/target/stm/b_u585i_iot02a/CMakeLists.txt | 3 +++ platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/stm/b_u585i_iot02a/CMakeLists.txt b/platform/ext/target/stm/b_u585i_iot02a/CMakeLists.txt index b6811ebec0..c2cebf5f09 100644 --- a/platform/ext/target/stm/b_u585i_iot02a/CMakeLists.txt +++ b/platform/ext/target/stm/b_u585i_iot02a/CMakeLists.txt @@ -72,6 +72,9 @@ if(BL2) ${STM_COMMON_DIR}/stm32u5xx/bl2/low_level_ospi_device.c ${STM_COMMON_DIR}/hal/CMSIS_Driver/low_level_ospi_flash.c ${STM_COMMON_DIR}/hal/Components/mx25lm51245g/mx25lm51245g.c + ${STM_COMMON_DIR}/hal/provision/otp_provision.c + ${STM_COMMON_DIR}/hal/provision/nvm_init.c + ${STM_COMMON_DIR}/hal/provision/nvmcnt_init.c ${B_U585I_IOT02A_DIR}/src/b_u585i_iot02a_ospi.c ) endif() diff --git a/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt b/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt index c1346f670b..3e8ff519ef 100644 --- a/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32u5xx/CMakeLists.txt @@ -220,10 +220,7 @@ if(BL2) ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32u5xx_hal_ospi.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32u5xx_ll_dlyb.c ${STM_COMMON_DIR}/hal/Native_Driver/low_level_rng.c - ${STM_COMMON_DIR}/hal/provision/otp_provision.c ${STM_COMMON_DIR}/hal/Native_Driver/nv_counters.c - ${STM_COMMON_DIR}/hal/provision/nvm_init.c - ${STM_COMMON_DIR}/hal/provision/nvmcnt_init.c ) target_compile_options(platform_bl2 From d500fde63c9ea6bd7a336ad503d1fca945fbcc08 Mon Sep 17 00:00:00 2001 From: BUDKE Gerson Fernando Date: Mon, 11 Aug 2025 17:33:05 +0200 Subject: [PATCH 085/133] [zep fromtree] platform: stm32h5xx: Move provision files The provision files are board dependent but are defined inside common CMakeLists.txt. This means that the current behaviour do not allow customize this values for Out of Tree buildings. This moves the definition to the board CMakeLists.txt to solve the issue. Change-Id: I593c070f5fe9280c14c344aa49c89230383033dd Signed-off-by: BUDKE Gerson Fernando (cherry picked from commit 62c51f68482511f13c5dc3c02d86f75d3c813ecb) --- platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt | 3 --- platform/ext/target/stm/stm32h573i_dk/CMakeLists.txt | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt b/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt index 6c5f73f600..57dd31064d 100644 --- a/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32h5xx/CMakeLists.txt @@ -152,9 +152,6 @@ if(BL2) ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32h5xx_hal_rtc_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32h5xx_hal_icache.c ${STM_COMMON_DIR}/hal/Native_Driver/low_level_rng.c - ${STM_COMMON_DIR}/hal/provision/otp_provision.c - ${STM_COMMON_DIR}/hal/provision/nvm_init.c - ${STM_COMMON_DIR}/hal/provision/nvmcnt_init.c ) target_compile_options(platform_bl2 diff --git a/platform/ext/target/stm/stm32h573i_dk/CMakeLists.txt b/platform/ext/target/stm/stm32h573i_dk/CMakeLists.txt index 0d4fc664b4..fa8898d4c1 100644 --- a/platform/ext/target/stm/stm32h573i_dk/CMakeLists.txt +++ b/platform/ext/target/stm/stm32h573i_dk/CMakeLists.txt @@ -31,6 +31,9 @@ if(BL2) target_sources(bl2 PRIVATE ${STM_COMMON_DIR}/stm32h5xx/Device/Source/startup_stm32h5xx_bl2.c + ${STM_COMMON_DIR}/hal/provision/otp_provision.c + ${STM_COMMON_DIR}/hal/provision/nvm_init.c + ${STM_COMMON_DIR}/hal/provision/nvmcnt_init.c ) endif() From 1125edf20cd369e16e0a56788c7b4521c7586c46 Mon Sep 17 00:00:00 2001 From: BUDKE Gerson Fernando Date: Mon, 11 Aug 2025 17:34:14 +0200 Subject: [PATCH 086/133] [zep fromtree] platform: stm32wbaxx: Move provision file The otp_provision.c file is board dependent but is defined inside common CMakeLists.txt. This means that the current behaviour do not allow customize the value for Out of Tree building. This moves the definition to the board CMakeLists.txt to solve the issue. Change-Id: I8ed751c51c7e07182b620b5cfbe5af15a25cde9a Signed-off-by: BUDKE Gerson Fernando (cherry picked from commit eb22a5b5fe3993d79e8217a737607cea9a1b044c) --- platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt | 1 - platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt index 858ccb03ab..108246d6ac 100644 --- a/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt +++ b/platform/ext/target/stm/common/stm32wbaxx/CMakeLists.txt @@ -62,7 +62,6 @@ target_sources(platform_s ${CMAKE_CURRENT_SOURCE_DIR}/secure/low_level_device.c ${STM_COMMON_DIR}/hal/CMSIS_Driver/low_level_flash.c ${STM_COMMON_DIR}/hal/CMSIS_Driver/low_level_com.c - ${STM_COMMON_DIR}/hal/provision/otp_provision.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal_flash.c ${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32wbaxx_hal_flash_ex.c diff --git a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt index 46049b8ad2..6300bc05f4 100644 --- a/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt +++ b/platform/ext/target/stm/stm32wba65i_dk/CMakeLists.txt @@ -23,6 +23,11 @@ target_sources(tfm_s ${STM_COMMON_DIR}/stm32wbaxx/Device/Source/startup_stm32wbaxx_s.c ) +target_sources(platform_s + PRIVATE + ${STM_COMMON_DIR}/hal/provision/otp_provision.c +) + if(NS) target_sources(${NS_TARGET_NAME} PRIVATE From 8b2924c2615307e12aacf0a7aeeca25bdcc175b0 Mon Sep 17 00:00:00 2001 From: Stefan Gloor Date: Wed, 22 Oct 2025 13:59:30 +0200 Subject: [PATCH 087/133] [zep fromtree] platform: stm: fix bl2 without hardware accelerator Add #ifdef to make sure crypto_hw_accelerator* functions are not called if CRYPTO_HW_ACCELERATOR is disabled. Change-Id: I76ee3ca377caea1d3ad663c86bd3d5d187c2995d Signed-off-by: Stefan Gloor (cherry picked from commit cc180f1d00a3ec755c922d6addd338dfd46aa7ca) Signed-off-by: Tim Pambor --- platform/ext/target/stm/common/stm32h5xx/bl2/boot_hal_bl2.c | 5 ++++- platform/ext/target/stm/common/stm32u5xx/bl2/boot_hal_bl2.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/stm/common/stm32h5xx/bl2/boot_hal_bl2.c b/platform/ext/target/stm/common/stm32h5xx/bl2/boot_hal_bl2.c index 5fa11efef1..3d038414c0 100644 --- a/platform/ext/target/stm/common/stm32h5xx/bl2/boot_hal_bl2.c +++ b/platform/ext/target/stm/common/stm32h5xx/bl2/boot_hal_bl2.c @@ -384,8 +384,9 @@ void boot_platform_start_next_image(struct boot_arm_vector_table *vector) #ifdef BL2_DATA TFM_BL2_CopySharedData(); #endif +#ifdef CRYPTO_HW_ACCELERATOR (void)crypto_hw_accelerator_finish(); - +#endif RNG_DeInit(); @@ -596,10 +597,12 @@ int32_t boot_platform_init(void) BOOT_LOG_ERR("Error while initializing RNG Ip"); Error_Handler(); } +#ifdef CRYPTO_HW_ACCELERATOR if (crypto_hw_accelerator_init()){ BOOT_LOG_ERR("Error while initializing HW accelerator Ip"); Error_Handler(); } +#endif /* Start HW randomization */ fih_delay_init(); /* Apply Run time Protection */ diff --git a/platform/ext/target/stm/common/stm32u5xx/bl2/boot_hal_bl2.c b/platform/ext/target/stm/common/stm32u5xx/bl2/boot_hal_bl2.c index c7340ea5e7..7246f95f39 100644 --- a/platform/ext/target/stm/common/stm32u5xx/bl2/boot_hal_bl2.c +++ b/platform/ext/target/stm/common/stm32u5xx/bl2/boot_hal_bl2.c @@ -400,8 +400,9 @@ void boot_platform_start_next_image(struct boot_arm_vector_table *vector) #ifdef BL2_DATA TFM_BL2_CopySharedData(); #endif +#ifdef CRYPTO_HW_ACCELERATOR (void)crypto_hw_accelerator_finish(); - +#endif RNG_DeInit(); @@ -612,10 +613,12 @@ int32_t boot_platform_init(void) BOOT_LOG_ERR("Error while initializing RNG Ip"); Error_Handler(); } +#ifdef CRYPTO_HW_ACCELERATOR if (crypto_hw_accelerator_init()){ BOOT_LOG_ERR("Error while initializing HW accelerator Ip"); Error_Handler(); } +#endif /* Start HW randomization */ fih_delay_init(); /* Apply Run time Protection */ From b11b834822197b4157a4105ac049b6a7f9dc7abc Mon Sep 17 00:00:00 2001 From: Stefan Gloor Date: Wed, 22 Oct 2025 13:59:30 +0200 Subject: [PATCH 088/133] [zep fromtree] platform: stm: fix parentheses for readability Add parantheses to get rid of the -Wparentheses warning: platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c:490:21: warning: suggest parentheses around comparison in operand of '&' [-Wparentheses] 490 | if(SCB->AIRCR & SCB_AIRCR_PRIS_Msk == 0) | ^ Change-Id: Icbbe6b0393f9ac0be3600fed60e3508dfe9a40eb Signed-off-by: Stefan Gloor (cherry picked from commit 43474c807dc5ef9aa32ce8092770428ff66bd23c) Signed-off-by: Tim Pambor --- platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c b/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c index 1482884ce8..8046a0df90 100644 --- a/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c +++ b/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c @@ -487,7 +487,7 @@ void gtzc_init_cfg(void) FLOW_CONTROL_STEP(uFlowProtectValue, FLOW_STEP_GTZC_VTOR_LCK, FLOW_CTRL_GTZC_VTOR_LCK); /* Check PRIS Is enabled */ - if(SCB->AIRCR & SCB_AIRCR_PRIS_Msk == 0) + if((SCB->AIRCR & SCB_AIRCR_PRIS_Msk) == 0) Error_Handler(); FLOW_CONTROL_STEP(uFlowProtectValue, FLOW_STEP_GTZC_PRIS_EN, FLOW_CTRL_GTZC_PRIS_EN); From 3b795941267d3d3c90bab6db17734c31d3b919bc Mon Sep 17 00:00:00 2001 From: Stefan Gloor Date: Wed, 22 Oct 2025 13:59:30 +0200 Subject: [PATCH 089/133] [zep fromtree] platform: stm: only use plat_data_ptr with isolation level 2 Fix the -Wunused-variable warning: platform/ext/target/stm/common/stm32h5xx/secure/tfm_hal_isolation.c:424:29: warning: unused variable 'plat_data_ptr' [-Wunused-variable] 424 | struct platform_data_t *plat_data_ptr; | ^~~~~~~~~~~~~ Change-Id: I8a48cf15302d64ba78d0aec891ec36b42a952cbd Signed-off-by: Stefan Gloor (cherry picked from commit 50da8e161cc1d2171565e94ae5846eea95a5d6bd) Signed-off-by: Tim Pambor --- .../ext/target/stm/common/stm32h5xx/secure/tfm_hal_isolation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/stm/common/stm32h5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32h5xx/secure/tfm_hal_isolation.c index b22a89225a..8340390c61 100644 --- a/platform/ext/target/stm/common/stm32h5xx/secure/tfm_hal_isolation.c +++ b/platform/ext/target/stm/common/stm32h5xx/secure/tfm_hal_isolation.c @@ -421,8 +421,8 @@ FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_bind_boundary( bool ns_agent; uint32_t partition_attrs = 0; const struct asset_desc_t *p_asset; - struct platform_data_t *plat_data_ptr; #if TFM_ISOLATION_LEVEL == 2 + struct platform_data_t *plat_data_ptr; struct mpu_armv8m_region_cfg_t localcfg; #endif From 87db898771983a9fefd8d4d450fcd74a1f59fb71 Mon Sep 17 00:00:00 2001 From: Stefan Gloor Date: Wed, 22 Oct 2025 13:59:30 +0200 Subject: [PATCH 090/133] [zep fromtree] platform: stm: remove gtzc_periph_att when unused Combine the #ifdef clauses of the gtzc_periph_att usages to only instantiate the variable when it is actually used. This fixes the -Wunused-variable warning: /platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c:480:12: warning: unused variable 'gtzc_periph_att' [-Wunused-variable] 480 | uint32_t gtzc_periph_att; | ^~~~~~~~~~~~~~~ Change-Id: I04e4eebedf791e76f943557633338c115164e410 Signed-off-by: Stefan Gloor (cherry picked from commit c91f4e60f112e3f63aa35f197f00112e0d43cd7f) Signed-off-by: Tim Pambor --- .../target/stm/common/stm32h5xx/secure/target_cfg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c b/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c index 8046a0df90..a7112f7073 100644 --- a/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c +++ b/platform/ext/target/stm/common/stm32h5xx/secure/target_cfg.c @@ -477,7 +477,17 @@ static void gtzc_internal_flash_priv(uint32_t offset_start, uint32_t offset_end) void gtzc_init_cfg(void) { +#if (defined (MBEDTLS_SHA256_C) && defined (MBEDTLS_SHA256_ALT)) \ + || (defined (MBEDTLS_SHA1_C) && defined (MBEDTLS_SHA1_ALT)) \ + || (defined (MBEDTLS_MD5_C) && defined (MBEDTLS_MD5_ALT)) \ + || (defined (MBEDTLS_ECP_C) && defined (MBEDTLS_ECP_ALT)) \ + || (defined (MBEDTLS_ECDSA_C) && (defined (MBEDTLS_ECDSA_SIGN_ALT) || defined (MBEDTLS_ECDSA_VERIFY_ALT))) \ + || (defined (MBEDTLS_AES_C) && defined (MBEDTLS_AES_ALT)) \ + || (defined (MBEDTLS_GCM_C) && defined (MBEDTLS_GCM_ALT)) \ + || (defined (MBEDTLS_CCM_C) && defined (MBEDTLS_CCM_ALT)) \ + || defined (HW_CRYPTO_DPA_AES) || defined (HW_CRYPTO_DPA_GCM) uint32_t gtzc_periph_att; +#endif if (uFlowStage == FLOW_STAGE_CFG) { From 98f3f8fce62912f7f8d25346561e8475f81b37e6 Mon Sep 17 00:00:00 2001 From: Stefan Gloor Date: Wed, 22 Oct 2025 13:59:30 +0200 Subject: [PATCH 091/133] [zep fromtree] bl2: add psa_util.c to list of crypto source files psa_crypto_ecp.c and psa_crypto_rsa.c reference functions from psa_util.c, e.g., mbedtls_psa_get_random, so it should be included in the library build to get rid of linker errors such as arm-zephyr-eabi/bin/ld: bl2/libbl2_crypto.a(psa_crypto_ecp.o): in function `mbedtls_psa_ecp_load_public_part': /modules/crypto/mbedtls/library/psa_crypto_ecp.c:447: undefined reference to `mbedtls_psa_get_random' Change-Id: Iacf3fb97dd87d3dcb20b9302c383f4061e1371a6 Signed-off-by: Stefan Gloor (cherry picked from commit 019755de4c86aebdae557ea59577eafd292338fb) Signed-off-by: Tim Pambor --- bl2/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bl2/CMakeLists.txt b/bl2/CMakeLists.txt index d852102427..b462dfee18 100644 --- a/bl2/CMakeLists.txt +++ b/bl2/CMakeLists.txt @@ -85,6 +85,7 @@ list(APPEND BL2_CRYPTO_SRC $<${build_sha_256}:${MBEDCRYPTO_PATH}/library/sha256.c> $<${build_sha_384}:${MBEDCRYPTO_PATH}/library/sha512.c> $<$>:${MBEDCRYPTO_PATH}/library/psa_crypto_ecp.c> + $<$>:${MBEDCRYPTO_PATH}/library/psa_util.c> $<$>:${MBEDCRYPTO_PATH}/library/ecp.c> $<$>:${MBEDCRYPTO_PATH}/library/ecp_curves.c> $<$>:${MBEDCRYPTO_PATH}/library/ecdsa.c> @@ -92,6 +93,7 @@ list(APPEND BL2_CRYPTO_SRC $<$>:${MBEDCRYPTO_PATH}/library/bignum_core.c> $<$>:${MBEDCRYPTO_PATH}/library/constant_time.c> $<${is_rsa_signature}:${MBEDCRYPTO_PATH}/library/psa_crypto_rsa.c> + $<${is_rsa_signature}:${MBEDCRYPTO_PATH}/library/psa_util.c> $<${is_rsa_signature}:${MBEDCRYPTO_PATH}/library/rsa.c> $<${is_rsa_signature}:${MBEDCRYPTO_PATH}/library/rsa_alt_helpers.c> $<${is_rsa_signature}:${MBEDCRYPTO_PATH}/library/bignum.c> From 1ebb5bebadb148cefe7db959a9b4379390c308da Mon Sep 17 00:00:00 2001 From: Raef Coles Date: Thu, 21 Aug 2025 11:44:48 +0100 Subject: [PATCH 092/133] [zep fromtree] BL1: Rename conflicting macro Using BL2_HEADER_SIZE conflicts with the existing BL2 header size macro, and is confusing. Change-Id: Ia5eede86a1765a617a374539e0111179e81096b3 Signed-off-by: Raef Coles (cherry picked from commit 690d20b88043fdad8a8730b367a54fa48f891d94) --- bl1/bl1_2/lib/image.c | 4 ++-- bl1/bl1_2/lib/interface/image.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bl1/bl1_2/lib/image.c b/bl1/bl1_2/lib/image.c index affb3aec88..397b398e9b 100644 --- a/bl1/bl1_2/lib/image.c +++ b/bl1/bl1_2/lib/image.c @@ -39,10 +39,10 @@ fih_int bl1_image_copy_to_sram(uint32_t image_id, uint8_t *out) flash_offset = bl1_image_get_flash_offset(image_id); fih_rc = fih_int_encode_zero_equality( - fih_not_eq(BL2_CODE_SIZE + BL2_HEADER_SIZE, + fih_not_eq(BL2_CODE_SIZE + BL1_2_HEADER_SIZE, (FLASH_DEV_NAME_BL1.ReadData(flash_offset, out, - BL2_CODE_SIZE + BL2_HEADER_SIZE)))); + BL2_CODE_SIZE + BL1_2_HEADER_SIZE)))); FIH_RET(fih_rc); } diff --git a/bl1/bl1_2/lib/interface/image.h b/bl1/bl1_2/lib/interface/image.h index fd4e306b31..8648fcf4e8 100644 --- a/bl1/bl1_2/lib/interface/image.h +++ b/bl1/bl1_2/lib/interface/image.h @@ -19,7 +19,7 @@ extern "C" { #endif -#define BL2_HEADER_SIZE (offsetof(struct bl1_2_image_t, protected_values.encrypted_data.data)) +#define BL1_2_HEADER_SIZE (offsetof(struct bl1_2_image_t, protected_values.encrypted_data.data)) /** * From 77bce46e34f0fdeeed6f1cd8a3488302764cac6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1vid=20H=C3=A1zi?= Date: Thu, 11 Sep 2025 21:32:12 +0000 Subject: [PATCH 093/133] [zep fromtree] mps4: Removed unneeded definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Dávid Házi Change-Id: I87f3e4d09b0f0eabe33190a4d069b791bb6707d4 (cherry picked from commit b4b4cff44b40e2f893153ecd2023339a3faf08a2) --- platform/ext/target/arm/mps4/common/common.cmake | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/platform/ext/target/arm/mps4/common/common.cmake b/platform/ext/target/arm/mps4/common/common.cmake index 6ffed428b6..36501c489b 100644 --- a/platform/ext/target/arm/mps4/common/common.cmake +++ b/platform/ext/target/arm/mps4/common/common.cmake @@ -292,12 +292,6 @@ target_compile_options(bl1_1_scatter ${COMPILER_CMSE_FLAG} ) -target_compile_definitions(bl1_1 - PRIVATE - MBEDTLS_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h" - MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/crypto_config_default.h" -) - target_compile_options(bl1_1 PUBLIC ${COMPILER_CMSE_FLAG} @@ -361,12 +355,6 @@ target_compile_options(bl1_2_scatter ${COMPILER_CMSE_FLAG} ) -target_compile_definitions(bl1_2 - PRIVATE - MBEDTLS_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h" - MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/crypto_config_default.h" -) - target_compile_options(bl1_2 PUBLIC ${COMPILER_CMSE_FLAG} From 0eef9545c76af711301c932921f5908cd576d8ec Mon Sep 17 00:00:00 2001 From: Sudan Landge Date: Wed, 8 Oct 2025 18:56:56 +0100 Subject: [PATCH 094/133] [zep fromtree] BL1: Fix unused-variable warnings To avoid "unused variable" compiler warnings: - Declare rotpk_hash and key_hash_alg conditionally in BL1_2. - Remove unused `hash_bytes_used` in BL1_1 Signed-off-by: Sudan Landge Change-Id: Id927a7db340a2d868f6a61a35174ac35303fa334 (cherry picked from commit 962a915aea6a9d0a0ba4f98dff772c7b31e135a6) --- bl1/bl1_2/main.c | 4 +++- platform/ext/target/arm/mps4/common/bl1/boot_hal_bl1_1.c | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/bl1/bl1_2/main.c b/bl1/bl1_2/main.c index 1b9f8726bd..d8bd278a65 100644 --- a/bl1/bl1_2/main.c +++ b/bl1/bl1_2/main.c @@ -107,9 +107,11 @@ static fih_int validate_image_signature(struct bl1_2_image_t *img, uint8_t rotpk[TFM_BL1_2_ROTPK_MAX_SIZE]; uint8_t *p_rotpk = rotpk; size_t rotpk_size; +#if defined(TFM_BL1_2_EMBED_ROTPK_IN_IMAGE) || defined(TFM_MEASURED_BOOT_API) uint8_t rotpk_hash[TFM_BL1_2_ROTPK_HASH_MAX_SIZE]; - enum tfm_bl1_key_type_t key_type; enum tfm_bl1_hash_alg_t key_hash_alg; +#endif /* TFM_BL1_2_EMBED_ROTPK_IN_IMAGE || TFM_MEASURED_BOOT_API */ + enum tfm_bl1_key_type_t key_type; if (sig->sig_len > sizeof(sig->sig)) { diff --git a/platform/ext/target/arm/mps4/common/bl1/boot_hal_bl1_1.c b/platform/ext/target/arm/mps4/common/bl1/boot_hal_bl1_1.c index 3510e9746c..5b98f5e66f 100644 --- a/platform/ext/target/arm/mps4/common/bl1/boot_hal_bl1_1.c +++ b/platform/ext/target/arm/mps4/common/bl1/boot_hal_bl1_1.c @@ -41,7 +41,6 @@ static mbedtls_hmac_drbg_context hmac_drbg_ctx; int32_t bl1_trng_generate_random_init(void) { int error; - size_t hash_bytes_used = 0; uint8_t entropy_seed[64]; const mbedtls_md_info_t *md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA256); From 781ecae9aa26852a1c79ed4920a51a4e2e48df96 Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Tue, 20 May 2025 15:34:14 +0200 Subject: [PATCH 095/133] [zep fromtree dirty] platform: nordic_nrf: Split the target_cfg for different platforms This splits the target_cfg.c file for the different platfoms. It splits the file into two files one for the nRF54L and one for the nRF91/nRF53 series. There is no need for the peripherals to be in the same file as the configuration code. There is already a header which provides extern definitions for all the peripherals a device supports which can be used for for source files needing to configure peripherals. So this peripheral definitions are placed in a separate file. Most of the code is taken unchanged from the target_cfg.c file and the uneeded ifdefs got removed. The init_debug function got rewritten without changing the logic of it. Signed-off-by: Georgios Vasilakis Change-Id: I19071727061b8952e3abbae20dd182c822234427 (cherry picked from commit 37e8dc47d4eb4aa0c0b905f80be5272aafbd9fa2) This is a dirty fromtree as the original commit does not apply cleanly. Attempts to cherry-pick it in cleanly leads to a large amount of extra commits being included. Signed-off-by: Georgios Vasilakis --- .../nordic_nrf/common/core/CMakeLists.txt | 3 + .../common/core/secure_peripherals_defs.c | 667 ++++++++ .../nordic_nrf/common/core/target_cfg.c | 1472 ----------------- .../nordic_nrf/common/core/target_cfg.h | 3 + .../nordic_nrf/common/core/target_cfg_53_91.c | 496 ++++++ .../nordic_nrf/common/core/target_cfg_54l.c | 524 ++++++ 6 files changed, 1693 insertions(+), 1472 deletions(-) create mode 100644 platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c create mode 100644 platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c create mode 100644 platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 33b49909f4..1d37517f52 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -206,6 +206,9 @@ target_sources(tfm_spm tfm_hal_platform_common.c faults.c target_cfg.c + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_54l.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_53_91.c> + secure_peripherals_defs.c ) target_sources(tfm_s diff --git a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c new file mode 100644 index 0000000000..7316baa086 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c @@ -0,0 +1,667 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#if TFM_PERIPHERAL_DCNF_SECURE +struct platform_data_t tfm_peripheral_dcnf = { + NRF_DCNF_S_BASE, + NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_FPU_SECURE +struct platform_data_t tfm_peripheral_fpu = { + NRF_FPU_S_BASE, + NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_OSCILLATORS_SECURE +struct platform_data_t tfm_peripheral_oscillators = { + NRF_OSCILLATORS_S_BASE, + NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_REGULATORS_SECURE +struct platform_data_t tfm_peripheral_regulators = { + NRF_REGULATORS_S_BASE, + NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_CLOCK_SECURE +struct platform_data_t tfm_peripheral_clock = { + NRF_CLOCK_S_BASE, + NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_POWER_SECURE +struct platform_data_t tfm_peripheral_power = { + NRF_POWER_S_BASE, + NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RESET_SECURE +struct platform_data_t tfm_peripheral_reset = { + NRF_RESET_S_BASE, + NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM0_SECURE +struct platform_data_t tfm_peripheral_spim0 = { + NRF_SPIM0_S_BASE, + NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM00_SECURE +struct platform_data_t tfm_peripheral_spim00 = { + NRF_SPIM00_S_BASE, + NRF_SPIM00_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM20_SECURE +struct platform_data_t tfm_peripheral_spim20 = { + NRF_SPIM20_S_BASE, + NRF_SPIM20_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +struct platform_data_t tfm_peripheral_spim21 = { + NRF_SPIM21_S_BASE, + NRF_SPIM21_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +struct platform_data_t tfm_peripheral_spim22 = { + NRF_SPIM22_S_BASE, + NRF_SPIM22_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM23_SECURE +struct platform_data_t tfm_peripheral_spim23 = { + NRF_SPIM23_S_BASE, + NRF_SPIM23_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM30_SECURE +struct platform_data_t tfm_peripheral_spim30 = { + NRF_SPIM30_S_BASE, + NRF_SPIM30_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS0_SECURE +struct platform_data_t tfm_peripheral_spis0 = { + NRF_SPIS0_S_BASE, + NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM0_SECURE +struct platform_data_t tfm_peripheral_twim0 = { + NRF_TWIM0_S_BASE, + NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS0_SECURE +struct platform_data_t tfm_peripheral_twis0 = { + NRF_TWIS0_S_BASE, + NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE0_SECURE +struct platform_data_t tfm_peripheral_uarte0 = { + NRF_UARTE0_S_BASE, + NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM1_SECURE +struct platform_data_t tfm_peripheral_spim1 = { + NRF_SPIM1_S_BASE, + NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS1_SECURE +struct platform_data_t tfm_peripheral_spis1 = { + NRF_SPIS1_S_BASE, + NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM1_SECURE +struct platform_data_t tfm_peripheral_twim1 = { + NRF_TWIM1_S_BASE, + NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS1_SECURE +struct platform_data_t tfm_peripheral_twis1 = { + NRF_TWIS1_S_BASE, + NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE1_SECURE +struct platform_data_t tfm_peripheral_uarte1 = { + NRF_UARTE1_S_BASE, + NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM4_SECURE +struct platform_data_t tfm_peripheral_spim4 = { + NRF_SPIM4_S_BASE, + NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM2_SECURE +struct platform_data_t tfm_peripheral_spim2 = { + NRF_SPIM2_S_BASE, + NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS2_SECURE +struct platform_data_t tfm_peripheral_spis2 = { + NRF_SPIS2_S_BASE, + NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM2_SECURE +struct platform_data_t tfm_peripheral_twim2 = { + NRF_TWIM2_S_BASE, + NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS2_SECURE +struct platform_data_t tfm_peripheral_twis2 = { + NRF_TWIS2_S_BASE, + NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE2_SECURE +struct platform_data_t tfm_peripheral_uarte2 = { + NRF_UARTE2_S_BASE, + NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM3_SECURE +struct platform_data_t tfm_peripheral_spim3 = { + NRF_SPIM3_S_BASE, + NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS3_SECURE +struct platform_data_t tfm_peripheral_spis3 = { + NRF_SPIS3_S_BASE, + NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM3_SECURE +struct platform_data_t tfm_peripheral_twim3 = { + NRF_TWIM3_S_BASE, + NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS3_SECURE +struct platform_data_t tfm_peripheral_twis3 = { + NRF_TWIS3_S_BASE, + NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE3_SECURE +struct platform_data_t tfm_peripheral_uarte3 = { + NRF_UARTE3_S_BASE, + NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE00_SECURE +struct platform_data_t tfm_peripheral_uarte00 = { + NRF_UARTE00_S_BASE, + NRF_UARTE00_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE20_SECURE +struct platform_data_t tfm_peripheral_uarte20 = { + NRF_UARTE20_S_BASE, + NRF_UARTE20_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE21_SECURE +struct platform_data_t tfm_peripheral_uarte21 = { + NRF_UARTE21_S_BASE, + NRF_UARTE21_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE22_SECURE +struct platform_data_t tfm_peripheral_uarte22 = { + NRF_UARTE22_S_BASE, + NRF_UARTE22_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE30_SECURE +struct platform_data_t tfm_peripheral_uarte30 = { + NRF_UARTE30_S_BASE, + NRF_UARTE30_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SAADC_SECURE +struct platform_data_t tfm_peripheral_saadc = { + NRF_SAADC_S_BASE, + NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER0_SECURE +struct platform_data_t tfm_peripheral_timer0 = { + NRF_TIMER0_S_BASE, + NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER00_SECURE +struct platform_data_t tfm_peripheral_timer00 = { + NRF_TIMER00_S_BASE, + NRF_TIMER00_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER10_SECURE +struct platform_data_t tfm_peripheral_timer10 = { + NRF_TIMER10_S_BASE, + NRF_TIMER10_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER20_SECURE +struct platform_data_t tfm_peripheral_timer20 = { + NRF_TIMER20_S_BASE, + NRF_TIMER20_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER21_SECURE +struct platform_data_t tfm_peripheral_timer21 = { + NRF_TIMER21_S_BASE, + NRF_TIMER21_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER22_SECURE +struct platform_data_t tfm_peripheral_timer22 = { + NRF_TIMER22_S_BASE, + NRF_TIMER22_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER23_SECURE +struct platform_data_t tfm_peripheral_timer23 = { + NRF_TIMER23_S_BASE, + NRF_TIMER23_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER24_SECURE +struct platform_data_t tfm_peripheral_timer24 = { + NRF_TIMER24_S_BASE, + NRF_TIMER24_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER1_SECURE +struct platform_data_t tfm_peripheral_timer1 = { + NRF_TIMER1_S_BASE, + NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER2_SECURE +struct platform_data_t tfm_peripheral_timer2 = { + NRF_TIMER2_S_BASE, + NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RTC0_SECURE +struct platform_data_t tfm_peripheral_rtc0 = { + NRF_RTC0_S_BASE, + NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RTC1_SECURE +struct platform_data_t tfm_peripheral_rtc1 = { + NRF_RTC1_S_BASE, + NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_DPPI_SECURE +struct platform_data_t tfm_peripheral_dppi = { + NRF_DPPIC_S_BASE, + NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT_SECURE +struct platform_data_t tfm_peripheral_wdt = { + NRF_WDT_S_BASE, + NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT0_SECURE +struct platform_data_t tfm_peripheral_wdt0 = { + NRF_WDT0_S_BASE, + NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT1_SECURE +struct platform_data_t tfm_peripheral_wdt1 = { + NRF_WDT1_S_BASE, + NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_COMP_SECURE +struct platform_data_t tfm_peripheral_comp = { + NRF_COMP_S_BASE, + NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_LPCOMP_SECURE +struct platform_data_t tfm_peripheral_lpcomp = { + NRF_LPCOMP_S_BASE, + NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU0_SECURE +struct platform_data_t tfm_peripheral_egu0 = { + NRF_EGU0_S_BASE, + NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU1_SECURE +struct platform_data_t tfm_peripheral_egu1 = { + NRF_EGU1_S_BASE, + NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU2_SECURE +struct platform_data_t tfm_peripheral_egu2 = { + NRF_EGU2_S_BASE, + NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU3_SECURE +struct platform_data_t tfm_peripheral_egu3 = { + NRF_EGU3_S_BASE, + NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU4_SECURE +struct platform_data_t tfm_peripheral_egu4 = { + NRF_EGU4_S_BASE, + NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU5_SECURE +struct platform_data_t tfm_peripheral_egu5 = { + NRF_EGU5_S_BASE, + NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU10_SECURE +struct platform_data_t tfm_peripheral_egu10 = { + NRF_EGU10_S_BASE, + NRF_EGU10_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU20_SECURE +struct platform_data_t tfm_peripheral_egu20 = { + NRF_EGU20_S_BASE, + NRF_EGU20_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM0_SECURE +struct platform_data_t tfm_peripheral_pwm0 = { + NRF_PWM0_S_BASE, + NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM1_SECURE +struct platform_data_t tfm_peripheral_pwm1 = { + NRF_PWM1_S_BASE, + NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM2_SECURE +struct platform_data_t tfm_peripheral_pwm2 = { + NRF_PWM2_S_BASE, + NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM3_SECURE +struct platform_data_t tfm_peripheral_pwm3 = { + NRF_PWM3_S_BASE, + NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM20_SECURE +struct platform_data_t tfm_peripheral_pwm20 = { + NRF_PWM20_S_BASE, + NRF_PWM20_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM21_SECURE +struct platform_data_t tfm_peripheral_pwm21 = { + NRF_PWM21_S_BASE, + NRF_PWM21_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM22_SECURE +struct platform_data_t tfm_peripheral_pwm22 = { + NRF_PWM22_S_BASE, + NRF_PWM22_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PDM0_SECURE +struct platform_data_t tfm_peripheral_pdm0 = { + NRF_PDM0_S_BASE, + NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PDM_SECURE +struct platform_data_t tfm_peripheral_pdm = { + NRF_PDM_S_BASE, + NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_I2S0_SECURE +struct platform_data_t tfm_peripheral_i2s0 = { + NRF_I2S0_S_BASE, + NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_I2S_SECURE +struct platform_data_t tfm_peripheral_i2s = { + NRF_I2S_S_BASE, + NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_IPC_SECURE +struct platform_data_t tfm_peripheral_ipc = { + NRF_IPC_S_BASE, + NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_FPU_SECURE +struct platform_data_t tfm_peripheral_fpu = { + NRF_FPU_S_BASE, + NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QSPI_SECURE +struct platform_data_t tfm_peripheral_qspi = { + NRF_QSPI_S_BASE, + NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_NFCT_SECURE +struct platform_data_t tfm_peripheral_nfct = { + NRF_NFCT_S_BASE, + NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_MUTEX_SECURE +struct platform_data_t tfm_peripheral_mutex = { + NRF_MUTEX_S_BASE, + NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QDEC0_SECURE +struct platform_data_t tfm_peripheral_qdec0 = { + NRF_QDEC0_S_BASE, + NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QDEC1_SECURE +struct platform_data_t tfm_peripheral_qdec1 = { + NRF_QDEC1_S_BASE, + NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_USBD_SECURE +struct platform_data_t tfm_peripheral_usbd = { + NRF_USBD_S_BASE, + NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_USBREG_SECURE +struct platform_data_t tfm_peripheral_usbreg = { + NRF_USBREGULATOR_S_BASE, + NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_NVMC_SECURE +struct platform_data_t tfm_peripheral_nvmc = { + NRF_NVMC_S_BASE, + NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIO0_SECURE +struct platform_data_t tfm_peripheral_gpio0 = { + NRF_P0_S_BASE, + NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIO1_SECURE +struct platform_data_t tfm_peripheral_gpio1 = { + NRF_P1_S_BASE, + NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_VMC_SECURE +struct platform_data_t tfm_peripheral_vmc = { + NRF_VMC_S_BASE, + NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIOTE20_SECURE +struct platform_data_t tfm_peripheral_gpiote20 = { + NRF_GPIOTE20_S_BASE, + NRF_GPIOTE20_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIOTE30_SECURE +struct platform_data_t tfm_peripheral_gpiote30 = { + NRF_GPIOTE30_S_BASE, + NRF_GPIOTE30_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), +}; +#endif \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.c b/platform/ext/target/nordic_nrf/common/core/target_cfg.c index 75afa398be..ca3d517943 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.c @@ -17,700 +17,9 @@ */ #include "target_cfg.h" #include "region_defs.h" -#include "tfm_plat_defs.h" -#include "tfm_peripherals_config.h" -#include "tfm_plat_provisioning.h" -#include "utilities.h" #include "region.h" -#include "array.h" - -#ifdef __NRF_TFM__ -#include -#endif - -#include #include -#include -#include - -#ifdef RRAMC_PRESENT -#include -#include - -#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 -#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE -#else -#define WRITE_BUFFER_SIZE 0 -#endif - -#endif - -#define SPU_ADDRESS_REGION (0x50000000) -#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) -#define GET_SPU_INSTANCE(periph) ((NRF_SPU_Type*)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) - - -#ifdef CACHE_PRESENT -#include -#endif - -#ifdef NVMC_PRESENT -#include -#include -#endif - -#ifdef MPC_PRESENT -#include -#endif - -#ifdef NRF53_SERIES -#define PIN_XL1 0 -#define PIN_XL2 1 -#endif - -#ifdef NRF54L_SERIES -/* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ -#define PIN_XL1 32 -#define PIN_XL2 33 - -/* During TF-M system initialization we invoke a function that comes - * from Zephyr. This function does not have a header file so we - * declare its prototype here. - */ -int nordicsemi_nrf54l_init(void); -#endif - -#if TFM_PERIPHERAL_DCNF_SECURE -struct platform_data_t tfm_peripheral_dcnf = { - NRF_DCNF_S_BASE, - NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_FPU_SECURE -struct platform_data_t tfm_peripheral_fpu = { - NRF_FPU_S_BASE, - NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_OSCILLATORS_SECURE -struct platform_data_t tfm_peripheral_oscillators = { - NRF_OSCILLATORS_S_BASE, - NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_REGULATORS_SECURE -struct platform_data_t tfm_peripheral_regulators = { - NRF_REGULATORS_S_BASE, - NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_CLOCK_SECURE -struct platform_data_t tfm_peripheral_clock = { - NRF_CLOCK_S_BASE, - NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_POWER_SECURE -struct platform_data_t tfm_peripheral_power = { - NRF_POWER_S_BASE, - NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RESET_SECURE -struct platform_data_t tfm_peripheral_reset = { - NRF_RESET_S_BASE, - NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM0_SECURE -struct platform_data_t tfm_peripheral_spim0 = { - NRF_SPIM0_S_BASE, - NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM00_SECURE -struct platform_data_t tfm_peripheral_spim00 = { - NRF_SPIM00_S_BASE, - NRF_SPIM00_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM20_SECURE -struct platform_data_t tfm_peripheral_spim20 = { - NRF_SPIM20_S_BASE, - NRF_SPIM20_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM22_SECURE -struct platform_data_t tfm_peripheral_spim21 = { - NRF_SPIM21_S_BASE, - NRF_SPIM21_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM22_SECURE -struct platform_data_t tfm_peripheral_spim22 = { - NRF_SPIM22_S_BASE, - NRF_SPIM22_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM23_SECURE -struct platform_data_t tfm_peripheral_spim23 = { - NRF_SPIM23_S_BASE, - NRF_SPIM23_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM30_SECURE -struct platform_data_t tfm_peripheral_spim30 = { - NRF_SPIM30_S_BASE, - NRF_SPIM30_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS0_SECURE -struct platform_data_t tfm_peripheral_spis0 = { - NRF_SPIS0_S_BASE, - NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM0_SECURE -struct platform_data_t tfm_peripheral_twim0 = { - NRF_TWIM0_S_BASE, - NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS0_SECURE -struct platform_data_t tfm_peripheral_twis0 = { - NRF_TWIS0_S_BASE, - NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE0_SECURE -struct platform_data_t tfm_peripheral_uarte0 = { - NRF_UARTE0_S_BASE, - NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM1_SECURE -struct platform_data_t tfm_peripheral_spim1 = { - NRF_SPIM1_S_BASE, - NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS1_SECURE -struct platform_data_t tfm_peripheral_spis1 = { - NRF_SPIS1_S_BASE, - NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM1_SECURE -struct platform_data_t tfm_peripheral_twim1 = { - NRF_TWIM1_S_BASE, - NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS1_SECURE -struct platform_data_t tfm_peripheral_twis1 = { - NRF_TWIS1_S_BASE, - NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE1_SECURE -struct platform_data_t tfm_peripheral_uarte1 = { - NRF_UARTE1_S_BASE, - NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM4_SECURE -struct platform_data_t tfm_peripheral_spim4 = { - NRF_SPIM4_S_BASE, - NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM2_SECURE -struct platform_data_t tfm_peripheral_spim2 = { - NRF_SPIM2_S_BASE, - NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS2_SECURE -struct platform_data_t tfm_peripheral_spis2 = { - NRF_SPIS2_S_BASE, - NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM2_SECURE -struct platform_data_t tfm_peripheral_twim2 = { - NRF_TWIM2_S_BASE, - NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS2_SECURE -struct platform_data_t tfm_peripheral_twis2 = { - NRF_TWIS2_S_BASE, - NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE2_SECURE -struct platform_data_t tfm_peripheral_uarte2 = { - NRF_UARTE2_S_BASE, - NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM3_SECURE -struct platform_data_t tfm_peripheral_spim3 = { - NRF_SPIM3_S_BASE, - NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS3_SECURE -struct platform_data_t tfm_peripheral_spis3 = { - NRF_SPIS3_S_BASE, - NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM3_SECURE -struct platform_data_t tfm_peripheral_twim3 = { - NRF_TWIM3_S_BASE, - NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS3_SECURE -struct platform_data_t tfm_peripheral_twis3 = { - NRF_TWIS3_S_BASE, - NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE3_SECURE -struct platform_data_t tfm_peripheral_uarte3 = { - NRF_UARTE3_S_BASE, - NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE00_SECURE -struct platform_data_t tfm_peripheral_uarte00 = { - NRF_UARTE00_S_BASE, - NRF_UARTE00_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE20_SECURE -struct platform_data_t tfm_peripheral_uarte20 = { - NRF_UARTE20_S_BASE, - NRF_UARTE20_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE21_SECURE -struct platform_data_t tfm_peripheral_uarte21 = { - NRF_UARTE21_S_BASE, - NRF_UARTE21_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE22_SECURE -struct platform_data_t tfm_peripheral_uarte22 = { - NRF_UARTE22_S_BASE, - NRF_UARTE22_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE30_SECURE -struct platform_data_t tfm_peripheral_uarte30 = { - NRF_UARTE30_S_BASE, - NRF_UARTE30_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SAADC_SECURE -struct platform_data_t tfm_peripheral_saadc = { - NRF_SAADC_S_BASE, - NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER0_SECURE -struct platform_data_t tfm_peripheral_timer0 = { - NRF_TIMER0_S_BASE, - NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER00_SECURE -struct platform_data_t tfm_peripheral_timer00 = { - NRF_TIMER00_S_BASE, - NRF_TIMER00_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER10_SECURE -struct platform_data_t tfm_peripheral_timer10 = { - NRF_TIMER10_S_BASE, - NRF_TIMER10_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER20_SECURE -struct platform_data_t tfm_peripheral_timer20 = { - NRF_TIMER20_S_BASE, - NRF_TIMER20_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER21_SECURE -struct platform_data_t tfm_peripheral_timer21 = { - NRF_TIMER21_S_BASE, - NRF_TIMER21_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER22_SECURE -struct platform_data_t tfm_peripheral_timer22 = { - NRF_TIMER22_S_BASE, - NRF_TIMER22_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER23_SECURE -struct platform_data_t tfm_peripheral_timer23 = { - NRF_TIMER23_S_BASE, - NRF_TIMER23_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER24_SECURE -struct platform_data_t tfm_peripheral_timer24 = { - NRF_TIMER24_S_BASE, - NRF_TIMER24_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER1_SECURE -struct platform_data_t tfm_peripheral_timer1 = { - NRF_TIMER1_S_BASE, - NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER2_SECURE -struct platform_data_t tfm_peripheral_timer2 = { - NRF_TIMER2_S_BASE, - NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RTC0_SECURE -struct platform_data_t tfm_peripheral_rtc0 = { - NRF_RTC0_S_BASE, - NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RTC1_SECURE -struct platform_data_t tfm_peripheral_rtc1 = { - NRF_RTC1_S_BASE, - NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_DPPI_SECURE -struct platform_data_t tfm_peripheral_dppi = { - NRF_DPPIC_S_BASE, - NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT_SECURE -struct platform_data_t tfm_peripheral_wdt = { - NRF_WDT_S_BASE, - NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT0_SECURE -struct platform_data_t tfm_peripheral_wdt0 = { - NRF_WDT0_S_BASE, - NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT1_SECURE -struct platform_data_t tfm_peripheral_wdt1 = { - NRF_WDT1_S_BASE, - NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_COMP_SECURE -struct platform_data_t tfm_peripheral_comp = { - NRF_COMP_S_BASE, - NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_LPCOMP_SECURE -struct platform_data_t tfm_peripheral_lpcomp = { - NRF_LPCOMP_S_BASE, - NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU0_SECURE -struct platform_data_t tfm_peripheral_egu0 = { - NRF_EGU0_S_BASE, - NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU1_SECURE -struct platform_data_t tfm_peripheral_egu1 = { - NRF_EGU1_S_BASE, - NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU2_SECURE -struct platform_data_t tfm_peripheral_egu2 = { - NRF_EGU2_S_BASE, - NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU3_SECURE -struct platform_data_t tfm_peripheral_egu3 = { - NRF_EGU3_S_BASE, - NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU4_SECURE -struct platform_data_t tfm_peripheral_egu4 = { - NRF_EGU4_S_BASE, - NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU5_SECURE -struct platform_data_t tfm_peripheral_egu5 = { - NRF_EGU5_S_BASE, - NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU10_SECURE -struct platform_data_t tfm_peripheral_egu10 = { - NRF_EGU10_S_BASE, - NRF_EGU10_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU20_SECURE -struct platform_data_t tfm_peripheral_egu20 = { - NRF_EGU20_S_BASE, - NRF_EGU20_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM0_SECURE -struct platform_data_t tfm_peripheral_pwm0 = { - NRF_PWM0_S_BASE, - NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM1_SECURE -struct platform_data_t tfm_peripheral_pwm1 = { - NRF_PWM1_S_BASE, - NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM2_SECURE -struct platform_data_t tfm_peripheral_pwm2 = { - NRF_PWM2_S_BASE, - NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM3_SECURE -struct platform_data_t tfm_peripheral_pwm3 = { - NRF_PWM3_S_BASE, - NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM20_SECURE -struct platform_data_t tfm_peripheral_pwm20 = { - NRF_PWM20_S_BASE, - NRF_PWM20_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM21_SECURE -struct platform_data_t tfm_peripheral_pwm21 = { - NRF_PWM21_S_BASE, - NRF_PWM21_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM22_SECURE -struct platform_data_t tfm_peripheral_pwm22 = { - NRF_PWM22_S_BASE, - NRF_PWM22_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PDM0_SECURE -struct platform_data_t tfm_peripheral_pdm0 = { - NRF_PDM0_S_BASE, - NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PDM_SECURE -struct platform_data_t tfm_peripheral_pdm = { - NRF_PDM_S_BASE, - NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_I2S0_SECURE -struct platform_data_t tfm_peripheral_i2s0 = { - NRF_I2S0_S_BASE, - NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_I2S_SECURE -struct platform_data_t tfm_peripheral_i2s = { - NRF_I2S_S_BASE, - NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_IPC_SECURE -struct platform_data_t tfm_peripheral_ipc = { - NRF_IPC_S_BASE, - NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_FPU_SECURE -struct platform_data_t tfm_peripheral_fpu = { - NRF_FPU_S_BASE, - NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QSPI_SECURE -struct platform_data_t tfm_peripheral_qspi = { - NRF_QSPI_S_BASE, - NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_NFCT_SECURE -struct platform_data_t tfm_peripheral_nfct = { - NRF_NFCT_S_BASE, - NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_MUTEX_SECURE -struct platform_data_t tfm_peripheral_mutex = { - NRF_MUTEX_S_BASE, - NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QDEC0_SECURE -struct platform_data_t tfm_peripheral_qdec0 = { - NRF_QDEC0_S_BASE, - NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QDEC1_SECURE -struct platform_data_t tfm_peripheral_qdec1 = { - NRF_QDEC1_S_BASE, - NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_USBD_SECURE -struct platform_data_t tfm_peripheral_usbd = { - NRF_USBD_S_BASE, - NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_USBREG_SECURE -struct platform_data_t tfm_peripheral_usbreg = { - NRF_USBREGULATOR_S_BASE, - NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_NVMC_SECURE -struct platform_data_t tfm_peripheral_nvmc = { - NRF_NVMC_S_BASE, - NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_GPIO0_SECURE -struct platform_data_t tfm_peripheral_gpio0 = { - NRF_P0_S_BASE, - NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_GPIO1_SECURE -struct platform_data_t tfm_peripheral_gpio1 = { - NRF_P1_S_BASE, - NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_VMC_SECURE -struct platform_data_t tfm_peripheral_vmc = { - NRF_VMC_S_BASE, - NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1), -}; -#endif - #ifdef PSA_API_TEST_IPC struct platform_data_t tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = { @@ -807,784 +116,3 @@ enum tfm_plat_err_t system_reset_cfg(void) return TFM_PLAT_ERR_SUCCESS; } - -enum tfm_plat_err_t init_debug(void) -{ -#if defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT) - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "Debug access controlled by NRF_APPROTECT and NRF_SECURE_APPROTECT." -#endif - -#if defined(NRF_APPROTECT) && !defined(NRF54L_SERIES) - /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot.*/ - if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, - UICR_APPROTECT_PALL_Protected)) { - nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->APPROTECT, UICR_APPROTECT_PALL_Protected); - } else { - return TFM_PLAT_ERR_SYSTEM_ERR; - } -#endif -#if defined(NRF_SECURE_APPROTECT) && !defined(NRF54L_SERIES) - /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot. */ - if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, - UICR_SECUREAPPROTECT_PALL_Protected)) { - nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, - UICR_SECUREAPPROTECT_PALL_Protected); - } else { - return TFM_PLAT_ERR_SYSTEM_ERR; - } -#endif - -#elif defined(NRF91_SERIES) || defined(NRF54L_SERIES) - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." -#endif - -#elif defined(NRF53_SERIES) - -#if defined(DAUTH_NONE) - /* Disable debugging */ - NRF_CTRLAP->APPROTECT.DISABLE = 0; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; -#elif defined(DAUTH_NS_ONLY) - /* Allow debugging Non-Secure only */ - NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; -#elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT) - /* Allow debugging */ - /* Use the configuration in UICR. */ - NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT; -#else -#error "No debug authentication setting is provided." -#endif - - /* Lock access to APPROTECT, SECUREAPPROTECT */ - NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked << - CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk; - NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked << - CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk; - -#else -#error "Unrecognized platform" - -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -#define NRF_UARTE_INSTANCE(id) NRF_UARTE ## id -#define NRF_UARTE_INSTANCE_GET(id) NRF_UARTE_INSTANCE(id) - -/*----------------- NVIC interrupt target state to NS configuration ----------*/ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) -{ - /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ - for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { - NVIC->ITNS[i] = 0xFFFFFFFF; - } - - /* Make sure that the SPU instance(s) are targeted to S state */ - for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); - } - -#ifdef NRF_CRACEN - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_CRACEN)); -#endif -#ifdef NRF_MPC00 - NVIC_ClearTargetState(MPC00_IRQn); -#endif - -#ifdef SECURE_UART1 - /* IRQ for the selected secure UART has to target S state */ - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ -enum tfm_plat_err_t nvic_interrupt_enable(void) -{ - /* SPU interrupt enabling */ - spu_enable_interrupts(); - - for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { - NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); - NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); - } - -#ifdef MPC_PRESENT - mpc_clear_events(); - /* MPC interrupt enabling */ - mpc_enable_interrupts(); - - NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); - NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); -#endif - - /* The CRACEN driver configures the NVIC for CRACEN and is - * therefore omitted here. - */ - - return TFM_PLAT_ERR_SUCCESS; -} - -/*------------------- SAU/IDAU configuration functions -----------------------*/ - -void sau_and_idau_cfg(void) -{ - /* - * SAU and IDAU configuration is very different between old - * (53/91) and new (54++) platforms. New platforms have a proper SAU - * and IDAU, whereas old platforms do not. - */ -#ifdef NRF54L_SERIES - /* - * This SAU configuration aligns with ARM's RSS implementation of - * sau_and_idau_cfg when possible. - */ - - /* Enables SAU */ - TZ_SAU_Enable(); - - /* Configures SAU regions to be non-secure */ - - /* Note that this SAU configuration assumes that there is only one - * secure NVM partition and one non-secure NVM partition. Meaning, - * memory_regions.non_secure_partition_limit is at the end of - * NVM. - */ - - /* Configure the end of NVM, and the FICR, to be non-secure using - a single region. Note that the FICR is placed after the - non-secure NVM and before the UICR.*/ - SAU->RNR = 0; - SAU->RBAR = (memory_regions.non_secure_partition_base - & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (NRF_UICR_S_BASE & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - - /* Leave SAU region 1 disabled until we find a use for it */ - - /* Configures veneers region to be non-secure callable */ - SAU->RNR = 2; - SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk; - - /* Configures SAU region 3 to cover both the end of SRAM and - * regions above it as shown in the "Example memory map" in the - * "Product Specification" */ - SAU->RNR = 3; - SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (0xFFFFFFFFul & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - -#else - /* IDAU (SPU) is always enabled. SAU is non-existent. - * Allow SPU to have precedence over (non-existing) ARMv8-M SAU. - */ - TZ_SAU_Disable(); - SAU->CTRL |= SAU_CTRL_ALLNS_Msk; -#endif -} - -#if NRF_SPU_HAS_MEMORY -enum tfm_plat_err_t spu_init_cfg(void) -{ - /* - * Configure SPU Regions for Non-Secure Code and SRAM (Data) - * Configure SPU for Peripheral Security - * Configure Non-Secure Callable Regions - * Configure Secondary Image Partition - * Configure Non-Secure Storage Partition - */ - - /* Reset Flash and SRAM configuration of regions that are not owned by - * the bootloader(s) to all-Secure. - */ - spu_regions_reset_unlocked_secure(); - - uint32_t perm; - - /* Configure Secure Code to be secure and RX */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - /* Do not permit writes to secure flash */ - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configure Secure RAM to be secure and RWX */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - /* Permit execute from Secure RAM because otherwise Crypto fails - * to initialize. */ - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configures SPU Code and Data regions to be non-secure */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_flash_config(memory_regions.non_secure_partition_base, - memory_regions.non_secure_partition_limit, SPU_SECURE_ATTR_NONSECURE, - perm, SPU_LOCK_CONF_LOCKED); - - spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configures veneers region to be non-secure callable */ - spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base, - memory_regions.veneer_limit - 1); - -#ifdef NRF_NS_SECONDARY - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - - /* Secondary image partition */ - spu_regions_flash_config(memory_regions.secondary_partition_base, - memory_regions.secondary_partition_limit, SPU_SECURE_ATTR_NONSECURE, - perm, SPU_LOCK_CONF_LOCKED); -#endif /* NRF_NS_SECONDARY */ - -#ifdef NRF_NS_STORAGE_PARTITION_START - /* Configures storage partition to be non-secure */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - - spu_regions_flash_config(memory_regions.non_secure_storage_partition_base, - memory_regions.non_secure_storage_partition_limit, - SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); -#endif /* NRF_NS_STORAGE_PARTITION_START */ - -#ifdef REGION_PCD_SRAM_ADDRESS - /* Netcore needs PCD memory area to be non-secure. */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - if (tfm_plat_provisioning_is_required()) { - perm |= NRF_SPU_MEM_PERM_WRITE; - } - - spu_regions_sram_config(REGION_PCD_SRAM_ADDRESS, REGION_PCD_SRAM_LIMIT, - SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} -#endif /* NRF_SPU_HAS_MEMORY */ - - -#ifdef MPC_PRESENT -struct mpc_region_override { - nrf_mpc_override_config_t config; - nrf_owner_t owner_id; - uintptr_t start_address; - size_t endaddr; - uint32_t perm; - uint32_t permmask; - size_t index; -}; - -static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) -{ - nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); - nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); - nrf_mpc_override_perm_set(mpc, override->index, override->perm); - nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); -#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID - nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); -#endif - nrf_mpc_override_config_set(mpc, override->index, &override->config); -} - -/* - * Configure the override struct with reasonable defaults. This includes: - * - * Use a slave number of 0 to avoid redirecting bus transactions from - * one slave to another. - * - * Lock the override to prevent the code that follows from tampering - * with the configuration. - * - * Enable the override so it takes effect. - * - * Indicate that secdom is not enabled as this driver is not used on - * platforms with secdom. - */ -static void init_mpc_region_override(struct mpc_region_override * override) -{ - *override = (struct mpc_region_override){ - .config = - (nrf_mpc_override_config_t){ - .slave_number = 0, - .lock = true, - .enable = true, - .secdom_enable = false, - .secure_mask = true, - }, - .perm = 0, /* 0 for non-secure */ - .owner_id = 0, - }; - - override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; -} - -enum tfm_plat_err_t nrf_mpc_init_cfg(void) -{ - /* On 54l the NRF_MPC00->REGION[]'s are fixed in HW and the - * OVERRIDE indexes (that are useful to us) start at 0 and end - * (inclusive) at 4. - * - * Note that the MPC regions configure all volatile and non-volatile memory as secure, so we only - * need to explicitly OVERRIDE the non-secure addresses to permit non-secure access. - * - * Explicitly configuring memory as secure is not necessary. - * - * The last OVERRIDE in 54L is fixed in HW and exists to prevent - * other bus masters than the KMU from accessing CRACEN protected RAM. - * - * Note that we must take care not to configure an OVERRIDE that - * affects an active bus transaction. - * - * Note that we don't configure the NSC region to be NS because - * from the MPC's perspective it is secure. NSC is only configurable from the SAU. - * - * Note that OVERRIDE[n].MASTERPORT has a reasonable reset value - * so it is left unconfigured. - * - * Note that there are two owners in 54L. KMU with owner ID 1, and everything else with owner ID 0. - */ - - uint32_t index = 0; - /* - * Configure the non-secure partition of the non-volatile - * memory. This MPC region is intended to cover both the - * non-secure partition in the NVM and also the FICR. The FICR - * starts after the NVM and ends just before the UICR. - */ - { - struct mpc_region_override override; - - init_mpc_region_override(&override); - - override.start_address = memory_regions.non_secure_partition_base; - override.endaddr = NRF_UICR_S_BASE; - override.index = index++; - - mpc_configure_override(NRF_MPC00, &override); - } - - /* Configure the non-secure partition of the volatile memory */ - { - struct mpc_region_override override; - - init_mpc_region_override(&override); - - override.start_address = NS_DATA_START; - override.endaddr = 1 + NS_DATA_LIMIT; - override.index = index++; - - mpc_configure_override(NRF_MPC00, &override); - } - - if(index > 4) { - /* Used more overrides than are available */ - tfm_core_panic(); - } - - /* Lock and disable any unused MPC overrides to prevent malicious configuration */ - while(index <= 4) { - struct mpc_region_override override; - - init_mpc_region_override(&override); - - override.config.enable = false; - - override.index = index++; - - mpc_configure_override(NRF_MPC00, &override); - } - - return TFM_PLAT_ERR_SUCCESS; -} - -#endif /* MPC_PRESENT */ - -static void dppi_channel_configuration(void) -{ - /* The SPU HW and corresponding NRFX HAL API have two different - * API's for DPPI security configuration. The defines - * NRF_SPU_HAS_OWNERSHIP and NRF_SPU_HAS_MEMORY identify which of the two API's - * are present. - * - * TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE is configurable, but - * usually defaults to 0, which results in all DPPI channels being - * non-secure. - */ -#if NRF_SPU_HAS_MEMORY - /* There is only one dppi_id */ - uint8_t dppi_id = 0; - nrf_spu_dppi_config_set(NRF_SPU, dppi_id, TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, - SPU_LOCK_CONF_LOCKED); -#else - /* TODO_NRF54L15: Use the nrf_spu_feature API to configure DPPI - channels according to a user-controllable config similar to - TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE. */ -#endif -} - -enum tfm_plat_err_t spu_periph_init_cfg(void) -{ - /* Peripheral configuration */ -#ifdef NRF54L_SERIES - /* Configure features to be non-secure */ - - /* - * Due to MLT-7600, many SPU HW reset values are wrong. The docs - * generally features being non-secure when coming out of HW - * reset, but the HW has a good mix of both. - * - * When configuring NRF_SPU 0 will indicate non-secure and 1 will - * indicate secure. - * - * Most of the chip should be non-secure so to simplify and be - * consistent, we memset the entire memory map of each SPU - * peripheral to 0. - * - * Just after memsetting to 0 we explicitly configure the - * peripherals that should be secure back to secure again. - */ - // TODO: NCSDK-22597: Evaluate if it is safe to memset everything - // in NRF_SPU to 0. - memset(NRF_SPU00, 0, sizeof(NRF_SPU_Type)); - memset(NRF_SPU10, 0, sizeof(NRF_SPU_Type)); - memset(NRF_SPU20, 0, sizeof(NRF_SPU_Type)); - memset(NRF_SPU30, 0, sizeof(NRF_SPU_Type)); - -#if SECURE_UART1 - /* Configure TF-M's UART peripheral to be secure */ -#if NRF_SECURE_UART_INSTANCE == 00 - uint32_t uart_periph_start = tfm_peripheral_uarte00.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 20 - uint32_t uart_periph_start = tfm_peripheral_uarte20.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 21 - uint32_t uart_periph_start = tfm_peripheral_uarte21.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 22 - uint32_t uart_periph_start = tfm_peripheral_uarte22.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 30 - uint32_t uart_periph_start = tfm_peripheral_uarte30.periph_start; -#endif - spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); -#endif /* SECURE_UART1 */ - - /* Configure the CTRL-AP mailbox interface to be secure as it is used by the secure ADAC service */ - spu_peripheral_config_secure(NRF_CTRLAP_S_BASE, SPU_LOCK_CONF_LOCKED); - - /* Configure NRF_MEMCONF to be secure as it could otherwise be used to corrupt secure RAM. */ - spu_peripheral_config_secure(NRF_MEMCONF_S_BASE, SPU_LOCK_CONF_LOCKED); - - /* Configure trace to be secure, as the security implications of non-secure trace are not understood */ - spu_peripheral_config_secure(NRF_TAD_S_BASE, SPU_LOCK_CONF_LOCKED); - - /* Configure these HW features, which are not in the MDK, to be - * secure, as the security implications of them being non-secure - * are not understood - */ - uint32_t base_addresses[4] = { - 0x50056000, - 0x5008C000, - 0x500E6000, - 0x5010F000 - }; - for(int i = 0; i < 4; i++) { - spu_peripheral_config_secure(base_addresses[i], SPU_LOCK_CONF_LOCKED); - } - - /* Configure NRF_REGULATORS, and NRF_OSCILLATORS to be secure as NRF_REGULATORS.POFCON is needed - * to prevent glitches when the power supply is attacked. - * - * NB: Note that NRF_OSCILLATORS and NRF_REGULATORS have the same base address and must therefore - * have the same security configuration. - */ - spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); -#else /* NRF54L_SERIES */ -static const uint32_t target_peripherals[] = { - /* The following peripherals share ID: - * - FPU (FPU cannot be configured in NRF91 series, it's always NS) - * - DCNF (On 53, but not 91) - */ -#ifndef NRF91_SERIES - NRF_FPU_S_BASE, -#endif - /* The following peripherals share ID: - * - REGULATORS - * - OSCILLATORS - */ - NRF_REGULATORS_S_BASE, - /* The following peripherals share ID: - * - CLOCK - * - POWER - * - RESET (On 53, but not 91) - */ - NRF_CLOCK_S_BASE, - /* The following peripherals share ID: (referred to as Serial-Box) - * - SPIMx - * - SPISx - * - TWIMx - * - TWISx - * - UARTEx - */ - - /* When UART0 is a secure peripheral we need to leave Serial-Box 0 as Secure. - * The UART Driver will configure it as non-secure when it uninitializes. - */ -#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 0) - NRF_SPIM0_S_BASE, -#endif -#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 1) - /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */ - NRF_SPIM1_S_BASE, -#endif - NRF_SPIM2_S_BASE, - NRF_SPIM3_S_BASE, -#ifdef NRF_SPIM4 - NRF_SPIM4_S_BASE, -#endif - NRF_SAADC_S_BASE, - NRF_TIMER0_S_BASE, - NRF_TIMER1_S_BASE, - NRF_TIMER2_S_BASE, - NRF_RTC0_S_BASE, - NRF_RTC1_S_BASE, - NRF_DPPIC_S_BASE, -#ifndef PSA_API_TEST_IPC -#ifdef NRF_WDT0 - /* WDT0 is used as a secure peripheral in PSA FF tests */ - NRF_WDT0_S_BASE, -#endif -#ifdef NRF_WDT - NRF_WDT_S_BASE, -#endif -#endif /* PSA_API_TEST_IPC */ -#ifdef NRF_WDT1 - NRF_WDT1_S_BASE, -#endif - /* The following peripherals share ID: - * - COMP - * - LPCOMP - */ -#ifdef NRF_COMP - NRF_COMP_S_BASE, -#endif - NRF_EGU0_S_BASE, - NRF_EGU1_S_BASE, - NRF_EGU2_S_BASE, - NRF_EGU3_S_BASE, - NRF_EGU4_S_BASE, -#ifndef PSA_API_TEST_IPC - /* EGU5 is used as a secure peripheral in PSA FF tests */ - NRF_EGU5_S_BASE, -#endif - NRF_PWM0_S_BASE, - NRF_PWM1_S_BASE, - NRF_PWM2_S_BASE, - NRF_PWM3_S_BASE, -#ifdef NRF_PDM - NRF_PDM_S_BASE, -#endif -#ifdef NRF_PDM0 - NRF_PDM0_S_BASE, -#endif -#ifdef NRF_I2S - NRF_I2S_S_BASE, -#endif -#ifdef NRF_I2S0 - NRF_I2S0_S_BASE, -#endif - NRF_IPC_S_BASE, -#ifndef SECURE_QSPI -#ifdef NRF_QSPI - NRF_QSPI_S_BASE, -#endif -#endif -#ifdef NRF_NFCT - NRF_NFCT_S_BASE, -#endif -#ifdef NRF_MUTEX - NRF_MUTEX_S_BASE, -#endif -#ifdef NRF_QDEC0 - NRF_QDEC0_S_BASE, -#endif -#ifdef NRF_QDEC1 - NRF_QDEC1_S_BASE, -#endif -#ifdef NRF_USBD - NRF_USBD_S_BASE, -#endif -#ifdef NRF_USBREGULATOR - NRF_USBREGULATOR_S_BASE, -#endif /* NRF_USBREGULATOR */ - NRF_NVMC_S_BASE, - NRF_P0_S_BASE, -#ifdef NRF_P1 - NRF_P1_S_BASE, -#endif /*NRF_P1 */ -#if defined(NRF91_SERIES) || defined(NRF53_SERIES) - NRF_VMC_S_BASE -#endif -}; - - for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) { - spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); - } - -#endif /* NRF54L_SERIES */ - - /* DPPI channel configuration */ - dppi_channel_configuration(); - - /* GPIO pin configuration */ - uint32_t secure_pins[] = { -#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE - TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, -#endif -#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE - TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, -#endif -#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE - TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, -#endif - }; - - /* Note that there are two different API's for SPU configuration */ -#if NRF_SPU_HAS_MEMORY - - for(int port = 0; port < ARRAY_SIZE(secure_pins); port++){ - nrf_spu_gpio_config_set(NRF_SPU, port, secure_pins[port], SPU_LOCK_CONF_LOCKED); - } - -#elif NRF_SPU_HAS_PERIPHERAL_ACCESS - - for(int port = 0; port < ARRAY_SIZE(secure_pins); port++) { - for (int pin = 0; pin < 32; pin++) { - if (secure_pins[port] & (1 << pin)) { - bool enable = true; // secure - - /* - * Unfortunately, NRF_P0 is not configured by NRF_SPU00, etc. - * so it is a bit convoluted to find the SPU instance for port x. - */ - uint32_t gpio_port_addr[2] = { - NRF_P0_S_BASE, - NRF_P1_S_BASE, - }; - - NRF_SPU_Type * spu_instance = spu_instance_from_peripheral_addr(gpio_port_addr[port]); - - nrf_spu_feature_secattr_set(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, port, pin, enable); - nrf_spu_feature_lock_enable(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, port, pin); - } - } - } -#else -#error "Expected either NRF_SPU_HAS_MEMORY or NRF_SPU_HAS_PERIPHERAL_ACCESS to be true" -#endif - - /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal - * oscillator (LFXO) can be used. - * This configuration can be done only from secure code, as otherwise those - * register fields are not accessible. That's why it is placed here. - */ -#ifdef NRF53_SERIES - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); -#endif /* NRF53_SERIES */ -#ifdef NRF54L_SERIES - /* NRF54L has a different define */ - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_GPIO); - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_GPIO); -#endif - - /* - * 91 has an instruction cache. - * 53 has both instruction cache and a data cache. - * - * 53's instruction cache has an nrfx driver, but 91's cache is - * not supported by nrfx at time of writing. - * - * We enable all caches available here because non-secure cannot - * configure caches. - */ -#if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK - nrfx_nvmc_icache_enable(); -#elif defined(CACHE_PRESENT) // From MDK - -#ifdef NRF_CACHE - nrf_cache_enable(NRF_CACHE); -#endif -#ifdef NRF_ICACHE - nrf_cache_enable(NRF_ICACHE); -#endif -#ifdef NRF_DCACHE - nrf_cache_enable(NRF_DCACHE); -#endif - -#endif - -#ifdef RRAMC_PRESENT - nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); - - config.mode_write = true; - -#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 - config.preload_timeout_enable = true; - config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; -#else - config.preload_timeout_enable = false; - config.preload_timeout = 0; -#endif - - /* Don't use an event handler until it's understood whether we - * want it or not - */ - nrfx_rramc_evt_handler_t handler = NULL; - - nrfx_err_t err = nrfx_rramc_init(&config, handler); - if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { - return err; - } -#endif /* RRAMC_PRESENT */ - -#ifdef NRF54L_SERIES - /* SOC configuration from Zephyr's soc.c. */ - int soc_err = nordicsemi_nrf54l_init(); - if (soc_err) { - return soc_err; - } -#endif - -#if NRF_SPU_HAS_MEMORY - /* Enforce that the nRF5340 Network MCU is in the Non-Secure - * domain. Non-secure is the HW reset value for the network core - * so configuring this should not be necessary, but we want to - * make sure that the bootloader has not accidentally configured - * it to be secure. Additionally we lock the register to make sure - * it doesn't get changed by accident. - */ - nrf_spu_extdomain_set(NRF_SPU, 0, false, true); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.h b/platform/ext/target/nordic_nrf/common/core/target_cfg.h index 1b3072582c..dd767b3865 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.h +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.h @@ -35,6 +35,9 @@ #include "tfm_plat_defs.h" #include "region_defs.h" +#define NRF_UARTE_INSTANCE(id) NRF_UARTE##id +#define NRF_UARTE_INSTANCE_GET(id) NRF_UARTE_INSTANCE(id) + #ifndef NRF_SECURE_UART_INSTANCE #define TFM_DRIVER_STDIO Driver_USART1 #elif NRF_SECURE_UART_INSTANCE == 0 diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c new file mode 100644 index 0000000000..c94181a475 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include +#include +#include +#include +#include + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +#ifdef NRF53_SERIES +#include +#define PIN_XL1 0 +#define PIN_XL2 1 +#endif + +extern const struct memory_region_limits memory_regions; + +static inline enum tfm_plat_err_t configure_approtect_nvmc(void) +{ +#if defined(NRF_APPROTECT) + /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot.*/ + if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected)) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif +#if defined(NRF_SECURE_APPROTECT) + /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot. */ + if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected)) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +#if defined(NRF53_SERIES) + +static inline enum tfm_plat_err_t configure_approtect_registers(void) +{ +#if defined(DAUTH_NONE) + /* Disable debugging */ + NRF_CTRLAP->APPROTECT.DISABLE = 0; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; +#elif defined(DAUTH_NS_ONLY) + /* Allow debugging Non-Secure only */ + NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; +#elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT) + /* Allow debugging */ + /* Use the configuration in UICR. */ + NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT; +#else +#error "No debug authentication setting is provided." +#endif + + /* Lock access to APPROTECT, SECUREAPPROTECT */ + NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked + << CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk; + NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked + << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk; + + return TFM_PLAT_ERR_SUCCESS; +} +#endif + +enum tfm_plat_err_t init_debug(void) +{ + +#if (defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT)) && !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access controlled by NRF_APPROTECT and NRF_SECURE_APPROTECT." +#elif defined(NRF91_SERIES) && !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on the nRF91 series can only be configured by programming the corresponding registers in UICR." +#endif + +#if defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT) + return configure_approtect_nvmc(); +#elif defined(NRF53_SERIES) + return configure_approtect_registers(); +#endif +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* IDAU (SPU) is always enabled. SAU is non-existent. + * Allow SPU to have precedence over (non-existing) ARMv8-M SAU. + */ + TZ_SAU_Disable(); + SAU->CTRL |= SAU_CTRL_ALLNS_Msk; +} + +enum tfm_plat_err_t spu_init_cfg(void) +{ + /* + * Configure SPU Regions for Non-Secure Code and SRAM (Data) + * Configure SPU for Peripheral Security + * Configure Non-Secure Callable Regions + * Configure Secondary Image Partition + * Configure Non-Secure Storage Partition + */ + + /* Reset Flash and SRAM configuration of regions that are not owned by + * the bootloader(s) to all-Secure. + */ + spu_regions_reset_unlocked_secure(); + + uint32_t perm; + + /* Configure Secure Code to be secure and RX */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + /* Do not permit writes to secure flash */ + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configure Secure RAM to be secure and RWX */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + /* Permit execute from Secure RAM because otherwise Crypto fails + * to initialize. */ + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configures SPU Code and Data regions to be non-secure */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_flash_config(memory_regions.non_secure_partition_base, + memory_regions.non_secure_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); + + spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configures veneers region to be non-secure callable */ + spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base, + memory_regions.veneer_limit - 1); + +#ifdef NRF_NS_SECONDARY + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + + /* Secondary image partition */ + spu_regions_flash_config(memory_regions.secondary_partition_base, + memory_regions.secondary_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* NRF_NS_SECONDARY */ + +#ifdef NRF_NS_STORAGE_PARTITION_START + /* Configures storage partition to be non-secure */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + + spu_regions_flash_config(memory_regions.non_secure_storage_partition_base, + memory_regions.non_secure_storage_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* NRF_NS_STORAGE_PARTITION_START */ + +#ifdef REGION_PCD_SRAM_ADDRESS + enum tfm_plat_err_t err; + bool provisioning_required; + /* Netcore needs PCD memory area to be non-secure. */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + + err = tfm_plat_provisioning_is_required(&provisioning_required); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + if (provisioning_required) { + perm |= NRF_SPU_MEM_PERM_WRITE; + } + + spu_regions_sram_config(REGION_PCD_SRAM_ADDRESS, REGION_PCD_SRAM_LIMIT, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* REGION_PCD_SRAM_ADDRESS */ + + return TFM_PLAT_ERR_SUCCESS; +} + +static void dppi_channel_configuration(void) +{ + /* The SPU HW and corresponding NRFX HAL API have two different + * API's for DPPI security configuration. The defines + * NRF_SPU_HAS_OWNERSHIP and NRF_SPU_HAS_MEMORY identify which of the two API's + * are present. + * + * TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE is configurable, but + * usually defaults to 0, which results in all DPPI channels being + * non-secure. + */ + /* There is only one dppi_id */ + uint8_t dppi_id = 0; + nrf_spu_dppi_config_set(NRF_SPU, dppi_id, TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, + SPU_LOCK_CONF_LOCKED); +} + +static void cache_configuration(void) +{ + /* + * 91 has an instruction cache. + * 53 has both instruction cache and a data cache. + * + * 53's instruction cache has an nrfx driver, but 91's cache is + * not supported by nrfx at time of writing. + * + * We enable all caches available here because non-secure cannot + * configure caches. + */ +#if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK + nrfx_nvmc_icache_enable(); +#endif +#if defined(CACHE_PRESENT) // From MDK + nrf_cache_enable(NRF_CACHE); +#endif +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + /* Note that there are two different API's for SPU configuration */ + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + nrf_spu_gpio_config_set(NRF_SPU, port, secure_pins[port], SPU_LOCK_CONF_LOCKED); + } + + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal + * oscillator (LFXO) can be used. + * This configuration can be done only from secure code, as otherwise those + * register fields are not accessible. That's why it is placed here. + */ +#ifdef NRF53_SERIES + nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); + nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); +#endif /* NRF53_SERIES */ +} + +static void peripheral_configuration(void) +{ + /* Peripheral configuration */ + static const uint32_t target_peripherals[] = { + /* The following peripherals share ID: + * - FPU (FPU cannot be configured in NRF91 series, it's always NS) + * - DCNF (On 53, but not 91) + */ +#ifndef NRF91_SERIES + NRF_FPU_S_BASE, +#endif + /* The following peripherals share ID: + * - REGULATORS + * - OSCILLATORS + */ + NRF_REGULATORS_S_BASE, + /* The following peripherals share ID: + * - CLOCK + * - POWER + * - RESET (On 53, but not 91) + */ + NRF_CLOCK_S_BASE, + /* The following peripherals share ID: (referred to as Serial-Box) + * - SPIMx + * - SPISx + * - TWIMx + * - TWISx + * - UARTEx + */ + + /* When UART0 is a secure peripheral we need to leave Serial-Box 0 as Secure. + * The UART Driver will configure it as non-secure when it uninitializes. + */ +#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 0) + NRF_SPIM0_S_BASE, +#endif +#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 1) + /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */ + NRF_SPIM1_S_BASE, +#endif + NRF_SPIM2_S_BASE, + NRF_SPIM3_S_BASE, +#ifdef NRF_SPIM4 + NRF_SPIM4_S_BASE, +#endif + NRF_SAADC_S_BASE, + NRF_TIMER0_S_BASE, + NRF_TIMER1_S_BASE, + NRF_TIMER2_S_BASE, + NRF_RTC0_S_BASE, + NRF_RTC1_S_BASE, + NRF_DPPIC_S_BASE, +#ifndef PSA_API_TEST_IPC +#ifdef NRF_WDT0 + /* WDT0 is used as a secure peripheral in PSA FF tests */ + NRF_WDT0_S_BASE, +#endif +#ifdef NRF_WDT + NRF_WDT_S_BASE, +#endif +#endif /* PSA_API_TEST_IPC */ +#ifdef NRF_WDT1 + NRF_WDT1_S_BASE, +#endif + /* The following peripherals share ID: + * - COMP + * - LPCOMP + */ +#ifdef NRF_COMP + NRF_COMP_S_BASE, +#endif + NRF_EGU0_S_BASE, + NRF_EGU1_S_BASE, + NRF_EGU2_S_BASE, + NRF_EGU3_S_BASE, + NRF_EGU4_S_BASE, +#ifndef PSA_API_TEST_IPC + /* EGU5 is used as a secure peripheral in PSA FF tests */ + NRF_EGU5_S_BASE, +#endif + NRF_PWM0_S_BASE, + NRF_PWM1_S_BASE, + NRF_PWM2_S_BASE, + NRF_PWM3_S_BASE, +#ifdef NRF_PDM + NRF_PDM_S_BASE, +#endif +#ifdef NRF_PDM0 + NRF_PDM0_S_BASE, +#endif +#ifdef NRF_I2S + NRF_I2S_S_BASE, +#endif +#ifdef NRF_I2S0 + NRF_I2S0_S_BASE, +#endif + NRF_IPC_S_BASE, +#ifndef SECURE_QSPI +#ifdef NRF_QSPI + NRF_QSPI_S_BASE, +#endif +#endif +#ifdef NRF_NFCT + NRF_NFCT_S_BASE, +#endif +#ifdef NRF_MUTEX + NRF_MUTEX_S_BASE, +#endif +#ifdef NRF_QDEC0 + NRF_QDEC0_S_BASE, +#endif +#ifdef NRF_QDEC1 + NRF_QDEC1_S_BASE, +#endif +#ifdef NRF_USBD + NRF_USBD_S_BASE, +#endif +#ifdef NRF_USBREGULATOR + NRF_USBREGULATOR_S_BASE, +#endif /* NRF_USBREGULATOR */ + NRF_NVMC_S_BASE, + NRF_P0_S_BASE, +#ifdef NRF_P1 + NRF_P1_S_BASE, +#endif /*NRF_P1 */ + NRF_VMC_S_BASE + }; + + for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) { + spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); + } +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + + /* The default peripheral configuration sets most of the peripherals with split-security + * as non-secure by default. The peripherals explicitly configured as secure + * will be configured as secure later in the tfm_hal_bind_boundary function. + */ + peripheral_configuration(); + dppi_channel_configuration(); + gpio_configuration(); + cache_configuration(); + +#ifdef NRF53_SERIES + /* Enforce that the nRF5340 Network MCU is in the Non-Secure + * domain. Non-secure is the HW reset value for the network core + * so configuring this should not be necessary, but we want to + * make sure that the bootloader has not accidentally configured + * it to be secure. Additionally we lock the register to make sure + * it doesn't get changed by accident. + */ + nrf_spu_extdomain_set(NRF_SPU, 0, false, true); +#endif /* NRF53_SERIES */ + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c new file mode 100644 index 0000000000..9e053fad2a --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -0,0 +1,524 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include + +#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 +#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE +#else +#define WRITE_BUFFER_SIZE 0 +#endif + +#if !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." +#endif + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +/* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ +#define PIN_XL1 32 +#define PIN_XL2 33 + +/* During TF-M system initialization we invoke a function that comes + * from Zephyr. This function does not have a header file so we + * declare its prototype here. + */ +int nordicsemi_nrf54l_init(void); + +extern const struct memory_region_limits memory_regions; + +struct mpc_region_override { + nrf_mpc_override_config_t config; + nrf_owner_t owner_id; + uintptr_t start_address; + size_t endaddr; + uint32_t perm; + uint32_t permmask; + size_t index; +}; + +static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) +{ + nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); + nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); + nrf_mpc_override_perm_set(mpc, override->index, override->perm); + nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); +#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID + nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); +#endif + nrf_mpc_override_config_set(mpc, override->index, &override->config); +} + +/* + * Configure the override struct with reasonable defaults. This includes: + * + * Use a slave number of 0 to avoid redirecting bus transactions from + * one slave to another. + * + * Lock the override to prevent the code that follows from tampering + * with the configuration. + * + * Enable the override so it takes effect. + * + * Indicate that secdom is not enabled as this driver is not used on + * platforms with secdom. + */ +static void init_mpc_region_override(struct mpc_region_override *override) +{ + *override = (struct mpc_region_override){ + .config = + (nrf_mpc_override_config_t){ + .slave_number = 0, + .lock = true, + .enable = true, + .secdom_enable = false, + .secure_mask = true, + }, + .perm = 0, /* 0 for non-secure */ + .owner_id = 0, + }; + + override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; +} + +static nrfx_err_t rramc_configuration(void) +{ + nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); + + config.mode_write = true; + +#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 + config.preload_timeout_enable = true; + config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; +#else + config.preload_timeout_enable = false; + config.preload_timeout = 0; +#endif + + /* Don't use an event handler until it's understood whether we + * want it or not + */ + nrfx_rramc_evt_handler_t handler = NULL; + + nrfx_err_t err = nrfx_rramc_init(&config, handler); + if (err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } + + return NRFX_SUCCESS; +} + +enum tfm_plat_err_t init_debug(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* + * This SAU configuration aligns with ARM's RSS implementation of + * sau_and_idau_cfg when possible. + */ + + /* Enables SAU */ + TZ_SAU_Enable(); + + /* Configures SAU regions to be non-secure */ + + /* Note that this SAU configuration assumes that there is only one + * secure NVM partition and one non-secure NVM partition. Meaning, + * memory_regions.non_secure_partition_limit is at the end of + * NVM. + */ + + /* Configure the end of NVM, and the FICR, to be non-secure using + a single region. Note that the FICR is placed after the + non-secure NVM and before the UICR.*/ + SAU->RNR = 0; + SAU->RBAR = (memory_regions.non_secure_partition_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (NRF_UICR_S_BASE & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Leave SAU region 1 disabled until we find a use for it */ + + /* Configures veneers region to be non-secure callable */ + SAU->RNR = 2; + SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk | + SAU_RLAR_NSC_Msk; + + /* Configures SAU region 3 to cover both the end of SRAM and + * regions above it as shown in the "Example memory map" in the + * "Product Specification" */ + SAU->RNR = 3; + SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (0xFFFFFFFFul & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; +} + +enum tfm_plat_err_t nrf_mpc_init_cfg(void) +{ + /* On 54l the NRF_MPC00->REGION[]'s are fixed in HW and the + * OVERRIDE indexes (that are useful to us) start at 0 and end + * (inclusive) at 4. + * + * Note that the MPC regions configure all volatile and non-volatile memory as secure, so we + * only need to explicitly OVERRIDE the non-secure addresses to permit non-secure access. + * + * Explicitly configuring memory as secure is not necessary. + * + * The last OVERRIDE in 54L is fixed in HW and exists to prevent + * other bus masters than the KMU from accessing CRACEN protected RAM. + * + * Note that we must take care not to configure an OVERRIDE that + * affects an active bus transaction. + * + * Note that we don't configure the NSC region to be NS because + * from the MPC's perspective it is secure. NSC is only configurable from the SAU. + * + * Note that OVERRIDE[n].MASTERPORT has a reasonable reset value + * so it is left unconfigured. + * + * Note that there are two owners in 54L. KMU with owner ID 1, and everything else with + * owner ID 0. + */ + + uint32_t index = 0; + /* + * Configure the non-secure partition of the non-volatile + * memory. This MPC region is intended to cover both the + * non-secure partition in the NVM and also the FICR. The FICR + * starts after the NVM and ends just before the UICR. + */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = memory_regions.non_secure_partition_base; + override.endaddr = NRF_UICR_S_BASE; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + /* Configure the non-secure partition of the volatile memory */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = NS_DATA_START; + override.endaddr = 1 + NS_DATA_LIMIT; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + if (index > 4) { + /* Used more overrides than are available */ + tfm_core_panic(); + } + + /* Lock and disable any unused MPC overrides to prevent malicious configuration */ + while (index <= 4) { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.config.enable = false; + + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + return TFM_PLAT_ERR_SUCCESS; +} + +void peripheral_configuration(void) +{ +#if SECURE_UART1 + /* Configure TF-M's UART peripheral to be secure */ +#if NRF_SECURE_UART_INSTANCE == 00 + uint32_t uart_periph_start = tfm_peripheral_uarte00.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 20 + uint32_t uart_periph_start = tfm_peripheral_uarte20.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 21 + uint32_t uart_periph_start = tfm_peripheral_uarte21.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 22 + uint32_t uart_periph_start = tfm_peripheral_uarte22.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 30 + uint32_t uart_periph_start = tfm_peripheral_uarte30.periph_start; +#endif + spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); +#endif /* SECURE_UART1 */ + + /* Configure the CTRL-AP mailbox interface to be secure as it is used by the secure ADAC + * service */ + spu_peripheral_config_secure(NRF_CTRLAP_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure NRF_MEMCONF to be secure as it could otherwise be used to corrupt secure RAM. + */ + spu_peripheral_config_secure(NRF_MEMCONF_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure trace to be secure, as the security implications of non-secure trace are not + * understood */ + spu_peripheral_config_secure(NRF_TAD_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure these HW features, which are not in the MDK, to be + * secure, as the security implications of them being non-secure + * are not understood + */ + uint32_t base_addresses[4] = {0x50056000, 0x5008C000, 0x500E6000, 0x5010F000}; + for (int i = 0; i < 4; i++) { + spu_peripheral_config_secure(base_addresses[i], SPU_LOCK_CONF_LOCKED); + } + + /* Configure NRF_REGULATORS, and NRF_OSCILLATORS to be secure as NRF_REGULATORS.POFCON is + * needed to prevent glitches when the power supply is attacked. + * + * NB: Note that NRF_OSCILLATORS and NRF_REGULATORS have the same base address and must + * therefore have the same security configuration. + */ + spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); +} + +static void gpiote_channel_configuration(void) +{ + /* Configure GPIOTE channels to be secure */ + uint32_t secure_gpiote_channels[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + uint32_t gpiote_instances[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + NRF_GPIOTE20_S_BASE, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + NRF_GPIOTE30_S_BASE, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + /* Configure the SPU GPIOTE registers. Each GPIOTE can fire 2 interrupts for + * each available channel. If a channel is configured as secure both of the + * interrupts will only available in secure mode so a single configuration + * should suffice. + */ + for (int i = 0; i < ARRAY_SIZE(gpiote_instances) - 1; i++) { + + NRF_SPU_Type *spu_instance = spu_instance_from_peripheral_addr(gpiote_instances[i]); + for (int channel = 0; channel < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT; channel++) { + if (secure_gpiote_channels[i] & (1 << channel)) { + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, channel); + + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, channel); + } + } + } +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + for (int pin = 0; pin < 32; pin++) { + if (secure_pins[port] & (1 << pin)) { + bool enable = true; // secure + + /* + * Unfortunately, NRF_P0 is not configured by NRF_SPU00, etc. + * so it is a bit convoluted to find the SPU instance for port x. + */ + uint32_t gpio_port_addr[2] = { + NRF_P0_S_BASE, + NRF_P1_S_BASE, + }; + + NRF_SPU_Type *spu_instance = + spu_instance_from_peripheral_addr(gpio_port_addr[port]); + + nrf_spu_feature_secattr_set(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin, enable); + nrf_spu_feature_lock_enable(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin); + } + } + } + + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal + * oscillator (LFXO) can be used. + * This configuration can be done only from secure code, as otherwise those + * register fields are not accessible. That's why it is placed here. + */ + nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_GPIO); + nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_GPIO); +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + /* Peripheral configuration */ + /* Configure features to be non-secure */ + + /* + * Due to MLT-7600, many SPU HW reset values are wrong. The docs + * generally features being non-secure when coming out of HW + * reset, but the HW has a good mix of both. + * + * When configuring NRF_SPU 0 will indicate non-secure and 1 will + * indicate secure. + * + * Most of the chip should be non-secure so to simplify and be + * consistent, we memset the entire memory map of each SPU + * peripheral to 0. + * + * Just after memsetting to 0 we explicitly configure the + * peripherals that should be secure back to secure again. + */ + // TODO: Evaluate if it is safe to memset everything + // in NRF_SPU to 0. + memset(NRF_SPU00, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU10, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU20, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU30, 0, sizeof(NRF_SPU_Type)); + + peripheral_configuration(); + + /* TODO_NRF54L15: Use the nrf_spu_feature API to configure DPPI + channels according to a user-controllable config similar to + TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE. */ + + gpiote_channel_configuration(); + gpio_configuration(); + + nrf_cache_enable(NRF_ICACHE); + + nrfx_err_t nrfx_err = rramc_configuration(); + if (nrfx_err != NRFX_SUCCESS) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* SOC configuration from Zephyr's soc.c. */ + int soc_err = nordicsemi_nrf54l_init(); + if (soc_err) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_CRACEN)); + NVIC_ClearTargetState(MPC00_IRQn); + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + mpc_clear_events(); + /* MPC interrupt enabling */ + mpc_enable_interrupts(); + + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + + /* The CRACEN driver configures the NVIC for CRACEN and is + * therefore omitted here. + */ + + return TFM_PLAT_ERR_SUCCESS; +} From 4aafc4b9ac3c4aa87001d117cc082b1b1a329c3c Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Tue, 10 Jun 2025 21:41:20 +0200 Subject: [PATCH 096/133] [zep fromtree] platform: nordic_nrf: Fix missing nrfx include The secure peripherals definitions use the base address macros provided by nrfx so include the nrfx header in the file. Change-Id: Ibc6ffd4256a349d47a6ae9f163b34eac797338ad Signed-off-by: Georgios Vasilakis (cherry picked from commit 62afa0c382cb7c9e2367302e889ea1be8d19ee42) --- .../target/nordic_nrf/common/core/secure_peripherals_defs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c index 7316baa086..29a2e42610 100644 --- a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c +++ b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c @@ -21,6 +21,7 @@ #include "utilities.h" #include "region.h" #include "array.h" +#include #if TFM_PERIPHERAL_DCNF_SECURE struct platform_data_t tfm_peripheral_dcnf = { @@ -664,4 +665,4 @@ struct platform_data_t tfm_peripheral_gpiote30 = { NRF_GPIOTE30_S_BASE, NRF_GPIOTE30_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), }; -#endif \ No newline at end of file +#endif From 6ae064484b259fc9dd2796bf6183bb6eb5750502 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Wed, 16 Jul 2025 14:50:48 +0200 Subject: [PATCH 097/133] [zep fromtree] Platform: nrf54lv10a: Add support for nrf54lv10a MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for nrf54lv10a This is based upon the existing nrf54l series of targets Update startup_nrf54l and target_cfg_54l to support this Change-Id: I0dc11ca4cb39485d29bf595dacc41c3ee6383cdd Signed-off-by: Dag Erik Gjørvad (cherry picked from commit a2280a58d13229f55bd4e10ef6a7fd34c389f1d0) --- .../nordic_nrf/common/core/CMakeLists.txt | 7 +- .../common/core/secure_peripherals_defs.c | 2 +- .../nordic_nrf/common/core/startup_nrf54l.c | 297 ++++++++++++++++++ .../nordic_nrf/common/core/target_cfg_54l.c | 9 +- .../nordic_nrf/common/nrf54l/tfm_interrupts.c | 15 + .../common/nrf54lv10a/CMakeLists.txt | 52 +++ .../nordic_nrf/common/nrf54lv10a/config.cmake | 10 + .../common/nrf54lv10a/cpuarch.cmake | 24 ++ .../common/nrf54lv10a/ns/CMakeLists.txt | 29 ++ .../nrf54lv10a/partition/flash_layout.h | 162 ++++++++++ .../common/nrf54lv10a/partition/region_defs.h | 132 ++++++++ .../tests/psa_arch_tests_config.cmake | 9 + .../CMakeLists.txt | 60 ++++ .../RTE_Device.h | 44 +++ .../config.cmake | 10 + .../cpuarch.cmake | 9 + .../device_cfg.h | 32 ++ .../ns/cpuarch_ns.cmake | 12 + .../include/tfm_platform_user_memory_ranges.h | 24 ++ .../services/src/tfm_platform_system.c | 30 ++ .../tests/psa_arch_tests_config.cmake | 8 + .../tests/tfm_tests_config.cmake | 8 + .../tfm_hal_platform.c | 14 + .../tfm_peripherals_config.h | 34 ++ 24 files changed, 1029 insertions(+), 4 deletions(-) create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c create mode 100644 platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 1d37517f52..d9fec83884 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -24,7 +24,12 @@ endif() # At the time of writing there is no systematic way to identify which # NVM technology is used by the SoC from the Kconfig, so we just # hardcode this information here instead. -if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR (TFM_PLATFORM MATCHES "nordic\_nrf\/nrf54l15dk\_nrf54l1[05]\_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$")) +if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR + (NRF_SOC_VARIANT MATCHES "^nrf54lv10a?$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54l15dk_nrf54l1[05]_cpuapp") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lv10dk_nrf54lv10a?_cpuapp") OR + (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$") OR + (PSA_API_TEST_TARGET MATCHES "^nrf54lv10a?$")) # Maybe we only need to check one of these options but these # variables keep changing so we check both to be future proof set(HAS_RRAMC 1) diff --git a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c index 29a2e42610..c3ce65755b 100644 --- a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c +++ b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c @@ -93,7 +93,7 @@ struct platform_data_t tfm_peripheral_spim20 = { }; #endif -#if TFM_PERIPHERAL_SPIM22_SECURE +#if TFM_PERIPHERAL_SPIM21_SECURE struct platform_data_t tfm_peripheral_spim21 = { NRF_SPIM21_S_BASE, NRF_SPIM21_S_BASE + (sizeof(NRF_SPIM_Type) - 1), diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c index 5006175b19..12e35c0ab4 100644 --- a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c @@ -118,6 +118,302 @@ DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) #pragma GCC diagnostic ignored "-Wpedantic" #endif +#if defined(NRF54LV10A_ENGA_XXAA) + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, /* SecureFault_IRQn */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + RRAMC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + default_tfm_IRQHandler, + CM33SS_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + default_tfm_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + default_tfm_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SAADC_IRQHandler, + default_tfm_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TAMPC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + default_tfm_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, + CLOCK_POWER_IRQHandler, +}; + +#else /* NRF54L15_XXAA || NRF54L10_XXAA */ + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ /* Exceptions */ @@ -409,6 +705,7 @@ const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { GPIOTE30_1_IRQHandler, }; +#endif /* nrf54lv10a */ #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c index 9e053fad2a..b44c6b7c96 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -53,9 +53,15 @@ #define GET_SPU_INSTANCE(periph) \ ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) +#if defined(NRF54LV10A_ENGA_XXAA) +/* On nRF54LV10A XL1 and XL2 are(P1.13) and XL2(P1.14) */ +#define PIN_XL1 45 +#define PIN_XL2 46 +#else /* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ #define PIN_XL1 32 #define PIN_XL2 33 +#endif /* SOC_NRF54LV10A_ENGA */ /* During TF-M system initialization we invoke a function that comes * from Zephyr. This function does not have a header file so we @@ -411,6 +417,7 @@ static void gpio_configuration(void) } } + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal * oscillator (LFXO) can be used. * This configuration can be done only from secure code, as otherwise those @@ -480,7 +487,6 @@ enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { NVIC->ITNS[i] = 0xFFFFFFFF; } - /* Make sure that the SPU instance(s) are targeted to S state */ for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); @@ -494,7 +500,6 @@ enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) NVIC_ClearTargetState( NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); #endif - return TFM_PLAT_ERR_SUCCESS; } diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c index b3bca1bfc8..1dff3596c7 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c @@ -192,6 +192,21 @@ enum tfm_hal_status_t tfm_spim00_irq_init(void *p_pt, } #endif +#if TFM_PERIPHERAL_SPIM21_SECURE +static struct irq_t spim21_irq = {0}; + +void SPIM21_IRQHandler(void) +{ + spm_handle_interrupt(spim21_irq.p_pt, spim21_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim21_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim21_irq, TFM_SPIM21_IRQ, p_pt, p_ildi); +} +#endif + #if TFM_PERIPHERAL_SPIM22_SECURE static struct irq_t spim22_irq = {0}; diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt new file mode 100644 index 0000000000..9f470348a1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lv10a +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lv10a +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake new file mode 100644 index 0000000000..2222734d24 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake new file mode 100644 index 0000000000..3124118308 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54LV10A_ENGA_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt new file mode 100644 index 0000000000..6e8396c35d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h new file mode 100644 index 0000000000..cb0fd77770 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54LV10A Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (384 KB) + * 0x0006_0000 Protected Storage Area (16 KB) + * 0x0006_4000 Internal Trusted Storage Area (16 KB) + * 0x0006_8000 OTP / NV counters area (8 KB) + * 0x0006_A000 Non-secure image primary (504 KB) + * 0x000E_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54LV10A has 1012 kB of non volatile memory (RRAM) but the last 62kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0xF0000) /* 960 kB since the last 62kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54LV10A has 192 kB of volatile memory (SRAM) but the last 48kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00024000) /* 144 kB since the last 48kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x7E000) /* NS partition: 504 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h new file mode 100644 index 0000000000..79112d5bac --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x47C) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..5258730b3e --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54lv10a") diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt new file mode 100644 index 0000000000..b23de56b74 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt @@ -0,0 +1,60 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54lv10a nrf54lv10a) + +target_include_directories(platform_region_defs + INTERFACE + ../common/nrf54lv10a/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54lv10a/partition + services/include +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h new file mode 100644 index 0000000000..3cba0224c8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake new file mode 100644 index 0000000000..5d91d95708 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54lv10a/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake new file mode 100644 index 0000000000..9f1545d534 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54lv10a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h new file mode 100644 index 0000000000..22ddb39ce1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 0000000000..58b5f3ac47 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54lv10a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..9ff8f6c37c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..8e4ebb23a1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54lv10a/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..619f1f92cf --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c new file mode 100644 index 0000000000..5f682a8253 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h new file mode 100644 index 0000000000..82ab7ad3b3 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF54L_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ From 05fed9ab12fb98bf6fc8fe5d70c9385f53d45c04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Mon, 11 Aug 2025 12:08:49 +0200 Subject: [PATCH 098/133] [zep fromtree] platform: nrf54lm20a: Add support for nrf54lm20a MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for nrf54lm20a This is based upon the existing nrf54l series of targets Update startup_nrf54l and target_cfg_54l to support this Change-Id: I6b0c1a818a255263411b67278ab7fcef65063e60 Signed-off-by: Dag Erik Gjørvad (cherry picked from commit 94403de41cad6763f3b08cabd529da5ad748b716) --- .../nordic_nrf/common/core/CMakeLists.txt | 42 +- .../target/nordic_nrf/common/core/startup.h | 18 +- .../nordic_nrf/common/core/startup_nrf54l.c | 711 ------------------ .../common/core/startup_nrf54l_common.c | 114 +++ .../common/core/startup_nrf54l_common.h | 82 ++ .../nordic_nrf/common/core/startup_nrf54lm.c | 368 +++++++++ .../nordic_nrf/common/core/startup_nrf54lv.c | 340 +++++++++ .../nordic_nrf/common/core/startup_nrf54lx.c | 338 +++++++++ .../nordic_nrf/common/core/target_cfg_54l.c | 6 +- .../common/nrf54lm20a/CMakeLists.txt | 52 ++ .../nordic_nrf/common/nrf54lm20a/config.cmake | 10 + .../common/nrf54lm20a/cpuarch.cmake | 24 + .../common/nrf54lm20a/ns/CMakeLists.txt | 29 + .../nrf54lm20a/partition/flash_layout.h | 162 ++++ .../common/nrf54lm20a/partition/region_defs.h | 132 ++++ .../tests/psa_arch_tests_config.cmake | 9 + .../CMakeLists.txt | 60 ++ .../RTE_Device.h | 44 ++ .../config.cmake | 10 + .../cpuarch.cmake | 9 + .../device_cfg.h | 32 + .../ns/cpuarch_ns.cmake | 12 + .../include/tfm_platform_user_memory_ranges.h | 24 + .../services/src/tfm_platform_system.c | 30 + .../tests/psa_arch_tests_config.cmake | 8 + .../tests/tfm_tests_config.cmake | 8 + .../tfm_hal_platform.c | 14 + .../tfm_peripherals_config.h | 38 + 28 files changed, 2008 insertions(+), 718 deletions(-) delete mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c create mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c create mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h create mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c create mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c create mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c create mode 100644 platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index d9fec83884..74f3b5ed64 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -26,10 +26,13 @@ endif() # hardcode this information here instead. if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR (NRF_SOC_VARIANT MATCHES "^nrf54lv10a?$") OR + (NRF_SOC_VARIANT MATCHES "^nrf54lm20a?$") OR (TFM_PLATFORM MATCHES "nordic_nrf/nrf54l15dk_nrf54l1[05]_cpuapp") OR (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lv10dk_nrf54lv10a?_cpuapp") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lm20dk_nrf54lm20a?_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$") OR - (PSA_API_TEST_TARGET MATCHES "^nrf54lv10a?$")) + (PSA_API_TEST_TARGET MATCHES "^nrf54lv10a?$") OR + (PSA_API_TEST_TARGET MATCHES "^nrf54lm20a?$")) # Maybe we only need to check one of these options but these # variables keep changing so we check both to be future proof set(HAS_RRAMC 1) @@ -216,16 +219,47 @@ target_sources(tfm_spm secure_peripherals_defs.c ) +# Determine the startup file based on SOC variant +if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54l15dk_nrf54l1[05]_cpuapp")) + # nrf54l10 and nrf54l15 share the same startup file + set(startup_file "startup_nrf54lx.c") +elseif((NRF_SOC_VARIANT MATCHES "^nrf54lm20a?$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lm20dk_nrf54lm20a?_cpuapp")) + # nrf54lm20 has its own startup file + set(startup_file "startup_nrf54lm.c") +elseif((NRF_SOC_VARIANT MATCHES "^nrf54lv10a?$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lv10dk_nrf54lv10a?_cpuapp")) + # nrf54lv10 has its own startup file + set(startup_file "startup_nrf54lv.c") +else() + # Default to the original startup file for other targets + set(startup_file "startup_${target}.c") +endif() + target_sources(tfm_s PRIVATE - $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_${target}.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/${startup_file}> ) +if(HAS_RRAMC) + target_sources(tfm_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_nrf54l_common.c> + ) +endif() + if(BL2) target_sources(bl2 PRIVATE - $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_${target}.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/${startup_file}> ) + if(HAS_RRAMC) + target_sources(bl2 + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_nrf54l_common.c> + ) + endif() endif() if(NRF_APPROTECT) @@ -252,7 +286,7 @@ install(FILES ${PROJECT_BINARY_DIR}/config_nordic_nrf_spe.cmake ) install(FILES startup.c - startup_${target}.c + ${startup_file} nrfx_glue.c pal_plat_test.c pal_plat_test.h diff --git a/platform/ext/target/nordic_nrf/common/core/startup.h b/platform/ext/target/nordic_nrf/common/core/startup.h index 4b3f738b06..937b495af2 100644 --- a/platform/ext/target/nordic_nrf/common/core/startup.h +++ b/platform/ext/target/nordic_nrf/common/core/startup.h @@ -13,6 +13,9 @@ #ifndef __STARTUP_H__ #define __STARTUP_H__ +#include +#include "cmsis.h" + extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; @@ -24,8 +27,19 @@ typedef void(*VECTOR_TABLE_Type)(void); __NO_RETURN void __PROGRAM_START(void); -#define DEFAULT_IRQ_HANDLER(handler_name) \ -__NO_RETURN void __attribute__((weak, alias("default_tfm_IRQHandler"))) handler_name(void); +#ifdef __cplusplus +extern "C" { +#endif + +__NO_RETURN void default_tfm_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void handler_name(void) __attribute__((weak)); \ +void handler_name(void) { default_tfm_IRQHandler(); } __NO_RETURN void Reset_Handler(void); __NO_RETURN void HardFault_Handler(void); diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c deleted file mode 100644 index 12e35c0ab4..0000000000 --- a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c - * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c - */ - -/* - * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) - * before including cmsis.h because TF-M's linker script - * tfm_common_s.ld assumes the vector table section is called .vectors - * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) - * default to using the name .isr_vector. - */ -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) - -#include "cmsis.h" -#include "startup.h" -#include "exception_info.h" - -__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { - EXCEPTION_INFO(); - - __ASM volatile( - "BL default_irq_handler \n" - "B . \n" - ); -} - -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(SWI00_IRQHandler) -DEFAULT_IRQ_HANDLER(SWI01_IRQHandler) -DEFAULT_IRQ_HANDLER(SWI02_IRQHandler) -DEFAULT_IRQ_HANDLER(SWI03_IRQHandler) -DEFAULT_IRQ_HANDLER(AAR00_CCM00_IRQHandler) -DEFAULT_IRQ_HANDLER(ECB00_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL00_IRQHandler) -DEFAULT_IRQ_HANDLER(RRAMC_IRQHandler) -DEFAULT_IRQ_HANDLER(VPR00_IRQHandler) -DEFAULT_IRQ_HANDLER(CTRLAP_IRQHandler) -DEFAULT_IRQ_HANDLER(CM33SS_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER00_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER10_IRQHandler) -DEFAULT_IRQ_HANDLER(RTC10_IRQHandler) -DEFAULT_IRQ_HANDLER(EGU10_IRQHandler) -DEFAULT_IRQ_HANDLER(AAR10_CCM10_IRQHandler) -DEFAULT_IRQ_HANDLER(ECB10_IRQHandler) -DEFAULT_IRQ_HANDLER(RADIO_0_IRQHandler) -DEFAULT_IRQ_HANDLER(RADIO_1_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL20_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL21_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL22_IRQHandler) -DEFAULT_IRQ_HANDLER(EGU20_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER20_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER21_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER22_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER23_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER24_IRQHandler) -DEFAULT_IRQ_HANDLER(PWM20_IRQHandler) -DEFAULT_IRQ_HANDLER(PWM21_IRQHandler) -DEFAULT_IRQ_HANDLER(PWM22_IRQHandler) -DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) -DEFAULT_IRQ_HANDLER(NFCT_IRQHandler) -DEFAULT_IRQ_HANDLER(TEMP_IRQHandler) -DEFAULT_IRQ_HANDLER(GPIOTE20_1_IRQHandler) -DEFAULT_IRQ_HANDLER(TAMPC_IRQHandler) -DEFAULT_IRQ_HANDLER(I2S20_IRQHandler) -DEFAULT_IRQ_HANDLER(QDEC20_IRQHandler) -DEFAULT_IRQ_HANDLER(QDEC21_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_0_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_1_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_2_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_3_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL30_IRQHandler) -DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) -DEFAULT_IRQ_HANDLER(COMP_LPCOMP_IRQHandler) -DEFAULT_IRQ_HANDLER(WDT30_IRQHandler) -DEFAULT_IRQ_HANDLER(WDT31_IRQHandler) -DEFAULT_IRQ_HANDLER(GPIOTE30_1_IRQHandler) - -#if defined(DOMAIN_NS) || defined(BL2) -DEFAULT_IRQ_HANDLER(MPC00_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU00_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU10_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU20_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU30_IRQHandler) -DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) -#endif - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -#if defined(NRF54LV10A_ENGA_XXAA) - -const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ -/* Exceptions */ - Reset_Handler, - NMI_Handler, - HardFault_Handler, - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, - UsageFault_Handler, - SecureFault_Handler, - default_tfm_IRQHandler, /* SecureFault_IRQn */ - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SVC_Handler, - DebugMon_Handler, - default_tfm_IRQHandler, - PendSV_Handler, - SysTick_Handler, -/* Device specific interrupt handlers */ - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SWI00_IRQHandler, - SWI01_IRQHandler, - SWI02_IRQHandler, - SWI03_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU00_IRQHandler, - MPC00_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - AAR00_CCM00_IRQHandler, - ECB00_IRQHandler, - VPR00_IRQHandler, - default_tfm_IRQHandler, - RRAMC_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - CTRLAP_IRQHandler, - default_tfm_IRQHandler, - CM33SS_IRQHandler, - TIMER00_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - CRACEN_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU10_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - TIMER10_IRQHandler, - EGU10_IRQHandler, - EGU10_IRQHandler, - EGU10_IRQHandler, - default_tfm_IRQHandler, - RADIO_0_IRQHandler, - RADIO_1_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU20_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SERIAL20_IRQHandler, - SERIAL21_IRQHandler, - default_tfm_IRQHandler, - EGU20_IRQHandler, - TIMER20_IRQHandler, - TIMER21_IRQHandler, - TIMER22_IRQHandler, - TIMER23_IRQHandler, - TIMER24_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SAADC_IRQHandler, - default_tfm_IRQHandler, - TEMP_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - GPIOTE20_1_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - GRTC_0_IRQHandler, - GRTC_1_IRQHandler, - GRTC_2_IRQHandler, - GRTC_3_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - TAMPC_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU30_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SERIAL30_IRQHandler, - default_tfm_IRQHandler, - COMP_LPCOMP_IRQHandler, - default_tfm_IRQHandler, - WDT30_IRQHandler, - WDT31_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - GPIOTE30_1_IRQHandler, - CLOCK_POWER_IRQHandler, -}; - -#else /* NRF54L15_XXAA || NRF54L10_XXAA */ - -const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ -/* Exceptions */ - Reset_Handler, - NMI_Handler, - HardFault_Handler, - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, - UsageFault_Handler, - SecureFault_Handler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SVC_Handler, - DebugMon_Handler, - default_tfm_IRQHandler, - PendSV_Handler, - SysTick_Handler, -/* Device specific interrupt handlers */ - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SWI00_IRQHandler, - SWI01_IRQHandler, - SWI02_IRQHandler, - SWI03_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU00_IRQHandler, - MPC00_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - AAR00_CCM00_IRQHandler, - ECB00_IRQHandler, - CRACEN_IRQHandler, - default_tfm_IRQHandler, - SERIAL00_IRQHandler, - RRAMC_IRQHandler, - VPR00_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - CTRLAP_IRQHandler, - CM33SS_IRQHandler, - default_tfm_IRQHandler, - TIMER00_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU10_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - TIMER10_IRQHandler, - RTC10_IRQHandler, - EGU10_IRQHandler, - AAR10_CCM10_IRQHandler, - ECB10_IRQHandler, - RADIO_0_IRQHandler, - RADIO_1_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU20_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SERIAL20_IRQHandler, - SERIAL21_IRQHandler, - SERIAL22_IRQHandler, - EGU20_IRQHandler, - TIMER20_IRQHandler, - TIMER21_IRQHandler, - TIMER22_IRQHandler, - TIMER23_IRQHandler, - TIMER24_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - PWM20_IRQHandler, - PWM21_IRQHandler, - PWM22_IRQHandler, - SAADC_IRQHandler, - NFCT_IRQHandler, - TEMP_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - GPIOTE20_1_IRQHandler, - TAMPC_IRQHandler, - I2S20_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - QDEC20_IRQHandler, - QDEC21_IRQHandler, - GRTC_0_IRQHandler, - GRTC_1_IRQHandler, - GRTC_2_IRQHandler, - GRTC_3_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SPU30_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - SERIAL30_IRQHandler, - CLOCK_POWER_IRQHandler, - COMP_LPCOMP_IRQHandler, - default_tfm_IRQHandler, - WDT30_IRQHandler, - WDT31_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - default_tfm_IRQHandler, - GPIOTE30_1_IRQHandler, -}; - -#endif /* nrf54lv10a */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c new file mode 100644 index 0000000000..8301c3199d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file contains common interrupt handlers shared by all nRF54L variants. + * It should be included by the variant-specific startup files. + */ + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { + EXCEPTION_INFO(); + + __ASM volatile( + "BL default_irq_handler \n" + "B . \n" + ); +} + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(SWI00_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI01_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI02_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI03_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR00_CCM00_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB00_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL00_IRQHandler) +DEFAULT_IRQ_HANDLER(RRAMC_IRQHandler) +DEFAULT_IRQ_HANDLER(VPR00_IRQHandler) +DEFAULT_IRQ_HANDLER(CTRLAP_IRQHandler) +DEFAULT_IRQ_HANDLER(CM33SS_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER00_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER10_IRQHandler) +DEFAULT_IRQ_HANDLER(RTC10_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU10_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR10_CCM10_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB10_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_0_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_1_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL20_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL21_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL22_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER21_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER22_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER23_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER24_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM21_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM22_IRQHandler) +DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) +DEFAULT_IRQ_HANDLER(NFCT_IRQHandler) +DEFAULT_IRQ_HANDLER(TEMP_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE20_1_IRQHandler) +DEFAULT_IRQ_HANDLER(TAMPC_IRQHandler) +DEFAULT_IRQ_HANDLER(I2S20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC21_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_0_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_1_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_2_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_3_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL30_IRQHandler) +DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) +DEFAULT_IRQ_HANDLER(COMP_LPCOMP_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT30_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT31_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE30_1_IRQHandler) + +#if defined(DOMAIN_NS) || defined(BL2) +DEFAULT_IRQ_HANDLER(MPC00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU10_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU20_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU30_IRQHandler) +DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h new file mode 100644 index 0000000000..5266d34a9a --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h @@ -0,0 +1,82 @@ +/* + * Prototypes for common nRF54L interrupt handlers used in vector tables. + * These are defined as weak defaults in startup_nrf54l_common.c. + */ + +#ifndef STARTUP_NRF54L_COMMON_H +#define STARTUP_NRF54L_COMMON_H + +#include "startup.h" + +/* Core/system exceptions */ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SecureFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +/* Shared nRF54L IRQ handlers */ +void SWI00_IRQHandler(void); +void SWI01_IRQHandler(void); +void SWI02_IRQHandler(void); +void SWI03_IRQHandler(void); +void AAR00_CCM00_IRQHandler(void); +void ECB00_IRQHandler(void); +void SERIAL00_IRQHandler(void); +void RRAMC_IRQHandler(void); +void VPR00_IRQHandler(void); +void CTRLAP_IRQHandler(void); +void CM33SS_IRQHandler(void); +void TIMER00_IRQHandler(void); +void TIMER10_IRQHandler(void); +void RTC10_IRQHandler(void); +void EGU10_IRQHandler(void); +void AAR10_CCM10_IRQHandler(void); +void ECB10_IRQHandler(void); +void RADIO_0_IRQHandler(void); +void RADIO_1_IRQHandler(void); +void SERIAL20_IRQHandler(void); +void SERIAL21_IRQHandler(void); +void SERIAL22_IRQHandler(void); +void EGU20_IRQHandler(void); +void TIMER20_IRQHandler(void); +void TIMER21_IRQHandler(void); +void TIMER22_IRQHandler(void); +void TIMER23_IRQHandler(void); +void TIMER24_IRQHandler(void); +void PWM20_IRQHandler(void); +void PWM21_IRQHandler(void); +void PWM22_IRQHandler(void); +void SAADC_IRQHandler(void); +void NFCT_IRQHandler(void); +void TEMP_IRQHandler(void); +void GPIOTE20_1_IRQHandler(void); +void TAMPC_IRQHandler(void); +void I2S20_IRQHandler(void); +void QDEC20_IRQHandler(void); +void QDEC21_IRQHandler(void); +void GRTC_0_IRQHandler(void); +void GRTC_1_IRQHandler(void); +void GRTC_2_IRQHandler(void); +void GRTC_3_IRQHandler(void); +void SERIAL30_IRQHandler(void); +void CLOCK_POWER_IRQHandler(void); +void COMP_LPCOMP_IRQHandler(void); +void WDT30_IRQHandler(void); +void WDT31_IRQHandler(void); +void GPIOTE30_1_IRQHandler(void); + +/* Conditionally defaulted in common file, but declare always for visibility */ +void MPC00_IRQHandler(void); +void SPU00_IRQHandler(void); +void SPU10_IRQHandler(void); +void SPU20_IRQHandler(void); +void SPU30_IRQHandler(void); +void CRACEN_IRQHandler(void); + +#endif /* STARTUP_NRF54L_COMMON_H */ diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c new file mode 100644 index 0000000000..12eb696e5d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +/* Declarations for common nRF54L interrupt handlers (built separately) */ +#include "startup_nrf54l_common.h" + +/* NRF54LM20A-specific interrupt handlers */ +DEFAULT_IRQ_HANDLER(EGU00_IRQHandler) +DEFAULT_IRQ_HANDLER(USBHS_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM21_IRQHandler) +DEFAULT_IRQ_HANDLER(TDM_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL23_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL24_IRQHandler) +DEFAULT_IRQ_HANDLER(VREGUSB_IRQHandler) + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + /* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, /* SecureFault_IRQn */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, + /* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + RRAMC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + default_tfm_IRQHandler, + CM33SS_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + default_tfm_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + default_tfm_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SAADC_IRQHandler, + default_tfm_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + QDEC20_IRQHandler, + QDEC21_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TDM_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL23_IRQHandler, + SERIAL24_IRQHandler, + TAMPC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + default_tfm_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, + CLOCK_POWER_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + VREGUSB_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c new file mode 100644 index 0000000000..e975ff56e8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +/* Declarations for common nRF54L interrupt handlers (built separately) */ +#include "startup_nrf54l_common.h" + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + /* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, /* SecureFault_IRQn */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, + /* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + RRAMC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + default_tfm_IRQHandler, + CM33SS_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + default_tfm_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + default_tfm_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SAADC_IRQHandler, + default_tfm_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TAMPC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + default_tfm_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, + CLOCK_POWER_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c new file mode 100644 index 0000000000..e790a29400 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +/* Declarations for common nRF54L interrupt handlers (built separately) */ +#include "startup_nrf54l_common.h" + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + /* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, + /* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + SERIAL00_IRQHandler, + RRAMC_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + CM33SS_IRQHandler, + default_tfm_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + RTC10_IRQHandler, + EGU10_IRQHandler, + AAR10_CCM10_IRQHandler, + ECB10_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + SERIAL22_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + PWM20_IRQHandler, + PWM21_IRQHandler, + PWM22_IRQHandler, + SAADC_IRQHandler, + NFCT_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + TAMPC_IRQHandler, + I2S20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + QDEC20_IRQHandler, + QDEC21_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + CLOCK_POWER_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c index b44c6b7c96..be19914c21 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -57,11 +57,15 @@ /* On nRF54LV10A XL1 and XL2 are(P1.13) and XL2(P1.14) */ #define PIN_XL1 45 #define PIN_XL2 46 +#elif defined(NRF54LM20A_ENGA_XXAA) +/* On nRF54LM20A XL1 and XL2 are(P1.13) and XL2(P1.14) */ +#define PIN_XL1 45 +#define PIN_XL2 46 #else /* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ #define PIN_XL1 32 #define PIN_XL2 33 -#endif /* SOC_NRF54LV10A_ENGA */ +#endif /* SOC_NRF54LV10A_ENGA || SOC_NRF54LM20A_ENGA */ /* During TF-M system initialization we invoke a function that comes * from Zephyr. This function does not have a header file so we diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt new file mode 100644 index 0000000000..485f1859b7 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lm20a +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lm20a +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake new file mode 100644 index 0000000000..2222734d24 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake new file mode 100644 index 0000000000..67d963b80c --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54LM20A_ENGA_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt new file mode 100644 index 0000000000..6e8396c35d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h new file mode 100644 index 0000000000..b80fa758c1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54LM20A Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (512 KB) + * 0x0008_0000 Protected Storage Area (16 KB) + * 0x0008_4000 Internal Trusted Storage Area (16 KB) + * 0x0008_8000 OTP / NV counters area (8 KB) + * 0x0008_A000 Non-secure image primary (1464 KB) + * 0x001F_2000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54LM20A has 2036 kB of non volatile memory (RRAM) but the last 96kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0x1E5000) /* 1940 kB since the last 96kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54LM20A has 512 kB of volatile memory (SRAM) but the last 96kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00068000) /* 416 kB since the last 96kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x17D000) /* NS partition: 1524 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h new file mode 100644 index 0000000000..79112d5bac --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x47C) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..f4cc1937f4 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54lm20a") diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt new file mode 100644 index 0000000000..9e87f0eac1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt @@ -0,0 +1,60 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54lm20a nrf54lm20a) + +target_include_directories(platform_region_defs + BEFORE INTERFACE + ../common/nrf54lm20a/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54lm20a/partition + services/include +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h new file mode 100644 index 0000000000..3cba0224c8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake new file mode 100644 index 0000000000..e3c56921db --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54lm20a/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake new file mode 100644 index 0000000000..721521cc08 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54lm20a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h new file mode 100644 index 0000000000..22ddb39ce1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 0000000000..23b1f06587 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54lm20a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..9ff8f6c37c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..6af19cd935 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54lm20a/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..619f1f92cf --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c new file mode 100644 index 0000000000..5f682a8253 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h new file mode 100644 index 0000000000..2fce36f8de --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + + +/* Explicitly configure UART20 as non-secure for NS world */ +#define TFM_PERIPHERAL_UARTE20_SECURE 0 + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF54L_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ From 100fe8d57a1727965c3d17d92739694e6d27597b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Tue, 12 Aug 2025 15:33:46 +0200 Subject: [PATCH 099/133] [zep fromtree] platform: lv10a: update uart configuration for lv10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit lv10 should use uart20 as the secure uart. Update configurations to reflect this Change-Id: Ic4d5bce62fc810dc5d3f313ff1a34d456c4d5ccd Signed-off-by: Dag Erik Gjørvad (cherry picked from commit 01a4fa46d6b9926849da847ba2c37ed17caded43) --- platform/ext/target/nordic_nrf/common/nrf54l/config.cmake | 4 ++-- .../nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake index e35ee17ebc..8fae67243e 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake @@ -8,7 +8,7 @@ include(${PLATFORM_PATH}/common/core/config.cmake) -set(SECURE_UART30 ON CACHE BOOL "Enable secure UART" FORCE) +set(SECURE_UART20 ON CACHE BOOL "Enable secure UART" FORCE) set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) -set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) +set(NRF_SECURE_UART_INSTANCE 20 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h index 82ab7ad3b3..5bd47a935c 100644 --- a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h @@ -13,7 +13,9 @@ extern "C" { #endif #ifdef SECURE_UART1 -#if NRF_SECURE_UART_INSTANCE == 30 +#if NRF_SECURE_UART_INSTANCE == 20 +#define TFM_PERIPHERAL_UARTE20_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 30 #define TFM_PERIPHERAL_UARTE30_SECURE 1 #endif #endif From b45d57f4e51ef997aba9e635d27d12ed40765157 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Tue, 19 Aug 2025 14:19:06 +0200 Subject: [PATCH 100/133] [zep fromtree] platform: nrf54l: remove forced uart settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART should not be force set for 54l devices. This to support user selecting which UARTs are secure. Change-Id: Ic4fffe748476b85e2e6758d92d687ec36b179e3e Signed-off-by: Dag Erik Gjørvad (cherry picked from commit b9ef3b259b19f69eb2a6e7b72f6f9bb03420c9c3) --- platform/ext/target/nordic_nrf/common/nrf54l/config.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake index 8fae67243e..eb21fdb1f9 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake @@ -8,7 +8,7 @@ include(${PLATFORM_PATH}/common/core/config.cmake) -set(SECURE_UART20 ON CACHE BOOL "Enable secure UART" FORCE) +set(SECURE_UART20 ON CACHE BOOL "Enable secure UART") set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) -set(NRF_SECURE_UART_INSTANCE 20 CACHE STRING "The UART instance number to use for secure UART" FORCE) +set(NRF_SECURE_UART_INSTANCE 20 CACHE STRING "The UART instance number to use for secure UART") From f8a6e7689de4e0818686a4cb16dff0ad5b598633 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Thu, 25 Sep 2025 16:34:20 +0200 Subject: [PATCH 101/133] [zep fromtree] platform: nordic_nrf: update nRF54LM20A flash layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update nRF54LM20A flash layout to correctly set ns partition size. Change-Id: I66aa51d2a1be6a16d5dfcb746a5e94f1547232a8 Signed-off-by: Dag Erik Gjørvad (cherry picked from commit c60128e90b1a405d46f2293c6c9a9345380b4dc5) --- .../nordic_nrf/common/nrf54lm20a/partition/flash_layout.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h index b80fa758c1..65ab9951ca 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h @@ -27,7 +27,7 @@ * 0x0008_0000 Protected Storage Area (16 KB) * 0x0008_4000 Internal Trusted Storage Area (16 KB) * 0x0008_8000 OTP / NV counters area (8 KB) - * 0x0008_A000 Non-secure image primary (1464 KB) + * 0x0008_A000 Non-secure image primary (1356 KB) * 0x001F_2000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, * otherwise unused (32 KB) */ @@ -54,8 +54,8 @@ #define SRAM_BASE_ADDRESS (0x20000000) #define TOTAL_RAM_SIZE (0x00068000) /* 416 kB since the last 96kB are reserved for FLPR */ -#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ -#define FLASH_NS_PARTITION_SIZE (0x17D000) /* NS partition: 1524 kB*/ +#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x153000) /* NS partition: 1356 kB*/ #define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS #define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS From db5a696a10b1fbe6e83181744733c779eac71178 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Fri, 26 Sep 2025 12:42:35 +0200 Subject: [PATCH 102/133] [zep fromtree] platform: nordic_nrf: Fix failing builds for 54L series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 54L series was failing to build due to two different issues. First was incorrectly selected SECURE_UART for some devices. Updated so both uart20 and uart30 can be selected. Secondly was missing SHARED_BOOT_MEASURMENT_BASE. it is not used so set to 0 for relevant devices. Change-Id: I4c72bd5300eb58fd2bf95976f9f8cb9fd4d76b41 Signed-off-by: Dag Erik Gjørvad (cherry picked from commit c58c975d5ffc9839ab3662f5a1d19e5daaf4ef6c) --- .../target/nordic_nrf/common/core/CMakeLists.txt | 2 ++ .../target/nordic_nrf/common/core/target_cfg_54l.c | 13 ++++++++----- .../target/nordic_nrf/common/nrf54l/config.cmake | 2 -- .../target/nordic_nrf/common/nrf54l10/config.cmake | 1 + .../common/nrf54l10/partition/region_defs.h | 5 +++++ .../target/nordic_nrf/common/nrf54l15/config.cmake | 1 + .../common/nrf54l15/partition/region_defs.h | 5 +++++ .../nordic_nrf/common/nrf54lm20a/config.cmake | 2 ++ .../common/nrf54lm20a/partition/region_defs.h | 7 ++++++- .../nordic_nrf/common/nrf54lv10a/config.cmake | 1 + .../common/nrf54lv10a/partition/region_defs.h | 5 +++++ .../tfm_peripherals_config.h | 4 +++- .../tfm_peripherals_config.h | 4 +++- 13 files changed, 42 insertions(+), 10 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 74f3b5ed64..31b0e3b60a 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -144,7 +144,9 @@ if(TFM_SPM_LOG_RAW_ENABLED) cmsis_drivers/Driver_USART.c ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_uarte.c ) +endif() +if(TFM_SPM_LOG_RAW_ENABLED OR SECURE_UART1) target_compile_definitions(platform_s PUBLIC NRF_SECURE_UART_INSTANCE=${NRF_SECURE_UART_INSTANCE} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c index be19914c21..1f148e044a 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -288,16 +288,19 @@ void peripheral_configuration(void) { #if SECURE_UART1 /* Configure TF-M's UART peripheral to be secure */ + uint32_t uart_periph_start; #if NRF_SECURE_UART_INSTANCE == 00 - uint32_t uart_periph_start = tfm_peripheral_uarte00.periph_start; + uart_periph_start = tfm_peripheral_uarte00.periph_start; #elif NRF_SECURE_UART_INSTANCE == 20 - uint32_t uart_periph_start = tfm_peripheral_uarte20.periph_start; + uart_periph_start = tfm_peripheral_uarte20.periph_start; #elif NRF_SECURE_UART_INSTANCE == 21 - uint32_t uart_periph_start = tfm_peripheral_uarte21.periph_start; + uart_periph_start = tfm_peripheral_uarte21.periph_start; #elif NRF_SECURE_UART_INSTANCE == 22 - uint32_t uart_periph_start = tfm_peripheral_uarte22.periph_start; + uart_periph_start = tfm_peripheral_uarte22.periph_start; #elif NRF_SECURE_UART_INSTANCE == 30 - uint32_t uart_periph_start = tfm_peripheral_uarte30.periph_start; + uart_periph_start = tfm_peripheral_uarte30.periph_start; +#else +#error "Unsupported NRF_SECURE_UART_INSTANCE for nrf54l series. Supported instances: 00, 20, 21, 22, 30" #endif spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); #endif /* SECURE_UART1 */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake index eb21fdb1f9..12281f1ff6 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake @@ -8,7 +8,5 @@ include(${PLATFORM_PATH}/common/core/config.cmake) -set(SECURE_UART20 ON CACHE BOOL "Enable secure UART") set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) -set(NRF_SECURE_UART_INSTANCE 20 CACHE STRING "The UART instance number to use for secure UART") diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake index 2222734d24..da98d7efda 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake @@ -8,3 +8,4 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h index 79112d5bac..a9ae3c4500 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h @@ -97,7 +97,12 @@ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) /* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #ifdef PSA_API_TEST_IPC /* Firmware Framework test suites */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake index 2222734d24..1bc002115f 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake @@ -8,3 +8,4 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) +sset(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h index 79112d5bac..a9ae3c4500 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h @@ -97,7 +97,12 @@ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) /* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #ifdef PSA_API_TEST_IPC /* Firmware Framework test suites */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake index 2222734d24..ebc2bbbb8c 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake @@ -8,3 +8,5 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) +# Override UART instance for nRF54LM20A - it uses UART30, not UART20 +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h index 79112d5bac..51a8a30e78 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h @@ -54,7 +54,7 @@ #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) /* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ -#define S_CODE_VECTOR_TABLE_SIZE (0x47C) +#define S_CODE_VECTOR_TABLE_SIZE (0x4D0) #if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 /* If this image is placed at the beginning of flash make sure we @@ -97,7 +97,12 @@ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) /* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #ifdef PSA_API_TEST_IPC /* Firmware Framework test suites */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake index 2222734d24..088d9a5d95 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake @@ -8,3 +8,4 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) +set(NRF_SECURE_UART_INSTANCE 20 CACHE STRING "The UART instance number to use for secure UART" FORCE) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h index 79112d5bac..a9ae3c4500 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h @@ -97,7 +97,12 @@ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) /* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #ifdef PSA_API_TEST_IPC /* Firmware Framework test suites */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h index 6159c19f4b..1059d56478 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h @@ -13,7 +13,9 @@ extern "C" { #endif #ifdef SECURE_UART1 -#if NRF_SECURE_UART_INSTANCE == 30 +#if NRF_SECURE_UART_INSTANCE == 20 +#define TFM_PERIPHERAL_UARTE20_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 30 #define TFM_PERIPHERAL_UARTE30_SECURE 1 #endif #endif diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h index 6159c19f4b..1059d56478 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h @@ -13,7 +13,9 @@ extern "C" { #endif #ifdef SECURE_UART1 -#if NRF_SECURE_UART_INSTANCE == 30 +#if NRF_SECURE_UART_INSTANCE == 20 +#define TFM_PERIPHERAL_UARTE20_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 30 #define TFM_PERIPHERAL_UARTE30_SECURE 1 #endif #endif From 6f4f73636dc3631d7183c3953ca72c9b35cb458b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Fri, 10 Oct 2025 13:25:53 +0200 Subject: [PATCH 103/133] [zep fromtree] platform: nordic_nrf: Remove excess S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sset changed to set. Change-Id: Id308ce67e1d49601dda6987f2bac5db909d6554f Signed-off-by: Dag Erik Gjørvad (cherry picked from commit e280ac1bcaee50afa407d7b16671296b0f1e968c) --- platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake index 1bc002115f..da98d7efda 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake @@ -8,4 +8,4 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) -sset(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) From 19c974e2950fb2711a38e20c6539bf35a25ccc9a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Mon, 13 Oct 2025 15:07:33 +0200 Subject: [PATCH 104/133] [zep fromtree] platform: nordic_nrf: Add memory service header for nRF54LV10A/M20A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a continuation of "Add memory service header in common folder" Adds a copy of the memory_services_range to the common folder to allow Zephyr builds. A proper solution to this is planned later to avoid the duplication. Change-Id: I303c2a24caa3149883ad4ddb592b3ba1be2a61d2 Signed-off-by: Dag Erik Gjørvad (cherry picked from commit 2f86a3d4b4d389a5e8c7abbd70541e1718453c62) --- .../common/nrf54lm20a/CMakeLists.txt | 7 ++++++ .../tfm_platform_user_memory_ranges.h | 24 +++++++++++++++++++ .../common/nrf54lv10a/CMakeLists.txt | 7 ++++++ .../tfm_platform_user_memory_ranges.h | 24 +++++++++++++++++++ 4 files changed, 62 insertions(+) create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt index 485f1859b7..118ebd0882 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt @@ -19,6 +19,13 @@ target_include_directories(platform_s ../nrf54l ) +if(NOT NRF_DIR) + target_include_directories(platform_s + PUBLIC + memory_service_ranges +) +endif() + target_sources(platform_s PRIVATE ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt index 9f470348a1..b189498b9e 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt @@ -19,6 +19,13 @@ target_include_directories(platform_s ../nrf54l ) +if(NOT NRF_DIR) + target_include_directories(platform_s + PUBLIC + memory_service_ranges +) +endif() + target_sources(platform_s PRIVATE ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ From ac69e1495935125b6f65dd8f23f948f8d93ef780 Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Thu, 23 Oct 2025 13:23:14 +0200 Subject: [PATCH 105/133] [zep fromtree] platform: nordic: Update nrf-pinctrl.h header Update the header nrf-pinctrl.h header to match the latest one from Zephyr. This file was copied and modified before in order to inlcude two relevant helper macros. I created another header called tfm-pinctrl.h which includes these two macros and the header nrf-pinctl.h. This makes it easier to understand that this is a custom header and also allows to copy the nrf-pinctrl.h as is. Change-Id: I3de6a0ac51de5a9b98f9897837c361be94e1ae29 Signed-off-by: Georgios Vasilakis (cherry picked from commit 784c04f8ef16ecd43cd132a5f0738d5ed654d506) --- .../common/core/cmsis_drivers/Driver_USART.c | 2 +- .../common/core/common/nrf-pinctrl.h | 309 ++++++++++++++++-- .../common/core/common/tfm-pinctrl.h | 34 ++ .../nrf5340dk_nrf5340_cpuapp/RTE_Device.h | 2 +- .../nordic_nrf/nrf9160dk_nrf9160/RTE_Device.h | 2 +- .../nordic_nrf/nrf9161dk_nrf9161/RTE_Device.h | 2 +- 6 files changed, 317 insertions(+), 34 deletions(-) create mode 100644 platform/ext/target/nordic_nrf/common/core/common/tfm-pinctrl.h diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c index db99c0bb73..f1156daff6 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #ifndef ARRAY_SIZE #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) diff --git a/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h b/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h index da11111793..4c7f1d3145 100644 --- a/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h +++ b/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h @@ -3,33 +3,57 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef NRF_INCLUDE_NRF_PINCTRL_H -#define NRF_INCLUDE_NRF_PINCTRL_H +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ /* * The whole nRF pin configuration information is encoded in a 32-bit bitfield * organized as follows: * - * - 31..16: Pin function. - * - 15: Reserved. - * - 14: Pin inversion mode. - * - 13: Pin low power mode. - * - 12..9: Pin output drive configuration. - * - 8..7: Pin pull configuration. - * - 6..0: Pin number (combination of port and pin). + * - 31..24: Pin function. + * - 19-23: Reserved. + * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only) + * - 17: Clockpin enable. + * - 16: Pin inversion mode. + * - 15: Pin low power mode. + * - 14..11: Pin output drive configuration. + * - 10..9: Pin pull configuration. + * - 8..0: Pin number (combination of port and pin). */ -/* NOTE: Keep in sync with Zephyr's nrf-pinctrl.h */ - /** * @name nRF pin configuration bit field positions and masks. * @{ */ /** Position of the function field. */ -#define NRF_FUN_POS 17U +#define NRF_FUN_POS 24U /** Mask for the function field. */ -#define NRF_FUN_MSK 0x7FFFU +#define NRF_FUN_MSK 0xFFU +/** Position of the GPD FAST ACTIVE1 */ +#define NRF_GPD_FAST_ACTIVE1_POS 18U +/** Mask for the GPD FAST ACTIVE1 */ +#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U +/** Position of the clockpin enable field. */ +#define NRF_CLOCKPIN_ENABLE_POS 17U +/** Mask for the clockpin enable field. */ +#define NRF_CLOCKPIN_ENABLE_MSK 0x1U +/** Position of the invert field. */ +#define NRF_INVERT_POS 16U +/** Mask for the invert field. */ +#define NRF_INVERT_MSK 0x1U +/** Position of the low power field. */ +#define NRF_LP_POS 15U +/** Mask for the low power field. */ +#define NRF_LP_MSK 0x1U +/** Position of the drive configuration field. */ +#define NRF_DRIVE_POS 11U +/** Mask for the drive configuration field. */ +#define NRF_DRIVE_MSK 0xFU +/** Position of the pull configuration field. */ +#define NRF_PULL_POS 9U +/** Mask for the pull configuration field. */ +#define NRF_PULL_MSK 0x3U /** Position of the pin field. */ #define NRF_PIN_POS 0U /** Mask for the pin field. */ @@ -50,6 +74,246 @@ #define NRF_FUN_UART_RTS 2U /** UART CTS */ #define NRF_FUN_UART_CTS 3U +/** SPI master SCK */ +#define NRF_FUN_SPIM_SCK 4U +/** SPI master MOSI */ +#define NRF_FUN_SPIM_MOSI 5U +/** SPI master MISO */ +#define NRF_FUN_SPIM_MISO 6U +/** SPI slave SCK */ +#define NRF_FUN_SPIS_SCK 7U +/** SPI slave MOSI */ +#define NRF_FUN_SPIS_MOSI 8U +/** SPI slave MISO */ +#define NRF_FUN_SPIS_MISO 9U +/** SPI slave CSN */ +#define NRF_FUN_SPIS_CSN 10U +/** TWI master SCL */ +#define NRF_FUN_TWIM_SCL 11U +/** TWI master SDA */ +#define NRF_FUN_TWIM_SDA 12U +/** I2S SCK in master mode */ +#define NRF_FUN_I2S_SCK_M 13U +/** I2S SCK in slave mode */ +#define NRF_FUN_I2S_SCK_S 14U +/** I2S LRCK in master mode */ +#define NRF_FUN_I2S_LRCK_M 15U +/** I2S LRCK in slave mode */ +#define NRF_FUN_I2S_LRCK_S 16U +/** I2S SDIN */ +#define NRF_FUN_I2S_SDIN 17U +/** I2S SDOUT */ +#define NRF_FUN_I2S_SDOUT 18U +/** I2S MCK */ +#define NRF_FUN_I2S_MCK 19U +/** PDM CLK */ +#define NRF_FUN_PDM_CLK 20U +/** PDM DIN */ +#define NRF_FUN_PDM_DIN 21U +/** PWM OUT0 */ +#define NRF_FUN_PWM_OUT0 22U +/** PWM OUT1 */ +#define NRF_FUN_PWM_OUT1 23U +/** PWM OUT2 */ +#define NRF_FUN_PWM_OUT2 24U +/** PWM OUT3 */ +#define NRF_FUN_PWM_OUT3 25U +/** QDEC A */ +#define NRF_FUN_QDEC_A 26U +/** QDEC B */ +#define NRF_FUN_QDEC_B 27U +/** QDEC LED */ +#define NRF_FUN_QDEC_LED 28U +/** QSPI SCK */ +#define NRF_FUN_QSPI_SCK 29U +/** QSPI CSN */ +#define NRF_FUN_QSPI_CSN 30U +/** QSPI IO0 */ +#define NRF_FUN_QSPI_IO0 31U +/** QSPI IO1 */ +#define NRF_FUN_QSPI_IO1 32U +/** QSPI IO2 */ +#define NRF_FUN_QSPI_IO2 33U +/** QSPI IO3 */ +#define NRF_FUN_QSPI_IO3 34U +/** EXMIF CK */ +#define NRF_FUN_EXMIF_CK 35U +/** EXMIF DQ0 */ +#define NRF_FUN_EXMIF_DQ0 36U +/** EXMIF DQ1 */ +#define NRF_FUN_EXMIF_DQ1 37U +/** EXMIF DQ2 */ +#define NRF_FUN_EXMIF_DQ2 38U +/** EXMIF DQ3 */ +#define NRF_FUN_EXMIF_DQ3 39U +/** EXMIF DQ4 */ +#define NRF_FUN_EXMIF_DQ4 40U +/** EXMIF DQ5 */ +#define NRF_FUN_EXMIF_DQ5 41U +/** EXMIF DQ6 */ +#define NRF_FUN_EXMIF_DQ6 42U +/** EXMIF DQ7 */ +#define NRF_FUN_EXMIF_DQ7 43U +/** EXMIF CS0 */ +#define NRF_FUN_EXMIF_CS0 44U +/** EXMIF CS1 */ +#define NRF_FUN_EXMIF_CS1 45U +/** CAN TX */ +#define NRF_FUN_CAN_TX 46U +/** CAN RX */ +#define NRF_FUN_CAN_RX 47U +/** TWIS SCL */ +#define NRF_FUN_TWIS_SCL 48U +/** TWIS SDA */ +#define NRF_FUN_TWIS_SDA 49U +/** EXMIF RWDS */ +#define NRF_FUN_EXMIF_RWDS 50U +/** GRTC fast clock output */ +#define NRF_FUN_GRTC_CLKOUT_FAST 55U +/** GRTC slow clock output */ +#define NRF_FUN_GRTC_CLKOUT_32K 56U +/** SDP_MSPI clock pin */ +#define NRF_FUN_SDP_MSPI_SCK 57U +/** SDP_MSPI data pin 0 */ +#define NRF_FUN_SDP_MSPI_DQ0 58U +/** SDP_MSPI data pin 1 */ +#define NRF_FUN_SDP_MSPI_DQ1 59U +/** SDP_MSPI data pin 2 */ +#define NRF_FUN_SDP_MSPI_DQ2 60U +/** SDP_MSPI data pin 3 */ +#define NRF_FUN_SDP_MSPI_DQ3 61U +/** SDP_MSPI data pin 4 */ +#define NRF_FUN_SDP_MSPI_DQ4 62U +/** SDP_MSPI data pin 5 */ +#define NRF_FUN_SDP_MSPI_DQ5 63U +/** SDP_MSPI data pin 6 */ +#define NRF_FUN_SDP_MSPI_DQ6 64U +/** SDP_MSPI data pin 7 */ +#define NRF_FUN_SDP_MSPI_DQ7 65U +/** SDP_MSPI chip select 0 */ +#define NRF_FUN_SDP_MSPI_CS0 66U +/** SDP_MSPI chip select 1 */ +#define NRF_FUN_SDP_MSPI_CS1 67U +/** SDP_MSPI chip select 2 */ +#define NRF_FUN_SDP_MSPI_CS2 68U +/** SDP_MSPI chip select 3 */ +#define NRF_FUN_SDP_MSPI_CS3 69U +/** SDP_MSPI chip select 4 */ +#define NRF_FUN_SDP_MSPI_CS4 70U +/** High-Performance Framework MSPI clock pin */ +#define NRF_FUN_HPF_MSPI_SCK NRF_FUN_SDP_MSPI_SCK +/** High-Performance Framework MSPI data pin 0 */ +#define NRF_FUN_HPF_MSPI_DQ0 NRF_FUN_SDP_MSPI_DQ0 +/** High-Performance Framework MSPI data pin 1 */ +#define NRF_FUN_HPF_MSPI_DQ1 NRF_FUN_SDP_MSPI_DQ1 +/** High-Performance Framework MSPI data pin 2 */ +#define NRF_FUN_HPF_MSPI_DQ2 NRF_FUN_SDP_MSPI_DQ2 +/** High-Performance Framework MSPI data pin 3 */ +#define NRF_FUN_HPF_MSPI_DQ3 NRF_FUN_SDP_MSPI_DQ3 +/** High-Performance Framework MSPI data pin 4 */ +#define NRF_FUN_HPF_MSPI_DQ4 NRF_FUN_SDP_MSPI_DQ4 +/** High-Performance Framework MSPI data pin 5 */ +#define NRF_FUN_HPF_MSPI_DQ5 NRF_FUN_SDP_MSPI_DQ5 +/** High-Performance Framework MSPI data pin 6 */ +#define NRF_FUN_HPF_MSPI_DQ6 NRF_FUN_SDP_MSPI_DQ6 +/** High-Performance Framework MSPI data pin 7 */ +#define NRF_FUN_HPF_MSPI_DQ7 NRF_FUN_SDP_MSPI_DQ7 +/** High-Performance Framework MSPI chip select pin 0 */ +#define NRF_FUN_HPF_MSPI_CS0 NRF_FUN_SDP_MSPI_CS0 +/** High-Performance Framework MSPI chip select pin 1 */ +#define NRF_FUN_HPF_MSPI_CS1 NRF_FUN_SDP_MSPI_CS1 +/** High-Performance Framework MSPI chip select pin 2 */ +#define NRF_FUN_HPF_MSPI_CS2 NRF_FUN_SDP_MSPI_CS2 +/** High-Performance Framework MSPI chip select pin 3 */ +#define NRF_FUN_HPF_MSPI_CS3 NRF_FUN_SDP_MSPI_CS3 +/** High-Performance Framework MSPI chip select pin 4 */ +#define NRF_FUN_HPF_MSPI_CS4 NRF_FUN_SDP_MSPI_CS4 +/** TDM SCK in master mode */ +#define NRF_FUN_TDM_SCK_M 71U +/** TDM SCK in slave mode */ +#define NRF_FUN_TDM_SCK_S 72U +/** TDM LRCK in master mode */ +#define NRF_FUN_TDM_FSYNC_M 73U +/** TDM LRCK in slave mode */ +#define NRF_FUN_TDM_FSYNC_S 74U +/** TDM SDIN */ +#define NRF_FUN_TDM_SDIN 75U +/** TDM SDOUT */ +#define NRF_FUN_TDM_SDOUT 76U +/** TDM MCK */ +#define NRF_FUN_TDM_MCK 77U +/** SPI master CSN */ +#define NRF_FUN_SPIM_CSN 78U +/** TPIU CLOCK */ +#define NRF_FUN_TPIU_CLOCK 79U +/** TPIU DATA0 */ +#define NRF_FUN_TPIU_DATA0 80U +/** TPIU DATA1 */ +#define NRF_FUN_TPIU_DATA1 81U +/** TPIU DATA2 */ +#define NRF_FUN_TPIU_DATA2 82U +/** TPIU DATA3 */ +#define NRF_FUN_TPIU_DATA3 83U + +/** @} */ + +/** + * @name nRF pinctrl output drive. + * @{ + */ + +/** Standard '0', standard '1'. */ +#define NRF_DRIVE_S0S1 0U +/** High drive '0', standard '1'. */ +#define NRF_DRIVE_H0S1 1U +/** Standard '0', high drive '1'. */ +#define NRF_DRIVE_S0H1 2U +/** High drive '0', high drive '1'. */ +#define NRF_DRIVE_H0H1 3U +/** Disconnect '0' standard '1'. */ +#define NRF_DRIVE_D0S1 4U +/** Disconnect '0', high drive '1'. */ +#define NRF_DRIVE_D0H1 5U +/** Standard '0', disconnect '1'. */ +#define NRF_DRIVE_S0D1 6U +/** High drive '0', disconnect '1'. */ +#define NRF_DRIVE_H0D1 7U +/** Extra high drive '0', extra high drive '1'. */ +#define NRF_DRIVE_E0E1 8U + +/** @} */ + +/** + * @name nRF pinctrl pull-up/down. + * @note Values match nrf_gpio_pin_pull_t constants. + * @{ + */ + +/** Pull-up disabled. */ +#define NRF_PULL_NONE 0U +/** Pull-down enabled. */ +#define NRF_PULL_DOWN 1U +/** Pull-up enabled. */ +#define NRF_PULL_UP 3U + +/** @} */ + +/** + * @name nRF pinctrl low power mode. + * @{ + */ + +/** Input. */ +#define NRF_LP_DISABLE 0U +/** Output. */ +#define NRF_LP_ENABLE 1U + +/** @} */ + +/** + * @name nRF pinctrl helpers to indicate disconnected pins. + * @{ + */ /** Indicates that a pin is disconnected */ #define NRF_PIN_DISCONNECTED NRF_PIN_MSK @@ -60,7 +324,7 @@ * @brief Utility macro to build nRF psels property entry. * * @param fun Pin function configuration (see NRF_FUNC_{name} macros). - * @param port Port (0 or 1). + * @param port Port (0 or 15). * @param pin Pin (0..31). */ #define NRF_PSEL(fun, port, pin) \ @@ -79,19 +343,4 @@ (NRF_PIN_DISCONNECTED | \ ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS)) -/** - * @brief Utility macro to obtain pin function. - * - * @param pincfg Pin configuration bit field. - */ -#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) - - -/** - * @brief Utility macro to obtain port and pin combination. - * - * @param pincfg Pin configuration bit field. - */ -#define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK) - -#endif /* NRF_INCLUDE_NRF_PINCTRL_H */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */ diff --git a/platform/ext/target/nordic_nrf/common/core/common/tfm-pinctrl.h b/platform/ext/target/nordic_nrf/common/core/common/tfm-pinctrl.h new file mode 100644 index 0000000000..963e5612a5 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/common/tfm-pinctrl.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef TFM_INCLUDE_NRF_PINCTRL_H +#define TFM_INCLUDE_NRF_PINCTRL_H + +/* The nrf-pinctrl.h is a copy of the header: + * include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h + * in Zephyr and it needs to be kept in sync. + */ +#include "nrf-pinctrl.h" + +/* Copied from the header soc/nordic/common/pinctrl_soc.h in Zephyr because they are + * used by the Driver_USART.c in TF-M. + */ + +/** + * @brief Utility macro to obtain pin function. + * + * @param pincfg Pin configuration bit field. + */ +#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) + +/** + * @brief Utility macro to obtain port and pin combination. + * + * @param pincfg Pin configuration bit field. + */ +#define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK) + +#endif /* TFM_INCLUDE_NRF_PINCTRL_H */ + diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/RTE_Device.h index 69d00a0879..7fe444a67f 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/RTE_Device.h +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/RTE_Device.h @@ -18,7 +18,7 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H -#include +#include #define RTE_USART0 1 diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/RTE_Device.h index fe3beef77c..516d827a07 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/RTE_Device.h +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/RTE_Device.h @@ -18,7 +18,7 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H -#include +#include #define RTE_USART0 1 diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/RTE_Device.h index 1a0fb035e7..9abf4a24a2 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/RTE_Device.h +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/RTE_Device.h @@ -7,7 +7,7 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H -#include +#include #define RTE_USART0 1 From f07350ae8b9fbb737c6b3b01130ba05edbd7f517 Mon Sep 17 00:00:00 2001 From: Travis Lam Date: Wed, 10 Sep 2025 17:41:44 +0200 Subject: [PATCH 106/133] [zep fromtree] platform: nrf7120: Add support for nrf7120 Add initial tfm support for nrf7120 This is based on nrf54l series soc, should have similar settings Added startup_nrf71 and target_cfg_71 to support this Change-Id: I83d9b971c4e46fc300092fd0badd30e2023639cc Signed-off-by: Travis Lam (cherry picked from commit 10be9b4fbd2a8d8201aee7ccd5b5fb3389099c40) --- .../nordic_nrf/common/core/CMakeLists.txt | 8 + .../common/core/cmsis_drivers/Driver_Flash.c | 26 +- .../nordic_nrf/common/core/nrfx_config.h | 4 + .../services/src/tfm_platform_hal_ioctl.c | 2 +- .../nordic_nrf/common/core/startup_nrf7120.c | 477 +++++++++++++++++ .../nordic_nrf/common/core/target_cfg.h | 10 +- .../nordic_nrf/common/core/target_cfg_71.c | 498 ++++++++++++++++++ .../nordic_nrf/common/nrf7120/CMakeLists.txt | 51 ++ .../nordic_nrf/common/nrf7120/config.cmake | 14 + .../nordic_nrf/common/nrf7120/cpuarch.cmake | 24 + .../nordic_nrf/common/nrf7120/mmio_defs.h | 106 ++++ .../nordic_nrf/common/nrf7120/nrf71_init.c | 31 ++ .../common/nrf7120/nrfx_config_nrf71.h | 74 +++ .../common/nrf7120/ns/CMakeLists.txt | 29 + .../common/nrf7120/partition/flash_layout.h | 166 ++++++ .../common/nrf7120/partition/region_defs.h | 132 +++++ .../nrf7120/tests/psa_arch_tests_config.cmake | 9 + .../common/nrf7120/tfm_interrupts.c | 320 +++++++++++ .../nrf7120/tfm_peripherals_config_nrf71.h | 40 ++ .../common/nrf7120/tfm_peripherals_def.h | 124 +++++ .../nrf7120pdk_nrf7120_cpuapp/CMakeLists.txt | 70 +++ .../nrf7120pdk_nrf7120_cpuapp/RTE_Device.h | 44 ++ .../nrf7120pdk_nrf7120_cpuapp/config.cmake | 10 + .../nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake | 9 + .../nrf7120pdk_nrf7120_cpuapp/device_cfg.h | 32 ++ .../ns/cpuarch_ns.cmake | 10 + .../include/tfm_platform_user_memory_ranges.h | 24 + .../services/src/tfm_platform_system.c | 30 ++ .../tests/psa_arch_tests_config.cmake | 8 + .../tests/tfm_tests_config.cmake | 8 + .../tfm_hal_platform.c | 14 + .../tfm_peripherals_config.h | 33 ++ 32 files changed, 2432 insertions(+), 5 deletions(-) create mode 100644 platform/ext/target/nordic_nrf/common/core/startup_nrf7120.c create mode 100644 platform/ext/target/nordic_nrf/common/core/target_cfg_71.c create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/config.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/nrf71_init.c create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/partition/flash_layout.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/partition/region_defs.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/tfm_interrupts.c create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h create mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/CMakeLists.txt create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/RTE_Device.h create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/device_cfg.h create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/include/tfm_platform_user_memory_ranges.h create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/src/tfm_platform_system.c create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/psa_arch_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/tfm_tests_config.cmake create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_hal_platform.c create mode 100644 platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_peripherals_config.h diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 31b0e3b60a..333006d4de 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -37,6 +37,9 @@ if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR # variables keep changing so we check both to be future proof set(HAS_RRAMC 1) set(HAS_CRACEN 1) +elseif((NRF_SOC_VARIANT MATCHES nrf7120) OR (TFM_PLATFORM MATCHES "nordic\_nrf\/nrf7120pdk\_nrf7120\_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "nrf7120")) + set(HAS_MRAMC 1) + set(HAS_CRACEN 1) else() set(HAS_NVMC 1) set(HAS_CRACEN 0) @@ -96,6 +99,10 @@ if(HAS_RRAMC) list(APPEND nvm_sources ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_rramc.c ) +elseif(HAS_MRAMC) + list(APPEND nvm_sources + ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_mramc.c + ) elseif(HAS_NVMC) list(APPEND nvm_sources ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_nvmc.c @@ -218,6 +225,7 @@ target_sources(tfm_spm target_cfg.c $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_54l.c> $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_53_91.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_71.c> secure_peripherals_defs.c ) diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c index cf0e932816..9b18b1c2b8 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c @@ -39,6 +39,8 @@ #define WRITE_BUFFER_SIZE 0 #endif +#elif defined(NRF_MRAMC_S) +#include #else #error "Unrecognized platform" #endif @@ -123,7 +125,15 @@ static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { return err; } -#endif /* RRAMC_PRESENT */ +#elif defined(MRAMC_PRESENT) + nrfx_mramc_config_t config = NRFX_MRAMC_DEFAULT_CONFIG(); + + nrfx_err_t err = nrfx_mramc_init(&config, NULL); + + if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } +#endif /* RRAMC_PRESENT or MRAMC_PRESENT*/ return ARM_DRIVER_OK; } @@ -166,7 +176,7 @@ static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, #ifdef NRF_NVMC_S nrfx_nvmc_words_write(addr, data, cnt); -#else +#elif defined(NRF_RRAMC_S) nrf_rramc_config_t rramc_config; nrf_rramc_config_get(NRF_RRAMC, &rramc_config); const nrf_rramc_config_t orig_rramc_config = rramc_config; @@ -176,6 +186,18 @@ static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, nrfx_rramc_words_write(addr, data, cnt); nrf_rramc_config_set(NRF_RRAMC, &orig_rramc_config); +#elif defined(NRF_MRAMC_S) + nrf_mramc_readynext_timeout_t orig_readynext_timeout; + nrf_mramc_readynext_timeout_get(NRF_MRAMC, &orig_readynext_timeout); + nrf_mramc_readynext_timeout_t readynext_timeout = { + .value = NRF_MRAMC_READYNEXTTIMEOUT_DEFAULT, + .direct_write = true, + }; + nrf_mramc_readynext_timeout_set(NRF_MRAMC, &readynext_timeout); + + nrfx_mramc_words_write(addr, data, cnt); + + nrf_mramc_readynext_timeout_set(NRF_MRAMC, &orig_readynext_timeout); #endif return cnt; diff --git a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h index 8d192b5887..93c0feafa7 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h +++ b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h @@ -42,6 +42,8 @@ #define NRFX_NVMC_ENABLED 1 #elif defined(NRF_RRAMC_S) #define NRFX_RRAMC_ENABLED 1 +#elif defined(NRF_MRAMC_S) +#define NRFX_MRAMC_ENABLED 1 #else #error "Unrecognized platform" #endif @@ -102,6 +104,8 @@ #include #elif defined(NRF54L_SERIES) #include +#elif defined(NRF71_SERIES) + #include #else #error "Unknown device." #endif diff --git a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c index 15fd17e316..56f071b098 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c +++ b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c @@ -103,7 +103,7 @@ tfm_platform_hal_read_service(const psa_invec *in_vec, static bool valid_mcu_select(uint32_t mcu) { switch (mcu) { -#if defined(NRF54L_SERIES) +#if defined(NRF54L_SERIES) || defined(NRF71_SERIES) case NRF_GPIO_PIN_SEL_GPIO: case NRF_GPIO_PIN_SEL_VPR: case NRF_GPIO_PIN_SEL_GRTC: diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf7120.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf7120.c new file mode 100644 index 0000000000..b15debdf07 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf7120.c @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { + EXCEPTION_INFO(); + + __ASM volatile( + "BL default_irq_handler \n" + "B . \n" + ); +} + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(SWI00_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI01_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI02_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI03_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR00_CCM00_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB00_IRQHandler) +DEFAULT_IRQ_HANDLER(VPR00_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL00_IRQHandler) +DEFAULT_IRQ_HANDLER(MRAMC_IRQHandler) +DEFAULT_IRQ_HANDLER(CTRLAP_IRQHandler) +DEFAULT_IRQ_HANDLER(CM33SS_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER00_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU00_IRQHandler) +DEFAULT_IRQ_HANDLER(USBHS_IRQHandler) +DEFAULT_IRQ_HANDLER(QSPI00_IRQHandler) +DEFAULT_IRQ_HANDLER(QSPI01_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL01_IRQHandler) +DEFAULT_IRQ_HANDLER(BELLBOARD_0_IRQHandler) +DEFAULT_IRQ_HANDLER(BELLBOARD_1_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER10_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU10_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_0_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_1_IRQHandler) +DEFAULT_IRQ_HANDLER(IPCT10_0_IRQHandler) +DEFAULT_IRQ_HANDLER(IPCT10_1_IRQHandler) +DEFAULT_IRQ_HANDLER(IPCT10_2_IRQHandler) +DEFAULT_IRQ_HANDLER(IPCT10_3_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL20_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL21_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL22_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER21_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER22_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER23_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER24_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM21_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM21_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM22_IRQHandler) +DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) +DEFAULT_IRQ_HANDLER(NFCT_IRQHandler) +DEFAULT_IRQ_HANDLER(TEMP_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE20_0_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE20_1_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC21_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_0_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_1_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_2_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_3_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_4_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_5_IRQHandler) +DEFAULT_IRQ_HANDLER(TDM_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL23_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL24_IRQHandler) +DEFAULT_IRQ_HANDLER(TAMPC_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL30_IRQHandler) +DEFAULT_IRQ_HANDLER(COMP_LPCOMP_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT30_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT31_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE30_0_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE30_1_IRQHandler) +DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) +DEFAULT_IRQ_HANDLER(VREGUSB_IRQHandler) +DEFAULT_IRQ_HANDLER(LFXO_IRQHandler) +DEFAULT_IRQ_HANDLER(LFRC_IRQHandler) +DEFAULT_IRQ_HANDLER(HFXO64M_IRQHandler) +DEFAULT_IRQ_HANDLER(VREGMRAM_IRQHandler) +DEFAULT_IRQ_HANDLER(VREGVBAT1V8_IRQHandler) +DEFAULT_IRQ_HANDLER(LDOHLP0V8_IRQHandler) +DEFAULT_IRQ_HANDLER(LDOBUCK0V8_IRQHandler) +DEFAULT_IRQ_HANDLER(VDETAO1V8_IRQHandler) +DEFAULT_IRQ_HANDLER(VDETAO0V8_IRQHandler) +DEFAULT_IRQ_HANDLER(HVBUCK_IRQHandler) +DEFAULT_IRQ_HANDLER(AUDIOPLL_AUDIOPLLM_IRQHandler) + +#if defined(DOMAIN_NS) || defined(BL2) +DEFAULT_IRQ_HANDLER(MPC00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU10_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU20_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU30_IRQHandler) +DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + default_tfm_IRQHandler, // 0 + default_tfm_IRQHandler, // 1 + default_tfm_IRQHandler, // 2 + default_tfm_IRQHandler, // 3 + default_tfm_IRQHandler, // 4 + default_tfm_IRQHandler, // 5 + default_tfm_IRQHandler, // 6 + default_tfm_IRQHandler, // 7 + default_tfm_IRQHandler, // 8 + default_tfm_IRQHandler, // 9 + default_tfm_IRQHandler, // 10 + default_tfm_IRQHandler, // 11 + default_tfm_IRQHandler, // 12 + default_tfm_IRQHandler, // 13 + default_tfm_IRQHandler, // 14 + default_tfm_IRQHandler, // 15 + default_tfm_IRQHandler, // 16 + default_tfm_IRQHandler, // 17 + default_tfm_IRQHandler, // 18 + default_tfm_IRQHandler, // 19 + default_tfm_IRQHandler, // 20 + default_tfm_IRQHandler, // 21 + default_tfm_IRQHandler, // 22 + default_tfm_IRQHandler, // 23 + default_tfm_IRQHandler, // 24 + default_tfm_IRQHandler, // 25 + default_tfm_IRQHandler, // 26 + default_tfm_IRQHandler, // 27 + SWI00_IRQHandler, // 28 + SWI01_IRQHandler, // 29 + SWI02_IRQHandler, // 30 + SWI03_IRQHandler, // 31 + default_tfm_IRQHandler, // 32 + default_tfm_IRQHandler, // 33 + default_tfm_IRQHandler, // 34 + default_tfm_IRQHandler, // 35 + default_tfm_IRQHandler, // 36 + default_tfm_IRQHandler, // 37 + default_tfm_IRQHandler, // 38 + default_tfm_IRQHandler, // 39 + default_tfm_IRQHandler, // 40 + default_tfm_IRQHandler, // 41 + default_tfm_IRQHandler, // 42 + default_tfm_IRQHandler, // 43 + default_tfm_IRQHandler, // 44 + default_tfm_IRQHandler, // 45 + default_tfm_IRQHandler, // 46 + default_tfm_IRQHandler, // 47 + default_tfm_IRQHandler, // 48 + default_tfm_IRQHandler, // 49 + default_tfm_IRQHandler, // 50 + default_tfm_IRQHandler, // 51 + default_tfm_IRQHandler, // 52 + default_tfm_IRQHandler, // 53 + default_tfm_IRQHandler, // 54 + default_tfm_IRQHandler, // 55 + default_tfm_IRQHandler, // 56 + default_tfm_IRQHandler, // 57 + default_tfm_IRQHandler, // 58 + default_tfm_IRQHandler, // 59 + default_tfm_IRQHandler, // 60 + default_tfm_IRQHandler, // 61 + default_tfm_IRQHandler, // 62 + default_tfm_IRQHandler, // 63 + SPU00_IRQHandler, // 64 + MPC00_IRQHandler, // 65 + default_tfm_IRQHandler, // 66 + default_tfm_IRQHandler, // 67 + default_tfm_IRQHandler, // 68 + default_tfm_IRQHandler, // 69 + default_tfm_IRQHandler, // 70 + default_tfm_IRQHandler, // 71 + default_tfm_IRQHandler, // 72 + default_tfm_IRQHandler, // 73 + AAR00_CCM00_IRQHandler, // 74 + ECB00_IRQHandler, // 75 + VPR00_IRQHandler, // 76 + SERIAL00_IRQHandler, // 77 + MRAMC_IRQHandler, // 78 + default_tfm_IRQHandler, // 79 + default_tfm_IRQHandler, // 80 + default_tfm_IRQHandler, // 81 + CTRLAP_IRQHandler, // 82 + default_tfm_IRQHandler, // 83 + CM33SS_IRQHandler, // 84 + TIMER00_IRQHandler, // 85 + default_tfm_IRQHandler, // 86 + default_tfm_IRQHandler, // 87 + EGU00_IRQHandler, // 88 + CRACEN_IRQHandler, // 89 + USBHS_IRQHandler, // 90 + QSPI00_IRQHandler, // 91 + QSPI01_IRQHandler, // 92 + SERIAL01_IRQHandler, // 93 + default_tfm_IRQHandler, // 94 + default_tfm_IRQHandler, // 95 + default_tfm_IRQHandler, // 96 + default_tfm_IRQHandler, // 97 + default_tfm_IRQHandler, // 98 + default_tfm_IRQHandler, // 99 + default_tfm_IRQHandler, // 100 + default_tfm_IRQHandler, // 101 + default_tfm_IRQHandler, // 102 + default_tfm_IRQHandler, // 103 + default_tfm_IRQHandler, // 104 + default_tfm_IRQHandler, // 105 + default_tfm_IRQHandler, // 106 + default_tfm_IRQHandler, // 107 + default_tfm_IRQHandler, // 108 + default_tfm_IRQHandler, // 109 + default_tfm_IRQHandler, // 110 + default_tfm_IRQHandler, // 111 + default_tfm_IRQHandler, // 112 + default_tfm_IRQHandler, // 113 + default_tfm_IRQHandler, // 114 + default_tfm_IRQHandler, // 115 + default_tfm_IRQHandler, // 116 + default_tfm_IRQHandler, // 117 + default_tfm_IRQHandler, // 118 + default_tfm_IRQHandler, // 119 + BELLBOARD_0_IRQHandler, // 120 + BELLBOARD_1_IRQHandler, // 121 + default_tfm_IRQHandler, // 122 + default_tfm_IRQHandler, // 123 + default_tfm_IRQHandler, // 124 + default_tfm_IRQHandler, // 125 + default_tfm_IRQHandler, // 126 + default_tfm_IRQHandler, // 127 + SPU10_IRQHandler, // 128 + default_tfm_IRQHandler, // 129 + default_tfm_IRQHandler, // 130 + default_tfm_IRQHandler, // 131 + default_tfm_IRQHandler, // 132 + TIMER10_IRQHandler, // 133 + default_tfm_IRQHandler, // 134 + EGU10_IRQHandler, // 135 + default_tfm_IRQHandler, // 136 + default_tfm_IRQHandler, // 137 + RADIO_0_IRQHandler, // 138 + RADIO_1_IRQHandler, // 139 + default_tfm_IRQHandler, // 140 + IPCT10_0_IRQHandler, // 141 + IPCT10_1_IRQHandler, // 142 + IPCT10_2_IRQHandler, // 143 + IPCT10_3_IRQHandler, // 144 + default_tfm_IRQHandler, // 145 + default_tfm_IRQHandler, // 146 + default_tfm_IRQHandler, // 147 + default_tfm_IRQHandler, // 148 + default_tfm_IRQHandler, // 149 + default_tfm_IRQHandler, // 150 + default_tfm_IRQHandler, // 151 + default_tfm_IRQHandler, // 152 + default_tfm_IRQHandler, // 153 + default_tfm_IRQHandler, // 154 + default_tfm_IRQHandler, // 155 + default_tfm_IRQHandler, // 156 + default_tfm_IRQHandler, // 157 + default_tfm_IRQHandler, // 158 + default_tfm_IRQHandler, // 159 + default_tfm_IRQHandler, // 160 + default_tfm_IRQHandler, // 161 + default_tfm_IRQHandler, // 162 + default_tfm_IRQHandler, // 163 + default_tfm_IRQHandler, // 164 + default_tfm_IRQHandler, // 165 + default_tfm_IRQHandler, // 166 + default_tfm_IRQHandler, // 167 + default_tfm_IRQHandler, // 168 + default_tfm_IRQHandler, // 169 + default_tfm_IRQHandler, // 170 + default_tfm_IRQHandler, // 171 + default_tfm_IRQHandler, // 172 + default_tfm_IRQHandler, // 173 + default_tfm_IRQHandler, // 174 + default_tfm_IRQHandler, // 175 + default_tfm_IRQHandler, // 176 + default_tfm_IRQHandler, // 177 + default_tfm_IRQHandler, // 178 + default_tfm_IRQHandler, // 179 + default_tfm_IRQHandler, // 180 + default_tfm_IRQHandler, // 181 + default_tfm_IRQHandler, // 182 + default_tfm_IRQHandler, // 183 + default_tfm_IRQHandler, // 184 + default_tfm_IRQHandler, // 185 + default_tfm_IRQHandler, // 186 + default_tfm_IRQHandler, // 187 + default_tfm_IRQHandler, // 188 + default_tfm_IRQHandler, // 189 + default_tfm_IRQHandler, // 190 + default_tfm_IRQHandler, // 191 + SPU20_IRQHandler, // 192 + default_tfm_IRQHandler, // 193 + default_tfm_IRQHandler, // 194 + default_tfm_IRQHandler, // 195 + default_tfm_IRQHandler, // 196 + default_tfm_IRQHandler, // 197 + SERIAL20_IRQHandler, // 198 + SERIAL21_IRQHandler, // 199 + SERIAL22_IRQHandler, // 200 + EGU20_IRQHandler, // 201 + TIMER20_IRQHandler, // 202 + TIMER21_IRQHandler, // 203 + TIMER22_IRQHandler, // 204 + TIMER23_IRQHandler, // 205 + TIMER24_IRQHandler, // 206 + default_tfm_IRQHandler, // 207 + PDM20_IRQHandler, // 208 + PDM21_IRQHandler, // 209 + PWM20_IRQHandler, // 210 + PWM21_IRQHandler, // 211 + PWM22_IRQHandler, // 212 + SAADC_IRQHandler, // 213 + NFCT_IRQHandler, // 214 + TEMP_IRQHandler, // 215 + default_tfm_IRQHandler, // 216 + default_tfm_IRQHandler, // 217 + GPIOTE20_0_IRQHandler, // 218 + GPIOTE20_1_IRQHandler, // 219 + default_tfm_IRQHandler, // 220 + default_tfm_IRQHandler, // 221 + default_tfm_IRQHandler, // 222 + default_tfm_IRQHandler, // 223 + QDEC20_IRQHandler, // 224 + QDEC21_IRQHandler, // 225 + GRTC_0_IRQHandler, // 226 + GRTC_1_IRQHandler, // 227 + GRTC_2_IRQHandler, // 228 + GRTC_3_IRQHandler, // 229 + GRTC_4_IRQHandler, // 230 + GRTC_5_IRQHandler, // 231 + TDM_IRQHandler, // 232 + default_tfm_IRQHandler, // 233 + default_tfm_IRQHandler, // 234 + default_tfm_IRQHandler, // 235 + default_tfm_IRQHandler, // 236 + SERIAL23_IRQHandler, // 237 + SERIAL24_IRQHandler, // 238 + TAMPC_IRQHandler, // 239 + default_tfm_IRQHandler, // 240 + default_tfm_IRQHandler, // 241 + default_tfm_IRQHandler, // 242 + default_tfm_IRQHandler, // 243 + default_tfm_IRQHandler, // 244 + default_tfm_IRQHandler, // 245 + default_tfm_IRQHandler, // 246 + default_tfm_IRQHandler, // 247 + default_tfm_IRQHandler, // 248 + default_tfm_IRQHandler, // 249 + default_tfm_IRQHandler, // 250 + default_tfm_IRQHandler, // 251 + default_tfm_IRQHandler, // 252 + default_tfm_IRQHandler, // 253 + default_tfm_IRQHandler, // 254 + default_tfm_IRQHandler, // 255 + SPU30_IRQHandler, // 256 + default_tfm_IRQHandler, // 257 + default_tfm_IRQHandler, // 258 + default_tfm_IRQHandler, // 259 + SERIAL30_IRQHandler, // 260 + default_tfm_IRQHandler, // 261 + COMP_LPCOMP_IRQHandler, // 262 + default_tfm_IRQHandler, // 263 + WDT30_IRQHandler, // 264 + WDT31_IRQHandler, // 265 + default_tfm_IRQHandler, // 266 + default_tfm_IRQHandler, // 267 + GPIOTE30_0_IRQHandler, // 268 + GPIOTE30_1_IRQHandler, // 269 + CLOCK_POWER_IRQHandler, // 270 + default_tfm_IRQHandler, // 271 + default_tfm_IRQHandler, // 272 + default_tfm_IRQHandler, // 273 + default_tfm_IRQHandler, // 274 + default_tfm_IRQHandler, // 275 + default_tfm_IRQHandler, // 276 + default_tfm_IRQHandler, // 277 + default_tfm_IRQHandler, // 278 + default_tfm_IRQHandler, // 279 + default_tfm_IRQHandler, // 280 + default_tfm_IRQHandler, // 281 + default_tfm_IRQHandler, // 282 + default_tfm_IRQHandler, // 283 + default_tfm_IRQHandler, // 284 + default_tfm_IRQHandler, // 285 + default_tfm_IRQHandler, // 286 + default_tfm_IRQHandler, // 287 + default_tfm_IRQHandler, // 288 + VREGUSB_IRQHandler, // 289 + LFXO_IRQHandler, // 290 + LFRC_IRQHandler, // 291 + HFXO64M_IRQHandler, // 292 + VREGMRAM_IRQHandler, // 293 + VREGVBAT1V8_IRQHandler, // 294 + LDOHLP0V8_IRQHandler, // 295 + LDOBUCK0V8_IRQHandler, // 296 + default_tfm_IRQHandler, // 297 + default_tfm_IRQHandler, // 298 + VDETAO1V8_IRQHandler, // 299 + VDETAO0V8_IRQHandler, // 300 + HVBUCK_IRQHandler, // 301 + default_tfm_IRQHandler, // 302 + default_tfm_IRQHandler, // 303 + AUDIOPLL_AUDIOPLLM_IRQHandler, // 304 +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.h b/platform/ext/target/nordic_nrf/common/core/target_cfg.h index dd767b3865..af42a416ec 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.h +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.h @@ -59,15 +59,21 @@ /* Only UART20 and UART30 are supported for TF-M tests, which are the * Non-secure applications build via the TF-M build system */ -#ifdef NRF54L_SERIES +#if defined(NRF54L_SERIES) #if NRF_SECURE_UART_INSTANCE == 20 #define NS_DRIVER_STDIO Driver_USART30 #else #define NS_DRIVER_STDIO Driver_USART20 #endif +#elif defined(NRF71_SERIES) +#if defined(NRF_SECURE_UART_INSTANCE) && (NRF_SECURE_UART_INSTANCE == 00) +#define NS_DRIVER_STDIO Driver_USART30 +#else +#define NS_DRIVER_STDIO Driver_USART00 +#endif #else #define NS_DRIVER_STDIO Driver_USART0 -#endif /* NRF54L_SERIES */ +#endif /* NRF54L_SERIES or NRF71_SERIES */ /** * \brief Store the addresses of memory regions diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_71.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_71.c new file mode 100644 index 0000000000..41475bea92 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_71.c @@ -0,0 +1,498 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include "tfm_spm_log.h" + + +#if !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." +#endif + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +/* During TF-M system initialization we invoke a function that comes + * from Zephyr. This function does not have a header file so we + * declare its prototype here. + */ +int soc_early_init_hook(void); + +extern const struct memory_region_limits memory_regions; + +struct mpc_region_override { + nrf_mpc_override_config_t config; + nrf_owner_t owner_id; + uintptr_t start_address; + size_t endaddr; + uint32_t perm; + uint32_t permmask; + size_t index; +}; + +static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) +{ + nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); + nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); + nrf_mpc_override_perm_set(mpc, override->index, override->perm); + nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); +#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID + nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); +#endif + nrf_mpc_override_config_set(mpc, override->index, &override->config); +} + +/* + * Configure the override struct with reasonable defaults. This includes: + * + * Use a slave number of 0 to avoid redirecting bus transactions from + * one slave to another. + * + * Lock the override to prevent the code that follows from tampering + * with the configuration. + * + * Enable the override so it takes effect. + * + * Indicate that secdom is not enabled as this driver is not used on + * platforms with secdom. + */ +static void init_mpc_region_override(struct mpc_region_override *override) +{ + *override = (struct mpc_region_override){ + .config = + (nrf_mpc_override_config_t){ + .slave_number = 0, + .lock = true, + .enable = true, + .secdom_enable = false, + .secure_mask = true, + }, + .perm = 0, /* 0 for non-secure */ + .owner_id = 0, + }; + + override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; +} + +static nrfx_err_t mramc_configuration(void) +{ + nrfx_mramc_config_t config = NRFX_MRAMC_DEFAULT_CONFIG(); + + config.config.mode_write = NRF_MRAMC_MODE_WRITE_DIRECT; + + /* Don't use an event handler until it's understood whether we + * want it or not + */ + nrfx_mramc_evt_handler_t handler = NULL; + + nrfx_err_t err = nrfx_mramc_init(&config, handler); + if (err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } + + return NRFX_SUCCESS; +} + +enum tfm_plat_err_t init_debug(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* + * This SAU configuration aligns with ARM's RSS implementation of + * sau_and_idau_cfg when possible. + */ + /* Enables SAU */ + TZ_SAU_Enable(); + + /* Configures SAU regions to be non-secure */ + + /* Note that this SAU configuration assumes that there is only one + * secure NVM partition and one non-secure NVM partition. Meaning, + * memory_regions.non_secure_partition_limit is at the end of + * NVM. + */ + + /* Configure the end of NVM, and the FICR, to be non-secure using + a single region. Note that the FICR is placed after the + non-secure NVM and before the UICR.*/ + SAU->RNR = 0; + SAU->RBAR = (memory_regions.non_secure_partition_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (NRF_UICR_S_BASE & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Leave SAU region 1 disabled until we find a use for it */ + + /* Configures veneers region to be non-secure callable */ + SAU->RNR = 2; + SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk | + SAU_RLAR_NSC_Msk; + + /* Configures SAU region 3 to cover both the end of SRAM and + * regions above it as shown in the "Example memory map" in the + * "Product Specification" */ + SAU->RNR = 3; + SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (0xFFFFFFFFul & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; +} + +enum tfm_plat_err_t nrf_mpc_init_cfg(void) +{ + /* On 7120 the NRF_MPC00->REGION[]'s are fixed in HW and the + * OVERRIDE indexes (that are useful to us) start at 0 and end + * (inclusive) at 4. + * + * Note that the MPC regions configure all volatile and non-volatile memory as secure, so we + * only need to explicitly OVERRIDE the non-secure addresses to permit non-secure access. + * + * Explicitly configuring memory as secure is not necessary. + * + * The last OVERRIDE in 7120 is fixed in HW and exists to prevent + * other bus masters than the KMU from accessing CRACEN protected RAM. + * + * Note that we must take care not to configure an OVERRIDE that + * affects an active bus transaction. + * + * Note that we don't configure the NSC region to be NS because + * from the MPC's perspective it is secure. NSC is only configurable from the SAU. + * + * Note that OVERRIDE[n].MASTERPORT has a reasonable reset value + * so it is left unconfigured. + * + * Note that there are two owners in 7120. KMU with owner ID 1, and everything else with + * owner ID 0. + */ + + uint32_t index = 0; + /* + * Configure the non-secure partition of the non-volatile + * memory. This MPC region is intended to cover both the + * non-secure partition in the NVM and also the FICR. The FICR + * starts after the NVM and ends just before the UICR. + */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = memory_regions.non_secure_partition_base; + override.endaddr = NRF_UICR_S_BASE; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + /* Configure the non-secure partition of the volatile memory */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = NS_DATA_START; + override.endaddr = 1 + NS_DATA_LIMIT; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + if (index > 6) { + /* Used more overrides than are available */ + tfm_core_panic(); + } + + /* Lock and disable any unused MPC overrides to prevent malicious configuration */ + while (index <= 6) { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.config.enable = false; + + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + return TFM_PLAT_ERR_SUCCESS; +} + +void peripheral_configuration(void) +{ +#if SECURE_UART1 + /* Configure TF-M's UART peripheral to be secure */ +#if NRF_SECURE_UART_INSTANCE == 00 + uint32_t uart_periph_start = tfm_peripheral_uarte00.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 20 + uint32_t uart_periph_start = tfm_peripheral_uarte20.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 21 + uint32_t uart_periph_start = tfm_peripheral_uarte21.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 22 + uint32_t uart_periph_start = tfm_peripheral_uarte22.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 30 + uint32_t uart_periph_start = tfm_peripheral_uarte30.periph_start; +#endif + spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); +#endif /* SECURE_UART1 */ + + /* Configure the CTRL-AP mailbox interface to be secure as it is used by the secure ADAC + * service */ + spu_peripheral_config_secure(NRF_CTRLAP_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure NRF_MEMCONF to be secure as it could otherwise be used to corrupt secure RAM. + */ + spu_peripheral_config_secure(NRF_MEMCONF_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure trace to be secure, as the security implications of non-secure trace are not + * understood */ + spu_peripheral_config_secure(NRF_TAD_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure these HW features, which are not in the MDK, to be + * secure, as the security implications of them being non-secure + * are not understood + */ + uint32_t base_addresses[4] = {0x5007E000, 0x5008C000, 0x500E6000, 0x5010F000}; + for (int i = 0; i < 4; i++) { + spu_peripheral_config_secure(base_addresses[i], SPU_LOCK_CONF_LOCKED); + } + + /* Configure NRF_REGULATORS, and NRF_OSCILLATORS to be secure as it is + * needed to prevent glitches when the power supply is attacked. + * + * NB: Note that NRF_OSCILLATORS and NRF_REGULATORS have the same base address and must + * therefore have the same security configuration. + */ + spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); +} + +static void gpiote_channel_configuration(void) +{ + /* Configure GPIOTE channels to be secure */ + uint32_t secure_gpiote_channels[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + uint32_t gpiote_instances[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + NRF_GPIOTE20_S_BASE, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + NRF_GPIOTE30_S_BASE, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + /* Configure the SPU GPIOTE registers. Each GPIOTE can fire 2 interrupts for + * each available channel. If a channel is configured as secure both of the + * interrupts will only available in secure mode so a single configuration + * should suffice. + */ + for (int i = 0; i < ARRAY_SIZE(gpiote_instances) - 1; i++) { + + NRF_SPU_Type *spu_instance = spu_instance_from_peripheral_addr(gpiote_instances[i]); + for (int channel = 0; channel < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT; channel++) { + if (secure_gpiote_channels[i] & (1 << channel)) { + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, channel); + + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, channel); + } + } + } +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + for (int pin = 0; pin < 32; pin++) { + if (secure_pins[port] & (1 << pin)) { + bool enable = true; // secure + + /* + * Unfortunately, NRF_P0 is not configured by NRF_SPU00, etc. + * so it is a bit convoluted to find the SPU instance for port x. + */ + uint32_t gpio_port_addr[2] = { + NRF_P0_S_BASE, + NRF_P1_S_BASE, + }; + + NRF_SPU_Type *spu_instance = + spu_instance_from_peripheral_addr(gpio_port_addr[port]); + + nrf_spu_feature_secattr_set(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin, enable); + nrf_spu_feature_lock_enable(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin); + } + } + } +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + /* Peripheral configuration */ + /* Configure features to be non-secure */ + + /* + * Due to MLT-7600, many SPU HW reset values are wrong. The docs + * generally features being non-secure when coming out of HW + * reset, but the HW has a good mix of both. + * + * When configuring NRF_SPU 0 will indicate non-secure and 1 will + * indicate secure. + * + * Most of the chip should be non-secure so to simplify and be + * consistent, we memset the entire memory map of each SPU + * peripheral to 0. + * + * Just after memsetting to 0 we explicitly configure the + * peripherals that should be secure back to secure again. + */ + // TODO: Evaluate if it is safe to memset everything + // in NRF_SPU to 0. + memset(NRF_SPU00, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU10, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU20, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU30, 0, sizeof(NRF_SPU_Type)); + + peripheral_configuration(); + + /* TODO_NRF7120: Use the nrf_spu_feature API to configure DPPI + channels according to a user-controllable config similar to + TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE. */ + + gpiote_channel_configuration(); + gpio_configuration(); + + nrf_cache_enable(NRF_ICACHE); + + nrfx_err_t nrfx_err = mramc_configuration(); + if (nrfx_err != NRFX_SUCCESS) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* SOC configuration from Zephyr's soc.c. */ + int soc_err = soc_early_init_hook(); + if (soc_err) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_CRACEN)); + NVIC_ClearTargetState(MPC00_IRQn); + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + mpc_clear_events(); + /* MPC interrupt enabling */ + mpc_enable_interrupts(); + + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + + /* The CRACEN driver configures the NVIC for CRACEN and is + * therefore omitted here. + */ + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt new file mode 100644 index 0000000000..df11cccc26 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt @@ -0,0 +1,51 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf7120) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf7120_enga.c + ./nrf71_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ./nrfx_config_nrf71.h + ./config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf7120 +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf7120 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/config.cmake b/platform/ext/target/nordic_nrf/common/nrf7120/config.cmake new file mode 100644 index 0000000000..2d5fa83c34 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/config.cmake @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/config.cmake) + +set(SECURE_UART30 ON CACHE BOOL "Enable secure UART" FORCE) +set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) +set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf7120/cpuarch.cmake new file mode 100644 index 0000000000..67476b33f1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF7120_ENGA_XXAA + NRF71_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h b/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h new file mode 100644 index 0000000000..6e2ecf8e16 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * + */ + +#ifndef __MMIO_DEFS_H__ +#define __MMIO_DEFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "handle_attr.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include + +/* Allowed named MMIO of this platform */ +const uintptr_t partition_named_mmio_list[] = { +#if TFM_PERIPHERAL_TIMER00_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER00, +#endif +#if TFM_PERIPHERAL_TIMER10_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER10, +#endif +#if TFM_PERIPHERAL_TIMER20_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER20, +#endif +#if TFM_PERIPHERAL_TIMER21_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER21, +#endif +#if TFM_PERIPHERAL_TIMER22_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER22, +#endif +#if TFM_PERIPHERAL_TIMER23_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER23, +#endif +#if TFM_PERIPHERAL_TIMER24_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER24, +#endif +#if TFM_PERIPHERAL_SPIM00_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM00, +#endif +#if TFM_PERIPHERAL_SPIM20_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM20, +#endif +#if TFM_PERIPHERAL_SPIM21_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM21, +#endif +#if TFM_PERIPHERAL_SPIM22_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM22, +#endif +#if TFM_PERIPHERAL_SPIM23_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM23, +#endif +#if TFM_PERIPHERAL_SPIM30_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM30, +#endif +#if TFM_PERIPHERAL_EGU10_SECURE + (uintptr_t)TFM_PERIPHERAL_EGU10, +#endif +#if TFM_PERIPHERAL_EGU20_SECURE + (uintptr_t)TFM_PERIPHERAL_EGU20, +#endif +#if TFM_PERIPHERAL_PWM20_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM20, +#endif +#if TFM_PERIPHERAL_PWM21_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM21, +#endif +#if TFM_PERIPHERAL_PWM22_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM22, +#endif +#if TFM_PERIPHERAL_PWM20_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM20, +#endif +#if TFM_PERIPHERAL_UARTE00_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE00, +#endif +#if TFM_PERIPHERAL_UARTE20_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE20, +#endif +#if TFM_PERIPHERAL_UARTE21_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE21, +#endif +#if TFM_PERIPHERAL_UARTE22_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE22, +#endif +#if TFM_PERIPHERAL_UARTE30_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE30, +#endif +#if TFM_PERIPHERAL_GPIOTE20_SECURE + (uintptr_t)TFM_PERIPHERAL_GPIOTE20, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE + (uintptr_t)TFM_PERIPHERAL_GPIOTE30, +#endif +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __MMIO_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/nrf71_init.c b/platform/ext/target/nordic_nrf/common/nrf7120/nrf71_init.c new file mode 100644 index 0000000000..c4dc1ec82a --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/nrf71_init.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include + +#ifndef BIT_MASK +/* Use Zephyr BIT_MASK for unasigned integers */ +#define BIT_MASK(n) ((1UL << (n)) - 1UL) +#endif + +/* This handler needs to be ported to the upstream TF-M project when Cracen is supported there. + * The implementation of this is currently in sdk-nrf. We define it to avoid warnings when we build + * the target_cfg.c file which is the same for both upsteam TF-M and sdk-nrf. + * It is defined as weak to allow the sdk-nrf version to be used when available. */ +void __attribute__((weak)) CRACEN_IRQHandler(void){}; + +int __attribute__((weak)) soc_early_init_hook(void){ + /* Update the SystemCoreClock global variable with current core clock + * retrieved from hardware state. + */ +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(__NRF_TFM__) + /* Currently not supported for non-secure */ + SystemCoreClockUpdate(); +#endif + return 0; +} diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h b/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h new file mode 100644 index 0000000000..f5ae9de955 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ +#define NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0 Maximum: 7 + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0 Maximum: 7 + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_MRAMC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MRAMC_ENABLED +#define NRFX_MRAMC_ENABLED 0 +#endif + +/** + * @brief NRFX_MRAMC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_MRAMC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_MRAMC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_MRAMC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MRAMC_CONFIG_LOG_ENABLED +#define NRFX_MRAMC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_MRAMC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_MRAMC_CONFIG_LOG_LEVEL +#define NRFX_MRAMC_CONFIG_LOG_LEVEL 3 +#endif + +#endif // NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt new file mode 100644 index 0000000000..9fa367062d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf7120) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf7120_enga.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf7120/partition/flash_layout.h new file mode 100644 index 0000000000..b1da1f42fe --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/partition/flash_layout.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF7120 Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (512 KB) + * 0x0008_0000 Protected Storage Area (16 KB) + * 0x0008_4000 Internal Trusted Storage Area (16 KB) + * 0x0008_8000 OTP / NV counters area (8 KB) + * 0x0008_A000 Non-secure image primary (844 KB) + * 0x0015_D000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF7120 has 4088 kB of non volatile memory (MRAM) but the last 116kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0x3E1000) /* 3972 kB since the last 116kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF7120 has 1024 kB of volatile memory (SRAM) but only 512kB are reserved for Arm Cortex-M33. + * RAM_00: 512 Kb - Arm® Cortex®-M33 code and data + * RAM_01: 256 Kb - ML accelerator + * RAM_02: 128 Kb - Network Buffer WiFi/Radio system + * RAM_03: 120 Kb - FLPR code, data and top 8Kb reserved + * For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00080000) /* 512 kB, since other 512 kB are reserved for others */ + +#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 kB*/ +#define FLASH_NS_PARTITION_SIZE (0xD3000) /* NS partition: 844 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf7120/partition/region_defs.h new file mode 100644 index 0000000000..a12e78adf5 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/partition/region_defs.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x504) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf7120/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..0ad6c7e4ae --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf7120") diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_interrupts.c b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_interrupts.c new file mode 100644 index 0000000000..c989555f39 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_interrupts.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include + +#include "cmsis.h" +#include "spm.h" +#include "tfm_hal_interrupt.h" +#include "tfm_peripherals_def.h" +#include "tfm_peripherals_config.h" +#include "load/interrupt_defs.h" +#include "interrupt.h" + +static enum tfm_hal_status_t irq_init(struct irq_t *irq, IRQn_Type irqn, + void * p_pt, + const struct irq_load_info_t *p_ildi) +{ + irq->p_ildi = p_ildi; + irq->p_pt = p_pt; + + NVIC_SetPriority(irqn, DEFAULT_IRQ_PRIORITY); + NVIC_ClearTargetState(irqn); + NVIC_DisableIRQ(irqn); + + return TFM_HAL_SUCCESS; +} + +#if TFM_PERIPHERAL_FPU_SECURE +static struct irq_t fpu_irq = {0}; + +void FPU_IRQHandler(void) +{ + spm_handle_interrupt(fpu_irq.p_pt, fpu_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_fpu_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&fpu_irq, TFM_FPU_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER00_SECURE +static struct irq_t timer00_irq = {0}; + +void TIMER00_IRQHandler(void) +{ + spm_handle_interrupt(timer00_irq.p_pt, timer00_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer00_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer00_irq, TFM_TIMER00_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER10_SECURE +static struct irq_t timer10_irq = {0}; + +void TIMER10_IRQHandler(void) +{ + spm_handle_interrupt(timer10_irq.p_pt, timer10_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer10_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer10_irq, TFM_TIMER10_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER20_SECURE +static struct irq_t timer20_irq = {0}; + +void TIMER20_IRQHandler(void) +{ + spm_handle_interrupt(timer20_irq.p_pt, timer20_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer20_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer20_irq, TFM_TIMER20_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER21_SECURE +static struct irq_t timer21_irq = {0}; + +void TIMER21_IRQHandler(void) +{ + spm_handle_interrupt(timer21_irq.p_pt, timer21_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer21_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer21_irq, TFM_TIMER21_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER22_SECURE +static struct irq_t timer22_irq = {0}; + +void TIMER22_IRQHandler(void) +{ + spm_handle_interrupt(timer22_irq.p_pt, timer22_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer22_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer22_irq, TFM_TIMER22_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER23_SECURE +static struct irq_t timer23_irq = {0}; + +void TIMER23_IRQHandler(void) +{ + spm_handle_interrupt(timer23_irq.p_pt, timer23_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer23_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer23_irq, TFM_TIMER23_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER24_SECURE +static struct irq_t timer24_irq = {0}; + +void TIMER24_IRQHandler(void) +{ + spm_handle_interrupt(timer24_irq.p_pt, timer24_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer24_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer24_irq, TFM_TIMER24_IRQ, p_pt, p_ildi); +} +#endif + +/* By NRFX convention GPIOTE interrupt 1 targets secure, while 0 targets non-secure. */ +static struct irq_t gpiote20_1_irq = {0}; + +void GPIOTE20_1_IRQHandler(void) +{ + spm_handle_interrupt(gpiote20_1_irq.p_pt, gpiote20_1_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_gpiote20_1_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&gpiote20_1_irq, TFM_GPIOTE20_1_IRQ, p_pt, p_ildi); +} + +/* By NRFX convention GPIOTE interrupt 1 targets secure, while 0 targets non-secure. */ +static struct irq_t gpiote30_1_irq = {0}; + +void GPIOTE30_1_IRQHandler(void) +{ + spm_handle_interrupt(gpiote30_1_irq.p_pt, gpiote30_1_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_gpiote30_1_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&gpiote30_1_irq, TFM_GPIOTE30_1_IRQ, p_pt, p_ildi); +} + +#if TFM_PERIPHERAL_SPIM00_SECURE +static struct irq_t spim00_irq = {0}; + +void SPIM00_IRQHandler(void) +{ + spm_handle_interrupt(spim00_irq.p_pt, spim00_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim00_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim00_irq, TFM_SPIM00_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +static struct irq_t spim22_irq = {0}; + +void SPIM22_IRQHandler(void) +{ + spm_handle_interrupt(spim22_irq.p_pt, spim22_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim22_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim22_irq, TFM_SPIM22_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_SPIM23_SECURE +static struct irq_t spim23_irq = {0}; + +void SPIM23_IRQHandler(void) +{ + spm_handle_interrupt(spim23_irq.p_pt, spim23_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim23_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim23_irq, TFM_SPIM23_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_SPIM30_SECURE +static struct irq_t spim30_irq = {0}; + +void SPIM30_IRQHandler(void) +{ + spm_handle_interrupt(spim30_irq.p_pt, spim30_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim30_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim30_irq, TFM_SPIM30_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_EGU10_SECURE +static struct irq_t egu10_irq = {0}; + +void EGU10_IRQHandler(void) +{ + spm_handle_interrupt(egu10_irq.p_pt, egu10_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_egu10_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&egu10_irq, TFM_EGU10_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_EGU20_SECURE +static struct irq_t egu20_irq = {0}; + +void EGU20_IRQHandler(void) +{ + spm_handle_interrupt(egu20_irq.p_pt, egu20_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_egu20_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&egu20_irq, TFM_EGU20_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_PWM20_SECURE +static struct irq_t pwm20_irq = {0}; + +void PWM20_IRQHandler(void) +{ + spm_handle_interrupt(pwm20_irq.p_pt, pwm20_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_pwm20_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&pwm20_irq, TFM_PWM20_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_PWM21_SECURE +static struct irq_t pwm21_irq = {0}; + +void PWM21_IRQHandler(void) +{ + spm_handle_interrupt(pwm21_irq.p_pt, pwm21_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_pwm21_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&pwm21_irq, TFM_PWM21_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_PWM22_SECURE +static struct irq_t pwm22_irq = {0}; + +void PWM22_IRQHandler(void) +{ + spm_handle_interrupt(pwm22_irq.p_pt, pwm22_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_pwm22_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&pwm22_irq, TFM_PWM22_IRQ, p_pt, p_ildi); +} +#endif + +#ifdef PSA_API_TEST_IPC +enum tfm_hal_status_t ff_test_uart_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +__attribute__((alias("tfm_egu10_irq_init"))); + +#endif diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h new file mode 100644 index 0000000000..a03b92d317 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h @@ -0,0 +1,40 @@ + +#ifndef TFM_PERIPHERAL_TIMER00_SECURE +#define TFM_PERIPHERAL_TIMER00_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE00_SECURE +#define TFM_PERIPHERAL_UARTE00_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE20_SECURE +#define TFM_PERIPHERAL_UARTE20_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE21_SECURE +#define TFM_PERIPHERAL_UARTE21_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE22_SECURE +#define TFM_PERIPHERAL_UARTE22_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE30_SECURE +#define TFM_PERIPHERAL_UARTE30_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE20_SECURE +#define TFM_PERIPHERAL_GPIOTE20_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK +#define TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE30_SECURE +#define TFM_PERIPHERAL_GPIOTE30_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK +#define TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK 0 +#endif diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h new file mode 100644 index 0000000000..7231c0018d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * + */ + +#ifndef __TFM_PERIPHERALS_DEF_H__ +#define __TFM_PERIPHERALS_DEF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define TFM_FPU_IRQ (NRFX_IRQ_NUMBER_GET(NRF_FPU)) +#define TFM_TIMER00_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER00)) +#define TFM_TIMER10_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER10)) +#define TFM_TIMER20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER20)) +#define TFM_TIMER21_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER21)) +#define TFM_TIMER22_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER22)) +#define TFM_TIMER23_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER23)) +#define TFM_TIMER24_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER24)) +#define TFM_SPIM00_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM00)) +#define TFM_SPIM20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM20)) +#define TFM_SPIM21_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM21)) +#define TFM_SPIM22_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM22)) +#define TFM_SPIM23_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM23)) +#define TFM_SPIM30_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM30)) +#define TFM_EGU10_IRQ (NRFX_IRQ_NUMBER_GET(NRF_EGU10)) +#define TFM_EGU20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_EGU20)) +#define TFM_GPIOTE20_1_IRQ GPIOTE20_1_IRQn +#define TFM_GPIOTE30_1_IRQ GPIOTE30_1_IRQn +#define TFM_PWM20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_PWM20)) +#define TFM_PWM21_IRQ (NRFX_IRQ_NUMBER_GET(NRF_PWM21)) +#define TFM_PWM22_IRQ (NRFX_IRQ_NUMBER_GET(NRF_PWM22)) + +extern struct platform_data_t tfm_peripheral_timer00; +extern struct platform_data_t tfm_peripheral_timer10; +extern struct platform_data_t tfm_peripheral_timer20; +extern struct platform_data_t tfm_peripheral_timer21; +extern struct platform_data_t tfm_peripheral_timer22; +extern struct platform_data_t tfm_peripheral_timer23; +extern struct platform_data_t tfm_peripheral_timer24; +extern struct platform_data_t tfm_peripheral_spim00; +extern struct platform_data_t tfm_peripheral_spim20; +extern struct platform_data_t tfm_peripheral_spim21; +extern struct platform_data_t tfm_peripheral_spim22; +extern struct platform_data_t tfm_peripheral_spim23; +extern struct platform_data_t tfm_peripheral_spim30; +extern struct platform_data_t tfm_peripheral_egu10; +extern struct platform_data_t tfm_peripheral_egu20; +extern struct platform_data_t tfm_peripheral_gpiote20; +extern struct platform_data_t tfm_peripheral_gpiote30; +extern struct platform_data_t tfm_peripheral_pwm20; +extern struct platform_data_t tfm_peripheral_pwm21; +extern struct platform_data_t tfm_peripheral_pwm22; + +#define TFM_PERIPHERAL_TIMER00 (&tfm_peripheral_timer00) +#define TFM_PERIPHERAL_TIMER10 (&tfm_peripheral_timer10) +#define TFM_PERIPHERAL_TIMER20 (&tfm_peripheral_timer20) +#define TFM_PERIPHERAL_TIMER21 (&tfm_peripheral_timer21) +#define TFM_PERIPHERAL_TIMER22 (&tfm_peripheral_timer22) +#define TFM_PERIPHERAL_TIMER23 (&tfm_peripheral_timer23) +#define TFM_PERIPHERAL_TIMER24 (&tfm_peripheral_timer24) +#define TFM_PERIPHERAL_SPIM00 (&tfm_peripheral_spim00) +#define TFM_PERIPHERAL_SPIM20 (&tfm_peripheral_spim20) +#define TFM_PERIPHERAL_SPIM21 (&tfm_peripheral_spim21) +#define TFM_PERIPHERAL_SPIM22 (&tfm_peripheral_spim22) +#define TFM_PERIPHERAL_SPIM23 (&tfm_peripheral_spim23) +#define TFM_PERIPHERAL_SPIM30 (&tfm_peripheral_spim30) +#define TFM_PERIPHERAL_EGU10 (&tfm_peripheral_egu10) +#define TFM_PERIPHERAL_EGU20 (&tfm_peripheral_egu20) +#define TFM_PERIPHERAL_GPIOTE20 (&tfm_peripheral_gpiote20) +#define TFM_PERIPHERAL_GPIOTE30 (&tfm_peripheral_gpiote30) +#define TFM_PERIPHERAL_PWM20 (&tfm_peripheral_pwm20) +#define TFM_PERIPHERAL_PWM21 (&tfm_peripheral_pwm21) +#define TFM_PERIPHERAL_PWM22 (&tfm_peripheral_pwm22) + +/* + * Quantized default IRQ priority, the value is: + * (Number of configurable priority) / 4: (1UL << __NVIC_PRIO_BITS) / 4 + */ +#define DEFAULT_IRQ_PRIORITY (1UL << (__NVIC_PRIO_BITS - 2)) + +extern struct platform_data_t tfm_peripheral_uarte00; +extern struct platform_data_t tfm_peripheral_uarte20; +extern struct platform_data_t tfm_peripheral_uarte21; +extern struct platform_data_t tfm_peripheral_uarte22; +extern struct platform_data_t tfm_peripheral_uarte30; + +#define TFM_PERIPHERAL_UARTE00 (&tfm_peripheral_uarte00) +#define TFM_PERIPHERAL_UARTE20 (&tfm_peripheral_uarte20) +#define TFM_PERIPHERAL_UARTE21 (&tfm_peripheral_uarte21) +#define TFM_PERIPHERAL_UARTE22 (&tfm_peripheral_uarte22) +#define TFM_PERIPHERAL_UARTE30 (&tfm_peripheral_uarte30) + +#define TFM_PERIPHERAL_STD_UART TFM_PERIPHERAL_UARTE30 + +extern struct platform_data_t tfm_peripheral_uarte00; +extern struct platform_data_t tfm_peripheral_uarte20; +extern struct platform_data_t tfm_peripheral_uarte21; +extern struct platform_data_t tfm_peripheral_uarte22; +extern struct platform_data_t tfm_peripheral_uarte30; + +#define TFM_PERIPHERAL_UARTE00 (&tfm_peripheral_uarte00) +#define TFM_PERIPHERAL_UARTE20 (&tfm_peripheral_uarte20) +#define TFM_PERIPHERAL_UARTE21 (&tfm_peripheral_uarte21) +#define TFM_PERIPHERAL_UARTE22 (&tfm_peripheral_uarte22) +#define TFM_PERIPHERAL_UARTE30 (&tfm_peripheral_uarte30) + +#define TFM_PERIPHERAL_STD_UART TFM_PERIPHERAL_UARTE30 + +#ifdef PSA_API_TEST_IPC +/* see other platforms when supporting this */ +#error "Not supported yet" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __TFM_PERIPHERALS_DEF_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/CMakeLists.txt new file mode 100644 index 0000000000..ceda0a1e20 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/CMakeLists.txt @@ -0,0 +1,70 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf7120 nrf7120) + +target_include_directories(platform_region_defs + INTERFACE + ../common/nrf7120/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf7120/partition + services/include +) + +if(BL2) + target_include_directories(platform_bl2 + PUBLIC + partition + ../common/nrf7120/partition + PRIVATE + . + ) +endif() + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/RTE_Device.h new file mode 100644 index 0000000000..2aa8afbbbd --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART00 1 + +#define RTE_USART00_PINS \ +{ \ + NRF_PSEL(UART_TX, 2, 2),\ + NRF_PSEL(UART_RX, 2, 0),\ + NRF_PSEL(UART_RTS, 2, 5),\ + NRF_PSEL(UART_CTS, 2, 4),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 5),\ + NRF_PSEL(UART_RX, 0, 6),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake new file mode 100644 index 0000000000..1779639f54 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf7120/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake new file mode 100644 index 0000000000..684b03cf43 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf7120/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/device_cfg.h new file mode 100644 index 0000000000..22ddb39ce1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 0000000000..e07ac6eb38 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,10 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf7120/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..ee79d246fd --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..9ff8f6c37c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..2428deadd8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf7120/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..619f1f92cf --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_hal_platform.c new file mode 100644 index 0000000000..5f682a8253 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_peripherals_config.h new file mode 100644 index 0000000000..77fc503c8a --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF71_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ From 3bbed60dc476d72a718968d5bf80004b02ccb9ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Tue, 4 Nov 2025 10:20:13 +0100 Subject: [PATCH 107/133] [zep fromtree] platform: nordic_nrf: Enable DCDC instead of LDO for 54L series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update nrf5l_init to enable DCDC during startup. LDO is not supported and therefore causes larger power consumption. Change-Id: I9a6dc928259895ed8b54c99aff9974ce1a13896e Signed-off-by: Dag Erik Gjørvad (cherry picked from commit 76c6c1df85238c2cfda11d16a8011cba3ea324ff) --- platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c index 54d14aa3ef..e457f93628 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c +++ b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #ifndef BIT_MASK @@ -156,6 +157,7 @@ int __attribute__((weak)) nordicsemi_nrf54l_init(void){ *((volatile uint32_t *)0x5012063Cul) &= ~(1<<19); } + nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true); return 0; } From c70c78267764a16a42d4a0f7196c185b7d030a14 Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Tue, 2 Sep 2025 17:45:37 +0200 Subject: [PATCH 108/133] [zep fromtree] platform: nordic: Update the Nordic USART function Update the Nordic USART functions to accept other miscellaneous control commands apart from the mode control ones. This makes the USART functions for Nordic platforms to acept the CONTROL_TX and CONTROL_RX commands as well. The sdtio_init function uses the ARM_USART_CONTROL_TX command which used to fail for Nordic platforms before but the return code of the control function was never checked. Recently this changed and it now checks for the return code which makes the Nordic platform failing to boot so this change is necessary. Signed-off-by: Georgios Vasilakis Change-Id: I65b0884338df924dbec3783421779d64ceaaf741 (cherry picked from commit f256c198e7ba794da5e4ac7f868c8a68ce6bad31) --- .../common/core/cmsis_drivers/Driver_USART.c | 246 ++++++++++++------ 1 file changed, 162 insertions(+), 84 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c index f1156daff6..7c44cb3ac5 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c @@ -249,102 +249,180 @@ static uint32_t ARM_USARTx_GetRxCount(const UARTx_Resources *uart_resources) return uart_resources->rx_count; } -static int32_t ARM_USARTx_Control(uint32_t control, uint32_t arg, - UARTx_Resources *uart_resources) -{ - if ((control & ARM_USART_CONTROL_Msk) != ARM_USART_MODE_ASYNCHRONOUS) { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - nrf_uarte_baudrate_t baudrate = uart_resources->baudrate; - nrf_uarte_config_t hal_cfg = uart_resources->hal_cfg; - switch (arg) { - case 1200: baudrate = NRF_UARTE_BAUDRATE_1200; break; - case 2400: baudrate = NRF_UARTE_BAUDRATE_2400; break; - case 4800: baudrate = NRF_UARTE_BAUDRATE_4800; break; - case 9600: baudrate = NRF_UARTE_BAUDRATE_9600; break; - case 14400: baudrate = NRF_UARTE_BAUDRATE_14400; break; - case 19200: baudrate = NRF_UARTE_BAUDRATE_19200; break; - case 28800: baudrate = NRF_UARTE_BAUDRATE_28800; break; - case 31250: baudrate = NRF_UARTE_BAUDRATE_31250; break; - case 38400: baudrate = NRF_UARTE_BAUDRATE_38400; break; - case 56000: baudrate = NRF_UARTE_BAUDRATE_56000; break; - case 57600: baudrate = NRF_UARTE_BAUDRATE_57600; break; - case 76800: baudrate = NRF_UARTE_BAUDRATE_76800; break; - case 115200: baudrate = NRF_UARTE_BAUDRATE_115200; break; - case 230400: baudrate = NRF_UARTE_BAUDRATE_230400; break; - case 250000: baudrate = NRF_UARTE_BAUDRATE_250000; break; - case 460800: baudrate = NRF_UARTE_BAUDRATE_460800; break; - case 921600: baudrate = NRF_UARTE_BAUDRATE_921600; break; - case 1000000: baudrate = NRF_UARTE_BAUDRATE_1000000; break; - default: - return ARM_USART_ERROR_BAUDRATE; - } - - if ((control & ARM_USART_DATA_BITS_Msk) != ARM_USART_DATA_BITS_8) { - return ARM_USART_ERROR_DATA_BITS; - } - - switch (control & ARM_USART_STOP_BITS_Msk) { - case ARM_USART_STOP_BITS_1: - hal_cfg.stop = NRF_UARTE_STOP_ONE; - break; - - case ARM_USART_STOP_BITS_2: - hal_cfg.stop = NRF_UARTE_STOP_TWO; - break; - - default: - return ARM_USART_ERROR_STOP_BITS; - } - switch (control & ARM_USART_PARITY_Msk) { - case ARM_USART_PARITY_NONE: - hal_cfg.parity = NRF_UARTE_PARITY_EXCLUDED; - break; +static int32_t ARM_USART_Control_Mode(uint32_t control, uint32_t arg, + UARTx_Resources *uart_resources) +{ + nrf_uarte_baudrate_t baudrate = uart_resources->baudrate; + nrf_uarte_config_t hal_cfg = uart_resources->hal_cfg; + switch (arg) { + case 1200: + baudrate = NRF_UARTE_BAUDRATE_1200; + break; + case 2400: + baudrate = NRF_UARTE_BAUDRATE_2400; + break; + case 4800: + baudrate = NRF_UARTE_BAUDRATE_4800; + break; + case 9600: + baudrate = NRF_UARTE_BAUDRATE_9600; + break; + case 14400: + baudrate = NRF_UARTE_BAUDRATE_14400; + break; + case 19200: + baudrate = NRF_UARTE_BAUDRATE_19200; + break; + case 28800: + baudrate = NRF_UARTE_BAUDRATE_28800; + break; + case 31250: + baudrate = NRF_UARTE_BAUDRATE_31250; + break; + case 38400: + baudrate = NRF_UARTE_BAUDRATE_38400; + break; + case 56000: + baudrate = NRF_UARTE_BAUDRATE_56000; + break; + case 57600: + baudrate = NRF_UARTE_BAUDRATE_57600; + break; + case 76800: + baudrate = NRF_UARTE_BAUDRATE_76800; + break; + case 115200: + baudrate = NRF_UARTE_BAUDRATE_115200; + break; + case 230400: + baudrate = NRF_UARTE_BAUDRATE_230400; + break; + case 250000: + baudrate = NRF_UARTE_BAUDRATE_250000; + break; + case 460800: + baudrate = NRF_UARTE_BAUDRATE_460800; + break; + case 921600: + baudrate = NRF_UARTE_BAUDRATE_921600; + break; + case 1000000: + baudrate = NRF_UARTE_BAUDRATE_1000000; + break; + default: + return ARM_USART_ERROR_BAUDRATE; + } + + if ((control & ARM_USART_DATA_BITS_Msk) != ARM_USART_DATA_BITS_8) { + return ARM_USART_ERROR_DATA_BITS; + } + + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: + hal_cfg.stop = NRF_UARTE_STOP_ONE; + break; + + case ARM_USART_STOP_BITS_2: + hal_cfg.stop = NRF_UARTE_STOP_TWO; + break; + + default: + return ARM_USART_ERROR_STOP_BITS; + } + + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: + hal_cfg.parity = NRF_UARTE_PARITY_EXCLUDED; + break; #if defined(UARTE_CONFIG_PARITYTYPE_Msk) - case ARM_USART_PARITY_EVEN: - hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; - hal_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN; - break; - - case ARM_USART_PARITY_ODD: - hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; - hal_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD; - break; + case ARM_USART_PARITY_EVEN: + hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; + hal_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN; + break; + + case ARM_USART_PARITY_ODD: + hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; + hal_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD; + break; #else - case ARM_USART_PARITY_EVEN: - hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; - break; + case ARM_USART_PARITY_EVEN: + hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; + break; #endif - default: - return ARM_USART_ERROR_PARITY; - } + default: + return ARM_USART_ERROR_PARITY; + } - switch (control & ARM_USART_FLOW_CONTROL_Msk) { - case ARM_USART_FLOW_CONTROL_NONE: - hal_cfg.hwfc = NRF_UARTE_HWFC_DISABLED; - break; + switch (control & ARM_USART_FLOW_CONTROL_Msk) { + case ARM_USART_FLOW_CONTROL_NONE: + hal_cfg.hwfc = NRF_UARTE_HWFC_DISABLED; + break; - case ARM_USART_FLOW_CONTROL_RTS_CTS: - hal_cfg.hwfc = NRF_UARTE_HWFC_ENABLED; - break; + case ARM_USART_FLOW_CONTROL_RTS_CTS: + hal_cfg.hwfc = NRF_UARTE_HWFC_ENABLED; + break; - default: - return ARM_USART_ERROR_FLOW_CONTROL; - } + default: + return ARM_USART_ERROR_FLOW_CONTROL; + } - uart_resources->baudrate = baudrate; - uart_resources->hal_cfg = hal_cfg; + uart_resources->baudrate = baudrate; + uart_resources->hal_cfg = hal_cfg; - nrf_uarte_baudrate_set(uart_resources->uarte.p_reg, - uart_resources->baudrate); - nrf_uarte_configure(uart_resources->uarte.p_reg, - &uart_resources->hal_cfg); + nrf_uarte_baudrate_set(uart_resources->uarte.p_reg, uart_resources->baudrate); + nrf_uarte_configure(uart_resources->uarte.p_reg, &uart_resources->hal_cfg); - return ARM_DRIVER_OK; + return ARM_DRIVER_OK; +} + +static void disconnect_tx_rx_pin(uint32_t operation, UARTx_Resources *uart_resources) +{ + bool uart_enabled = nrf_uarte_enable_check(uart_resources->uarte.p_reg); + + /* To update the PSEL register the UART needs to be disabled in case it is enabled */ + if (uart_enabled) { + nrf_uarte_disable(uart_resources->uarte.p_reg); + } + + switch (operation) { + case ARM_USART_CONTROL_RX: + nrf_uarte_rx_pin_set(uart_resources->uarte.p_reg, NRF_UARTE_PSEL_DISCONNECTED); + break; + case ARM_USART_CONTROL_TX: + nrf_uarte_tx_pin_set(uart_resources->uarte.p_reg, NRF_UARTE_PSEL_DISCONNECTED); + break; + default: + break; + } + + if (uart_enabled) { + nrf_uarte_enable(uart_resources->uarte.p_reg); + } +} + +static int32_t ARM_USARTx_Control(uint32_t control, uint32_t arg, UARTx_Resources *uart_resources) +{ + uint32_t operation = control & ARM_USART_CONTROL_Msk; + + switch (operation) { + case ARM_USART_MODE_ASYNCHRONOUS: + return ARM_USART_Control_Mode(control, arg, uart_resources); + case ARM_USART_CONTROL_RX: + case ARM_USART_CONTROL_TX: + /* There is not an option to enable/disable the receiver in the NRF devices. + * In case of disabling (arg == 0) what can be done is to release the pin + * which is used by the peripheral. + */ + if (arg == 0) { + disconnect_tx_rx_pin(operation, uart_resources); + } + return ARM_DRIVER_OK; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } } static ARM_USART_STATUS ARM_USART_GetStatus(void) From 7536f91798d15fd55c59e9f3571c3e4473237647 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Thu, 23 Oct 2025 14:19:30 +0300 Subject: [PATCH 109/133] [zep fromtree] platform: nordic_nrf: change includes of nrf.h to nrfx.h Starting with nrfx 4.0 nrfx.h must now be included instead of nrf.h. Prepare for the update of nrfx by updating the includes accordingly. Change-Id: Ic92f2d954ceebc79226681114abc7e0457fc01a6 Signed-off-by: Tomi Fontanilles (cherry picked from commit b913372934c7748600ad6ae3b69cdcee8c487293) --- .../target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c | 2 +- platform/ext/target/nordic_nrf/common/core/common/cmsis.h | 2 +- platform/ext/target/nordic_nrf/common/core/hw_init.c | 1 - .../nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c | 2 +- .../nordic_nrf/common/core/services/src/tfm_ioctl_core_s_api.c | 2 +- .../memory_service_ranges/tfm_platform_user_memory_ranges.h | 2 +- .../memory_service_ranges/tfm_platform_user_memory_ranges.h | 2 +- .../memory_service_ranges/tfm_platform_user_memory_ranges.h | 2 +- .../memory_service_ranges/tfm_platform_user_memory_ranges.h | 2 +- .../memory_service_ranges/tfm_platform_user_memory_ranges.h | 2 +- .../memory_service_ranges/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- .../services/include/tfm_platform_user_memory_ranges.h | 2 +- 18 files changed, 17 insertions(+), 18 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c index 9b18b1c2b8..54b540560c 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c @@ -22,7 +22,7 @@ #include #include -#include +#include #ifdef __NRF_TFM__ #include diff --git a/platform/ext/target/nordic_nrf/common/core/common/cmsis.h b/platform/ext/target/nordic_nrf/common/core/common/cmsis.h index f2ffa435d8..b3437887dd 100644 --- a/platform/ext/target/nordic_nrf/common/core/common/cmsis.h +++ b/platform/ext/target/nordic_nrf/common/core/common/cmsis.h @@ -32,6 +32,6 @@ #ifndef __NORDIC_NRF_CMSIS_H__ #define __NORDIC_NRF_CMSIS_H__ -#include +#include #endif /*__NORDIC_NRF_CMSIS_H__*/ diff --git a/platform/ext/target/nordic_nrf/common/core/hw_init.c b/platform/ext/target/nordic_nrf/common/core/hw_init.c index a64b3ce77f..5c56627c0f 100644 --- a/platform/ext/target/nordic_nrf/common/core/hw_init.c +++ b/platform/ext/target/nordic_nrf/common/core/hw_init.c @@ -6,7 +6,6 @@ #include #include -#include #include "array.h" #include diff --git a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c index 32f653a90e..8785018001 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c +++ b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "nrf.h" +#include #include #include #include diff --git a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_s_api.c b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_s_api.c index 4a1189e2f0..efb89e6285 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_s_api.c +++ b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_s_api.c @@ -5,7 +5,7 @@ */ -#include "nrf.h" +#include #include #include "tfm_platform_api.h" #include "tfm_ioctl_core_api.h" diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf5340/memory_service_ranges/tfm_platform_user_memory_ranges.h index be9c72f3b8..947c719b24 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/memory_service_ranges/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/common/nrf5340/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include #define FICR_BASE NRF_FICR_S_BASE diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54l15/memory_service_ranges/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/memory_service_ranges/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/common/nrf91/memory_service_ranges/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/common/nrf91/memory_service_ranges/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/memory_service_ranges/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/common/nrf91/memory_service_ranges/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h index be9c72f3b8..947c719b24 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include #define FICR_BASE NRF_FICR_S_BASE diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h index 0847daa215..eb62b563af 100644 --- a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include static const struct tfm_read_service_range ranges[] = { diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h index f1419bd6a2..90537775c1 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include #define FICR_BASE NRF_FICR_S_BASE diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h index 61c8fd0e23..716825817d 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h @@ -9,7 +9,7 @@ #include -#include "nrf.h" +#include #define FICR_BASE NRF_FICR_S_BASE From 9b47c05cc92dc2358ce5c525ae8c4f31c1615e1c Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Thu, 23 Oct 2025 14:22:17 +0300 Subject: [PATCH 110/133] [zep fromtree] platform: nordic_nrf: do not include the MDK in nrfx_config.h Starting from nrfx 4.0 nrf.h must not be included directly and because we are in the nrfx configuration header file we cannot include nrfx.h. So remove the include and instead of using MDK defines use device-specific compile definitions that are defined by TF-M. Change-Id: I23a7ab5a0def59317db7a35419da28643bbf706e Signed-off-by: Tomi Fontanilles (cherry picked from commit cb43291fb2032ee5b8bf7c277cc93c89fe749207) --- platform/ext/target/nordic_nrf/common/core/nrfx_config.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h index 93c0feafa7..35a5c79b83 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h +++ b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h @@ -36,13 +36,11 @@ #if RTE_FLASH0 -#include - -#if defined(NRF_NVMC_S) +#if defined(NRF5340_XXAA_APPLICATION) || defined(NRF91_SERIES) #define NRFX_NVMC_ENABLED 1 -#elif defined(NRF_RRAMC_S) +#elif defined(NRF54L_SERIES) #define NRFX_RRAMC_ENABLED 1 -#elif defined(NRF_MRAMC_S) +#elif defined(NRF71_SERIES) #define NRFX_MRAMC_ENABLED 1 #else #error "Unrecognized platform" From 2bf254cf157875cd88fecd21cd193d05b609ac86 Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Wed, 5 Nov 2025 14:04:43 +0100 Subject: [PATCH 111/133] [zep fromtree] platform: nordic_nrf: align to nrfx 4.0 Align common files. Change-Id: I73509382d31476f88c20dee42fde4de6126f565d Signed-off-by: Marcin Szymczyk (cherry picked from commit 8ff947dd53f91cc850ee05164d9df5e377a48fbd) --- platform/ext/target/nordic_nrf/common/core/CMakeLists.txt | 4 ++-- platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h | 2 +- platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt | 2 +- platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt | 4 ++-- .../ext/target/nordic_nrf/common/nrf5340/ns/CMakeLists.txt | 2 +- platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c | 1 - platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt | 2 +- platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt | 2 +- platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt | 2 +- .../ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt | 2 +- platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt | 4 ++-- platform/ext/target/nordic_nrf/common/nrf91/ns/CMakeLists.txt | 2 +- 18 files changed, 20 insertions(+), 21 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 333006d4de..b022ab9a77 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -82,7 +82,7 @@ target_include_directories(platform_s . native_drivers ${HAL_NORDIC_PATH}/nrfx - ${HAL_NORDIC_PATH}/nrfx/mdk + ${HAL_NORDIC_PATH}/nrfx/bsp/stable ${HAL_NORDIC_PATH}/nrfx/drivers/include common ${PLATFORM_DIR}/.. @@ -192,7 +192,7 @@ if(BL2) PUBLIC . ${HAL_NORDIC_PATH}/nrfx - ${HAL_NORDIC_PATH}/nrfx/mdk + ${HAL_NORDIC_PATH}/nrfx/bsp/stable ${HAL_NORDIC_PATH}/nrfx/drivers/include common PRIVATE diff --git a/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h b/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h index f8473d622b..51496570f4 100644 --- a/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h +++ b/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h @@ -35,7 +35,7 @@ /* Include the spm utilities for the SPM_ASSERT symbol */ #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt index 27fb4912e1..0257adce45 100644 --- a/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt @@ -54,7 +54,7 @@ target_include_directories(platform_ns . common ${HAL_NORDIC_PATH}/nrfx - ${HAL_NORDIC_PATH}/nrfx/mdk + ${HAL_NORDIC_PATH}/nrfx/bsp/stable ${HAL_NORDIC_PATH}/nrfx/drivers/include ${PLATFORM_DIR}/include ${PLATFORM_DIR}/ext/cmsis/Include diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt index af32d13a0c..ded298e7d6 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt @@ -28,7 +28,7 @@ endif() target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf5340_application.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf5340_application.c ) target_compile_definitions(platform_s @@ -44,7 +44,7 @@ if(BL2) target_sources(platform_bl2 PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf5340_application.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf5340_application.c ) target_compile_definitions(platform_bl2 diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf5340/ns/CMakeLists.txt index 52593d1255..b36a8047e2 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf5340/ns/CMakeLists.txt @@ -18,7 +18,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf5340_application.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf5340_application.c ) target_compile_definitions(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c index e457f93628..5963b9295c 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c +++ b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #ifndef BIT_MASK /* Use Zephyr BIT_MASK for unasigned integers */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt index fd83dd0f1c..8508a1e1d9 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt @@ -28,7 +28,7 @@ endif() target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ../nrf54l/nrf54l_init.c ) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt index 6e8396c35d..0c53e35d84 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt @@ -18,7 +18,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ) target_compile_definitions(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt index 71735a5410..17ac20142c 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt @@ -28,7 +28,7 @@ endif() target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ../nrf54l/nrf54l_init.c ) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt index 6e8396c35d..0c53e35d84 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt @@ -18,7 +18,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ) target_compile_definitions(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt index 118ebd0882..6a3d87316b 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt @@ -28,7 +28,7 @@ endif() target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ../nrf54l/nrf54l_init.c ) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt index 6e8396c35d..0c53e35d84 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt @@ -18,7 +18,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ) target_compile_definitions(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt index b189498b9e..7ec95e428d 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt @@ -28,7 +28,7 @@ endif() target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ../nrf54l/nrf54l_init.c ) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt index 6e8396c35d..0c53e35d84 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt @@ -18,7 +18,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf54l.c ) target_compile_definitions(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt index df11cccc26..a7696c8781 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt @@ -20,7 +20,7 @@ target_include_directories(platform_s target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf7120_enga.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf7120_enga.c ./nrf71_init.c ) diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt index 9fa367062d..52a569b360 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf7120/ns/CMakeLists.txt @@ -18,7 +18,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf7120_enga.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf7120_enga.c ) target_compile_definitions(platform_ns diff --git a/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt index 7f4d07f23a..92c0c680f7 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt @@ -28,7 +28,7 @@ endif() target_sources(platform_s PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf91.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf91.c ) target_compile_definitions(platform_s @@ -46,7 +46,7 @@ if(BL2) target_sources(platform_bl2 PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf91.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf91.c ) target_compile_definitions(platform_bl2 diff --git a/platform/ext/target/nordic_nrf/common/nrf91/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf91/ns/CMakeLists.txt index 290d7f4c53..d6dc558508 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf91/ns/CMakeLists.txt @@ -21,7 +21,7 @@ target_include_directories(platform_ns target_sources(platform_ns PRIVATE - ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf91.c + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf91.c ) target_compile_definitions(platform_ns From 757e8492a24dc08d24cdb870cf89a073756a0c7c Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Fri, 7 Nov 2025 15:19:07 +0100 Subject: [PATCH 112/133] [zep fromtree] platform: nrf: driver: usart: align to nrfx 4.0 and refactor Align with changes needed for nrfx 4.0. Refactor to use nrfx layer instead of HAL. Change-Id: Ibbffe2c2e27ea98ac08e0e23f4c33603c04fe5ea Signed-off-by: Marcin Szymczyk (cherry picked from commit f07f10b9c028ee1de036037264e6b1929432af1d) --- .../common/core/cmsis_drivers/Driver_USART.c | 134 +++++++++--------- 1 file changed, 67 insertions(+), 67 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c index 7c44cb3ac5..9c1f039581 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c @@ -42,23 +42,6 @@ #if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || \ RTE_UART00 || RTE_USART20 || RTE_UART21 || RTE_UART22 || RTE_USART30 -#define PSEL_DISCONNECTED 0xFFFFFFFFUL - -#define UART_CONFIG_INITIALIZER() \ -{ \ - .txd_pin = PSEL_DISCONNECTED, \ - .rxd_pin = PSEL_DISCONNECTED, \ - .rts_pin = PSEL_DISCONNECTED, \ - .cts_pin = PSEL_DISCONNECTED, \ - .baudrate = NRF_UARTE_BAUDRATE_115200, \ - .interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .config = { \ - .hwfc = NRF_UARTE_HWFC_DISABLED, \ - .parity = NRF_UARTE_PARITY_EXCLUDED, \ - .stop = NRF_UARTE_STOP_ONE, \ - }, \ -} - void uart_config_set_uart_pins(nrfx_uarte_config_t *uart_config, const uint32_t uart_pins[], size_t uart_pins_count) @@ -67,7 +50,7 @@ void uart_config_set_uart_pins(nrfx_uarte_config_t *uart_config, uint32_t psel = NRF_GET_PIN(uart_pins[i]); if (psel == NRF_PIN_DISCONNECTED) { - psel = PSEL_DISCONNECTED; + psel = NRF_UARTE_PSEL_DISCONNECTED; } switch (NRF_GET_FUN(uart_pins[i])) { @@ -89,14 +72,12 @@ static const ARM_USART_CAPABILITIES DriverCapabilities = { }; typedef struct { - const nrfx_uarte_t uarte; + nrfx_uarte_t uarte; const uint32_t *uart_pins; size_t uart_pins_count; size_t tx_count; size_t rx_count; - nrf_uarte_config_t hal_cfg; - nrf_uarte_baudrate_t baudrate; - bool initialized; + nrfx_uarte_config_t cfg; } UARTx_Resources; static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) @@ -119,25 +100,21 @@ static int32_t ARM_USARTx_Initialize(ARM_USART_SignalEvent_t cb_event, NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET((uint32_t)uart_resources->uarte.p_reg)); #endif - nrfx_uarte_config_t uart_config = UART_CONFIG_INITIALIZER(); - uart_config_set_uart_pins(&uart_config, + uart_config_set_uart_pins(&uart_resources->cfg, uart_resources->uart_pins, uart_resources->uart_pins_count); - nrfx_err_t err_code = nrfx_uarte_init(&uart_resources->uarte, - &uart_config, - NULL); - if (err_code != NRFX_SUCCESS) { + int err_code = nrfx_uarte_init(&uart_resources->uarte, + &uart_resources->cfg, + NULL); + if (err_code < 0) { return ARM_DRIVER_ERROR_BUSY; } uart_resources->tx_count = 0; uart_resources->rx_count = 0; - uart_resources->hal_cfg = uart_config.config; - uart_resources->baudrate = uart_config.baudrate; - uart_resources->initialized = true; return ARM_DRIVER_OK; } @@ -145,8 +122,6 @@ static int32_t ARM_USARTx_Uninitialize(UARTx_Resources *uart_resources) { nrfx_uarte_uninit(&uart_resources->uarte); - uart_resources->initialized = false; - #ifdef SPU_CONFIGURE_UART spu_peripheral_config_non_secure((uint32_t)uart_resources->uarte.p_reg, false); NVIC_SetTargetState(NRFX_IRQ_NUMBER_GET((uint32_t)uart_resources->uarte.p_reg)); @@ -181,7 +156,7 @@ static int32_t ARM_USARTx_PowerControl(ARM_POWER_STATE state, static int32_t ARM_USARTx_Send(const void *data, uint32_t num, UARTx_Resources *uart_resources) { - if (!uart_resources->initialized) { + if (!nrfx_uarte_init_check(&uart_resources->uarte)) { return ARM_DRIVER_ERROR; } @@ -198,10 +173,10 @@ static int32_t ARM_USARTx_Send(const void *data, uint32_t num, } } } else { - nrfx_err_t err_code = nrfx_uarte_tx(&uart_resources->uarte, data, num, 0); - if (err_code == NRFX_ERROR_BUSY) { + int err_code = nrfx_uarte_tx(&uart_resources->uarte, data, num, 0); + if (err_code == -EBUSY) { return ARM_DRIVER_ERROR_BUSY; - } else if (err_code != NRFX_SUCCESS) { + } else if (err_code < 0) { return ARM_DRIVER_ERROR; } @@ -214,14 +189,43 @@ static int32_t ARM_USARTx_Send(const void *data, uint32_t num, static int32_t ARM_USARTx_Receive(void *data, uint32_t num, UARTx_Resources *uart_resources) { - if (!uart_resources->initialized) { + if (!nrfx_uarte_init_check(&uart_resources->uarte)) { + return ARM_DRIVER_ERROR; + } + + int err_code = nrfx_uarte_rx_buffer_set(&uart_resources->uarte, data, num); + + if (err_code == -EBUSY) { + return ARM_DRIVER_ERROR_BUSY; + } else if (err_code < 0) { return ARM_DRIVER_ERROR; } - nrfx_err_t err_code = nrfx_uarte_rx(&uart_resources->uarte, data, num); - if (err_code == NRFX_ERROR_BUSY) { + uint32_t flags = NRFX_UARTE_RX_ENABLE_CONT | NRFX_UARTE_RX_ENABLE_STOP_ON_END; + err_code = nrfx_uarte_rx_enable(&uart_resources->uarte, flags); + + if (err_code == -EBUSY) { return ARM_DRIVER_ERROR_BUSY; - } else if (err_code != NRFX_SUCCESS) { + } else if (err_code < 0) { + return ARM_DRIVER_ERROR; + } + + size_t rx_amount = 0; + + do + { + err_code = nrfx_uarte_rx_ready(&uart_resources->uarte, &rx_amount); + } while (err_code == -EBUSY); + + if ((err_code == -EALREADY) || (num > rx_amount)) + { + return ARM_DRIVER_ERROR; + } + + err_code = nrfx_uarte_rx_abort(&uart_resources->uarte, true, true); + + if (err_code < 0) + { return ARM_DRIVER_ERROR; } @@ -253,8 +257,8 @@ static uint32_t ARM_USARTx_GetRxCount(const UARTx_Resources *uart_resources) static int32_t ARM_USART_Control_Mode(uint32_t control, uint32_t arg, UARTx_Resources *uart_resources) { - nrf_uarte_baudrate_t baudrate = uart_resources->baudrate; - nrf_uarte_config_t hal_cfg = uart_resources->hal_cfg; + nrf_uarte_baudrate_t baudrate = uart_resources->cfg.baudrate; + nrf_uarte_config_t hal_cfg = uart_resources->cfg.config; switch (arg) { case 1200: baudrate = NRF_UARTE_BAUDRATE_1200; @@ -369,37 +373,25 @@ static int32_t ARM_USART_Control_Mode(uint32_t control, uint32_t arg, return ARM_USART_ERROR_FLOW_CONTROL; } - uart_resources->baudrate = baudrate; - uart_resources->hal_cfg = hal_cfg; + uart_resources->cfg.baudrate = baudrate; + uart_resources->cfg.config = hal_cfg; - nrf_uarte_baudrate_set(uart_resources->uarte.p_reg, uart_resources->baudrate); - nrf_uarte_configure(uart_resources->uarte.p_reg, &uart_resources->hal_cfg); + nrfx_uarte_reconfigure(&uart_resources->uarte, &uart_resources->cfg); return ARM_DRIVER_OK; } -static void disconnect_tx_rx_pin(uint32_t operation, UARTx_Resources *uart_resources) +static int disconnect_tx_rx_pin(uint32_t operation, UARTx_Resources *uart_resources) { - bool uart_enabled = nrf_uarte_enable_check(uart_resources->uarte.p_reg); - - /* To update the PSEL register the UART needs to be disabled in case it is enabled */ - if (uart_enabled) { - nrf_uarte_disable(uart_resources->uarte.p_reg); - } - switch (operation) { case ARM_USART_CONTROL_RX: - nrf_uarte_rx_pin_set(uart_resources->uarte.p_reg, NRF_UARTE_PSEL_DISCONNECTED); - break; + uart_resources->cfg.rxd_pin = NRF_UARTE_PSEL_DISCONNECTED; + return nrfx_uarte_reconfigure(&uart_resources->uarte, &uart_resources->cfg); case ARM_USART_CONTROL_TX: - nrf_uarte_tx_pin_set(uart_resources->uarte.p_reg, NRF_UARTE_PSEL_DISCONNECTED); - break; + uart_resources->cfg.txd_pin = NRF_UARTE_PSEL_DISCONNECTED; + return nrfx_uarte_reconfigure(&uart_resources->uarte, &uart_resources->cfg); default: - break; - } - - if (uart_enabled) { - nrf_uarte_enable(uart_resources->uarte.p_reg); + return 0; } } @@ -417,7 +409,13 @@ static int32_t ARM_USARTx_Control(uint32_t control, uint32_t arg, UARTx_Resource * which is used by the peripheral. */ if (arg == 0) { - disconnect_tx_rx_pin(operation, uart_resources); + int err_code = disconnect_tx_rx_pin(operation, uart_resources); + + if (err_code == -EBUSY) { + return ARM_DRIVER_ERROR_BUSY; + } else if (err_code < 0) { + return ARM_DRIVER_ERROR; + } } return ARM_DRIVER_OK; default: @@ -446,9 +444,11 @@ static ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void) #define DRIVER_USART(idx) \ static const uint32_t UART##idx##_pins[] = RTE_USART##idx##_PINS; \ static UARTx_Resources UART##idx##_Resources = { \ - .uarte = NRFX_UARTE_INSTANCE(idx), \ + .uarte = NRFX_UARTE_INSTANCE(NRF_UARTE##idx), \ .uart_pins = UART##idx##_pins, \ - .uart_pins_count = ARRAY_SIZE(UART##idx##_pins) \ + .uart_pins_count = ARRAY_SIZE(UART##idx##_pins), \ + .cfg = NRFX_UARTE_DEFAULT_CONFIG(NRF_UARTE_PSEL_DISCONNECTED, \ + NRF_UARTE_PSEL_DISCONNECTED), \ }; \ static int32_t ARM_USART##idx##_Initialize( \ ARM_USART_SignalEvent_t cb_event) \ From 924890d5d55cc37f46be5770d463f232a9766642 Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Wed, 23 Apr 2025 09:54:15 +0200 Subject: [PATCH 113/133] [zep fromtree] platform: nordic_nrf: Fix broken path for NS in nRF54L Fix a path issue with the non secure application config.cmake file. The config.cmake for nRF54L10 and nRF54L15 is the same. To avoid duplicating the file the config.cmake is placed in a common nrf54l folder and it is included by each platforms config.cmake files. This doesn't work for the non secure application because the path does not exist. To fix that install to the non secure application the common file directly. Signed-off-by: Georgios Vasilakis Change-Id: I36d6bed5d1f2a71ed12f9004485accfcbca1b0d6 (cherry picked from commit 51352be0fde5b1d318bbe26ab03c08227542f399) --- platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt | 2 +- platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt index 8508a1e1d9..570d275416 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt @@ -47,8 +47,8 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake ns/CMakeLists.txt - config.cmake cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10 ) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt index 17ac20142c..a3c4a7be69 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt @@ -47,8 +47,8 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake ns/CMakeLists.txt - config.cmake cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l15 ) From 89670e9635280d0f0695116e2528081a376c05ca Mon Sep 17 00:00:00 2001 From: Anton Zyma Date: Mon, 20 Oct 2025 15:59:53 +0300 Subject: [PATCH 114/133] [zep fromtree] platform: nordic_nrf: Update copyright headers All copyright headers updated to comply with BSD-3-Clause. Change-Id: Ie36f8039cdf5fb6f3fa768c588850d95abaf0027 Signed-off-by: Anton Zyma (cherry picked from commit d33d42d6728172d7db69805d1c3985bd11a89455) --- .../nrf5340/tfm_peripherals_config_nrf5340_application.h | 5 +++++ platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h | 2 +- platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c | 2 +- .../target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h | 2 +- .../ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c | 2 +- .../common/nrf54l/tfm_peripherals_config_nrf54l.h | 6 ++++++ .../target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h | 2 +- platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h | 2 +- .../target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h | 2 +- .../common/nrf7120/tfm_peripherals_config_nrf71.h | 5 +++++ .../target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h | 2 +- .../nordic_nrf/common/nrf91/tfm_peripherals_config_nrf91.h | 5 +++++ .../nordic_nrf/nrf5340dk_nrf5340_cpuapp/cpuarch.cmake | 3 ++- .../nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake | 2 +- .../nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake | 3 ++- .../nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake | 5 +++-- .../nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake | 2 +- .../nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake | 3 ++- .../nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake | 5 +++-- .../nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake | 2 +- .../nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake | 3 ++- .../nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake | 5 +++-- .../nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake | 2 +- .../nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake | 3 ++- .../nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake | 5 +++-- .../nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake | 2 +- .../nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake | 3 ++- .../nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake | 5 +++-- .../ext/target/nordic_nrf/nrf9160dk_nrf9160/cpuarch.cmake | 3 ++- .../target/nordic_nrf/nrf9160dk_nrf9160/ns/cpuarch_ns.cmake | 3 ++- .../ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt | 3 ++- .../ext/target/nordic_nrf/nrf9161dk_nrf9161/config.cmake | 3 ++- .../ext/target/nordic_nrf/nrf9161dk_nrf9161/cpuarch.cmake | 3 ++- .../target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt | 5 +++-- .../target/nordic_nrf/nrf9161dk_nrf9161/ns/cpuarch_ns.cmake | 3 ++- 35 files changed, 76 insertions(+), 37 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_config_nrf5340_application.h b/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_config_nrf5340_application.h index 827a2ab3cd..ec2b6123ef 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_config_nrf5340_application.h +++ b/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_config_nrf5340_application.h @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ #ifndef TFM_PERIPHERAL_DCNF_SECURE #define TFM_PERIPHERAL_DCNF_SECURE 0 diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h index ab6e099e8a..408771c395 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2024 Nordic Semiconductor ASA * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c index 5963b9295c..02b6980c48 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c +++ b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2024, Nordic Semiconductor ASA. * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h b/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h index 814f022b4a..bceb069eac 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2024 Nordic Semiconductor ASA * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef NRFX_CONFIG_NRF54L15_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c index 1dff3596c7..4788e8539b 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2024, Nordic Semiconductor ASA. * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h index 12f3a003cc..ff1b733d38 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h @@ -1,3 +1,9 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ #ifndef TFM_PERIPHERAL_TIMER00_SECURE #define TFM_PERIPHERAL_TIMER00_SECURE 0 diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h index 77227a3fb7..9cb209a831 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2024 Nordic Semiconductor ASA * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h b/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h index 6e2ecf8e16..3260f8c369 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf7120/mmio_defs.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2025 Nordic Semiconductor ASA * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h b/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h index f5ae9de955..2072531aec 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h +++ b/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2025 Nordic Semiconductor ASA * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h index a03b92d317..30d96d98ee 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h +++ b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_config_nrf71.h @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ #ifndef TFM_PERIPHERAL_TIMER00_SECURE #define TFM_PERIPHERAL_TIMER00_SECURE 0 diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h index 7231c0018d..3c62f1cd99 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h +++ b/platform/ext/target/nordic_nrf/common/nrf7120/tfm_peripherals_def.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2025 Nordic Semiconductor ASA * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/platform/ext/target/nordic_nrf/common/nrf91/tfm_peripherals_config_nrf91.h b/platform/ext/target/nordic_nrf/common/nrf91/tfm_peripherals_config_nrf91.h index 0aa23eaf9e..f0166395ac 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/tfm_peripherals_config_nrf91.h +++ b/platform/ext/target/nordic_nrf/common/nrf91/tfm_peripherals_config_nrf91.h @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ #ifndef TFM_PERIPHERAL_REGULATORS_SECURE #define TFM_PERIPHERAL_REGULATORS_SECURE 0 diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/cpuarch.cmake index 631e6333ca..9c37b42af8 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake index 72efe7db74..1e9a834c6b 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake index eb59334c85..ff4814fd7b 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake index 97f8d12093..d41a48b7a7 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake index b2e0fb28b2..966e36fe02 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake index 3c4e406087..5c383ecee0 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake index 622a3414fc..25a0442659 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake index e3c56921db..745dd2565e 100644 --- a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------- # Copyright (c) 2025, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake index 721521cc08..5f985f74cb 100644 --- a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake index 23b1f06587..36b6eee72e 100644 --- a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake index 5d91d95708..f939c21c18 100644 --- a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------- # Copyright (c) 2025, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake index 9f1545d534..d8b404bd9a 100644 --- a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2025, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake index 58b5f3ac47..61d5144899 100644 --- a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2024, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake index 1779639f54..49e807f69f 100644 --- a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/config.cmake @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------- # Copyright (c) 2025, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake index 684b03cf43..e226910758 100644 --- a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2025, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake index e07ac6eb38..1fc44dab81 100644 --- a/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf7120pdk_nrf7120_cpuapp/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2025, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/cpuarch.cmake index 72de85b5b3..e26e6868eb 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/cpuarch_ns.cmake index 251e983cad..bb501c4a9d 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt index 33e914283b..cd78c7b3ec 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- cmake_policy(SET CMP0076 NEW) set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/config.cmake b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/config.cmake index 0c1626e5b1..32d2a64016 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/config.cmake +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/config.cmake @@ -1,7 +1,8 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- include(${PLATFORM_PATH}/common/nrf91/config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/cpuarch.cmake index 01bfb2e506..c60ecd12ba 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/cpuarch.cmake +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/cpuarch.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt index e65f7a9699..36171f7d2f 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- cmake_policy(SET CMP0076 NEW) set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/cpuarch_ns.cmake index c9c32ff6ff..038d8dceed 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/cpuarch_ns.cmake +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/cpuarch_ns.cmake @@ -1,8 +1,9 @@ -# +#------------------------------------------------------------------------------- # Copyright (c) 2023, Nordic Semiconductor ASA. # # SPDX-License-Identifier: BSD-3-Clause # +#------------------------------------------------------------------------------- set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) From 3b7ed79147c24352407933099b39b51d5fbc27e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dag=20Erik=20Gj=C3=B8rvad?= Date: Thu, 10 Jul 2025 15:18:21 +0200 Subject: [PATCH 115/133] [zep fromtree] Platform: nordic_nrf: Update HAL_NORIC to 3.12.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Updated tag to 3.12.1 Change-Id: I650d2f85e137c6d0c5af3206cc4daee66448af13 Signed-off-by: Dag Erik Gjørvad (cherry picked from commit dfdd45978d07bc7b44e4b7dcf3a9ea99d1295112) --- platform/ext/target/nordic_nrf/common/core/config.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/nordic_nrf/common/core/config.cmake b/platform/ext/target/nordic_nrf/common/core/config.cmake index 3fef000927..85fc75874c 100644 --- a/platform/ext/target/nordic_nrf/common/core/config.cmake +++ b/platform/ext/target/nordic_nrf/common/core/config.cmake @@ -9,7 +9,7 @@ #------------------------------------------------------------------------------- set(HAL_NORDIC_PATH "DOWNLOAD" CACHE PATH "Path to the Nordic HAL (or DOWNLOAD to fetch automatically)") -set(HAL_NORDIC_VERSION "nrfx-3.9.0" CACHE STRING "Version of the Nordic HAL to download") +set(HAL_NORDIC_VERSION "nrfx-3.12.1" CACHE STRING "Version of the Nordic HAL to download") set(HAL_NORDIC_REMOTE "https://github.com/zephyrproject-rtos/hal_nordic" CACHE STRING "Remote of the Nordic HAL to download") # Set to FALSE if HAL_NORDIC_VERSION is a SHA. set(HAL_NORDIC_SHALLOW_FETCH CACHE BOOL TRUE "Use shallow fetch to download Nordic HAL.") From 6c5b4ff9dd644d97e2e2e65b6be2466cad6b4524 Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Tue, 18 Nov 2025 12:13:52 +0100 Subject: [PATCH 116/133] [zep fromtree] platform: nrf: remove custom nrfx_config nrfx_config from nrfx's templates can be used. Change-Id: I5f532376ef0c9c73ec19b3933685a644a35a9c19 Signed-off-by: Marcin Szymczyk Signed-off-by: Tomi Fontanilles (cherry picked from commit 863c713b61c876bf3204871e17e6f7646a2e59be) --- .../nordic_nrf/common/core/CMakeLists.txt | 2 + .../nordic_nrf/common/core/nrfx_config.h | 12 +- .../nordic_nrf/common/core/ns/CMakeLists.txt | 1 + .../nordic_nrf/common/nrf5340/CMakeLists.txt | 3 +- .../nrf5340/nrfx_config_nrf5340_application.h | 2158 ----------------- .../common/nrf54l/nrfx_config_nrf54l.h | 74 - .../nordic_nrf/common/nrf54l10/CMakeLists.txt | 3 +- .../nordic_nrf/common/nrf54l15/CMakeLists.txt | 3 +- .../common/nrf54lm20a/CMakeLists.txt | 3 +- .../common/nrf54lv10a/CMakeLists.txt | 3 +- .../nordic_nrf/common/nrf7120/CMakeLists.txt | 3 +- .../common/nrf7120/nrfx_config_nrf71.h | 74 - .../nordic_nrf/common/nrf91/CMakeLists.txt | 3 +- .../common/nrf91/nrfx_config_nrf91.h | 1657 ------------- 14 files changed, 11 insertions(+), 3988 deletions(-) delete mode 100644 platform/ext/target/nordic_nrf/common/nrf5340/nrfx_config_nrf5340_application.h delete mode 100644 platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h delete mode 100644 platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h delete mode 100644 platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index b022ab9a77..81fdef31b0 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -83,6 +83,7 @@ target_include_directories(platform_s native_drivers ${HAL_NORDIC_PATH}/nrfx ${HAL_NORDIC_PATH}/nrfx/bsp/stable + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/templates ${HAL_NORDIC_PATH}/nrfx/drivers/include common ${PLATFORM_DIR}/.. @@ -193,6 +194,7 @@ if(BL2) . ${HAL_NORDIC_PATH}/nrfx ${HAL_NORDIC_PATH}/nrfx/bsp/stable + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/templates ${HAL_NORDIC_PATH}/nrfx/drivers/include common PRIVATE diff --git a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h index 35a5c79b83..eba5c7b961 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h +++ b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h @@ -96,16 +96,6 @@ #define NRF_PERIPH(P) P##_S #endif -#if defined(NRF5340_XXAA_APPLICATION) - #include -#elif defined(NRF91_SERIES) - #include -#elif defined(NRF54L_SERIES) - #include -#elif defined(NRF71_SERIES) - #include -#else - #error "Unknown device." -#endif +#include #endif // NRFX_CONFIG_H__ diff --git a/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt index 0257adce45..f4cd8852df 100644 --- a/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/ns/CMakeLists.txt @@ -55,6 +55,7 @@ target_include_directories(platform_ns common ${HAL_NORDIC_PATH}/nrfx ${HAL_NORDIC_PATH}/nrfx/bsp/stable + ${HAL_NORDIC_PATH}/nrfx/bsp/stable/templates ${HAL_NORDIC_PATH}/nrfx/drivers/include ${PLATFORM_DIR}/include ${PLATFORM_DIR}/ext/cmsis/Include diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt index ded298e7d6..480a1e52a2 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt @@ -62,8 +62,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES nrfx_config_nrf5340_application.h - ns/CMakeLists.txt +install(FILES ns/CMakeLists.txt config.cmake cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf5340 diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/nrfx_config_nrf5340_application.h b/platform/ext/target/nordic_nrf/common/nrf5340/nrfx_config_nrf5340_application.h deleted file mode 100644 index a48cc77870..0000000000 --- a/platform/ext/target/nordic_nrf/common/nrf5340/nrfx_config_nrf5340_application.h +++ /dev/null @@ -1,2158 +0,0 @@ -/* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef NRFX_CONFIG_NRF5340_APPLICATION_H__ -#define NRFX_CONFIG_NRF5340_APPLICATION_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -#define NRF_CLOCK NRF_PERIPH(NRF_CLOCK) -#define NRF_COMP NRF_PERIPH(NRF_COMP) -#define NRF_CTRLAP NRF_PERIPH(NRF_CTRLAP) -#define NRF_DCNF NRF_PERIPH(NRF_DCNF) -#define NRF_DPPIC NRF_PERIPH(NRF_DPPIC) -#define NRF_EGU0 NRF_PERIPH(NRF_EGU0) -#define NRF_EGU1 NRF_PERIPH(NRF_EGU1) -#define NRF_EGU2 NRF_PERIPH(NRF_EGU2) -#define NRF_EGU3 NRF_PERIPH(NRF_EGU3) -#define NRF_EGU4 NRF_PERIPH(NRF_EGU4) -#define NRF_EGU5 NRF_PERIPH(NRF_EGU5) -#define NRF_FPU NRF_PERIPH(NRF_FPU) -#define NRF_I2S0 NRF_PERIPH(NRF_I2S0) -#define NRF_IPC NRF_PERIPH(NRF_IPC) -#define NRF_KMU NRF_PERIPH(NRF_KMU) -#define NRF_LPCOMP NRF_PERIPH(NRF_LPCOMP) -#define NRF_MUTEX NRF_PERIPH(NRF_MUTEX) -#define NRF_NFCT NRF_PERIPH(NRF_NFCT) -#define NRF_NVMC NRF_PERIPH(NRF_NVMC) -#define NRF_OSCILLATORS NRF_PERIPH(NRF_OSCILLATORS) -#define NRF_P0 NRF_PERIPH(NRF_P0) -#define NRF_P1 NRF_PERIPH(NRF_P1) -#define NRF_PDM0 NRF_PERIPH(NRF_PDM0) -#define NRF_POWER NRF_PERIPH(NRF_POWER) -#define NRF_PWM0 NRF_PERIPH(NRF_PWM0) -#define NRF_PWM1 NRF_PERIPH(NRF_PWM1) -#define NRF_PWM2 NRF_PERIPH(NRF_PWM2) -#define NRF_PWM3 NRF_PERIPH(NRF_PWM3) -#define NRF_QDEC0 NRF_PERIPH(NRF_QDEC0) -#define NRF_QDEC1 NRF_PERIPH(NRF_QDEC1) -#define NRF_QSPI NRF_PERIPH(NRF_QSPI) -#define NRF_REGULATORS NRF_PERIPH(NRF_REGULATORS) -#define NRF_RESET NRF_PERIPH(NRF_RESET) -#define NRF_RTC0 NRF_PERIPH(NRF_RTC0) -#define NRF_RTC1 NRF_PERIPH(NRF_RTC1) -#define NRF_SAADC NRF_PERIPH(NRF_SAADC) -#define NRF_SPIM0 NRF_PERIPH(NRF_SPIM0) -#define NRF_SPIM1 NRF_PERIPH(NRF_SPIM1) -#define NRF_SPIM2 NRF_PERIPH(NRF_SPIM2) -#define NRF_SPIM3 NRF_PERIPH(NRF_SPIM3) -#define NRF_SPIM4 NRF_PERIPH(NRF_SPIM4) -#define NRF_SPIS0 NRF_PERIPH(NRF_SPIS0) -#define NRF_SPIS1 NRF_PERIPH(NRF_SPIS1) -#define NRF_SPIS2 NRF_PERIPH(NRF_SPIS2) -#define NRF_SPIS3 NRF_PERIPH(NRF_SPIS3) -#define NRF_TIMER0 NRF_PERIPH(NRF_TIMER0) -#define NRF_TIMER1 NRF_PERIPH(NRF_TIMER1) -#define NRF_TIMER2 NRF_PERIPH(NRF_TIMER2) -#define NRF_TWIM0 NRF_PERIPH(NRF_TWIM0) -#define NRF_TWIM1 NRF_PERIPH(NRF_TWIM1) -#define NRF_TWIM2 NRF_PERIPH(NRF_TWIM2) -#define NRF_TWIM3 NRF_PERIPH(NRF_TWIM3) -#define NRF_TWIS0 NRF_PERIPH(NRF_TWIS0) -#define NRF_TWIS1 NRF_PERIPH(NRF_TWIS1) -#define NRF_TWIS2 NRF_PERIPH(NRF_TWIS2) -#define NRF_TWIS3 NRF_PERIPH(NRF_TWIS3) -#define NRF_UARTE0 NRF_PERIPH(NRF_UARTE0) -#define NRF_UARTE1 NRF_PERIPH(NRF_UARTE1) -#define NRF_UARTE2 NRF_PERIPH(NRF_UARTE2) -#define NRF_UARTE3 NRF_PERIPH(NRF_UARTE3) -#define NRF_USBD NRF_PERIPH(NRF_USBD) -#define NRF_USBREGULATOR NRF_PERIPH(NRF_USBREGULATOR) -#define NRF_VMC NRF_PERIPH(NRF_VMC) -#define NRF_WDT0 NRF_PERIPH(NRF_WDT0) -#define NRF_WDT1 NRF_PERIPH(NRF_WDT1) - -/* - * The following section provides the name translation for peripherals with - * only one type of access available. For these peripherals, you cannot choose - * between secure and non-secure mapping. - */ -#if defined(NRF_TRUSTZONE_NONSECURE) -#define NRF_GPIOTE1 NRF_GPIOTE1_NS -#else -#define NRF_CACHE NRF_CACHE_S -#define NRF_CACHEINFO NRF_CACHEINFO_S -#define NRF_CACHEDATA NRF_CACHEDATA_S -#define NRF_CRYPTOCELL NRF_CRYPTOCELL_S -#define NRF_CTI NRF_CTI_S -#define NRF_FICR NRF_FICR_S -#define NRF_GPIOTE0 NRF_GPIOTE0_S -#define NRF_SPU NRF_SPU_S -#define NRF_TAD NRF_TAD_S -#define NRF_UICR NRF_UICR_S -#endif - -/* Fixup for the QDEC driver. */ -#define NRF_QDEC NRF_QDEC0 - -/* Fixup for the GPIOTE driver. */ -#if defined(NRF_TRUSTZONE_NONSECURE) -#define NRF_GPIOTE NRF_GPIOTE1 -#else -#define NRF_GPIOTE NRF_GPIOTE0 -#endif - - -// <<< Use Configuration Wizard in Context Menu >>>\n - -// nRF_Drivers - -// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver. -//========================================================== -#ifndef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LF_SRC - LF clock source. - -// <0=> ULP -// <1=> RC -// <2=> XTAL -// <3=> Synth - -#ifndef NRFX_CLOCK_CONFIG_LF_SRC -#define NRFX_CLOCK_CONFIG_LF_SRC 2 -#endif - -// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support - -#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED -#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 -#endif - -// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure - -// If set to a non-zero value, LFRC will be started before LFXO and corresponding -// event will be generated. It means that CPU will be woken up when LFRC -// oscillator starts, but user callback will be invoked only after LFXO -// finally starts. - -#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED -#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 -#endif - - -// NRFX_CLOCK_CONFIG_HFCLK192M_SRC - HFCLK192M source. - -// <0=> HFINT -// <1=> HFXO - -#ifndef NRFX_CLOCK_CONFIG_HFCLK192M_SRC -#define NRFX_CLOCK_CONFIG_HFCLK192M_SRC 1 -#endif - -// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED -#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL -#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR -#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR -#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver -//========================================================== -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -// NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_COMP_CONFIG_INFO_COLOR -#define NRFX_COMP_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR -#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_DPPI_ENABLED - nrfx_dppi - DPPI allocator. -//========================================================== -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif -// NRFX_DPPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_DPPI_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_DPPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_DPPI_CONFIG_INFO_COLOR -#define NRFX_DPPI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_DPPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_DPPI_CONFIG_DEBUG_COLOR -#define NRFX_DPPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver. -//========================================================== -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -// NRFX_EGU0_ENABLED - Enable EGU0 instance. - -#ifndef NRFX_EGU0_ENABLED -#define NRFX_EGU0_ENABLED 0 -#endif - -// NRFX_EGU1_ENABLED - Enable EGU1 instance. - -#ifndef NRFX_EGU1_ENABLED -#define NRFX_EGU1_ENABLED 0 -#endif - -// NRFX_EGU2_ENABLED - Enable EGU2 instance. - -#ifndef NRFX_EGU2_ENABLED -#define NRFX_EGU2_ENABLED 0 -#endif - -// NRFX_EGU3_ENABLED - Enable EGU3 instance. - -#ifndef NRFX_EGU3_ENABLED -#define NRFX_EGU3_ENABLED 0 -#endif - -// NRFX_EGU4_ENABLED - Enable EGU4 instance. - -#ifndef NRFX_EGU4_ENABLED -#define NRFX_EGU4_ENABLED 0 -#endif - -// NRFX_EGU5_ENABLED - Enable EGU5 instance. - -#ifndef NRFX_EGU5_ENABLED -#define NRFX_EGU5_ENABLED 0 -#endif - -// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver. -//========================================================== -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins. -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR -#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR -#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver. -//========================================================== -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 0 -#endif - -// NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_I2S_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_INFO_COLOR -#define NRFX_I2S_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR -#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_IPC_ENABLED - nrfx_ipc - IPC peripheral driver -//========================================================== -#ifndef NRFX_IPC_ENABLED -#define NRFX_IPC_ENABLED 0 -#endif - -// - -// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver -//========================================================== -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -// NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR -#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR -#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver -//========================================================== -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif -// NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. - -// <0=> 0 -// <1=> 1 -// <2=> 2 - -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 2 -#endif - -// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_NFCT_CONFIG_INFO_COLOR -#define NRFX_NFCT_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR -#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver -//========================================================== -#ifndef NRFX_NVMC_ENABLED -#define NRFX_NVMC_ENABLED 0 -#endif - -// - -// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver. -//========================================================== -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -// NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PDM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_INFO_COLOR -#define NRFX_PDM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR -#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver. -//========================================================== -#ifndef NRFX_POWER_ENABLED -#define NRFX_POWER_ENABLED 0 -#endif -// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing (PRS) module. -//========================================================== -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif -// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. - - -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. - - -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. - - -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module. - - -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module. - - -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - - -// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PRS_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PRS_CONFIG_INFO_COLOR -#define NRFX_PRS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR -#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver. -//========================================================== -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif -// NRFX_PWM0_ENABLED - Enables PWM0 instance. - - -#ifndef NRFX_PWM0_ENABLED -#define NRFX_PWM0_ENABLED 0 -#endif - -// NRFX_PWM1_ENABLED - Enables PWM1 instance. - - -#ifndef NRFX_PWM1_ENABLED -#define NRFX_PWM1_ENABLED 0 -#endif - -// NRFX_PWM2_ENABLED - Enables PWM2 instance. - - -#ifndef NRFX_PWM2_ENABLED -#define NRFX_PWM2_ENABLED 0 -#endif - -// NRFX_PWM3_ENABLED - Enables PWM3 instance. - - -#ifndef NRFX_PWM3_ENABLED -#define NRFX_PWM3_ENABLED 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PWM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_INFO_COLOR -#define NRFX_PWM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR -#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver -//========================================================== -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -// NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_QDEC_CONFIG_INFO_COLOR -#define NRFX_QDEC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR -#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver -//========================================================== -#ifndef NRFX_QSPI_ENABLED -#define NRFX_QSPI_ENABLED 0 -#endif - -// NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver. -//========================================================== -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif -// NRFX_RTC0_ENABLED - Enables RTC0 instance. - - -#ifndef NRFX_RTC0_ENABLED -#define NRFX_RTC0_ENABLED 0 -#endif - -// NRFX_RTC1_ENABLED - Enables RTC1 instance. - - -#ifndef NRFX_RTC1_ENABLED -#define NRFX_RTC1_ENABLED 0 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_RTC_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_INFO_COLOR -#define NRFX_RTC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR -#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver. -//========================================================== -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SAADC_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_INFO_COLOR -#define NRFX_SAADC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR -#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver. -//========================================================== -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif -// NRFX_SPIM0_ENABLED - Enables SPIM0 instance. - - -#ifndef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 0 -#endif - -// NRFX_SPIM1_ENABLED - Enables SPIM1 instance. - - -#ifndef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED 0 -#endif - -// NRFX_SPIM2_ENABLED - Enables SPIM2 instance. - - -#ifndef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED 0 -#endif - -// NRFX_SPIM3_ENABLED - Enables SPIM3 instance. - - -#ifndef NRFX_SPIM3_ENABLED -#define NRFX_SPIM3_ENABLED 0 -#endif - -// NRFX_SPIM4_ENABLED - Enables SPIM4 instance. - - -#ifndef NRFX_SPIM4_ENABLED -#define NRFX_SPIM4_ENABLED 0 -#endif - -// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features - - -#ifndef NRFX_SPIM_EXTENDED_ENABLED -#define NRFX_SPIM_EXTENDED_ENABLED 0 -#endif - -// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_INFO_COLOR -#define NRFX_SPIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR -#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver. -//========================================================== -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif -// NRFX_SPIS0_ENABLED - Enables SPIS0 instance. - - -#ifndef NRFX_SPIS0_ENABLED -#define NRFX_SPIS0_ENABLED 0 -#endif - -// NRFX_SPIS1_ENABLED - Enables SPIS1 instance. - - -#ifndef NRFX_SPIS1_ENABLED -#define NRFX_SPIS1_ENABLED 0 -#endif - -// NRFX_SPIS2_ENABLED - Enables SPIS2 instance. - - -#ifndef NRFX_SPIS2_ENABLED -#define NRFX_SPIS2_ENABLED 0 -#endif - -// NRFX_SPIS3_ENABLED - Enables SPIS3 instance. - - -#ifndef NRFX_SPIS3_ENABLED -#define NRFX_SPIS3_ENABLED 0 -#endif - -// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIS_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_INFO_COLOR -#define NRFX_SPIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR -#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver. - - -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 0 -#endif - -// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver. -//========================================================== -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif -// NRFX_TIMER0_ENABLED - Enables TIMER0 instance. - - -#ifndef NRFX_TIMER0_ENABLED -#define NRFX_TIMER0_ENABLED 0 -#endif - -// NRFX_TIMER1_ENABLED - Enables TIMER1 instance. - - -#ifndef NRFX_TIMER1_ENABLED -#define NRFX_TIMER1_ENABLED 0 -#endif - -// NRFX_TIMER2_ENABLED - Enables TIMER2 instance. - - -#ifndef NRFX_TIMER2_ENABLED -#define NRFX_TIMER2_ENABLED 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TIMER_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_INFO_COLOR -#define NRFX_TIMER_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR -#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver. -//========================================================== -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif -// NRFX_TWIM0_ENABLED - Enables TWIM0 instance. - - -#ifndef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED 0 -#endif - -// NRFX_TWIM1_ENABLED - Enables TWIM1 instance. - - -#ifndef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED 0 -#endif - -// NRFX_TWIM2_ENABLED - Enables TWIM2 instance. - - -#ifndef NRFX_TWIM2_ENABLED -#define NRFX_TWIM2_ENABLED 0 -#endif - -// NRFX_TWIM3_ENABLED - Enables TWIM3 instance. - - -#ifndef NRFX_TWIM3_ENABLED -#define NRFX_TWIM3_ENABLED 0 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_INFO_COLOR -#define NRFX_TWIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR -#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver. -//========================================================== -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -// NRFX_TWIS0_ENABLED - Enables TWIS0 instance. - -#ifndef NRFX_TWIS0_ENABLED -#define NRFX_TWIS0_ENABLED 0 -#endif - -// NRFX_TWIS1_ENABLED - Enables TWIS1 instance. - -#ifndef NRFX_TWIS1_ENABLED -#define NRFX_TWIS1_ENABLED 0 -#endif - -// NRFX_TWIS2_ENABLED - Enables TWIS2 instance. - -#ifndef NRFX_TWIS2_ENABLED -#define NRFX_TWIS2_ENABLED 0 -#endif - -// NRFX_TWIS3_ENABLED - Enables TWIS3 instance. - -#ifndef NRFX_TWIS3_ENABLED -#define NRFX_TWIS3_ENABLED 0 -#endif - -// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assumes that any instance would be initialized only once. - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// NRFX_TWIS_NO_SYNC_MODE - Removes support for synchronous mode. - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIS_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_INFO_COLOR -#define NRFX_TWIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR -#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver. -//========================================================== -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif -// NRFX_UARTE0_ENABLED - Enables UARTE0 instances -#ifndef NRFX_UARTE0_ENABLED -#define NRFX_UARTE0_ENABLED 0 -#endif - -// NRFX_UARTE1_ENABLED - Enables UARTE1 instance. -#ifndef NRFX_UARTE1_ENABLED -#define NRFX_UARTE1_ENABLED 0 -#endif - -// NRFX_UARTE2_ENABLED - Enables UARTE2 instance. -#ifndef NRFX_UARTE2_ENABLED -#define NRFX_UARTE2_ENABLED 0 -#endif - -// NRFX_UARTE3_ENABLED - Enables UARTE3 instance. -#ifndef NRFX_UARTE3_ENABLED -#define NRFX_UARTE3_ENABLED 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_UARTE_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_INFO_COLOR -#define NRFX_UARTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR -#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver -//========================================================== -#ifndef NRFX_USBD_ENABLED -#define NRFX_USBD_ENABLED 0 -#endif -// NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers - -// This option gives priority to isochronous transfers. -// Enabling it assures that isochronous transfers are always processed, -// even if multiple other transfers are pending. -// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm -// function is called, so the option is independent of the algorithm chosen. - -#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST -#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 -#endif - -// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready - - -// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. -// Else, there will be no response. - -#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP -#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0 -#endif - -// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module -//========================================================== -#ifndef NRFX_USBD_CONFIG_LOG_ENABLED -#define NRFX_USBD_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_USBD_CONFIG_LOG_LEVEL -#define NRFX_USBD_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_USBD_CONFIG_INFO_COLOR -#define NRFX_USBD_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR -#define NRFX_USBD_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_USBREG_ENABLED - nrfx_usbreg - USBREG peripheral driver -//========================================================== -#ifndef NRFX_USBREG_ENABLED -#define NRFX_USBREG_ENABLED 0 -#endif -// NRFX_USBREG_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_USBREG_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_USBREG_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// - -// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver. -//========================================================== -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif -// NRFX_WDT0_ENABLED - Enable WDT0 instance. - - -#ifndef NRFX_WDT0_ENABLED -#define NRFX_WDT0_ENABLED 0 -#endif - -// NRFX_WDT1_ENABLED - Enable WDT1 instance. - - -#ifndef NRFX_WDT1_ENABLED -#define NRFX_WDT1_ENABLED 0 -#endif - -// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver. - -// <0=> Include WDT IRQ handling -// <1=> Remove WDT IRQ handling - -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_WDT_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_INFO_COLOR -#define NRFX_WDT_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR -#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// - -#endif // NRFX_CONFIG_NRF5340_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h b/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h deleted file mode 100644 index bceb069eac..0000000000 --- a/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef NRFX_CONFIG_NRF54L15_APPLICATION_H__ -#define NRFX_CONFIG_NRF54L15_APPLICATION_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0 Maximum: 7 - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 7 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0 Maximum: 7 - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RRAMC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RRAMC_ENABLED -#define NRFX_RRAMC_ENABLED 0 -#endif - -/** - * @brief NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RRAMC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RRAMC_CONFIG_LOG_ENABLED -#define NRFX_RRAMC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RRAMC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RRAMC_CONFIG_LOG_LEVEL -#define NRFX_RRAMC_CONFIG_LOG_LEVEL 3 -#endif - -#endif // NRFX_CONFIG_NRF54L15_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt index 570d275416..de4a40fac3 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt @@ -46,8 +46,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES ../nrf54l/nrfx_config_nrf54l.h - ../nrf54l/config.cmake +install(FILES ../nrf54l/config.cmake ns/CMakeLists.txt cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10 diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt index a3c4a7be69..3b86f89a1e 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt @@ -46,8 +46,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES ../nrf54l/nrfx_config_nrf54l.h - ../nrf54l/config.cmake +install(FILES ../nrf54l/config.cmake ns/CMakeLists.txt cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l15 diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt index 6a3d87316b..c3d6d61b81 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt @@ -46,8 +46,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES ../nrf54l/nrfx_config_nrf54l.h - ../nrf54l/config.cmake +install(FILES ../nrf54l/config.cmake ns/CMakeLists.txt cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lm20a diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt index 7ec95e428d..2078fb76af 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt @@ -46,8 +46,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES ../nrf54l/nrfx_config_nrf54l.h - ../nrf54l/config.cmake +install(FILES ../nrf54l/config.cmake ns/CMakeLists.txt cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lv10a diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt index a7696c8781..9e3f758d64 100644 --- a/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt @@ -38,8 +38,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES ./nrfx_config_nrf71.h - ./config.cmake +install(FILES ./config.cmake ns/CMakeLists.txt cpuarch.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf7120 diff --git a/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h b/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h deleted file mode 100644 index 2072531aec..0000000000 --- a/platform/ext/target/nordic_nrf/common/nrf7120/nrfx_config_nrf71.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ -#define NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0 Maximum: 7 - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 7 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0 Maximum: 7 - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_MRAMC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MRAMC_ENABLED -#define NRFX_MRAMC_ENABLED 0 -#endif - -/** - * @brief NRFX_MRAMC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_MRAMC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_MRAMC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_MRAMC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MRAMC_CONFIG_LOG_ENABLED -#define NRFX_MRAMC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_MRAMC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_MRAMC_CONFIG_LOG_LEVEL -#define NRFX_MRAMC_CONFIG_LOG_LEVEL 3 -#endif - -#endif // NRFX_CONFIG_NRF7120_ENGA_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt index 92c0c680f7..10e1619a83 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt @@ -64,8 +64,7 @@ target_sources(tfm_spm #========================= Files for building NS side platform ================# -install(FILES nrfx_config_nrf91.h - ns/CMakeLists.txt +install(FILES ns/CMakeLists.txt config.cmake DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf91 ) diff --git a/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h b/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h deleted file mode 100644 index e95f3920a4..0000000000 --- a/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h +++ /dev/null @@ -1,1657 +0,0 @@ -/* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef NRFX_CONFIG_NRF91_H__ -#define NRFX_CONFIG_NRF91_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/* - * The MDK for nRF9120 used in the nRF9161 target doesn't define the Secure FPU - * as it doesn't exist, but for other platforms like the 9160 it has a dummy - * define. - * Therefore we define it here manually until it is fixed in the MDK. - * See: NCSDK-23046 - */ -#ifdef NRF9120_XXAA -#define NRF_FPU_S 1 -#endif - -#define NRF_CLOCK NRF_PERIPH(NRF_CLOCK) -#define NRF_DPPIC NRF_PERIPH(NRF_DPPIC) -#define NRF_EGU0 NRF_PERIPH(NRF_EGU0) -#define NRF_EGU1 NRF_PERIPH(NRF_EGU1) -#define NRF_EGU2 NRF_PERIPH(NRF_EGU2) -#define NRF_EGU3 NRF_PERIPH(NRF_EGU3) -#define NRF_EGU4 NRF_PERIPH(NRF_EGU4) -#define NRF_EGU5 NRF_PERIPH(NRF_EGU5) -#define NRF_FPU NRF_PERIPH(NRF_FPU) -#define NRF_IPC NRF_PERIPH(NRF_IPC) -#define NRF_I2S NRF_PERIPH(NRF_I2S) -#define NRF_KMU NRF_PERIPH(NRF_KMU) -#define NRF_NVMC NRF_PERIPH(NRF_NVMC) -#define NRF_P0 NRF_PERIPH(NRF_P0) -#define NRF_PDM NRF_PERIPH(NRF_PDM) -#define NRF_POWER NRF_PERIPH(NRF_POWER) -#define NRF_PWM0 NRF_PERIPH(NRF_PWM0) -#define NRF_PWM1 NRF_PERIPH(NRF_PWM1) -#define NRF_PWM2 NRF_PERIPH(NRF_PWM2) -#define NRF_PWM3 NRF_PERIPH(NRF_PWM3) -#define NRF_REGULATORS NRF_PERIPH(NRF_REGULATORS) -#define NRF_RTC0 NRF_PERIPH(NRF_RTC0) -#define NRF_RTC1 NRF_PERIPH(NRF_RTC1) -#define NRF_SAADC NRF_PERIPH(NRF_SAADC) -#define NRF_SPIM0 NRF_PERIPH(NRF_SPIM0) -#define NRF_SPIM1 NRF_PERIPH(NRF_SPIM1) -#define NRF_SPIM2 NRF_PERIPH(NRF_SPIM2) -#define NRF_SPIM3 NRF_PERIPH(NRF_SPIM3) -#define NRF_SPIS0 NRF_PERIPH(NRF_SPIS0) -#define NRF_SPIS1 NRF_PERIPH(NRF_SPIS1) -#define NRF_SPIS2 NRF_PERIPH(NRF_SPIS2) -#define NRF_SPIS3 NRF_PERIPH(NRF_SPIS3) -#define NRF_TIMER0 NRF_PERIPH(NRF_TIMER0) -#define NRF_TIMER1 NRF_PERIPH(NRF_TIMER1) -#define NRF_TIMER2 NRF_PERIPH(NRF_TIMER2) -#define NRF_TWIM0 NRF_PERIPH(NRF_TWIM0) -#define NRF_TWIM1 NRF_PERIPH(NRF_TWIM1) -#define NRF_TWIM2 NRF_PERIPH(NRF_TWIM2) -#define NRF_TWIM3 NRF_PERIPH(NRF_TWIM3) -#define NRF_TWIS0 NRF_PERIPH(NRF_TWIS0) -#define NRF_TWIS1 NRF_PERIPH(NRF_TWIS1) -#define NRF_TWIS2 NRF_PERIPH(NRF_TWIS2) -#define NRF_TWIS3 NRF_PERIPH(NRF_TWIS3) -#define NRF_UARTE0 NRF_PERIPH(NRF_UARTE0) -#define NRF_UARTE1 NRF_PERIPH(NRF_UARTE1) -#define NRF_UARTE2 NRF_PERIPH(NRF_UARTE2) -#define NRF_UARTE3 NRF_PERIPH(NRF_UARTE3) -#define NRF_VMC NRF_PERIPH(NRF_VMC) -#define NRF_WDT NRF_PERIPH(NRF_WDT) - -/* - * The following section provides the name translation for peripherals with - * only one type of access available. For these peripherals, you cannot choose - * between secure and non-secure mapping. - */ -#if defined(NRF_TRUSTZONE_NONSECURE) -#define NRF_GPIOTE1 NRF_GPIOTE1_NS -#else -#define NRF_CC_HOST_RGF NRF_CC_HOST_RGF_S -#define NRF_CRYPTOCELL NRF_CRYPTOCELL_S -#define NRF_CTRL_AP_PERI NRF_CTRL_AP_PERI_S -#define NRF_FICR NRF_FICR_S -#define NRF_GPIOTE0 NRF_GPIOTE0_S -#define NRF_SPU NRF_SPU_S -#define NRF_TAD NRF_TAD_S -#define NRF_UICR NRF_UICR_S -#endif - -/* Fixup for the GPIOTE driver. */ -#if defined(NRF_TRUSTZONE_NONSECURE) -#define NRF_GPIOTE NRF_GPIOTE1 -#else -#define NRF_GPIOTE NRF_GPIOTE0 -#endif - - -// <<< Use Configuration Wizard in Context Menu >>>\n - -// nRF_Drivers - -// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver. -//========================================================== -#ifndef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LF_SRC - LF clock source. - -// <1=> RC -// <2=> XTAL - -#ifndef NRFX_CLOCK_CONFIG_LF_SRC -#define NRFX_CLOCK_CONFIG_LF_SRC 2 -#endif - -// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure - -// If set to a non-zero value, LFRC will be started before LFXO and corresponding -// event will be generated. It means that CPU will be woken up when LFRC -// oscillator starts, but user callback will be invoked only after LFXO -// finally starts. - -#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED -#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 -#endif - - -// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED -#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL -#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR -#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR -#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_DPPI_ENABLED - nrfx_dppi - DPPI allocator. -//========================================================== -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif -// NRFX_DPPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_DPPI_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_DPPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_DPPI_CONFIG_INFO_COLOR -#define NRFX_DPPI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_DPPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_DPPI_CONFIG_DEBUG_COLOR -#define NRFX_DPPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver. -//========================================================== -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -// NRFX_EGU0_ENABLED - Enable EGU0 instance. - -#ifndef NRFX_EGU0_ENABLED -#define NRFX_EGU0_ENABLED 0 -#endif - -// NRFX_EGU1_ENABLED - Enable EGU1 instance. - -#ifndef NRFX_EGU1_ENABLED -#define NRFX_EGU1_ENABLED 0 -#endif - -// NRFX_EGU2_ENABLED - Enable EGU2 instance. - -#ifndef NRFX_EGU2_ENABLED -#define NRFX_EGU2_ENABLED 0 -#endif - -// NRFX_EGU3_ENABLED - Enable EGU3 instance. - -#ifndef NRFX_EGU3_ENABLED -#define NRFX_EGU3_ENABLED 0 -#endif - -// NRFX_EGU4_ENABLED - Enable EGU4 instance. - -#ifndef NRFX_EGU4_ENABLED -#define NRFX_EGU4_ENABLED 0 -#endif - -// NRFX_EGU5_ENABLED - Enable EGU5 instance. - -#ifndef NRFX_EGU5_ENABLED -#define NRFX_EGU5_ENABLED 0 -#endif - -// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver. -//========================================================== -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins. -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR -#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR -#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver. -//========================================================== -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 0 -#endif - -// NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_I2S_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_INFO_COLOR -#define NRFX_I2S_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR -#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_IPC_ENABLED - nrfx_ipc - IPC peripheral driver -//========================================================== -#ifndef NRFX_IPC_ENABLED -#define NRFX_IPC_ENABLED 0 -#endif - -// - -// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver -//========================================================== -#ifndef NRFX_NVMC_ENABLED -#define NRFX_NVMC_ENABLED 0 -#endif - -// - -// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver. -//========================================================== -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -// NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PDM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_INFO_COLOR -#define NRFX_PDM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR -#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver. -//========================================================== -#ifndef NRFX_POWER_ENABLED -#define NRFX_POWER_ENABLED 0 -#endif -// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing (PRS) module. -//========================================================== -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif -// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. - - -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. - - -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. - - -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module. - - -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PRS_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PRS_CONFIG_INFO_COLOR -#define NRFX_PRS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR -#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver. -//========================================================== -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif -// NRFX_PWM0_ENABLED - Enables PWM0 instance. - - -#ifndef NRFX_PWM0_ENABLED -#define NRFX_PWM0_ENABLED 0 -#endif - -// NRFX_PWM1_ENABLED - Enables PWM1 instance. - - -#ifndef NRFX_PWM1_ENABLED -#define NRFX_PWM1_ENABLED 0 -#endif - -// NRFX_PWM2_ENABLED - Enables PWM2 instance. - - -#ifndef NRFX_PWM2_ENABLED -#define NRFX_PWM2_ENABLED 0 -#endif - -// NRFX_PWM3_ENABLED - Enables PWM3 instance. - - -#ifndef NRFX_PWM3_ENABLED -#define NRFX_PWM3_ENABLED 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PWM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_INFO_COLOR -#define NRFX_PWM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR -#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver. -//========================================================== -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif -// NRFX_RTC0_ENABLED - Enables RTC0 instance. - - -#ifndef NRFX_RTC0_ENABLED -#define NRFX_RTC0_ENABLED 0 -#endif - -// NRFX_RTC1_ENABLED - Enables RTC1 instance. - - -#ifndef NRFX_RTC1_ENABLED -#define NRFX_RTC1_ENABLED 0 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_RTC_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_INFO_COLOR -#define NRFX_RTC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR -#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver. -//========================================================== -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SAADC_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_INFO_COLOR -#define NRFX_SAADC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR -#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver. -//========================================================== -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif -// NRFX_SPIM0_ENABLED - Enables SPIM0 instance. - - -#ifndef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 0 -#endif - -// NRFX_SPIM1_ENABLED - Enables SPIM1 instance. - - -#ifndef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED 0 -#endif - -// NRFX_SPIM2_ENABLED - Enables SPIM2 instance. - - -#ifndef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED 0 -#endif - -// NRFX_SPIM3_ENABLED - Enables SPIM3 instance. - - -#ifndef NRFX_SPIM3_ENABLED -#define NRFX_SPIM3_ENABLED 0 -#endif - -// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_INFO_COLOR -#define NRFX_SPIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR -#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver. -//========================================================== -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif -// NRFX_SPIS0_ENABLED - Enables SPIS0 instance. - - -#ifndef NRFX_SPIS0_ENABLED -#define NRFX_SPIS0_ENABLED 0 -#endif - -// NRFX_SPIS1_ENABLED - Enables SPIS1 instance. - - -#ifndef NRFX_SPIS1_ENABLED -#define NRFX_SPIS1_ENABLED 0 -#endif - -// NRFX_SPIS2_ENABLED - Enables SPIS2 instance. - - -#ifndef NRFX_SPIS2_ENABLED -#define NRFX_SPIS2_ENABLED 0 -#endif - -// NRFX_SPIS3_ENABLED - Enables SPIS3 instance. - - -#ifndef NRFX_SPIS3_ENABLED -#define NRFX_SPIS3_ENABLED 0 -#endif - -// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIS_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_INFO_COLOR -#define NRFX_SPIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR -#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver. - - -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 0 -#endif - -// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver. -//========================================================== -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -// NRFX_TIMER0_ENABLED - Enables TIMER0 instance. - -#ifndef NRFX_TIMER0_ENABLED -#define NRFX_TIMER0_ENABLED 0 -#endif - -// NRFX_TIMER1_ENABLED - Enables TIMER1 instance. - -#ifndef NRFX_TIMER1_ENABLED -#define NRFX_TIMER1_ENABLED 0 -#endif - -// NRFX_TIMER2_ENABLED - Enables TIMER2 instance. - -#ifndef NRFX_TIMER2_ENABLED -#define NRFX_TIMER2_ENABLED 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TIMER_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_INFO_COLOR -#define NRFX_TIMER_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR -#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver. -//========================================================== -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif -// NRFX_TWIM0_ENABLED - Enables TWIM0 instance. - - -#ifndef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED 0 -#endif - -// NRFX_TWIM1_ENABLED - Enables TWIM1 instance. - - -#ifndef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED 0 -#endif - -// NRFX_TWIM2_ENABLED - Enables TWIM2 instance. - - -#ifndef NRFX_TWIM2_ENABLED -#define NRFX_TWIM2_ENABLED 0 -#endif - -// NRFX_TWIM3_ENABLED - Enables TWIM3 instance. - - -#ifndef NRFX_TWIM3_ENABLED -#define NRFX_TWIM3_ENABLED 0 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIM_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_INFO_COLOR -#define NRFX_TWIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR -#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver. -//========================================================== -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif -// NRFX_TWIS0_ENABLED - Enables TWIS0 instance. - - -#ifndef NRFX_TWIS0_ENABLED -#define NRFX_TWIS0_ENABLED 0 -#endif - -// NRFX_TWIS1_ENABLED - Enables TWIS1 instance. - - -#ifndef NRFX_TWIS1_ENABLED -#define NRFX_TWIS1_ENABLED 0 -#endif - -// NRFX_TWIS2_ENABLED - Enables TWIS2 instance. - - -#ifndef NRFX_TWIS2_ENABLED -#define NRFX_TWIS2_ENABLED 0 -#endif - -// NRFX_TWIS3_ENABLED - Enables TWIS3 instance. - - -#ifndef NRFX_TWIS3_ENABLED -#define NRFX_TWIS3_ENABLED 0 -#endif - -// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assumes that any instance would be initialized only once. - - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// NRFX_TWIS_NO_SYNC_MODE - Removes support for synchronous mode. - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIS_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_INFO_COLOR -#define NRFX_TWIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR -#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver. -//========================================================== -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif -// NRFX_UARTE0_ENABLED - Enables UARTE0 instances -#ifndef NRFX_UARTE0_ENABLED -#define NRFX_UARTE0_ENABLED 0 -#endif - -// NRFX_UARTE1_ENABLED - Enables UARTE1 instance. -#ifndef NRFX_UARTE1_ENABLED -#define NRFX_UARTE1_ENABLED 0 -#endif - -// NRFX_UARTE2_ENABLED - Enables UARTE2 instance. -#ifndef NRFX_UARTE2_ENABLED -#define NRFX_UARTE2_ENABLED 0 -#endif - -// NRFX_UARTE3_ENABLED - Enables UARTE3 instance. -#ifndef NRFX_UARTE3_ENABLED -#define NRFX_UARTE3_ENABLED 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_UARTE_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_INFO_COLOR -#define NRFX_UARTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR -#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver. -//========================================================== -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif -// NRFX_WDT0_ENABLED - Enable WDT0 instance. - - -#ifndef NRFX_WDT0_ENABLED -#define NRFX_WDT0_ENABLED 0 -#endif - -// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver. - -// <0=> Include WDT IRQ handling -// <1=> Remove WDT IRQ handling - -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_WDT_CONFIG_LOG_LEVEL - Default severity level. - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_INFO_COLOR -#define NRFX_WDT_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR -#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// - -#endif // NRFX_CONFIG_NRF91_H__ From df6ea3be54e6a602ef694db51cb89b66d95c130d Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Fri, 21 Nov 2025 13:44:11 +0100 Subject: [PATCH 117/133] [zep fromtree] nrf: driver: flash: align to nrfx 4.0 Update error codes. Change-Id: I492f82cfb777a5acfac536ae5e647ed8b7a61df3 Signed-off-by: Marcin Szymczyk Signed-off-by: Tomi Fontanilles (cherry picked from commit c2d19e07ebb8cc93ac5edee023606859ba1c1bcf) --- .../common/core/cmsis_drivers/Driver_Flash.c | 12 ++++++------ .../target/nordic_nrf/common/core/target_cfg_54l.c | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c index 54b540560c..5a7d138d14 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c @@ -120,17 +120,17 @@ static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) */ nrfx_rramc_evt_handler_t handler = NULL; - nrfx_err_t err = nrfx_rramc_init(&config, handler); + int err = nrfx_rramc_init(&config, handler); - if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + if(err != 0 && err != -EALREADY) { return err; } #elif defined(MRAMC_PRESENT) nrfx_mramc_config_t config = NRFX_MRAMC_DEFAULT_CONFIG(); - nrfx_err_t err = nrfx_mramc_init(&config, NULL); + int err = nrfx_mramc_init(&config, NULL); - if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + if(err != 0 && err != -EALREADY) { return err; } #endif /* RRAMC_PRESENT or MRAMC_PRESENT*/ @@ -206,9 +206,9 @@ static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, static int32_t ARM_Flash_EraseSector(uint32_t addr) { #ifdef NRF_NVMC_S - nrfx_err_t err_code = nrfx_nvmc_page_erase(addr); + int err_code = nrfx_nvmc_page_erase(addr); - if (err_code != NRFX_SUCCESS) { + if (err_code != 0) { return ARM_DRIVER_ERROR_PARAMETER; } #else diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c index 1f148e044a..3c26a588b7 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -129,7 +129,7 @@ static void init_mpc_region_override(struct mpc_region_override *override) override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; } -static nrfx_err_t rramc_configuration(void) +static int rramc_configuration(void) { nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); @@ -148,12 +148,12 @@ static nrfx_err_t rramc_configuration(void) */ nrfx_rramc_evt_handler_t handler = NULL; - nrfx_err_t err = nrfx_rramc_init(&config, handler); - if (err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + int err = nrfx_rramc_init(&config, handler); + if (err != 0 && err != -EALREADY) { return err; } - return NRFX_SUCCESS; + return 0; } enum tfm_plat_err_t init_debug(void) @@ -472,8 +472,8 @@ enum tfm_plat_err_t spu_periph_init_cfg(void) nrf_cache_enable(NRF_ICACHE); - nrfx_err_t nrfx_err = rramc_configuration(); - if (nrfx_err != NRFX_SUCCESS) { + int nrfx_err = rramc_configuration(); + if (nrfx_err != 0) { return TFM_PLAT_ERR_SYSTEM_ERR; } From b946525b963a47776014b6f6b169fb6f67b37088 Mon Sep 17 00:00:00 2001 From: Nicola Mazzucato Date: Thu, 3 Apr 2025 15:50:43 +0100 Subject: [PATCH 118/133] [zep fromtree] CC3XX: Fix 'unused variable' warning for lock_dfa_enabled Fix the following warning in cc3xx_init.c warning: unused variable 'lock_dfa_enabled' [-Wunused-variable] 75 | uint32_t lock_dfa_enabled = dfa_is_supported; | ^~~~~~~~~~~~~~~~ Signed-off-by: Nicola Mazzucato Change-Id: I6d6ad2100557b55d4aabdfcdb1ea3b9e2d799b22 (cherry picked from commit e201cb6ca1dc393a635d5a40d65487c122390749) --- .../target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_init.c b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_init.c index 97f9f22cf2..dcaf024521 100644 --- a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_init.c +++ b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_init.c @@ -91,6 +91,7 @@ static cc3xx_err_t setup_dfa_countermeasures(void) * to be switched off. */ { + (void)lock_dfa_enabled; #endif /* CC3XX_CONFIG_AES_TUNNELLING_ENABLE */ P_CC3XX->ao.host_ao_lock_bits &= ~(0b1U << 7); /* Unset HOST_FORCE_DFA_ENABLE */ } From 52d683d7b19a6b275c3abdddfad000431c6184ba Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Sat, 12 Jul 2025 10:17:47 -0400 Subject: [PATCH 119/133] [zep fromtree] CC312: guard ecc_conv_scalar_to_mpi based on usage or else we get defined-but-not-used warnings which would turn into errors. Change-Id: I2640defa6740e5c3fd49cf8b3f1220d62e26ea53 Signed-off-by: Anas Nashif (cherry picked from commit 0655a7681e497b2cd7ffa264e1e98bc7fcca98c2) --- .../codesafe/src/mbedtls_api/cc_ecp_internal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/ext/cryptocell-312-runtime/codesafe/src/mbedtls_api/cc_ecp_internal.c b/lib/ext/cryptocell-312-runtime/codesafe/src/mbedtls_api/cc_ecp_internal.c index 8c05aacbfa..e61a53694c 100644 --- a/lib/ext/cryptocell-312-runtime/codesafe/src/mbedtls_api/cc_ecp_internal.c +++ b/lib/ext/cryptocell-312-runtime/codesafe/src/mbedtls_api/cc_ecp_internal.c @@ -72,6 +72,7 @@ #define mbedtls_free free #endif +#if defined(ECP_MONTGOMERY) static int ecc_conv_scalar_to_mpi( uint8_t * scalar, size_t scalarSize, mbedtls_mpi * X) { CCError_t status; @@ -139,7 +140,6 @@ static int ecc_conv_mpi_to_scalar( const mbedtls_mpi * X, uint8_t *scalar, size_ return 0; } -#if defined(ECP_MONTGOMERY) static int ecp_mont_mul( mbedtls_ecp_point *R, const mbedtls_mpi *m, const mbedtls_ecp_point *P ) { From b369ad7dbab8c30ba707a7004115d57ef5c0e0cf Mon Sep 17 00:00:00 2001 From: Anton Komlev Date: Mon, 19 May 2025 14:52:23 +0100 Subject: [PATCH 120/133] [zep fromtree] Build: Avoid compiler warning in an521 driver The warning: control reaches end of non-void function [-Wreturn-type] Signed-off-by: Anton Komlev Change-Id: Ic228c145506acc9d612b880ffa7e60993b160667 (cherry picked from commit 2a23a3663da65447c9e1dda544abf58975f7b232) --- .../ext/target/arm/mps2/an521/cmsis_drivers/Driver_MPC.c | 3 ++- .../ext/target/arm/mps2/an521/cmsis_drivers/Driver_USART.c | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_MPC.c b/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_MPC.c index e3c3168b61..9c8128e9fc 100644 --- a/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_MPC.c +++ b/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_MPC.c @@ -60,8 +60,9 @@ static int32_t error_trans(enum mpc_sie200_error_t err) /* default: The default is not defined intentionally to force the * compiler to check that all the enumeration values are * covered in the switch. - */ + */ } + return ARM_DRIVER_ERROR; } #if (RTE_ISRAM0_MPC) diff --git a/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_USART.c b/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_USART.c index b9d9aa97ab..5c604ec575 100644 --- a/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_USART.c +++ b/platform/ext/target/arm/mps2/an521/cmsis_drivers/Driver_USART.c @@ -100,8 +100,11 @@ static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev, return ARM_DRIVER_OK; /* default: The default is not defined intentionally to force the * compiler to check that all the enumeration values are - * covered in the switch.*/ + * covered in the switch. + */ } + + return ARM_DRIVER_ERROR; } static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *data, From 5a6a3cdf4565a331dd0e4e525c5860c94463448b Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Thu, 13 Nov 2025 12:41:50 +0200 Subject: [PATCH 121/133] [zep fromtree] Platform: Fix return-type compiler warnings e3e7d6d9a178d136ccbe79b7341b21a0a0cb4166 enabled the return-type compiler warnings. Fix occurrences where this warning now comes up. Change-Id: I3493554afd3fa11c06979c7828cec593b573c0d8 Signed-off-by: Tomi Fontanilles (cherry picked from commit 99dff4b63b80c4f4f3bf4211b1f58d457b4cd549) --- platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c | 1 + .../ext/target/arm/drivers/usart/cmsdk/Driver_USART_CMSDK.h | 1 + platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c index 2f357fb688..4b97673e74 100644 --- a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c @@ -143,6 +143,7 @@ static int32_t error_trans(enum mpc_sie200_error_t err) * covered in the switch. */ } + return ARM_DRIVER_ERROR; } #if (RTE_SRAM0_MPC) diff --git a/platform/ext/target/arm/drivers/usart/cmsdk/Driver_USART_CMSDK.h b/platform/ext/target/arm/drivers/usart/cmsdk/Driver_USART_CMSDK.h index 94d51f982c..ebbfc0bce6 100644 --- a/platform/ext/target/arm/drivers/usart/cmsdk/Driver_USART_CMSDK.h +++ b/platform/ext/target/arm/drivers/usart/cmsdk/Driver_USART_CMSDK.h @@ -84,6 +84,7 @@ static inline int32_t ARM_USARTx_PowerControl(UARTx_Resources *uart_dev, * compiler to check that all the enumeration values are * covered in the switch.*/ } + return ARM_DRIVER_ERROR; } static inline int32_t ARM_USARTx_Send(UARTx_Resources *uart_dev, diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c index c94181a475..9ed22c2859 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c @@ -118,6 +118,8 @@ enum tfm_plat_err_t init_debug(void) return configure_approtect_nvmc(); #elif defined(NRF53_SERIES) return configure_approtect_registers(); +#else + return TFM_PLAT_ERR_SUCCESS; #endif } From f6e859952c5b688e36f1d23f99d6ebe186143d0a Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Wed, 2 Apr 2025 09:52:54 +0100 Subject: [PATCH 122/133] [zep fromtree] Build: Remove -Wno-return-type This flag suppresses warnings of missing return statements or where the return statement type mismatches the function signature. These are warnings which will lead to undefined behaviour and therefore should not be ignored. Change-Id: I5cc75f5b4ed3a2e20b206f15ffc24274e8b25a3d Signed-off-by: Jackson Cooper-Driver (cherry picked from commit e3e7d6d9a178d136ccbe79b7341b21a0a0cb4166) --- platform/ns/toolchain_ns_GNUARM.cmake | 1 - toolchain_GNUARM.cmake | 1 - 2 files changed, 2 deletions(-) diff --git a/platform/ns/toolchain_ns_GNUARM.cmake b/platform/ns/toolchain_ns_GNUARM.cmake index 71ed5c7689..52985b39e6 100644 --- a/platform/ns/toolchain_ns_GNUARM.cmake +++ b/platform/ns/toolchain_ns_GNUARM.cmake @@ -181,7 +181,6 @@ add_compile_options( -specs=nosys.specs -Wall -Wno-format - -Wno-return-type -Wno-unused-but-set-variable -c -fdata-sections diff --git a/toolchain_GNUARM.cmake b/toolchain_GNUARM.cmake index 56a220ba84..8d828f31ee 100644 --- a/toolchain_GNUARM.cmake +++ b/toolchain_GNUARM.cmake @@ -111,7 +111,6 @@ add_compile_options( -specs=nosys.specs -Wall -Wno-format - -Wno-return-type -Wno-unused-but-set-variable -c -fdata-sections From d4bcb00c026487fd7dd95c422ae22e8c831912ab Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Sat, 12 Jul 2025 10:15:39 -0400 Subject: [PATCH 123/133] [zep fromtree] Build: GNUARM: Enable -Warray-parameter Enable -Warray-parameter for GCC, to align with behaviour required by some integrations such as Zephyr Change-Id: I64746b5aa549c38d1f84bc777f253628e3c9c8f8 Signed-off-by: Anas Nashif (cherry picked from commit a114a1eb9f80e66f6e89ac24a6d3d6fa92cece7e) --- platform/ns/toolchain_ns_GNUARM.cmake | 1 + toolchain_GNUARM.cmake | 1 + 2 files changed, 2 insertions(+) diff --git a/platform/ns/toolchain_ns_GNUARM.cmake b/platform/ns/toolchain_ns_GNUARM.cmake index 52985b39e6..8f23f818bc 100644 --- a/platform/ns/toolchain_ns_GNUARM.cmake +++ b/platform/ns/toolchain_ns_GNUARM.cmake @@ -181,6 +181,7 @@ add_compile_options( -specs=nosys.specs -Wall -Wno-format + -Warray-parameter -Wno-unused-but-set-variable -c -fdata-sections diff --git a/toolchain_GNUARM.cmake b/toolchain_GNUARM.cmake index 8d828f31ee..27097536fe 100644 --- a/toolchain_GNUARM.cmake +++ b/toolchain_GNUARM.cmake @@ -111,6 +111,7 @@ add_compile_options( -specs=nosys.specs -Wall -Wno-format + -Warray-parameter -Wno-unused-but-set-variable -c -fdata-sections From 8797c4246c760cc9887f805e09d14f533b5e6ddd Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 11 Jul 2025 22:22:34 -0400 Subject: [PATCH 124/133] [zep fromtree] boot_hal: workaround compiler warning Add code_unreachable to satisfy compiler and convince it we do not return in this function. The error we are getting: error: 'noreturn' function does return [-Werror] Change-Id: I64d5dbe15d327496dfa09fa08d900a14b0234cd0 Signed-off-by: Anas Nashif (cherry picked from commit 82df363d85ebb50bcfb09d6cb833be7aa33f132a) --- platform/ext/common/boot_hal_bl2.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/platform/ext/common/boot_hal_bl2.c b/platform/ext/common/boot_hal_bl2.c index 6c36414e65..56ef94d5b7 100644 --- a/platform/ext/common/boot_hal_bl2.c +++ b/platform/ext/common/boot_hal_bl2.c @@ -237,6 +237,14 @@ __WEAK void boot_platform_start_next_image(struct boot_arm_vector_table *vt) __WEAK __NO_RETURN void boot_platform_error_state(uint32_t error) { FIH_PANIC; +#if defined(__ICCARM__) +#pragma diag_default = Pe111 +#else + __builtin_unreachable(); +#endif + while (1) { + __NOP(); + } } __WEAK int boot_platform_pre_load(uint32_t image_id) From 6b19070a55c09b83672a6a20ef7398ea60d09a59 Mon Sep 17 00:00:00 2001 From: Waqar Tahir Date: Fri, 10 Oct 2025 10:46:14 +0200 Subject: [PATCH 125/133] [zep fromtree] platform: LPCXpresso55s69: Use of local drivers All drivers required by lpcxpresso55s69 are placed in platform/common folder of NXP, copied from sdk 25.09.00. Instead of fetching drivers at run time, all required drivers are placed in platform or common directory. This is to re-use the drivers by upcoming platforms as well as keep using same drivers during zephyr builds. Change-Id: I5500dad96ebbe5d000d140a5bab25349ce36cc5f Signed-off-by: Waqar Tahir (cherry picked from commit 0b704878e8a30559d0e13c5e7bb1e8bab0787d6d) --- .../lists/fsl_component_generic_list.c | 499 +++ .../lists/fsl_component_generic_list.h | 219 + .../fsl_component_serial_manager.c | 2093 +++++++++ .../fsl_component_serial_manager.h | 856 ++++ .../fsl_component_serial_port_internal.h | 189 + .../fsl_component_serial_port_uart.c | 717 +++ .../fsl_component_serial_port_uart.h | 106 + .../components/uart/fsl_adapter_lpuart.c | 2464 +++++++++++ .../components/uart/fsl_adapter_uart.h | 828 ++++ .../components/uart/fsl_adapter_usart.c | 1101 +++++ .../Native_Driver/drivers/common/fsl_common.c | 90 + .../Native_Driver/drivers/common/fsl_common.h | 356 ++ .../drivers/{ => common}/fsl_common_arm.c | 138 +- .../drivers/common/fsl_common_arm.h | 1198 +++++ .../Native_Driver/drivers/ctimer/fsl_ctimer.c | 678 +++ .../Native_Driver/drivers/ctimer/fsl_ctimer.h | 702 +++ .../drivers/flexcomm/fsl_flexcomm.c | 401 ++ .../drivers/flexcomm/fsl_flexcomm.h | 64 + .../drivers/flexcomm/i2c/fsl_i2c.c | 2116 +++++++++ .../drivers/flexcomm/i2c/fsl_i2c.h | 1155 +++++ .../drivers/flexcomm/spi/fsl_spi.c | 1077 +++++ .../drivers/flexcomm/spi/fsl_spi.h | 758 ++++ .../drivers/flexcomm/usart/fsl_usart.c | 1314 ++++++ .../drivers/flexcomm/usart/fsl_usart.h | 977 +++++ .../Native_Driver/drivers/iap1/fsl_iap.c | 691 +++ .../Native_Driver/drivers/iap1/fsl_iap.h | 569 +++ .../Native_Driver/drivers/iap1/fsl_iap_ffr.h | 388 ++ .../Native_Driver/drivers/iap1/fsl_iap_kbp.h | 245 ++ .../iap1/fsl_iap_skboot_authenticate.h | 77 + .../Native_Driver/drivers/lpc_gpio/fsl_gpio.c | 317 ++ .../Native_Driver/drivers/lpc_gpio/fsl_gpio.h | 364 ++ .../drivers/lpc_iocon/fsl_iocon.h | 215 + .../utilities/assert/fsl_assert.c | 107 + .../utilities/assert/fsl_assert.h | 50 + .../debug_console/fsl_debug_console.c | 1417 ++++++ .../debug_console/fsl_debug_console.h | 317 ++ .../debug_console/fsl_debug_console_conf.h | 160 + .../Native_Driver/utilities/str/fsl_str.c | 1711 ++++++++ .../Native_Driver/utilities/str/fsl_str.h | 128 + .../target/nxp/lpcxpresso55s69/CMakeLists.txt | 58 +- .../Native_Driver/LPC55S69_cm33_core0.h | 97 + .../LPC55S69_cm33_core0_COMMON.h | 2175 +++++++++ .../LPC55S69_cm33_core0_features.h | 517 +++ .../Native_Driver/LPC55S69_cm33_core1.h | 97 + .../LPC55S69_cm33_core1_COMMON.h | 2175 +++++++++ .../LPC55S69_cm33_core1_features.h | 517 +++ .../Native_Driver/drivers/fsl_clock.c | 2176 +++++++++ .../Native_Driver/drivers/fsl_clock.h | 1508 +++++++ .../Native_Driver/drivers/fsl_power.c | 1888 ++++++++ .../Native_Driver/drivers/fsl_power.h | 610 +++ .../Native_Driver/drivers/fsl_reset.c | 101 + .../Native_Driver/drivers/fsl_reset.h | 317 ++ .../Native_Driver/fsl_device_registers.h | 28 + .../Native_Driver/periph/PERI_ADC.h | 1204 +++++ .../periph/PERI_AHB_SECURE_CTRL.h | 3472 +++++++++++++++ .../Native_Driver/periph/PERI_ANACTRL.h | 934 ++++ .../Native_Driver/periph/PERI_CASPER.h | 486 +++ .../Native_Driver/periph/PERI_CRC.h | 243 ++ .../Native_Driver/periph/PERI_CTIMER.h | 657 +++ .../Native_Driver/periph/PERI_DBGMAILBOX.h | 245 ++ .../Native_Driver/periph/PERI_DMA.h | 740 ++++ .../Native_Driver/periph/PERI_FLASH.h | 421 ++ .../Native_Driver/periph/PERI_FLASH_CFPA.h | 639 +++ .../Native_Driver/periph/PERI_FLASH_CMPA.h | 713 +++ .../periph/PERI_FLASH_KEY_STORE.h | 582 +++ .../Native_Driver/periph/PERI_FLEXCOMM.h | 265 ++ .../Native_Driver/periph/PERI_GINT.h | 237 + .../Native_Driver/periph/PERI_GPIO.h | 363 ++ .../Native_Driver/periph/PERI_HASHCRYPT.h | 595 +++ .../Native_Driver/periph/PERI_I2C.h | 972 +++++ .../Native_Driver/periph/PERI_I2S.h | 812 ++++ .../Native_Driver/periph/PERI_INPUTMUX.h | 704 +++ .../Native_Driver/periph/PERI_IOCON.h | 292 ++ .../Native_Driver/periph/PERI_MAILBOX.h | 231 + .../Native_Driver/periph/PERI_MRT.h | 356 ++ .../Native_Driver/periph/PERI_OSTIMER.h | 277 ++ .../Native_Driver/periph/PERI_PINT.h | 692 +++ .../Native_Driver/periph/PERI_PLU.h | 345 ++ .../Native_Driver/periph/PERI_PMC.h | 1172 +++++ .../Native_Driver/periph/PERI_POWERQUAD.h | 543 +++ .../Native_Driver/periph/PERI_PRINCE.h | 380 ++ .../Native_Driver/periph/PERI_PUF.h | 799 ++++ .../Native_Driver/periph/PERI_RNG.h | 288 ++ .../Native_Driver/periph/PERI_RTC.h | 344 ++ .../Native_Driver/periph/PERI_SCT.h | 1757 ++++++++ .../Native_Driver/periph/PERI_SDIF.h | 1145 +++++ .../Native_Driver/periph/PERI_SPI.h | 942 ++++ .../Native_Driver/periph/PERI_SYSCON.h | 3885 +++++++++++++++++ .../Native_Driver/periph/PERI_SYSCTL.h | 356 ++ .../Native_Driver/periph/PERI_USART.h | 1094 +++++ .../Native_Driver/periph/PERI_USB.h | 645 +++ .../Native_Driver/periph/PERI_USBFSH.h | 751 ++++ .../Native_Driver/periph/PERI_USBHSD.h | 520 +++ .../Native_Driver/periph/PERI_USBHSH.h | 589 +++ .../Native_Driver/periph/PERI_USBPHY.h | 1927 ++++++++ .../Native_Driver/periph/PERI_UTICK.h | 301 ++ .../Native_Driver/periph/PERI_WWDT.h | 273 ++ .../system_LPC55S69_cm33_core0.c | 385 ++ .../system_LPC55S69_cm33_core0.h | 118 + .../target/nxp/lpcxpresso55s69/config.cmake | 6 +- .../nxp/lpcxpresso55s69/ns/CMakeLists.txt | 27 +- .../nxp/lpcxpresso55s69/pull_drivers.cmake | 82 - 102 files changed, 73798 insertions(+), 124 deletions(-) create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_lpuart.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.h rename platform/ext/target/nxp/common/Native_Driver/drivers/{ => common}/fsl_common_arm.c (57%) create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_ffr.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_kbp.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_skboot_authenticate.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/drivers/lpc_iocon/fsl_iocon.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c create mode 100644 platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_COMMON.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_COMMON.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ADC.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_AHB_SECURE_CTRL.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ANACTRL.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CASPER.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CRC.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CTIMER.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DBGMAILBOX.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DMA.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CFPA.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CMPA.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_KEY_STORE.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLEXCOMM.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GINT.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GPIO.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_HASHCRYPT.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2C.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2S.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_INPUTMUX.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_IOCON.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MAILBOX.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MRT.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_OSTIMER.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PINT.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PLU.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PMC.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_POWERQUAD.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PRINCE.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PUF.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RNG.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RTC.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SCT.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SDIF.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SPI.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCON.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCTL.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USART.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USB.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBFSH.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSD.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSH.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBPHY.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_UTICK.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_WWDT.h create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c create mode 100644 platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h delete mode 100644 platform/ext/target/nxp/lpcxpresso55s69/pull_drivers.cmake diff --git a/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c new file mode 100644 index 0000000000..5644f385d2 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c @@ -0,0 +1,499 @@ +/* + * Copyright 2018-2019, 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_component_generic_list.h" + +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define LIST_ENTER_CRITICAL() \ + OSA_SR_ALLOC(); \ + OSA_ENTER_CRITICAL() +#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif +#else +#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif + +static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; +#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U)) + list_element_handle_t element = list->head; +#endif + if ((list->max != 0U) && (list->max == list->size)) + { + listStatus = kLIST_Full; /*List is full*/ + } +#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U)) + else + { + while (element != NULL) /*Scan list*/ + { + /* Determine if element is duplicated */ + if (element == newElement) + { + listStatus = kLIST_DuplicateError; + break; + } + element = element->next; + } + } +#endif + return listStatus; +} + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* + * \brief Initializes the list descriptor. + * + * \param[in] list - LIST_ handle to init. + * max - Maximum number of elements in list. 0 for unlimited. + * + * \return void. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +void LIST_Init(list_handle_t list, uint32_t max) +{ + list->head = NULL; + list->tail = NULL; + list->max = max; + list->size = 0; +} + +/*! ********************************************************************************* + * \brief Gets the list that contains the given element. + * + * \param[in] element - Handle of the element. + * + * \return NULL if element is orphan. + * Handle of the list the element is inserted into. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_handle_t LIST_GetList(list_element_handle_t listElement) +{ + return listElement->list; +} + +/*! ********************************************************************************* + * \brief Links element to the tail of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement) +{ + LIST_ENTER_CRITICAL(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, listElement); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + if (list->size == 0U) + { + list->head = listElement; + } + else + { + list->tail->next = listElement; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + listElement->prev = list->tail; +#endif + listElement->list = list; + listElement->next = NULL; + list->tail = listElement; + list->size++; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links element to the head of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement) +{ + LIST_ENTER_CRITICAL(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, listElement); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + /* Links element to the head of the list */ + if (list->size == 0U) + { + list->tail = listElement; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + list->head->prev = listElement; + } + listElement->prev = NULL; +#endif + listElement->list = list; + listElement->next = list->head; + list->head = listElement; + list->size++; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Unlinks element from the head of the list. + * + * \param[in] list - ID of list to remove from. + * + * \return NULL if list is empty. + * ID of removed element(pointer) if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_RemoveHead(list_handle_t list) +{ + list_element_handle_t listElement; + + LIST_ENTER_CRITICAL(); + + if ((NULL == list) || (list->size == 0U)) + { + listElement = NULL; /*LIST_ is empty*/ + } + else + { + listElement = list->head; + list->size--; + if (list->size == 0U) + { + list->tail = NULL; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + listElement->next->prev = NULL; + } +#endif + listElement->list = NULL; + list->head = listElement->next; /*Is NULL if element is head*/ + } + + LIST_EXIT_CRITICAL(); + return listElement; +} + +/*! ********************************************************************************* + * \brief Gets head element ID. + * + * \param[in] list - ID of list. + * + * \return NULL if list is empty. + * ID of head element if list is not empty. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetHead(list_handle_t list) +{ + return list->head; +} + +/*! ********************************************************************************* + * \brief Gets next element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is tail. + * ID of next element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetNext(list_element_handle_t listElement) +{ + return listElement->next; +} + +/*! ********************************************************************************* + * \brief Gets previous element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is head. + * ID of previous element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetPrev(list_element_handle_t listElement) +{ +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + return NULL; +#else + return listElement->prev; +#endif +} + +/*! ********************************************************************************* + * \brief Unlinks an element from its list. + * + * \param[in] element - ID of the element to remove. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Ok if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_RemoveElement(list_element_handle_t listElement) +{ + list_status_t listStatus = kLIST_Ok; + LIST_ENTER_CRITICAL(); + + if (listElement->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = listElement->list->head; + list_element_handle_t element_Prev = NULL; + while (NULL != element_list) + { + if (listElement->list->head == listElement) + { + listElement->list->head = element_list->next; + break; + } + if (element_list->next == listElement) + { + element_Prev = element_list; + element_list->next = listElement->next; + break; + } + element_list = element_list->next; + } + if (listElement->next == NULL) + { + listElement->list->tail = element_Prev; + } +#else + if (listElement->prev == NULL) /*Element is head or solo*/ + { + listElement->list->head = listElement->next; /*is null if solo*/ + } + if (listElement->next == NULL) /*Element is tail or solo*/ + { + listElement->list->tail = listElement->prev; /*is null if solo*/ + } + if (listElement->prev != NULL) /*Element is not head*/ + { + listElement->prev->next = listElement->next; + } + if (listElement->next != NULL) /*Element is not tail*/ + { + listElement->next->prev = listElement->prev; + } +#endif + listElement->list->size--; + listElement->list = NULL; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links an element in the previous position relative to a given member + * of a list. + * + * \param[in] element - ID of a member of a list. + * newElement - new element to insert before the given member. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + LIST_ENTER_CRITICAL(); + + if (listElement->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { + listStatus = LIST_Error_Check(listElement->list, newElement); + if (listStatus == kLIST_Ok) + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = listElement->list->head; + while (NULL != element_list) + { + if ((element_list->next == listElement) || (element_list == listElement)) + { + if (element_list == listElement) + { + listElement->list->head = newElement; + } + else + { + element_list->next = newElement; + } + newElement->list = listElement->list; + newElement->next = listElement; + listElement->list->size++; + break; + } + element_list = element_list->next; + } + +#else + if (listElement->prev == NULL) /*Element is list head*/ + { + listElement->list->head = newElement; + } + else + { + listElement->prev->next = newElement; + } + newElement->list = listElement->list; + listElement->list->size++; + newElement->next = listElement; + newElement->prev = listElement->prev; + listElement->prev = newElement; +#endif + } + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Gets the current size of a list. + * + * \param[in] list - ID of the list. + * + * \return Current size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetSize(list_handle_t list) +{ + return list->size; +} + +/*! ********************************************************************************* + * \brief Gets the number of free places in the list. + * + * \param[in] list - ID of the list. + * + * \return Available size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetAvailableSize(list_handle_t list) +{ + return (list->max - list->size); /*Gets the number of free places in the list*/ +} diff --git a/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h new file mode 100644 index 0000000000..ab7ea1a46a --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h @@ -0,0 +1,219 @@ +/* + * Copyright 2018-2020, 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _GENERIC_LIST_H_ +#define _GENERIC_LIST_H_ + +#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON +#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U) +#endif +#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U)) +#include "fsl_common.h" +#else +#endif +/*! + * @addtogroup GenericList + * @{ + */ + +/********************************************************************************** + * Include + ***********************************************************************************/ + +/********************************************************************************** + * Public macro definitions + ***********************************************************************************/ +/*! @brief Definition to determine whether use list light. */ +#ifndef GENERIC_LIST_LIGHT +#define GENERIC_LIST_LIGHT (1) +#endif + +/*! @brief Definition to determine whether enable list duplicated checking. */ +#ifndef GENERIC_LIST_DUPLICATED_CHECKING +#define GENERIC_LIST_DUPLICATED_CHECKING (0) +#endif + +/********************************************************************************** + * Public type definitions + ***********************************************************************************/ +/*! @brief The list status */ +#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U)) +typedef enum _list_status +{ + kLIST_Ok = kStatus_Success, /*!< Success */ + kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ + kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ + kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ + kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ + kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */ +} list_status_t; +#else +typedef enum _list_status +{ + kLIST_Ok = 0, /*!< Success */ + kLIST_DuplicateError = 1, /*!< Duplicate Error */ + kLIST_Full = 2, /*!< FULL */ + kLIST_Empty = 3, /*!< Empty */ + kLIST_OrphanElement = 4, /*!< Orphan Element */ + kLIST_NotSupport = 5, /*!< Not Support */ +} list_status_t; +#endif + +/*! @brief The list structure*/ +typedef struct list_label +{ + struct list_element_tag *head; /*!< list head */ + struct list_element_tag *tail; /*!< list tail */ + uint32_t size; /*!< list size */ + uint32_t max; /*!< list max number of elements */ +} list_label_t, *list_handle_t; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#else +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_element_tag *prev; /*!< previous list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#endif +/********************************************************************************** + * Public prototypes + ***********************************************************************************/ +/********************************************************************************** + * API + **********************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +/*! + * @brief Initialize the list. + * + * This function initialize the list. + * + * @param list - List handle to initialize. + * @param max - Maximum number of elements in list. 0 for unlimited. + */ +void LIST_Init(list_handle_t list, uint32_t max); + +/*! + * @brief Gets the list that contains the given element. + * + * + * @param listElement - Handle of the element. + * @retval NULL if element is orphan, Handle of the list the element is inserted into. + */ +list_handle_t LIST_GetList(list_element_handle_t listElement); + +/*! + * @brief Links element to the head of the list. + * + * @param list - Handle of the list. + * @param listElement - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement); + +/*! + * @brief Links element to the tail of the list. + * + * @param list - Handle of the list. + * @param listElement - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement); + +/*! + * @brief Unlinks element from the head of the list. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_RemoveHead(list_handle_t list); + +/*! + * @brief Gets head element handle. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetHead(list_handle_t list); + +/*! + * @brief Gets next element handle for given element handle. + * + * @param listElement - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetNext(list_element_handle_t listElement); + +/*! + * @brief Gets previous element handle for given element handle. + * + * @param listElement - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetPrev(list_element_handle_t listElement); + +/*! + * @brief Unlinks an element from its list. + * + * @param listElement - Handle of the element. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_RemoveElement(list_element_handle_t listElement); + +/*! + * @brief Links an element in the previous position relative to a given member of a list. + * + * @param listElement - Handle of the element. + * @param newElement - New element to insert before the given member. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement); + +/*! + * @brief Gets the current size of a list. + * + * @param list - Handle of the list. + * + * @retval Current size of the list. + */ +uint32_t LIST_GetSize(list_handle_t list); + +/*! + * @brief Gets the number of free places in the list. + * + * @param list - Handle of the list. + * + * @retval Available size of the list. + */ +uint32_t LIST_GetAvailableSize(list_handle_t list); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /*_GENERIC_LIST_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c new file mode 100644 index 0000000000..d1570d9a01 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c @@ -0,0 +1,2093 @@ +/* + * Copyright 2018-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_component_serial_manager.h" +#include "fsl_component_serial_port_internal.h" +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#include "fsl_component_generic_list.h" + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#else + +#endif + +#endif + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__DSC__) || defined(__CW__) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define SERIAL_EVENT_DATA_RECEIVED (0U) +#define SERIAL_EVENT_DATA_SENT (1U) +#define SERIAL_EVENT_DATA_START_SEND (2U) +#define SERIAL_EVENT_DATA_RX_NOTIFY (3U) +#define SERIAL_EVENT_DATA_NUMBER (4U) + +#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U +#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U + +#ifndef RINGBUFFER_WATERMARK_THRESHOLD +#define RINGBUFFER_WATERMARK_THRESHOLD 95U / 100U +#endif + +#ifndef gSerialManagerLpConstraint_c +#define gSerialManagerLpConstraint_c 0 +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +typedef enum _serial_manager_transmission_mode +{ + kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/ + kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/ +} serial_manager_transmission_mode_t; + +/* TX transfer structure */ +typedef struct _serial_manager_transfer +{ + uint8_t *buffer; + volatile uint32_t length; + volatile uint32_t soFar; + serial_manager_transmission_mode_t mode; + serial_manager_status_t status; +} serial_manager_transfer_t; +#endif + +/* write handle structure */ +typedef struct _serial_manager_send_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_element_t link; /*!< list element of the link */ + serial_manager_transfer_t transfer; +#endif + struct _serial_manager_handle *serialManagerHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_callback_t callback; + void *callbackParam; + uint32_t tag; +#endif +} serial_manager_write_handle_t; +typedef struct _serial_manager_send_block_handle +{ + struct _serial_manager_handle *serialManagerHandle; + +} serial_manager_write_block_handle_t; + +typedef serial_manager_write_handle_t serial_manager_read_handle_t; +typedef serial_manager_write_block_handle_t serial_manager_read_block_handle_t; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/* receive state structure */ +typedef struct _serial_manager_read_ring_buffer +{ + uint8_t *ringBuffer; + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; +} serial_manager_read_ring_buffer_t; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +typedef struct _serial_manager_block_handle +{ + serial_manager_type_t handleType; + serial_port_type_t type; + serial_manager_read_handle_t *volatile openedReadHandleHead; + volatile uint32_t openedWriteHandleCount; + union + { + uint32_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_BLOCK_HANDLE_SIZE]; +#endif + }; + +} serial_manager_block_handle_t; +#endif + +/* The serial manager handle structure */ +typedef struct _serial_manager_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_type_t handleType; +#endif + serial_port_type_t serialPortType; + serial_manager_read_handle_t *volatile openedReadHandleHead; + volatile uint32_t openedWriteHandleCount; + union + { + uint32_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + uint8_t uartDmaHandleBuffer[SERIAL_PORT_UART_DMA_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_VIRTUAL_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + uint8_t rpmsgHandleBuffer[SERIAL_PORT_RPMSG_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + uint8_t spiMasterHandleBuffer[SERIAL_PORT_SPI_MASTER_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + uint8_t spiSlaveHandleBuffer[SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + uint8_t bleWuHandleBuffer[SERIAL_PORT_BLE_WU_HANDLE_SIZE]; +#endif + }; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_read_ring_buffer_t ringBuffer; +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + common_task_message_t commontaskMsg; +#else + OSA_SEMAPHORE_HANDLE_DEFINE(serSemaphore); /*!< Semaphore instance */ + OSA_TASK_HANDLE_DEFINE(taskId); /*!< Task handle */ +#endif + uint8_t serialManagerState[SERIAL_EVENT_DATA_NUMBER]; /*!< Used to indicate the serial mnager state */ + +#endif + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_label_t runningWriteHandleHead; /*!< The queue of running write handle */ + list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */ +#endif + +} serial_manager_handle_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_Task(void *param); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + +#else + /* + * \brief Defines the serial manager task's stack + */ +static OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false); +#endif + +#endif + +#endif +static const serial_manager_lowpower_critical_CBs_t *s_pfserialLowpowerCriticalCallbacks = NULL; +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node) +{ + (void)LIST_AddTail(queue, &node->link); +} + +static void SerialManager_RemoveHead(list_label_t *queue) +{ + (void)LIST_RemoveHead(queue); +} + +static int32_t SerialManager_SetLpConstraint(int32_t power_mode) +{ + int32_t status = -1; + if ((s_pfserialLowpowerCriticalCallbacks != NULL) && + (s_pfserialLowpowerCriticalCallbacks->serialEnterLowpowerCriticalFunc != NULL)) + { + status = s_pfserialLowpowerCriticalCallbacks->serialEnterLowpowerCriticalFunc(power_mode); + } + return status; +} +static int32_t SerialManager_ReleaseLpConstraint(int32_t power_mode) +{ + int32_t status = -1; + if ((s_pfserialLowpowerCriticalCallbacks != NULL) && + (s_pfserialLowpowerCriticalCallbacks->serialExitLowpowerCriticalFunc != NULL)) + { + status = s_pfserialLowpowerCriticalCallbacks->serialExitLowpowerCriticalFunc(power_mode); + } + return status; +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + serial_manager_write_handle_t *writeHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead); + + if (writeHandle != NULL) + { + (void)SerialManager_SetLpConstraint(gSerialManagerLpConstraint_c); + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + status = Serial_SpiSlaveWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif + + default: + status = kStatus_SerialManager_Error; + break; + } + if (kStatus_SerialManager_Success != status) + { + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (NULL != readHandle) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ + { + status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (serHandle->serialPortType == kSerialPort_UsbCdc) + { + status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (serHandle->serialPortType == kSerialPort_Virtual) + { + status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + if (serHandle->serialPortType == kSerialPort_SpiMaster) + { + status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + if (serHandle->serialPortType == kSerialPort_SpiSlave) + { + status = Serial_SpiSlaveRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif + +#if 0 +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (serHandle->serialPortType == kSerialPort_Rpmsg) + { + status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + if (serHandle->serialPortType == kSerialPort_BleWu) + { + status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif + } + return status; +} + +#else /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle, + serial_manager_write_handle_t *writeHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ + { + status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */ + { + status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port Rpmsg */ + { + status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */ + { + status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */ + { + status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ + { + status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */ + { + status = Serial_SwoRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ + { + status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */ + { + status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */ + { + status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} +#endif /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_IsrFunction(serial_manager_handle_t *serHandle) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + Serial_UsbCdcIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + Serial_SwoIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + Serial_PortVirtualIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + Serial_PortBleWuIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + EnableGlobalIRQ(regPrimask); +} + +static void SerialManager_Task(void *param) +{ + serial_manager_handle_t *serHandle = (serial_manager_handle_t *)param; + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_read_handle_t *serialReadHandle; + uint32_t primask; + serial_manager_callback_message_t serialMsg; +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) + uint32_t ringBufferLength; +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + + if (NULL != serHandle) + { +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + + do + { + if (KOSA_StatusSuccess == + OSA_SemaphoreWait((osa_semaphore_handle_t)serHandle->serSemaphore, osaWaitForever_c)) + { +#endif +#endif +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + uint8_t *ev = serHandle->serialManagerState; + EnableGlobalIRQ(primask); + if (0U != (ev[SERIAL_EVENT_DATA_START_SEND])) +#endif +#endif + { + (void)SerialManager_StartWriting(serHandle); +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]--; + EnableGlobalIRQ(primask); +#endif +#endif + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev[SERIAL_EVENT_DATA_SENT])) +#endif + +#endif + { + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead); + while (NULL != serialWriteHandle) + { + SerialManager_RemoveHead(&serHandle->completedWriteHandleHead); + serialMsg.buffer = serialWriteHandle->transfer.buffer; + serialMsg.length = serialWriteHandle->transfer.soFar; + serialWriteHandle->transfer.buffer = NULL; + if (NULL != serialWriteHandle->callback) + { + serialWriteHandle->callback(serialWriteHandle->callbackParam, &serialMsg, + serialWriteHandle->transfer.status); + } + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead); + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]--; + EnableGlobalIRQ(primask); +#endif +#endif + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev[SERIAL_EVENT_DATA_RECEIVED])) +#endif + +#endif + { + primask = DisableGlobalIRQ(); + serialReadHandle = serHandle->openedReadHandleHead; + EnableGlobalIRQ(primask); + + if (NULL != serialReadHandle) + { + if (NULL != serialReadHandle->transfer.buffer) + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + serialMsg.buffer = serialReadHandle->transfer.buffer; + serialMsg.length = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + if (NULL != serialReadHandle->callback) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, + serialReadHandle->transfer.status); + } + } + } + } +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]--; + EnableGlobalIRQ(primask); +#endif +#endif + } + +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev[SERIAL_EVENT_DATA_RX_NOTIFY])) +#endif + { + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] = 0; + ringBufferLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize; + EnableGlobalIRQ(primask); + /* Notify there are data in ringbuffer */ + if (0U != ringBufferLength) + { + serialMsg.buffer = NULL; + serialMsg.length = ringBufferLength; + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback)) + { + serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, &serialMsg, + kStatus_SerialManager_Notify); + } + } + } +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + } + } while (0U != gUseRtos_c); +#endif + +#endif + } +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_TxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *serHandle; + serial_manager_write_handle_t *writeHandle; +#if (defined(OSA_USED)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + uint32_t primask; +#endif +#endif + assert(NULL != callbackParam); + assert(NULL != message); + + serHandle = (serial_manager_handle_t *)callbackParam; + + writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead); + + if (NULL != writeHandle) + { + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); + +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + if (kSerialManager_TransmissionBlocking == writeHandle->transfer.mode) + { + (void)SerialManager_StartWriting(serHandle); + } +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + + writeHandle->transfer.soFar = message->length; + writeHandle->transfer.status = status; + if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode) + { + SerialManager_AddTail(&serHandle->completedWriteHandleHead, writeHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serHandle); +#endif + } + else + { + writeHandle->transfer.buffer = NULL; + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } + } +} + +void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); +void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *serHandle; +#if (!((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))) && \ + !((defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)))) + uint32_t ringBufferLength = 0; + uint32_t primask; +#endif + assert(NULL != callbackParam); + assert(NULL != message); + + serHandle = (serial_manager_handle_t *)callbackParam; +#if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \ + (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))) + serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + serHandle->openedReadHandleHead->transfer.soFar = message->length; + serHandle->openedReadHandleHead->transfer.length = message->length; + serHandle->openedReadHandleHead->transfer.buffer = message->buffer; +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serHandle); +#endif +#else + status = kStatus_SerialManager_Notify; + + primask = DisableGlobalIRQ(); + + /* If wrap around is expected copy byte one after the other. Note that this could also be done with 2 memcopy for + * better efficiency. */ + if (serHandle->ringBuffer.ringHead + message->length >= serHandle->ringBuffer.ringBufferSize) + { + for (uint32_t i = 0; i < message->length; i++) + { + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead++] = message->buffer[i]; + + if (serHandle->ringBuffer.ringHead >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringHead = 0U; + } + if (serHandle->ringBuffer.ringHead == serHandle->ringBuffer.ringTail) + { + status = kStatus_SerialManager_RingBufferOverflow; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + } + } + else /*No wrap is expected so do a memcpy*/ + { + (void)memcpy(&serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead], message->buffer, + message->length); + serHandle->ringBuffer.ringHead += message->length; + } + + ringBufferLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize; + + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->transfer.buffer)) + { + if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar) + { + uint32_t remainLength = + serHandle->openedReadHandleHead->transfer.length - serHandle->openedReadHandleHead->transfer.soFar; + for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++) + { + serHandle->openedReadHandleHead->transfer.buffer[serHandle->openedReadHandleHead->transfer.soFar] = + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + serHandle->openedReadHandleHead->transfer.soFar++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength); + } + + if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar) + { + } + else + { + if (kSerialManager_TransmissionBlocking == serHandle->openedReadHandleHead->transfer.mode) + { + serHandle->openedReadHandleHead->transfer.buffer = NULL; + } + else + { + serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); +#else + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serHandle); +#endif + } + } + } +#if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U)) + uint32_t ringBufferWaterMark = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize; + if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) + { + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); + } +#else + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); +#endif + if (0U != ringBufferLength) + { +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) + if (serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] == 0) + { + serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY]++; + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); + } + + (void)status; /* Fix "set but never used" warning. */ +#else /* !SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + message->buffer = NULL; + message->length = ringBufferLength; + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback)) + { + serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, message, status); + } +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + } + +#if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \ + !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)))) + if (kSerialManager_Blocking == + serHandle->handleType) /* No need to check for (NULL != serHandle->openedReadHandleHead) condition as it is + already done in SerialManager_StartReading() */ +#else + if (NULL != serHandle->openedReadHandleHead) +#endif + { + ringBufferLength = serHandle->ringBuffer.ringBufferSize - 1U - ringBufferLength; + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); + } + EnableGlobalIRQ(primask); +#endif +} + +/* + * This function is used for perdiodic check if the transfer is complete, and will be called in blocking transfer at + * non-blocking mode. The perdiodic unit is ms and default value is define by + * SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE/SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE. The function + * SerialManager_WriteTimeDelay()/SerialManager_ReadTimeDelay() is a weak function, so it could be re-implemented by + * upper layer. + */ +__WEAK_FUNC void SerialManager_WriteTimeDelay(uint32_t ms); +__WEAK_FUNC void SerialManager_WriteTimeDelay(uint32_t ms) +{ +#if defined(OSA_USED) + OSA_TimeDelay(ms); +#endif +} + +__WEAK_FUNC void SerialManager_ReadTimeDelay(uint32_t ms); +__WEAK_FUNC void SerialManager_ReadTimeDelay(uint32_t ms) +{ +#if defined(OSA_USED) + OSA_TimeDelay(ms); +#endif +} + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *serHandle; + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + /* Do nothing. */ +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + serial_manager_status_t status = kStatus_SerialManager_Success; +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + + uint32_t primask; + uint8_t isEmpty = 0U; + + assert(NULL != writeHandle); + assert(NULL != buffer); + assert(length > 0U); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + serHandle = serialWriteHandle->serialManagerHandle; + assert(NULL != serHandle); + + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback))); + + primask = DisableGlobalIRQ(); + if (NULL != serialWriteHandle->transfer.buffer) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialWriteHandle->transfer.buffer = buffer; + serialWriteHandle->transfer.length = length; + serialWriteHandle->transfer.soFar = 0U; + serialWriteHandle->transfer.mode = mode; + + if (NULL == LIST_GetHead(&serHandle->runningWriteHandleHead)) + { + isEmpty = 1U; + } + SerialManager_AddTail(&serHandle->runningWriteHandleHead, serialWriteHandle); + EnableGlobalIRQ(primask); + + if (0U != isEmpty) + { +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); + +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + status = SerialManager_StartWriting(serHandle); + if ((serial_manager_status_t)kStatus_SerialManager_Success != status) + { +#if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) + if (status == kStatus_SerialManager_NotConnected) + { + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); + serialWriteHandle->transfer.buffer = 0U; + serialWriteHandle->transfer.length = 0U; + } +#endif /* USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1 */ + return status; + } +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar) + { + if (SerialManager_needPollingIsr()) + { + SerialManager_IsrFunction(serHandle); + } + else + { + SerialManager_WriteTimeDelay(SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE); + } + } + } + return kStatus_SerialManager_Success; +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode, + uint32_t *receivedLength) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *serHandle; + uint32_t dataLength; + uint32_t primask; + + assert(NULL != readHandle); + assert(NULL != buffer); + assert(length > 0U); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + serHandle = serialReadHandle->serialManagerHandle; + assert(NULL != serHandle); + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback))); + + primask = DisableGlobalIRQ(); + if (NULL != serialReadHandle->transfer.buffer) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialReadHandle->transfer.buffer = buffer; + serialReadHandle->transfer.length = length; + serialReadHandle->transfer.soFar = 0U; + serialReadHandle->transfer.mode = mode; + + /* This code is reached if (serHandle->handleType != kSerialManager_Blocking)*/ +#if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \ + !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)))) + if (length == 1U) + { + if (serHandle->ringBuffer.ringHead != serHandle->ringBuffer.ringTail) + { + buffer[serialReadHandle->transfer.soFar++] = + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + } + else +#endif /*(!defined(SERIAL_PORT_TYPE_USBCDC) && !defined(SERIAL_PORT_TYPE_VIRTUAL))*/ + { + dataLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + dataLength = dataLength % serHandle->ringBuffer.ringBufferSize; + + for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length); + serialReadHandle->transfer.soFar++) + { + buffer[serialReadHandle->transfer.soFar] = serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + + dataLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + dataLength = dataLength % serHandle->ringBuffer.ringBufferSize; + dataLength = serHandle->ringBuffer.ringBufferSize - 1U - dataLength; + + (void)SerialManager_StartReading(serHandle, readHandle, NULL, dataLength); + } + + if (NULL != receivedLength) + { + *receivedLength = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + } + else + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + if (kSerialManager_TransmissionNonBlocking == mode) + { + if (NULL != serialReadHandle->callback) + { + serial_manager_callback_message_t serialMsg; + serialMsg.buffer = buffer; + serialMsg.length = serialReadHandle->transfer.soFar; + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, + kStatus_SerialManager_Success); + } + } + } + else + { + EnableGlobalIRQ(primask); + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar) + { + SerialManager_ReadTimeDelay(SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE); + } + } + } +#if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U)) + uint32_t ringBufferWaterMark = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize; + if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) + { + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, + serialReadHandle->transfer.length); + } +#endif + return kStatus_SerialManager_Success; +} + +#else + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *serHandle; + + assert(writeHandle); + assert(buffer); + assert(length); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + serHandle = serialWriteHandle->serialManagerHandle; + + assert(serHandle); + + return SerialManager_StartWriting(serHandle, serialWriteHandle, buffer, length); +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *serHandle; + + assert(readHandle); + assert(buffer); + assert(length); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + serHandle = serialReadHandle->serialManagerHandle; + + assert(serHandle); + + return SerialManager_StartReading(serHandle, serialReadHandle, buffer, length); +} +#endif + +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig) +{ + serial_manager_handle_t *serHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(NULL != serialConfig); + + assert(NULL != serialHandle); + assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t)); + + serHandle = (serial_manager_handle_t *)serialHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + assert(NULL != serialConfig->ringBuffer); + assert(serialConfig->ringBufferSize > 0U); + (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE); + serHandle->handleType = serialConfig->blockType; +#else + (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE); +#endif + serHandle->serialPortType = serialConfig->type; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serHandle->ringBuffer.ringBuffer = serialConfig->ringBuffer; + serHandle->ringBuffer.ringBufferSize = serialConfig->ringBufferSize; +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + + COMMON_TASK_init(); + +#else + if (KOSA_StatusSuccess != OSA_SemaphoreCreate((osa_semaphore_handle_t)serHandle->serSemaphore, 1U)) + { + return kStatus_SerialManager_Error; + } + + if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)serHandle->taskId, OSA_TASK(SerialManager_Task), serHandle)) + { + return kStatus_SerialManager_Error; + } +#endif + +#endif + +#endif + + switch (serialConfig->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + (void)Serial_UartInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + + (void)Serial_UartInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + (void)Serial_UartDmaInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + + (void)Serial_UartDmaInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } +#endif + break; +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SwoInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + status = + Serial_PortVirtualInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortVirtualInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortVirtualInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + status = Serial_RpmsgInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), (void *)serialConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_RpmsgInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_RpmsgInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + status = + Serial_SpiMasterInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiMasterInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiMasterInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + status = Serial_SpiSlaveInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiSlaveInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiSlaveInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + status = + Serial_PortBleWuInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortBleWuInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortBleWuInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + + return status; +} + +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) +{ + serial_manager_handle_t *serHandle; + + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + + assert(NULL != serialHandle); + + serHandle = (serial_manager_handle_t *)serialHandle; + + if ((NULL != serHandle->openedReadHandleHead) || (0U != serHandle->openedWriteHandleCount)) + { + serialManagerStatus = kStatus_SerialManager_Busy; /*Serial Manager Busy*/ + } + else + { + switch (serHandle->serialPortType) /*serial port type*/ + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + (void)Serial_PortVirtualDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + (void)Serial_RpmsgDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + (void)Serial_SpiSlaveDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + (void)Serial_SpiMasterDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + (void)Serial_PortBleWuDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + (void)OSA_SemaphoreDestroy((osa_event_handle_t)serHandle->serSemaphore); + (void)OSA_TaskDestroy((osa_task_handle_t)serHandle->taskId); +#endif + +#endif + +#endif + } + return serialManagerStatus; +} + +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + + assert(NULL != serialHandle); + assert(NULL != writeHandle); + assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t)); + + serHandle = (serial_manager_handle_t *)serialHandle; + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + primask = DisableGlobalIRQ(); + serHandle->openedWriteHandleCount++; + EnableGlobalIRQ(primask); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (serHandle->handleType == kSerialManager_Blocking) + { + serialWriteHandle->serialManagerHandle = serHandle; + return kStatus_SerialManager_Success; + } + else +#endif + { + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); + } + + serialWriteHandle->serialManagerHandle = serHandle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG; +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *serialHandle; + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + + assert(NULL != writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + serialHandle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; + + assert(NULL != serialHandle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelWriting(writeHandle); +#endif + primask = DisableGlobalIRQ(); + if (serialHandle->openedWriteHandleCount > 0U) + { + serialHandle->openedWriteHandleCount--; + } + EnableGlobalIRQ(primask); +#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); +#else + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE); +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_read_handle_t *serialReadHandle; /* read handle structure */ + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + uint32_t primask; + + assert(NULL != serialHandle); + assert(NULL != readHandle); + assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t)); + + serHandle = (serial_manager_handle_t *)serialHandle; + serialReadHandle = (serial_manager_read_handle_t *)readHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (serHandle->handleType == kSerialManager_Blocking) + { + serialReadHandle->serialManagerHandle = serHandle; + return kStatus_SerialManager_Success; + } +#endif + primask = DisableGlobalIRQ(); + if (serHandle->openedReadHandleHead != NULL) + { + serialManagerStatus = kStatus_SerialManager_Busy; + } + else + { + serHandle->openedReadHandleHead = serialReadHandle; + + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); + + serialReadHandle->serialManagerHandle = serHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialReadHandle->tag = SERIAL_MANAGER_READ_TAG; +#endif + } + EnableGlobalIRQ(primask); + return serialManagerStatus; +} + +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle) +{ + serial_manager_handle_t *serialHandle; + serial_manager_read_handle_t *serialReadHandle; + uint32_t primask; + + assert(NULL != readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + serialHandle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; + + assert((NULL != serialHandle) && (serialHandle->openedReadHandleHead == serialReadHandle)); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelReading(readHandle); +#endif + + primask = DisableGlobalIRQ(); + serialHandle->openedReadHandleHead = NULL; + EnableGlobalIRQ(primask); +#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); +#else + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE); +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking); +#else + return SerialManager_Write(writeHandle, buffer, length); +#endif +} + +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL); +#else + return SerialManager_Read(readHandle, buffer, length); +#endif +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length) +{ + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking); +} + +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ +#if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \ + (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))) + + serial_manager_read_handle_t *serialReadHandle; + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + return (serial_manager_status_t)SerialManager_StartReading(serialReadHandle->serialManagerHandle, readHandle, + buffer, length); +#else + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL); +#endif +} + +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle) +{ + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + uint8_t isNotUsed = 0U; + uint8_t isNotNeed2Cancel = 0U; + + assert(NULL != writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(NULL != serialWriteHandle->serialManagerHandle); + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + if ((NULL != serialWriteHandle->transfer.buffer) && + (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead( + &serialWriteHandle->serialManagerHandle->runningWriteHandleHead)) + { + if (kLIST_Ok == LIST_RemoveElement(&serialWriteHandle->link)) + { + isNotUsed = 1U; + } + else + { + isNotNeed2Cancel = 1U; + } + } + EnableGlobalIRQ(primask); + + if (0U == isNotNeed2Cancel) + { + if (0U != isNotUsed) + { + serialWriteHandle->transfer.soFar = 0; + serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled; + + SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task; + serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = + serialWriteHandle->serialManagerHandle; + COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg); +#else + primask = DisableGlobalIRQ(); + serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serialWriteHandle->serialManagerHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serialWriteHandle->serialManagerHandle); +#endif + } + else + { + switch (serialWriteHandle->serialManagerHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + (void)Serial_PortVirtualCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + (void)Serial_SpiMasterCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + (void)Serial_SpiSlaveCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + (void)Serial_PortBleWuCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + } + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + primask = DisableGlobalIRQ(); + serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serialWriteHandle->serialManagerHandle->serSemaphore); + +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle); +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + } + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_callback_message_t serialMsg; + uint8_t *buffer; + uint32_t primask; + + assert(NULL != readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + if ((NULL != serialReadHandle->transfer.buffer) && + (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + buffer = serialReadHandle->transfer.buffer; + serialReadHandle->transfer.buffer = NULL; + serialReadHandle->transfer.length = 0; + serialMsg.buffer = buffer; + serialMsg.length = serialReadHandle->transfer.soFar; + EnableGlobalIRQ(primask); + + if (NULL != buffer) + { + if (NULL != serialReadHandle->callback) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength) +{ + assert(NULL != receivedLength); + + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength); +} + +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_write_handle_t *serialWriteHandle; + + assert(NULL != writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + serialWriteHandle->callbackParam = callbackParam; + serialWriteHandle->callback = callback; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_read_handle_t *serialReadHandle; + + assert(NULL != readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + serialReadHandle->callbackParam = callbackParam; + serialReadHandle->callback = callback; + + return kStatus_SerialManager_Success; +} +#endif + +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(NULL != serialHandle); + + serHandle = (serial_manager_handle_t *)serialHandle; + + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Rpmsg: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + return status; +} + +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(NULL != serialHandle); + + serHandle = (serial_manager_handle_t *)serialHandle; + + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Rpmsg: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + return status; +} +/*! + * @brief This function performs initialization of the callbacks structure used to disable lowpower + * when serial manager is active. + * + * + * @param pfCallback Pointer to the function structure used to allow/disable lowpower. + * + */ +void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback) +{ + s_pfserialLowpowerCriticalCallbacks = pfCallback; + (void)s_pfserialLowpowerCriticalCallbacks; +} diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h new file mode 100644 index 0000000000..16d7ef5a58 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h @@ -0,0 +1,856 @@ +/* + * Copyright 2018-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_MANAGER_H__ +#define __SERIAL_MANAGER_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup serialmanager + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U)) +#error When SERIAL_MANAGER_NON_BLOCKING_MODE=0, DEBUG_CONSOLE_TRANSFER_NON_BLOCKING can not be set. +#else +#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) +#endif +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U) +#endif +#endif + +/*! @brief Enable or ring buffer flow control (1 - enable, 0 - disable) */ +#ifndef SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL +#define SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL (0U) +#endif + +/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_UART +#define SERIAL_PORT_TYPE_UART (0U) +#endif + +/*! @brief Enable or disable uart dma port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_UART_DMA +#define SERIAL_PORT_TYPE_UART_DMA (0U) +#endif +/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_USBCDC +#define SERIAL_PORT_TYPE_USBCDC (0U) +#endif + +/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SWO +#define SERIAL_PORT_TYPE_SWO (0U) +#endif + +/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_VIRTUAL +#define SERIAL_PORT_TYPE_VIRTUAL (0U) +#endif + +/*! @brief Enable or disable rPMSG port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_RPMSG +#define SERIAL_PORT_TYPE_RPMSG (0U) +#endif + +/*! @brief Enable or disable SPI Master port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SPI_MASTER +#define SERIAL_PORT_TYPE_SPI_MASTER (0U) +#endif + +/*! @brief Enable or disable SPI Slave port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SPI_SLAVE +#define SERIAL_PORT_TYPE_SPI_SLAVE (0U) +#endif + +/*! @brief Enable or disable BLE WU port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_BLE_WU +#define SERIAL_PORT_TYPE_BLE_WU (0U) +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE == 1U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U)) +#warning When SERIAL_PORT_TYPE_SPI_SLAVE=1, SERIAL_MANAGER_NON_BLOCKING_MODE should be set. +#undef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) +#endif +#endif + +/*! @brief Set the default delay time in ms used by SerialManager_WriteTimeDelay(). */ +#ifndef SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE +#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE (1U) +#endif + +/*! @brief Set the default delay time in ms used by SerialManager_ReadTimeDelay(). */ +#ifndef SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE +#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE (1U) +#endif + +/*! @brief Enable or disable SerialManager_Task() handle RX data available notify */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY +#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY (0U) +#endif +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) +#ifndef OSA_USED +#error When SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY=1, OSA_USED must be set. +#endif +#endif + +/*! @brief Set serial manager write handle size */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U) +#else +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U) +#endif + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#include "fsl_component_serial_port_uart.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#include "fsl_component_serial_port_uart.h" +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) +#include "fsl_component_serial_port_rpmsg.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "fsl_component_serial_port_usb.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +#include "fsl_component_serial_port_swo.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) +#include "fsl_component_serial_port_spi.h" +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) +#include "fsl_component_serial_port_spi.h" +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "fsl_component_serial_port_virtual.h" +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for BLE WU. +#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */ + +#include "fsl_component_serial_port_ble_wu.h" +#endif /* SERIAL_PORT_TYPE_BLE_WU */ + +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + +#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#if (SERIAL_PORT_UART_DMA_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_DMA_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + +#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) +#if (SERIAL_PORT_SPI_MASTER_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_MASTER_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) +#if (SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + +#if (SERIAL_PORT_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_VIRTUAL_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + +#if (SERIAL_PORT_RPMSG_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_RPMSG_HANDLE_SIZE + +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + +#if (SERIAL_PORT_BLE_WU_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_BLE_WU_HANDLE_SIZE +#endif + +#endif + +/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */ +#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U))) +#else +#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO, SERIAL_PORT_TYPE_VIRTUAL, and SERIAL_PORT_TYPE_BLE_WU should not be cleared at same time. +#endif + +/*! @brief Macro to determine whether use common task. */ +#ifndef SERIAL_MANAGER_USE_COMMON_TASK +#define SERIAL_MANAGER_USE_COMMON_TASK (0U) +#endif + +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#endif +/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_TX +#define SERIAL_MANAGER_TASK_HANDLE_TX (1U) +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) +#include "fsl_os_abstraction.h" +#endif +#endif + +/*! @brief Definition of serial manager handle size. */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) +#define SERIAL_MANAGER_HANDLE_SIZE \ + (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U + OSA_TASK_HANDLE_SIZE + OSA_EVENT_HANDLE_SIZE) +#else /*defined(OSA_USED)*/ +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U) +#endif /*defined(OSA_USED)*/ +#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U) +#else +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#endif + +/*! + * @brief Defines the serial manager handle + * + * This macro is used to define a 4 byte aligned serial manager handle. + * Then use "(serial_handle_t)name" to get the serial manager handle. + * + * The macro should be global and could be optional. You could also define serial manager handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle); + * @endcode + * + * @param name The name string of the serial manager handle. + */ +#define SERIAL_MANAGER_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +/*! + * @brief Defines the serial manager write handle + * + * This macro is used to define a 4 byte aligned serial manager write handle. + * Then use "(serial_write_handle_t)name" to get the serial manager write handle. + * + * The macro should be global and could be optional. You could also define serial manager write handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle); + * @endcode + * + * @param name The name string of the serial manager write handle. + */ +#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +/*! + * @brief Defines the serial manager read handle + * + * This macro is used to define a 4 byte aligned serial manager read handle. + * Then use "(serial_read_handle_t)name" to get the serial manager read handle. + * + * The macro should be global and could be optional. You could also define serial manager read handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle); + * @endcode + * + * @param name The name string of the serial manager read handle. + */ +#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief Macro to set serial manager task priority. */ +#ifndef SERIAL_MANAGER_TASK_PRIORITY +#define SERIAL_MANAGER_TASK_PRIORITY (2U) +#endif + +/*! @brief Macro to set serial manager task stack size. */ +#ifndef SERIAL_MANAGER_TASK_STACK_SIZE +#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U) +#endif + +/*! @brief The handle of the serial manager module */ +typedef void *serial_handle_t; + +/*! @brief The write handle of the serial manager module */ +typedef void *serial_write_handle_t; + +/*! @brief The read handle of the serial manager module */ +typedef void *serial_read_handle_t; + +#ifndef _SERIAL_PORT_T_ +#define _SERIAL_PORT_T_ +/*! @brief serial port type*/ +typedef enum _serial_port_type +{ + kSerialPort_None = 0U, /*!< Serial port is none */ + kSerialPort_Uart = 1U, /*!< Serial port UART */ + kSerialPort_UsbCdc, /*!< Serial port USB CDC */ + kSerialPort_Swo, /*!< Serial port SWO */ + kSerialPort_Virtual, /*!< Serial port Virtual */ + kSerialPort_Rpmsg, /*!< Serial port RPMSG */ + kSerialPort_UartDma, /*!< Serial port UART DMA*/ + kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/ + kSerialPort_SpiSlave, /*!< Serial port SPISLAVE*/ + kSerialPort_BleWu, /*!< Serial port BLE WU */ +} serial_port_type_t; +#endif + +/*! @brief serial manager type*/ +typedef enum _serial_manager_type +{ + kSerialManager_NonBlocking = 0x0U, /*!< None blocking handle*/ + kSerialManager_Blocking = 0x8F41U, /*!< Blocking handle*/ +} serial_manager_type_t; +/*! @brief serial manager config structure*/ +typedef struct _serial_manager_config +{ +#if defined(SERIAL_MANAGER_NON_BLOCKING_MODE) + uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. + Besides, the memory space cannot be free during the lifetime of the serial + manager module. */ + uint32_t ringBufferSize; /*!< The size of the ring buffer */ +#endif + serial_port_type_t type; /*!< Serial port type */ + serial_manager_type_t blockType; /*!< Serial manager port type */ + void *portConfig; /*!< Serial port configuration */ +} serial_manager_config_t; + +/*! @brief serial manager error code*/ +typedef enum _serial_manager_status +{ + kStatus_SerialManager_Success = kStatus_Success, /*!< Success */ + kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */ + kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */ + kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */ + kStatus_SerialManager_Canceled = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */ + kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */ + kStatus_SerialManager_RingBufferOverflow = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */ + kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7), /*!< The host is not connected */ +} serial_manager_status_t; + +/*! @brief Callback message structure */ +typedef struct _serial_manager_callback_message +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ +} serial_manager_callback_message_t; + +/*! @brief serial manager callback function */ +typedef void (*serial_manager_callback_t)(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); + +/*! @brief serial manager Lowpower Critical callback function */ +typedef int32_t (*serial_manager_lowpower_critical_callback_t)(int32_t power_mode); +typedef struct _serial_manager_lowpower_critical_CBs_t +{ + serial_manager_lowpower_critical_callback_t serialEnterLowpowerCriticalFunc; + serial_manager_lowpower_critical_callback_t serialExitLowpowerCriticalFunc; +} serial_manager_lowpower_critical_CBs_t; +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure. + * + * This function configures the Serial Manager module with user-defined settings. + * The user can configure the configuration structure. + * The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE + * allocated by the caller. + * The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB + * CDC and swo. + * Please refer to #serial_port_type_t for serial port setting. + * These three types can be set by using #serial_manager_config_t. + * + * Example below shows how to use this API to configure the Serial Manager. + * For UART, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_uart_config_t uartConfig; + * config.type = kSerialPort_Uart; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * uartConfig.instance = 0; + * uartConfig.clockRate = 24000000; + * uartConfig.baudRate = 115200; + * uartConfig.parityMode = kSerialManager_UartParityDisabled; + * uartConfig.stopBitCount = kSerialManager_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * uartConfig.enableRxRTS = 0; + * uartConfig.enableTxCTS = 0; + * config.portConfig = &uartConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode + * For USB CDC, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_usb_cdc_config_t usbCdcConfig; + * config.type = kSerialPort_UsbCdc; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0; + * config.portConfig = &usbCdcConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode + * + * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle); + * or + * uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param serialConfig Pointer to user-defined configuration structure. + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed. + */ +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig); + +/*! + * @brief De-initializes the serial manager module instance. + * + * This function de-initializes the serial manager module instance. If the opened writing or + * reading handle is not closed, the function will return kStatus_SerialManager_Busy. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed. + * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed. + */ +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle); + +/*! + * @brief Opens a writing handle for the serial manager module. + * + * This function Opens a writing handle for the serial manager module. If the serial manager needs to + * be used in different tasks, the task should open a dedicated write handle for itself by calling + * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing + * handle at the same time, multiple writing handles need to be opened when the multiple transmission + * is needed for a task. + * + * @param serialHandle The serial manager module handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param writeHandle The serial manager module writing handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle); + * or + * uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_HandleConflict The writing handle was opened. + * @retval kStatus_SerialManager_Success The writing handle is opened. + * + * Example below shows how to use this API to write data. + * For task 1, + * @code + * static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1); + * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n"; + * SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1); + * SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1, + * Task1_SerialManagerTxCallback, + * s_serialWriteHandle1); + * SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1, + * s_nonBlockingWelcome1, + * sizeof(s_nonBlockingWelcome1) - 1U); + * @endcode + * For task 2, + * @code + * static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2); + * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n"; + * SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2); + * SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2, + * Task2_SerialManagerTxCallback, + * s_serialWriteHandle2); + * SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2, + * s_nonBlockingWelcome2, + * sizeof(s_nonBlockingWelcome2) - 1U); + * @endcode + */ +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle); + +/*! + * @brief Closes a writing handle for the serial manager module. + * + * This function Closes a writing handle for the serial manager module. + * + * @param writeHandle The serial manager module writing handle pointer. + * @retval kStatus_SerialManager_Success The writing handle is closed. + */ +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle); + +/*! + * @brief Opens a reading handle for the serial manager module. + * + * This function Opens a reading handle for the serial manager module. The reading handle can not be + * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when + * the previous reading handle is not closed. And there can only be one buffer for receiving for the + * reading handle at the same time. + * + * @param serialHandle The serial manager module handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param readHandle The serial manager module reading handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle); + * or + * uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The reading handle is opened. + * @retval kStatus_SerialManager_Busy Previous reading handle is not closed. + * + * Example below shows how to use this API to read data. + * @code + * static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle); + * SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle); + * static uint8_t s_nonBlockingBuffer[64]; + * SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle, + * APP_SerialManagerRxCallback, + * s_serialReadHandle); + * SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle, + * s_nonBlockingBuffer, + * sizeof(s_nonBlockingBuffer)); + * @endcode + */ +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle); + +/*! + * @brief Closes a reading for the serial manager module. + * + * This function Closes a reading for the serial manager module. + * + * @param readHandle The serial manager module reading handle pointer. + * @retval kStatus_SerialManager_Success The reading handle is closed. + */ +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle); + +/*! + * @brief Transmits data with the blocking mode. + * + * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking + * cannot be used at the same time. + * And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the blocking mode. + * + * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking + * cannot be used at the same time. + * And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief Transmits data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be sent. + * When all data is sent, the module notifies the upper layer through a TX callback function and passes + * the status parameter @ref kStatus_SerialManager_Success. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking + * cannot be used at the same time. And, the TX callback is mandatory before the function could be used. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be received. + * When all data is received, the module driver notifies the upper layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking + * cannot be used at the same time. And, the RX callback is mandatory before the function could be used. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Tries to read data. + * + * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be + * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length. + * After the data is copied, the actual data length is passed by the parameter length. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @param receivedLength Length received from the ring buffer directly. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength); + +/*! + * @brief Cancels unfinished send transmission. + * + * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer + * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of + * the function #SerialManager_WriteBlocking. + * + * @param writeHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the sending. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle); + +/*! + * @brief Cancels unfinished receive transmission. + * + * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper + * layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of + * the function #SerialManager_ReadBlocking. + * + * @param readHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the receiving. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle); + +/*! + * @brief Installs a TX callback and callback parameter. + * + * This function is used to install the TX callback and callback parameter for the serial manager module. + * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param writeHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam); + +/*! + * @brief Installs a RX callback and callback parameter. + * + * This function is used to install the RX callback and callback parameter for the serial manager module. + * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param readHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam); + +/*! + * @brief Check if need polling ISR. + * + * This function is used to check if need polling ISR. + * + * @retval TRUE if need polling. + */ +static inline bool SerialManager_needPollingIsr(void) +{ +#if (defined(__DSC__) && defined(__CW__)) + return !(isIRQAllowed()); +#elif defined(CPSR_M_Msk) + return (0x13 == (__get_CPSR() & CPSR_M_Msk)); +#elif defined(DAIF_I_BIT) + return (__get_DAIF() & DAIF_I_BIT); +#elif defined(__XCC__) + return (xthal_get_interrupt() & xthal_get_intenable()); +#else + return (0U != __get_IPSR()); +#endif +} +#endif + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle); + +/*! + * @brief This function performs initialization of the callbacks structure used to disable lowpower + * when serial manager is active. + * + * + * @param pfCallback Pointer to the function structure used to allow/disable lowpower. + * + */ +void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback); + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* __SERIAL_MANAGER_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h new file mode 100644 index 0000000000..c2090348d3 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h @@ -0,0 +1,189 @@ +/* + * Copyright 2019-2020, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_INTERNAL_H__ +#define __SERIAL_PORT_INTERNAL_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UartIsrFunction(serial_handle_t serialHandle); +#endif +serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle); +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UartDmaIsrFunction(serial_handle_t serialHandle); +#endif +serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) +serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +#endif +serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) +serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_SwoIsrFunction(serial_handle_t serialHandle); +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) +serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle); +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && SERIAL_PORT_TYPE_SPI_MASTER > 0U) +serial_manager_status_t Serial_SpiMasterInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_SpiMasterDeinit(serial_handle_t serialHandle); +void Serial_SpiMasterTxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam); +void Serial_SpiMasterRxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam); +serial_manager_status_t Serial_SpiMasterWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_SpiMasterRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SpiMasterInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiMasterInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiMasterCancelWrite(serial_handle_t serialHandle); + +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) +serial_manager_status_t Serial_SpiSlaveInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_SpiSlaveDeinit(serial_handle_t serialHandle); +void Serial_SpiSlaveTxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam); +void Serial_SpiSlaveRxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam); +serial_manager_status_t Serial_SpiSlaveWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_SpiSlaveRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SpiSlaveInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiSlaveInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiSlaveCancelWrite(serial_handle_t serialHandle); + +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) +serial_manager_status_t Serial_PortBleWuInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_PortBleWuDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortBleWuWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortBleWuRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortBleWuCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortBleWuInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_PortBleWuInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_PortBleWuIsrFunction(serial_handle_t serialHandle); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __SERIAL_PORT_INTERNAL_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c new file mode 100644 index 0000000000..c2073f7989 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c @@ -0,0 +1,717 @@ +/* + * Copyright 2018 -2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_component_serial_manager.h" +#include "fsl_component_serial_port_internal.h" + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) || \ + (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#include "fsl_adapter_uart.h" + +#include "fsl_component_serial_port_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U +typedef struct _serial_uart_send_state +{ + uint8_t *buffer; + uint32_t length; + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; +} serial_uart_send_state_t; + +typedef struct _serial_uart_recv_state +{ + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; + volatile uint8_t rxEnable; + uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH]; +} serial_uart_recv_state_t; + +typedef struct _serial_uart_dma_recv_state +{ + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; + volatile uint8_t rxEnable; + uint8_t readBuffer[SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH]; +} serial_uart_dma_recv_state_t; + +typedef struct _serial_uart_block_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); +} serial_uart_block_state_t; +#endif + +typedef struct _serial_uart_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_uart_send_state_t tx; + serial_uart_recv_state_t rx; +#endif +} serial_uart_state_t; +#endif +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +typedef struct _serial_uart_dma_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); + UART_DMA_HANDLE_DEFINE(uartDmaHandle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_uart_send_state_t tx; + serial_uart_dma_recv_state_t rx; +#endif +} serial_uart_dma_state_t; +#endif +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static serial_manager_status_t Serial_UartEnableReceiving(serial_uart_state_t *serialUartHandle) +{ +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + if (1U == serialUartHandle->rx.rxEnable) + { + serialUartHandle->rx.busy = 1U; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = &serialUartHandle->rx.readBuffer[0]; + transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); + if (kStatus_HAL_UartSuccess != + HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if (kStatus_HAL_UartSuccess != + HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) +#endif + { + serialUartHandle->rx.busy = 0U; + return kStatus_SerialManager_Error; + } + } + return kStatus_SerialManager_Success; +} + +/* UART user callback */ +static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t serialMsg; + + assert(userData); + serialUartHandle = (serial_uart_state_t *)userData; + + if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status) + { +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif + if ((NULL != serialUartHandle->rx.callback)) + { + serialMsg.buffer = &serialUartHandle->rx.readBuffer[0]; + serialMsg.length = sizeof(serialUartHandle->rx.readBuffer); + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg, + kStatus_SerialManager_Success); + } + } + else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status) + { + if (0U != serialUartHandle->tx.busy) + { + serialUartHandle->tx.busy = 0U; + if ((NULL != serialUartHandle->tx.callback)) + { + serialMsg.buffer = serialUartHandle->tx.buffer; + serialMsg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Success); + } + } + } + else + { + } +} +#endif + +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig) +{ + serial_uart_state_t *serialUartHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_port_uart_config_t *uartConfig = (serial_port_uart_config_t *)serialConfig; +#endif + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +#if 0 /* Not used below! */ + hal_uart_transfer_t transfer; +#endif +#endif +#endif + + assert(serialConfig); + assert(serialHandle); + assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t)); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + serialManagerStatus = (serial_manager_status_t)HAL_UartInit( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig); + assert(kStatus_SerialManager_Success == serialManagerStatus); + (void)serialManagerStatus; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->rx.rxEnable = uartConfig->enableRx; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + + (void)HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartCallback, serialUartHandle); +#else + (void)HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), Serial_UartCallback, + serialUartHandle); +#endif +#endif + + return serialManagerStatus; +} + +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif +#endif + (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->tx.busy = 0U; + serialUartHandle->rx.busy = 0U; +#endif + + return kStatus_SerialManager_Success; +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + hal_uart_status_t uartstatus; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + if (0U != serialUartHandle->tx.busy) + { + return kStatus_SerialManager_Busy; + } + serialUartHandle->tx.busy = 1U; + + serialUartHandle->tx.buffer = buffer; + serialUartHandle->tx.length = length; + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = buffer; + transfer.dataSize = length; + uartstatus = + HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer); +#else + + uartstatus = HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +#endif + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + assert(serialHandle); + (void)buffer; + (void)length; + return (serial_manager_status_t)Serial_UartEnableReceiving(serialHandle); +} + +#else + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + buffer, length); +} + +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartReceiveBlocking( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +} + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t serialMsg; + uint32_t primask; + uint8_t isBusy = 0U; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + primask = DisableGlobalIRQ(); + isBusy = serialUartHandle->tx.busy; + serialUartHandle->tx.busy = 0U; + EnableGlobalIRQ(primask); + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif + if (0U != isBusy) + { + if ((NULL != serialUartHandle->tx.callback)) + { + serialMsg.buffer = serialUartHandle->tx.buffer; + serialMsg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->tx.callback = callback; + serialUartHandle->tx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->rx.callback = callback; + serialUartHandle->rx.callbackParam = callbackParam; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)Serial_UartEnableReceiving(serialUartHandle); +#endif + return kStatus_SerialManager_Success; +} + +void Serial_UartIsrFunction(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +} +#endif + +serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_status_t status = kStatus_SerialManager_Success; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + status = Serial_UartEnableReceiving(serialUartHandle); +#endif + + return status; +} + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static serial_manager_status_t Serial_UartDmaEnableReceiving(serial_uart_dma_state_t *serialUartHandle) +{ + if (1U == serialUartHandle->rx.rxEnable) + { + serialUartHandle->rx.busy = 1U; + if (kStatus_HAL_UartDmaSuccess != + HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer), + false)) + + { + serialUartHandle->rx.busy = 0U; + return kStatus_SerialManager_Error; + } + } + return kStatus_SerialManager_Success; +} + +/* UART user callback */ +static void Serial_UartDmaCallback(hal_uart_dma_handle_t handle, hal_dma_callback_msg_t *dmaMsg, void *callbackParam) +{ + serial_uart_dma_state_t *serialUartHandle; + serial_manager_callback_message_t cb_msg; + + assert(callbackParam); + serialUartHandle = (serial_uart_dma_state_t *)callbackParam; + + if (((hal_uart_dma_status_t)kStatus_HAL_UartDmaRxIdle == dmaMsg->status) || + (kStatus_HAL_UartDmaIdleline == dmaMsg->status)) + { + if ((NULL != serialUartHandle->rx.callback)) + { + cb_msg.buffer = dmaMsg->data; + cb_msg.length = dmaMsg->dataSize; + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &cb_msg, kStatus_SerialManager_Success); + } + + if (kStatus_HAL_UartDmaSuccess == + HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer), + false)) + { + serialUartHandle->rx.busy = 1U; + } + } + else if (kStatus_HAL_UartDmaTxIdle == dmaMsg->status) + { + if (0U != serialUartHandle->tx.busy) + { + serialUartHandle->tx.busy = 0U; + if ((NULL != serialUartHandle->tx.callback)) + { + cb_msg.buffer = dmaMsg->data; + cb_msg.length = dmaMsg->dataSize; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &cb_msg, + kStatus_SerialManager_Success); + } + } + } + else + { + } +} + +#endif + +serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig) +{ + serial_uart_dma_state_t *serialUartHandle; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + serial_port_uart_dma_config_t *uartConfig = (serial_port_uart_dma_config_t *)serialConfig; +#endif + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + + assert(serialConfig); + assert(serialHandle); + + assert(SERIAL_PORT_UART_DMA_HANDLE_SIZE >= sizeof(serial_uart_dma_state_t)); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + serialManagerStatus = (serial_manager_status_t)HAL_UartInit( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig); + assert(kStatus_SerialManager_Success == serialManagerStatus); + (void)serialManagerStatus; + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + + hal_uart_dma_config_t dmaConfig; + + dmaConfig.uart_instance = uartConfig->instance; + dmaConfig.dma_instance = uartConfig->dma_instance; + dmaConfig.rx_channel = uartConfig->rx_channel; + dmaConfig.tx_channel = uartConfig->tx_channel; + dmaConfig.dma_mux_configure = uartConfig->dma_mux_configure; + dmaConfig.dma_channel_mux_configure = uartConfig->dma_channel_mux_configure; + + // Init uart dma + (void)HAL_UartDMAInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + (hal_uart_dma_handle_t *)serialUartHandle->uartDmaHandle, &dmaConfig); + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + serialUartHandle->rx.rxEnable = uartConfig->enableRx; + (void)HAL_UartDMATransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartDmaCallback, serialUartHandle); + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialManagerStatus = Serial_UartDmaEnableReceiving(serialUartHandle); +#endif + + return serialManagerStatus; +} + +serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + (void)HAL_UartDMAAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + + (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + (void)HAL_UartDMADeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->tx.busy = 0U; + serialUartHandle->rx.busy = 0U; +#endif + + return kStatus_SerialManager_Success; +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_dma_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + if (0U != serialUartHandle->tx.busy) + { + return kStatus_SerialManager_Busy; + } + serialUartHandle->tx.busy = 1U; + + serialUartHandle->tx.buffer = buffer; + serialUartHandle->tx.length = length; + + uartstatus = (hal_uart_status_t)HAL_UartDMATransferSend( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); + + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + serial_manager_callback_message_t serialMsg; + uint32_t primask; + uint8_t isBusy = 0U; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + primask = DisableGlobalIRQ(); + isBusy = serialUartHandle->tx.busy; + serialUartHandle->tx.busy = 0U; + EnableGlobalIRQ(primask); + + (void)HAL_UartDMAAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + + if (0U != isBusy) + { + if ((NULL != serialUartHandle->tx.callback)) + { + serialMsg.buffer = serialUartHandle->tx.buffer; + serialMsg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + serialUartHandle->tx.callback = callback; + serialUartHandle->tx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + serialUartHandle->rx.callback = callback; + serialUartHandle->rx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +void Serial_UartDmaIsrFunction(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +} +#endif + +serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + serial_manager_status_t status = kStatus_SerialManager_Success; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return status; +} +#endif +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h new file mode 100644 index 0000000000..a4221cbfe5 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h @@ -0,0 +1,106 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_UART_H__ +#define __SERIAL_PORT_UART_H__ + +#include "fsl_adapter_uart.h" + +/*! + * @addtogroup serial_port_uart + * @ingroup serialmanager + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief serial port uart handle size*/ + +#ifndef SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH +#define SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH (64U) +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE) +#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE) +#else +#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE) +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#define SERIAL_PORT_UART_DMA_HANDLE_SIZE (76U + HAL_UART_DMA_HANDLE_SIZE + 132U) +#endif + +#ifndef SERIAL_USE_CONFIGURE_STRUCTURE +#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */ +#endif + +/*! @brief serial port uart parity mode*/ +typedef enum _serial_port_uart_parity_mode +{ + kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kSerialManager_UartParityEven = 0x2U, /*!< Parity even enabled */ + kSerialManager_UartParityOdd = 0x3U, /*!< Parity odd enabled */ +} serial_port_uart_parity_mode_t; + +/*! @brief serial port uart stop bit count*/ +typedef enum _serial_port_uart_stop_bit_count +{ + kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */ + kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */ +} serial_port_uart_stop_bit_count_t; + +typedef struct _serial_port_uart_config +{ + uint32_t clockRate; /*!< clock rate */ + uint32_t baudRate; /*!< baud rate */ + serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ + +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif +} serial_port_uart_config_t; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +typedef struct _serial_port_uart_dma_config +{ + uint32_t clockRate; /*!< clock rate */ + uint32_t baudRate; /*!< baud rate */ + serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif + uint8_t dma_instance; + uint8_t rx_channel; + uint8_t tx_channel; + void *dma_mux_configure; + void *dma_channel_mux_configure; + +} serial_port_uart_dma_config_t; +#endif +/*! @} */ +#endif /* __SERIAL_PORT_UART_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_lpuart.c b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_lpuart.c new file mode 100644 index 0000000000..ee34ac7fbe --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_lpuart.c @@ -0,0 +1,2464 @@ +/* + * Copyright 2018, 2020, 2022, 2025 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +#include "fsl_adapter_uart.h" + +#if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) +#include "fsl_lpflexcomm.h" +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ + +/*! @brief MACROs for whether a software idleline detection should be used. */ +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +#define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (1) +#else /* HAL_UART_TRANSFER_MODE */ +#define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (0) +#endif /* HAL_UART_TRANSFER_MODE */ +#else /* UART_ADAPTER_NON_BLOCKING_MODE */ +#define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (1) +#endif /* UART_ADAPTER_NON_BLOCKING_MODE */ +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#include "fsl_component_timer_manager.h" +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +#include "fsl_lpuart_edma.h" +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#include "fsl_lpuart_dma.h" +#endif +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT +#include "fsl_dmamux.h" +#endif +#ifdef DMA_IRQS +#define DMA_CHN_IRQS DMA_IRQS +#endif +#endif /* HAL_UART_DMA_ENABLE */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#ifndef HAL_UART_ADAPTER_LOWPOWER_RESTORE +#define HAL_UART_ADAPTER_LOWPOWER_RESTORE (1) +#endif + +#ifndef HAL_UART_DMA_RING_BUFFER_ENABLE +#define HAL_UART_DMA_RING_BUFFER_ENABLE (0U) +#endif /* HAL_UART_DMA_ENABLE */ +#ifndef LPUART_RING_BUFFER_SIZE +#define LPUART_RING_BUFFER_SIZE (128U) +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_dma_receive_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; + volatile uint32_t timeout; + volatile bool receiveAll; +} hal_uart_dma_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_dma_send_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; + volatile uint32_t timeout; +} hal_uart_dma_send_state_t; + +typedef struct _hal_uart_dma_state +{ + struct _hal_uart_dma_state *next; + uint8_t instance; /* LPUART instance */ + hal_uart_dma_transfer_callback_t dma_callback; + void *dma_callback_param; + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + lpuart_edma_handle_t edmaHandle; + edma_handle_t txEdmaHandle; + edma_handle_t rxEdmaHandle; +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + lpuart_dma_handle_t dmaHandle; + dma_handle_t txDmaHandle; + dma_handle_t rxDmaHandle; +#endif + hal_uart_dma_receive_state_t dma_rx; + hal_uart_dma_send_state_t dma_tx; +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + dma_channel_mux_configure_t dma_channel_mux_configure; + dma_mux_configure_t dma_mux_configure; + hal_uart_dma_config_t hal_uart_dma_config; +#endif +} hal_uart_dma_state_t; + +typedef struct _lpuart_dma_list +{ +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) + TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle); +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + hal_uart_dma_state_t *dma_list; + volatile int8_t activeCount; +} hal_lpuart_dma_list_t; + +static hal_lpuart_dma_list_t s_dmaHandleList; +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_receive_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_send_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_send_state_t; +#endif +/*! @brief uart state structure. */ +typedef struct _hal_uart_state +{ + uint8_t instance; +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + hal_uart_transfer_callback_t callback; + void *callbackParam; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + lpuart_handle_t hardwareHandle; +#endif + hal_uart_receive_state_t rx; + hal_uart_send_state_t tx; +#endif +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) + uint32_t reg_BAUD; + uint32_t reg_CTRL; + uint32_t reg_WATER; + uint32_t reg_MODIR; +#else + hal_uart_config_t config; +#endif +#endif +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + hal_uart_dma_state_t *dmaHandle; +#endif /* HAL_UART_DMA_ENABLE */ +} hal_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static LPUART_Type *const s_LpuartAdapterBase[] = LPUART_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) +static const clock_ip_name_t s_LpuartAdapterClock[] = LPUART_CLOCKS; +#endif /* HAL_UART_ADAPTER_LOWPOWER_RESTORE */ +#endif /* HAL_UART_ADAPTER_LOWPOWER */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) +static const IRQn_Type s_LpuartRxIRQ[] = LPUART_RX_IRQS; +#endif +#if defined(LPUART_TX_IRQS) +static const IRQn_Type s_LpuartTxIRQ[] = LPUART_TX_IRQS; +#endif +#else +#if defined(LPUART_RX_TX_IRQS) +static const IRQn_Type s_LpuartIRQ[] = LPUART_RX_TX_IRQS; +#endif +#endif +#endif + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static hal_uart_state_t *s_UartState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)]; +#endif +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ +static hal_uart_dma_state_t *s_UartDmaState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)] = {0}; +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) +#warning HAL_UART_DMA_RING_BUFFER_ENABLE is deprecated and will be removed in a future release. +/* allocate ring buffer section. */ +AT_NONCACHEABLE_SECTION_INIT( + static uint8_t s_ringBuffer[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)][LPUART_RING_BUFFER_SIZE]) = {0}; +/* Allocate TCD memory poll with ring buffer used. */ +AT_NONCACHEABLE_SECTION_ALIGN( + static edma_tcd_t tcdMemoryPoolPtr[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)][1], sizeof(edma_tcd_t)); + +static volatile uint32_t ringBufferIndex[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)] = {0U}; +static void LPUART_StartRingBufferEDMA(hal_uart_handle_t handle); +static void LPUART_DMACallbacks(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData); +#endif +#endif /* HAL_UART_DMA_ENABLE */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \ + (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))) +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus = kStatus_HAL_UartError; + switch (status) + { + case (int32_t)kStatus_Success: + uartStatus = kStatus_HAL_UartSuccess; + break; + case (int32_t)kStatus_LPUART_TxBusy: + uartStatus = kStatus_HAL_UartTxBusy; + break; + case (int32_t)kStatus_LPUART_RxBusy: + uartStatus = kStatus_HAL_UartRxBusy; + break; + case (int32_t)kStatus_LPUART_TxIdle: + uartStatus = kStatus_HAL_UartTxIdle; + break; + case (int32_t)kStatus_LPUART_RxIdle: + uartStatus = kStatus_HAL_UartRxIdle; + break; + case (int32_t)kStatus_LPUART_BaudrateNotSupport: + uartStatus = kStatus_HAL_UartBaudrateNotSupport; + break; + case (int32_t)kStatus_LPUART_NoiseError: + case (int32_t)kStatus_LPUART_FramingError: + case (int32_t)kStatus_LPUART_ParityError: + uartStatus = kStatus_HAL_UartProtocolError; + break; + default: + /*MISRA rule 16.4*/ + break; + } + return uartStatus; +} +#else +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus; + if ((int32_t)kStatus_Success == status) + { + uartStatus = kStatus_HAL_UartSuccess; /* Successfully */ + } + else + { + uartStatus = kStatus_HAL_UartError; /* Error occurs on HAL uart */ + } + return uartStatus; +} +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) +static uint32_t HAL_UartGetDmaReceivedBytes(uint8_t instance) +{ + volatile uint32_t receivedBytes = 0U; + uint32_t remainingBytes = 0U; + uint32_t newIndex = 0U; + + hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance]; + + remainingBytes = + EDMA_GetRemainingMajorLoopCount(uartDmaHandle->rxEdmaHandle.base, uartDmaHandle->rxEdmaHandle.channel); + if (remainingBytes == LPUART_RING_BUFFER_SIZE) + { + remainingBytes = 0; + } + else + { + newIndex = LPUART_RING_BUFFER_SIZE - remainingBytes; + } + + if (newIndex < ringBufferIndex[instance]) + { + newIndex = newIndex + LPUART_RING_BUFFER_SIZE; + } + receivedBytes = newIndex - ringBufferIndex[instance]; + + return receivedBytes; +} +#endif +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ +static void HAL_UartDMARxIdlelineInterruptHandle(uint8_t instance) +{ + hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance]; + hal_dma_callback_msg_t dmaMsg; +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + uint32_t receiveLength = 0; + uint32_t callbackLength = 0; + uint32_t remianLength = 0; + uint32_t key; +#endif /* HAL_UART_DMA_RING_BUFFER_ENABLE */ + assert(uartDmaHandle); +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + if ((NULL != uartDmaHandle->dma_callback) && (NULL != uartDmaHandle->dma_rx.buffer)) + { + key = DisableGlobalIRQ(); +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + receiveLength = HAL_UartGetDmaReceivedBytes(instance); +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + if (uartDmaHandle->dma_rx.receiveAll == true) + { + if (receiveLength < uartDmaHandle->dma_rx.bufferLength) + { + LPUART_EnableInterrupts(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_IdleLineInterruptEnable); + EnableGlobalIRQ(key); + return; + } + } + callbackLength = + (receiveLength < uartDmaHandle->dma_rx.bufferLength) ? receiveLength : uartDmaHandle->dma_rx.bufferLength; + if (callbackLength != 0U) + { + dmaMsg.status = kStatus_HAL_UartDmaIdleline; + dmaMsg.dataSize = callbackLength; + + if (ringBufferIndex[instance] + callbackLength < LPUART_RING_BUFFER_SIZE) + { + (void)memcpy(uartDmaHandle->dma_rx.buffer, &s_ringBuffer[instance][ringBufferIndex[instance]], + callbackLength); + ringBufferIndex[instance] += callbackLength; + } + else + { + remianLength = callbackLength + ringBufferIndex[instance] - LPUART_RING_BUFFER_SIZE; + (void)memcpy(uartDmaHandle->dma_rx.buffer, &s_ringBuffer[instance][ringBufferIndex[instance]], + (callbackLength - remianLength)); + (void)memcpy(uartDmaHandle->dma_rx.buffer + (callbackLength - remianLength), &s_ringBuffer[instance][0], + remianLength); + ringBufferIndex[instance] = remianLength; + } + dmaMsg.data = uartDmaHandle->dma_rx.buffer; + uartDmaHandle->dma_rx.buffer = NULL; + + uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param); + } + EnableGlobalIRQ(key); + } +#else + if ((NULL != uartDmaHandle->dma_callback) && (NULL != uartDmaHandle->dma_rx.buffer)) + { + /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */ + /* HAL_UartDMAAbortReceive(uartDmaHandle); */ + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + EDMA_StopTransfer(uartDmaHandle->edmaHandle.rxEdmaHandle); + (void)LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->edmaHandle, &dmaMsg.dataSize); + LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + dmaMsg.status = kStatus_HAL_UartDmaIdleline; + dmaMsg.data = uartDmaHandle->dma_rx.buffer; + uartDmaHandle->dma_rx.buffer = NULL; + + uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param); + } + +#endif +} + +static void HAL_UartDMAIdlelineInterruptHandle(uint8_t instance, uint32_t status) +{ + hal_dma_callback_msg_t dmaMsg; + hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance]; + uint32_t sentCount = 0U; + + /* DMA send complete interrupt. */ + if ((NULL != uartDmaHandle) && (instance == uartDmaHandle->instance)) + { + if (NULL != uartDmaHandle->dma_tx.buffer) + { + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & + (uint32_t)kLPUART_TransmissionCompleteFlag))) + + { +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + (void)LPUART_TransferGetSendCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->edmaHandle, &sentCount); +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + + /* Disable tx complete interrupt */ + (void)LPUART_DisableInterrupts(s_LpuartAdapterBase[instance], + (uint32_t)kLPUART_TransmissionCompleteFlag); + uartDmaHandle->edmaHandle.txState = 0; + dmaMsg.status = kStatus_HAL_UartDmaTxIdle; + dmaMsg.data = uartDmaHandle->dma_tx.buffer; + dmaMsg.dataSize = uartDmaHandle->dma_tx.bufferLength; + uartDmaHandle->dma_tx.buffer = NULL; + uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param); + } + } + /* DMA receive Idleline interrupt. */ +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + if (NULL != uartDmaHandle->dma_rx.buffer) +#else + if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll)) +#endif + { + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & + (uint32_t)kLPUART_IdleLineInterruptEnable))) + { + HAL_UartDMARxIdlelineInterruptHandle(instance); + (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_IdleLineFlag); + } + } + } +} +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static void HAL_UartCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + assert(callbackParam); + + uartHandle = (hal_uart_state_t *)callbackParam; + + if (kStatus_HAL_UartProtocolError == uartStatus) + { + if (0U != uartHandle->hardwareHandle.rxDataSize) + { + uartStatus = kStatus_HAL_UartError; + } + } + + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); + } +} + +#else /* HAL_UART_TRANSFER_MODE */ + +static void HAL_UartInterruptHandle(uint8_t instance) +{ + hal_uart_state_t *uartHandle = s_UartState[instance]; + uint32_t status; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t count; +#endif + + assert(NULL != uartHandle); + + status = LPUART_GetStatusFlags(s_LpuartAdapterBase[instance]); + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + HAL_UartDMAIdlelineInterruptHandle(instance, status); +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + s_LpuartAdapterBase[instance]->STAT = + ((s_LpuartAdapterBase[instance]->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + } +#endif + if ((0u != ((uint32_t)kLPUART_NoiseErrorFlag & status)) || (0u != ((uint32_t)kLPUART_FramingErrorFlag & status)) || + (0u != ((uint32_t)kLPUART_ParityErrorFlag & status))) + { + if (0u != ((uint32_t)kLPUART_NoiseErrorFlag & status)) + { + (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_NoiseErrorFlag); + } + if (0u != ((uint32_t)kLPUART_FramingErrorFlag & status)) + { + (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_FramingErrorFlag); + } + if (0u != ((uint32_t)kLPUART_ParityErrorFlag & status)) + { + (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_ParityErrorFlag); + } + + /*clean RDRF flag and drop the data with status error*/ + if (0u != ((uint32_t)(kLPUART_RxDataRegFullFlag)&status)) + { + (void)LPUART_ReadByte(s_LpuartAdapterBase[instance]); + } + status = LPUART_GetStatusFlags(s_LpuartAdapterBase[instance]); + } +#if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) + if (((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && +#else + /* Receive data register full */ + if (((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ + (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & + (uint32_t)kLPUART_RxDataRegFullInterruptEnable))) +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + || ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != + (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable))) +#endif + ) + { + if (NULL != uartHandle->rx.buffer) + { +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_RXCOUNT_MASK) >> + LPUART_WATER_RXCOUNT_SHIFT)); +#else + if (0U != (status & (uint32_t)kLPUART_RxDataRegFullInterruptEnable)) + { + count = 1U; + } + else + { + count = 0U; + } +#endif + while (0u != count) + { + count--; +#endif + uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = LPUART_ReadByte(s_LpuartAdapterBase[instance]); + if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) + { + LPUART_DisableInterrupts( + s_LpuartAdapterBase[instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + | (uint32_t)kLPUART_IdleLineInterruptEnable +#endif + ); + uartHandle->rx.buffer = NULL; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + count = 0u; +#endif + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); + } + } +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + } +#endif + } +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != + (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable))) + { + s_LpuartAdapterBase[instance]->STAT |= ((uint32_t)kLPUART_IdleLineFlag); + } +#endif + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != (LPUART_STAT_TDRE_MASK & status)) && (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & + (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable))) + { + if (NULL != uartHandle->tx.buffer) + { +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + /* Get the size that transmit buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[instance]) - + (uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_TXCOUNT_MASK) >> + LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1u; +#endif + while (0u != count) + { + count--; +#endif + LPUART_WriteByte(s_LpuartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); + if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) + { + LPUART_DisableInterrupts(s_LpuartAdapterBase[instance], + (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + uartHandle->tx.buffer = NULL; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + count = 0u; +#endif + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); + } + } +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + } +#endif + } + } + +#if !(defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], status); +#endif +} +#endif /* HAL_UART_TRANSFER_MODE */ +#if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) +static void HAL_LpUartInterruptHandle_Wrapper(uint32_t instance, void *handle) +{ + hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle; + HAL_UartInterruptHandle(uartHandle->instance); +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ + +#endif /* UART_ADAPTER_NON_BLOCKING_MODE */ + +static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *uart_config) +{ + lpuart_config_t lpuartConfig; + status_t status; + hal_uart_status_t uartStatus = kStatus_HAL_UartSuccess; + + LPUART_GetDefaultConfig(&lpuartConfig); + lpuartConfig.baudRate_Bps = uart_config->baudRate_Bps; + lpuartConfig.parityMode = (lpuart_parity_mode_t)uart_config->parityMode; + lpuartConfig.stopBitCount = (lpuart_stop_bit_count_t)uart_config->stopBitCount; + lpuartConfig.enableRx = (bool)uart_config->enableRx; + lpuartConfig.enableTx = (bool)uart_config->enableTx; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + if (uart_config->txFifoWatermark > 0U) + { + lpuartConfig.txFifoWatermark = + MIN(uart_config->txFifoWatermark, + (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[uart_config->instance])) - + 1U; + } + if (uart_config->rxFifoWatermark > 0U) + { + lpuartConfig.rxFifoWatermark = + MIN(uart_config->rxFifoWatermark, + (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[uart_config->instance])) - + 1U; + } +#endif +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + lpuartConfig.enableRxRTS = (bool)uart_config->enableRxRTS; + lpuartConfig.enableTxCTS = (bool)uart_config->enableTxCTS; +#endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */ + + /* Idleline config */ +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + lpuartConfig.rxIdleType = kLPUART_IdleTypeStopBit; + lpuartConfig.rxIdleConfig = kLPUART_IdleCharacter2; +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + + status = LPUART_Init(s_LpuartAdapterBase[uart_config->instance], (const lpuart_config_t *)&lpuartConfig, uart_config->srcClock_Hz); + + if ((int32_t)kStatus_Success != status) + { + uartStatus = HAL_UartGetStatus(status); /*Get current uart status*/ + } + + return uartStatus; +} + +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t uartStatus; + assert(NULL != handle); + assert(NULL != uart_config); + assert(uart_config->instance < (sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *))); + assert(NULL != s_LpuartAdapterBase[uart_config->instance]); + assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t)); + + uartStatus = HAL_UartInitCommon(handle, uart_config); + + if (kStatus_HAL_UartSuccess == uartStatus) + { + uartHandle = (hal_uart_state_t *)handle; + uartHandle->instance = uart_config->instance; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + uartHandle->dmaHandle = NULL; +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + LPUART_TransferCreateHandle(s_LpuartAdapterBase[uart_config->instance], &uartHandle->hardwareHandle, + (lpuart_transfer_callback_t)HAL_UartCallback, handle); +#else + s_UartState[uartHandle->instance] = uartHandle; +#if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) + LP_FLEXCOMM_SetIRQHandler(uart_config->instance, HAL_LpUartInterruptHandle_Wrapper, handle, + LP_FLEXCOMM_PERIPH_LPUART); +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); +#endif +#if defined(LPUART_TX_IRQS) + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#endif +#else +#if defined(LPUART_RX_TX_IRQS) + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +#endif + +#endif +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) + uartHandle->reg_BAUD = s_LpuartAdapterBase[uartHandle->instance]->BAUD; + uartHandle->reg_CTRL = s_LpuartAdapterBase[uartHandle->instance]->CTRL; + uartHandle->reg_WATER = s_LpuartAdapterBase[uartHandle->instance]->WATER; + uartHandle->reg_MODIR = s_LpuartAdapterBase[uartHandle->instance]->MODIR; +#else + (void)memcpy(&uartHandle->config, uart_config, sizeof(hal_uart_config_t)); +#endif +#endif + } + + return uartStatus; +} + +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + + assert(NULL != handle); + + uartHandle = (hal_uart_state_t *)handle; + + LPUART_Deinit(s_LpuartAdapterBase[uartHandle->instance]); /*LPUART Deinitialization*/ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + s_UartState[uartHandle->instance] = NULL; +#endif + +#endif + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(NULL != handle); + assert(NULL != data); + assert(length > 0U); + + uartHandle = (hal_uart_state_t *)handle; + + status = LPUART_ReadBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + + assert(NULL != handle); + assert(NULL != data); + assert(length > 0U); + + uartHandle = (hal_uart_state_t *)handle; + + (void)LPUART_WriteBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle) +{ + assert(NULL != handle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle) +{ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + hal_uart_state_t *uartHandle; + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable lpuart clock */ + CLOCK_EnableClock(s_LpuartAdapterClock[uartHandle->instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + s_LpuartAdapterBase[uartHandle->instance]->BAUD = uartHandle->reg_BAUD; + s_LpuartAdapterBase[uartHandle->instance]->WATER = uartHandle->reg_WATER; + s_LpuartAdapterBase[uartHandle->instance]->MODIR = uartHandle->reg_MODIR; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Enable tx/rx FIFO */ + s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + /* Flush FIFO */ + s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif /* FSL_FEATURE_LPUART_HAS_FIFO */ + s_LpuartAdapterBase[uartHandle->instance]->CTRL = uartHandle->reg_CTRL; +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + s_UartState[uartHandle->instance] = handle; +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); +#endif +#if defined(LPUART_TX_IRQS) + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#endif +#else +#if defined(LPUART_RX_TX_IRQS) + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif + s_LpuartAdapterBase[uartHandle->instance]->CTRL |= LPUART_CTRL_RIE_MASK; + HAL_UartIsrFunction(uartHandle); + +#endif +#else + (void)HAL_UartInit(handle, &uartHandle->config); +#endif +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else + /* Enable RX interrupt for detecting the IDLE line interrupt. */ + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], kLPUART_IdleLineInterruptEnable); +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + HAL_UartDMAInit(uartHandle, uartHandle->dmaHandle, &uartHandle->dmaHandle->hal_uart_dma_config); + LPUART_StartRingBufferEDMA(handle); + ringBufferIndex[uartHandle->instance] = 0; +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ +#endif +#endif + return kStatus_HAL_UartSuccess; +} + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = LPUART_TransferReceiveNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (lpuart_transfer_t *)(void *)transfer, NULL); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = LPUART_TransferSendNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (lpuart_transfer_t *)(void *)transfer); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = + LPUART_TransferGetReceiveCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = LPUART_TransferGetSendCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + LPUART_TransferAbortReceive(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + LPUART_TransferAbortSend(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +#else /* HAL_UART_TRANSFER_MODE */ + +/* None transactional API with non-blocking mode. */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(NULL != handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(NULL != data); + assert(length > 0U); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + if (NULL != uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } + + uartHandle->rx.bufferLength = length; + uartHandle->rx.bufferSofar = 0; + uartHandle->rx.buffer = data; + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + | (uint32_t)kLPUART_IdleLineInterruptEnable +#endif + ); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(NULL != data); + assert(length > 0U); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + if (NULL != uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } + uartHandle->tx.bufferLength = length; + uartHandle->tx.bufferSofar = 0; + uartHandle->tx.buffer = data; + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(NULL != reCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + if (NULL != uartHandle->rx.buffer) + { + *reCount = uartHandle->rx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(NULL != seCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + if (NULL != uartHandle->tx.buffer) + { + *seCount = uartHandle->tx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + LPUART_DisableInterrupts( + s_LpuartAdapterBase[uartHandle->instance], + (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + uartHandle->rx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + LPUART_DisableInterrupts(s_LpuartAdapterBase[uartHandle->instance], + (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + uartHandle->tx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +#endif /* HAL_UART_TRANSFER_MODE */ + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + DisableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +#if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) + LPUART_TransferHandleIRQ(uartHandle->instance, &uartHandle->hardwareHandle); +#else /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ + LPUART_TransferHandleIRQ(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +} + +#else /* HAL_UART_TRANSFER_MODE */ + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(NULL != handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[uartHandle->instance]; +#endif +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + DisableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + if ((NULL != uartDmaHandle) && (uartDmaHandle->dma_tx.buffer != NULL)) + { + EDMA_HandleIRQ(&uartHandle->dmaHandle->txEdmaHandle); + } +#endif +#endif + + HAL_UartInterruptHandle(uartHandle->instance); + +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_IRQHandler(void) +{ + if ((s_UartState[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) || + ((LPUART_STAT_IDLE_MASK & LPUART0->STAT) && (LPUART_STAT_IDLE_MASK & LPUART0->CTRL))) + { + HAL_UartInterruptHandle(0); + } + } + if ((s_UartState[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) || + ((LPUART_STAT_IDLE_MASK & LPUART1->STAT) && (LPUART_STAT_IDLE_MASK & LPUART1->CTRL))) + { + HAL_UartInterruptHandle(1); + } + } + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_LPUART1_TX_IRQHandler(void) +{ + if ((s_UartState[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)) || + ((LPUART_CTRL_TCIE_MASK & LPUART0->STAT) && (LPUART_CTRL_TCIE_MASK & LPUART0->CTRL))) + { + HAL_UartInterruptHandle(0); + } + } + if ((s_UartState[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)) || + ((LPUART_CTRL_TCIE_MASK & LPUART1->STAT) && (LPUART_CTRL_TCIE_MASK & LPUART1->CTRL))) + { + HAL_UartInterruptHandle(1); + } + } + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +void LPUART0_LPUART1_IRQHandler(void); +void LPUART0_LPUART1_IRQHandler(void) +{ + uint32_t orMask; + uint32_t rdrfMask; + uint32_t rieMask; + uint32_t tdreMask; + uint32_t tieMask; + uint32_t ilieMask; + uint32_t tcieMask; + if (NULL != (s_UartState[0])) + { + orMask = LPUART_STAT_OR_MASK & LPUART0->STAT; + rdrfMask = LPUART_STAT_RDRF_MASK & LPUART0->STAT; + rieMask = LPUART_CTRL_RIE_MASK & LPUART0->CTRL; + tdreMask = LPUART0->STAT & LPUART_STAT_TDRE_MASK; + tieMask = LPUART0->CTRL & LPUART_CTRL_TIE_MASK; + ilieMask = LPUART0->STAT & LPUART_CTRL_ILIE_MASK; + tcieMask = LPUART0->STAT & LPUART_CTRL_TCIE_MASK; + if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask) || (bool)ilieMask || + (bool)tcieMask) + { + HAL_UartInterruptHandle(0); + } + } + if (NULL != (s_UartState[1])) + { + orMask = LPUART_STAT_OR_MASK & LPUART1->STAT; + rdrfMask = LPUART_STAT_RDRF_MASK & LPUART1->STAT; + rieMask = LPUART_CTRL_RIE_MASK & LPUART1->CTRL; + tdreMask = LPUART1->STAT & LPUART_STAT_TDRE_MASK; + tieMask = LPUART1->CTRL & LPUART_CTRL_TIE_MASK; + ilieMask = LPUART1->STAT & LPUART_CTRL_ILIE_MASK; + tcieMask = LPUART1->STAT & LPUART_CTRL_TCIE_MASK; + if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask) || (bool)ilieMask || + (bool)tcieMask) + { + HAL_UartInterruptHandle(1); + } + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */ + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART0_IRQHandler(void); +void LPUART0_IRQHandler(void) +{ + HAL_UartInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */ +#endif /* LPUART0 */ + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +void LPUART1_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART1_IRQHandler(void); +void LPUART1_IRQHandler(void) +{ + HAL_UartInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */ +#endif /* LPUART1 */ + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +void LPUART2_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART2_IRQHandler(void); +void LPUART2_IRQHandler(void) +{ + HAL_UartInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART2 */ + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +void LPUART3_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART3_IRQHandler(void); +void LPUART3_IRQHandler(void) +{ + HAL_UartInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART3 */ + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(4); + SDK_ISR_EXIT_BARRIER; +} +void LPUART4_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(4); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART4_IRQHandler(void); +void LPUART4_IRQHandler(void) +{ + HAL_UartInterruptHandle(4); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART4 */ + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(5); + SDK_ISR_EXIT_BARRIER; +} +void LPUART5_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(5); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART5_IRQHandler(void); +void LPUART5_IRQHandler(void) +{ + HAL_UartInterruptHandle(5); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART5 */ + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(6); + SDK_ISR_EXIT_BARRIER; +} +void LPUART6_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(6); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART6_IRQHandler(void); +void LPUART6_IRQHandler(void) +{ + HAL_UartInterruptHandle(6); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART6 */ + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(7); + SDK_ISR_EXIT_BARRIER; +} +void LPUART7_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(7); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART7_IRQHandler(void); +void LPUART7_IRQHandler(void) +{ + HAL_UartInterruptHandle(7); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART7 */ + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(8); + SDK_ISR_EXIT_BARRIER; +} +void LPUART8_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(8); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART8_IRQHandler(void); +void LPUART8_IRQHandler(void) +{ + HAL_UartInterruptHandle(8); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART8 */ + +#if defined(LPUART9) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART9_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(9); + SDK_ISR_EXIT_BARRIER; +} +void LPUART9_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(9); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART9_IRQHandler(void); +void LPUART9_IRQHandler(void) +{ + HAL_UartInterruptHandle(9); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART9 */ + +#if defined(LPUART10) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART10_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(10); + SDK_ISR_EXIT_BARRIER; +} +void LPUART10_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(10); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART10_IRQHandler(void); +void LPUART10_IRQHandler(void) +{ + HAL_UartInterruptHandle(10); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART10 */ + +#if defined(LPUART11) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART11_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(11); + SDK_ISR_EXIT_BARRIER; +} +void LPUART11_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(11); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART11_IRQHandler(void); +void LPUART11_IRQHandler(void) +{ + HAL_UartInterruptHandle(11); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART11 */ + +#if defined(LPUART12) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART12_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(12); + SDK_ISR_EXIT_BARRIER; +} +void LPUART12_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(12); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART12_IRQHandler(void); +void LPUART12_IRQHandler(void) +{ + HAL_UartInterruptHandle(12); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART12 */ + +#if defined(LPUART13) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART13_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(13); + SDK_ISR_EXIT_BARRIER; +} +void LPUART13_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(13); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART13_IRQHandler(void); +void LPUART13_IRQHandler(void) +{ + HAL_UartInterruptHandle(13); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART13 */ + +#if defined(LPUART17) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART17_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(17); + SDK_ISR_EXIT_BARRIER; +} +void LPUART17_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(17); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART17_IRQHandler(void); +void LPUART17_IRQHandler(void) +{ + HAL_UartInterruptHandle(17); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART17 */ + +#if defined(LPUART18) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART18_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(18); + SDK_ISR_EXIT_BARRIER; +} +void LPUART18_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(18); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART18_IRQHandler(void); +void LPUART18_IRQHandler(void) +{ + HAL_UartInterruptHandle(18); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART18 */ + +#if defined(LPUART19) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART19_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(19); + SDK_ISR_EXIT_BARRIER; +} +void LPUART19_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(19); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART19_IRQHandler(void); +void LPUART19_IRQHandler(void) +{ + HAL_UartInterruptHandle(19); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART19 */ + +#if defined(LPUART20) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART20_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(20); + SDK_ISR_EXIT_BARRIER; +} +void LPUART20_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(20); + SDK_ISR_EXIT_BARRIER; +} +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if !(defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && FSL_FEATURE_LPUART_IS_LPFLEXCOMM) +void LPUART20_IRQHandler(void); +void LPUART20_IRQHandler(void) +{ + HAL_UartInterruptHandle(20); + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* LPUART20 */ + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_IRQHandler(void); +void M4_0_LPUART_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(CM4_0__LPUART)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_IRQHandler(void); +void M4_1_LPUART_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(CM4_1__LPUART)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_IRQHandler(void); +void M4_LPUART_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(CM4__LPUART)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART0)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART1)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART2)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART3)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART4)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_IRQHandler(void); +void ADMA_UART0_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART0)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_IRQHandler(void); +void ADMA_UART1_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART1)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_IRQHandler(void); +void ADMA_UART2_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART2)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_IRQHandler(void); +void ADMA_UART3_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART3)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#endif /* HAL_UART_TRANSFER_MODE */ + +#endif /* UART_ADAPTER_NON_BLOCKING_MODE */ + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) +static volatile uint32_t ringBufferFlag = 0U; +/* LPUART RX EDMA call back. */ +static void LPUART_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + if (true == transferDone) + { + ringBufferFlag++; + } +} + +/* Start ring buffer. */ +static void LPUART_StartRingBufferEDMA(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + edma_transfer_config_t xferConfig; + + /* Install TCD memory for using only one TCD queue. */ + EDMA_InstallTCDMemory(&uartDmaHandle->rxEdmaHandle, (edma_tcd_t *)&tcdMemoryPoolPtr[uartHandle->instance], 1U); + + /* Prepare transfer to receive data to ring buffer. */ + EDMA_PrepareTransfer(&xferConfig, + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(s_LpuartAdapterBase[uartHandle->instance]), + sizeof(uint8_t), &s_ringBuffer[uartHandle->instance], sizeof(uint8_t), sizeof(uint8_t), + LPUART_RING_BUFFER_SIZE, kEDMA_PeripheralToMemory); + + /* Submit transfer. */ + uartDmaHandle->rxEdmaHandle.tcdUsed = 1U; + uartDmaHandle->rxEdmaHandle.tail = 0U; + EDMA_TcdReset(&uartDmaHandle->rxEdmaHandle.tcdPool[0U]); + EDMA_TcdSetTransferConfig(&uartDmaHandle->rxEdmaHandle.tcdPool[0U], &xferConfig, + tcdMemoryPoolPtr[uartHandle->instance]); + + /* Enable major interrupt for counting received bytes. */ + EDMA_TcdEnableInterrupts(&uartDmaHandle->rxEdmaHandle.tcdPool[0U], (uint32_t)kEDMA_MajorInterruptEnable); + + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(uartDmaHandle->rxEdmaHandle.base, uartDmaHandle->rxEdmaHandle.channel, + &uartDmaHandle->rxEdmaHandle.tcdPool[0U]); + + /* Setup call back function. */ + EDMA_SetCallback(&uartDmaHandle->rxEdmaHandle, LPUART_RxEDMACallback, NULL); + + /* Start EDMA transfer. */ + EDMA_StartTransfer(&uartDmaHandle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(s_LpuartAdapterBase[uartHandle->instance], true); + + /* Enable RX interrupt for detecting the IDLE line interrupt. */ + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); + // EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); +} +#endif +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +static void LPUART_DMACallbacks(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData) +{ + hal_uart_dma_state_t *uartDmaHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + hal_dma_callback_msg_t dmaMsg; + assert(handle); + + uartDmaHandle = (hal_uart_dma_state_t *)userData; + + if (NULL != uartDmaHandle->dma_callback) + { + if (kStatus_HAL_UartTxIdle == uartStatus) + { + dmaMsg.status = kStatus_HAL_UartDmaTxIdle; + dmaMsg.data = uartDmaHandle->dma_tx.buffer; + dmaMsg.dataSize = uartDmaHandle->dma_tx.bufferLength; + uartDmaHandle->dma_tx.buffer = NULL; + } + else if (kStatus_HAL_UartRxIdle == uartStatus) + { + dmaMsg.status = kStatus_HAL_UartDmaRxIdle; + dmaMsg.data = uartDmaHandle->dma_rx.buffer; + dmaMsg.dataSize = uartDmaHandle->dma_rx.bufferLength; + uartDmaHandle->dma_rx.buffer = NULL; + } + else + { + /* MISRA */ + } + + uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param); + } +} +#endif +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +static void TimeoutTimer_Callbcak(void *param) +{ + hal_lpuart_dma_list_t *uartDmaHandleList; + hal_uart_dma_state_t *uartDmaHandle; + hal_dma_callback_msg_t dmaMsg; + uint32_t newReceived = 0U; + + uartDmaHandleList = (hal_lpuart_dma_list_t *)param; + uartDmaHandle = uartDmaHandleList->dma_list; + + while (NULL != uartDmaHandle) + { + if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll)) + { + /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */ +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + +#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, + &dmaMsg.dataSize); +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + newReceived = dmaMsg.dataSize - uartDmaHandle->dma_rx.bufferSofar; + uartDmaHandle->dma_rx.bufferSofar = dmaMsg.dataSize; + + /* 1, If it is in idle state. */ + if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) + { + uartDmaHandle->dma_rx.timeout++; + if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT) + { + /* HAL_UartDMAAbortReceive(uartDmaHandle); */ +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + +#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->edmaHandle); +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + dmaMsg.data = uartDmaHandle->dma_rx.buffer; + dmaMsg.status = kStatus_HAL_UartDmaIdleline; + uartDmaHandle->dma_rx.buffer = NULL; + uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param); + } + } + /* 2, If got new data again. */ + if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) + { + uartDmaHandle->dma_rx.timeout = 0U; + } + } + + uartDmaHandle = uartDmaHandle->next; + } +} +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + +hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, + hal_uart_dma_handle_t dmaHandle, + hal_uart_dma_config_t *dmaConfig) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +#if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U)) + edma_config_t config; +#endif /* HAL_UART_DMA_INIT_ENABLE > 0 */ +#endif + assert(handle); + assert(dmaHandle); + assert(HAL_UART_DMA_HANDLE_SIZE >= sizeof(hal_uart_dma_state_t)); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle; + uartHandle->dmaHandle = uartDmaHandle; + + /* DMA init process. */ + uartDmaHandle->instance = dmaConfig->uart_instance; + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) + dma_mux_configure_t *dmaMux = dmaConfig->dma_mux_configure; + /* Set channel for LPUART */ + DMAMUX_Type *dmaMuxBases[] = DMAMUX_BASE_PTRS; +#if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U)) + DMAMUX_Init(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance]); +#endif /* HAL_UART_DMA_INIT_ENABLE > 0 */ + DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel, + (int32_t)dmaMux->dma_dmamux_configure.tx_request); + DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel, + (int32_t)dmaMux->dma_dmamux_configure.rx_request); + DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel); + DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel); +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + (void)memcpy(&uartDmaHandle->dma_mux_configure, dmaConfig->dma_mux_configure, sizeof(dma_mux_configure_t)); +#endif /* HAL_UART_ADAPTER_LOWPOWER */ +#endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ + /* Init the EDMA module */ +#if defined(EDMA_BASE_PTRS) + EDMA_Type *dmaBases[] = EDMA_BASE_PTRS; + IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; +#elif (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) + DMA_Type *dmaBases[] = DMA_BASE_PTRS; + IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; +#else + DMA_Type *dmaBases[] = DMA_BASE_PTRS; + IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; +#endif + +#if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U)) + EDMA_GetDefaultConfig(&config); +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + edma_channel_config_t channelConfig = { + .enableMasterIDReplication = true, +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + .securityLevel = kEDMA_ChannelSecurityLevelSecure, +#endif + .protectionLevel = kEDMA_ChannelProtectionLevelPrivileged, + }; + + config.enableMasterIdReplication = true; + config.channelConfig[dmaConfig->tx_channel] = &channelConfig; + config.channelConfig[dmaConfig->rx_channel] = &channelConfig; +#endif + EDMA_Init(dmaBases[dmaConfig->dma_instance], &config); +#endif /* HAL_UART_DMA_INIT_ENABLE > 0 */ + EDMA_CreateHandle(&uartDmaHandle->txEdmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel); + EDMA_CreateHandle(&uartDmaHandle->rxEdmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel); +#if (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) + dma_channel_mux_configure_t *dmaChannelMux = dmaConfig->dma_channel_mux_configure; + EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel, + dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux); + EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel, + dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux); +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + (void)memcpy(&uartDmaHandle->dma_channel_mux_configure, dmaConfig->dma_channel_mux_configure, + sizeof(dma_channel_mux_configure_t)); +#endif /* HAL_UART_ADAPTER_LOWPOWER */ +#endif /* FSL_FEATURE_EDMA_HAS_CHANNEL_MUX */ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + (void)memcpy(&uartDmaHandle->hal_uart_dma_config, dmaConfig, sizeof(hal_uart_dma_config_t)); + uartDmaHandle->hal_uart_dma_config.dma_mux_configure = &uartDmaHandle->dma_mux_configure; + uartDmaHandle->hal_uart_dma_config.dma_channel_mux_configure = &uartDmaHandle->dma_channel_mux_configure; +#endif /* HAL_UART_ADAPTER_LOWPOWER */ +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + NVIC_SetPriority(s_edmaIRQNumbers[dmaConfig->dma_instance][dmaConfig->tx_channel], HAL_UART_ISR_PRIORITY); + NVIC_SetPriority(s_edmaIRQNumbers[dmaConfig->dma_instance][dmaConfig->rx_channel], HAL_UART_ISR_PRIORITY); +#endif +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + s_UartDmaState[uartDmaHandle->instance] = uartDmaHandle; + + /* Enable RX interrupt for detecting the IDLE line interrupt. */ + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) + (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); +#endif +#else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#if defined(LPUART_RX_TX_IRQS) + (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + + if (0 == s_dmaHandleList.activeCount) + { + s_dmaHandleList.dma_list = uartDmaHandle; + uartDmaHandle->next = NULL; + s_dmaHandleList.activeCount++; + +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) + timer_status_t timerStatus; + timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle); + assert(kStatus_TimerSuccess == timerStatus); + + timerStatus = TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, + &s_dmaHandleList); + assert(kStatus_TimerSuccess == timerStatus); + + (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1); + + (void)timerStatus; +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + } + else + { + uartDmaHandle->next = s_dmaHandleList.dma_list; + s_dmaHandleList.dma_list = uartDmaHandle; + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + hal_uart_dma_state_t *prev; + hal_uart_dma_state_t *curr; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + uartHandle->dmaHandle = NULL; + + assert(uartDmaHandle); + + /* Abort rx/tx */ + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + /* Here we should not abort before create transfer handle. */ + if (NULL != uartDmaHandle->edmaHandle.rxEdmaHandle) + { + LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); + } + if (NULL != uartDmaHandle->edmaHandle.txEdmaHandle) + { + LPUART_TransferAbortSendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); + } +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + + /* Disable rx/tx channels */ + + /* Remove handle from list */ + prev = NULL; + curr = s_dmaHandleList.dma_list; + while (curr != NULL) + { + if (curr == uartDmaHandle) + { + /* 1, if it is the first one */ + if (prev == NULL) + { + s_dmaHandleList.dma_list = curr->next; + } + /* 2, if it is the last one */ + else if (curr->next == NULL) + { + prev->next = NULL; + } + /* 3, if it is in the middle */ + else + { + prev->next = curr->next; + } + break; + } + + prev = curr; + curr = curr->next; + } + + /* Reset all handle data. */ + (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t)); + + s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0; +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) + if (0 == s_dmaHandleList.activeCount) + { + (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle); + } +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle, + hal_uart_dma_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + uartDmaHandle->dma_callback = callback; + uartDmaHandle->dma_callback_param = callbackParam; + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + LPUART_TransferCreateHandleEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, + LPUART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txEdmaHandle, + &uartDmaHandle->rxEdmaHandle); + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) + LP_FLEXCOMM_SetIRQHandler(uartHandle->instance, HAL_LpUartInterruptHandle_Wrapper, handle, + LP_FLEXCOMM_PERIPH_LPUART); +#endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */ +#endif /* UART_ADAPTER_NON_BLOCKING_MODE */ + +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + LPUART_StartRingBufferEDMA(handle); +#endif /* HAL_UART_DMA_RING_BUFFER_ENABLE */ +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle, + uint8_t *data, + size_t length, + bool receiveAll) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + assert(data); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (NULL == uartDmaHandle->dma_rx.buffer) + { + uartDmaHandle->dma_rx.buffer = data; + uartDmaHandle->dma_rx.bufferLength = length; + uartDmaHandle->dma_rx.bufferSofar = 0U; + uartDmaHandle->dma_rx.timeout = 0U; + uartDmaHandle->dma_rx.receiveAll = receiveAll; + } + else + { + /* Already in reading process. */ + return kStatus_HAL_UartDmaRxBusy; + } +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + HAL_UartDMARxIdlelineInterruptHandle(uartHandle->instance); +#endif +#else /* HAL_UART_DMA_RING_BUFFER_ENABLE */ +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + lpuart_transfer_t xfer; + xfer.data = data; + xfer.dataSize = length; +#endif +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + +#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + (void)LPUART_ReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, &xfer); +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + +#endif +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else + /* Enable RX interrupt for detecting the IDLE line interrupt. */ + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + lpuart_transfer_t xfer; +#endif + assert(handle); + assert(data); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (NULL == uartDmaHandle->dma_tx.buffer) + { + uartDmaHandle->dma_tx.buffer = data; + uartDmaHandle->dma_tx.bufferLength = length; + uartDmaHandle->dma_tx.bufferSofar = 0U; + } + else + { + /* Already in writing process. */ + return kStatus_HAL_UartDmaTxBusy; + } + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + xfer.data = data; + xfer.dataSize = length; + (void)LPUART_SendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, &xfer); +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + +#if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) +#else + /* Enable RX interrupt for detecting the IDLE line interrupt. */ + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); +#endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + (void)uartDmaHandle; +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + *reCount = HAL_UartGetDmaReceivedBytes(uartDmaHandle->instance); +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ +#else /* HAL_UART_DMA_RING_BUFFER_ENABLE */ +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + if (kStatus_Success != LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->edmaHandle, reCount)) + { + return kStatus_HAL_UartDmaError; + } +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_DMA_COUNT */ + +#endif +#else + *reCount = 0; + +#endif + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + if (kStatus_Success != LPUART_TransferGetSendCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->edmaHandle, seCount)) + { + return kStatus_HAL_UartDmaError; + } +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) + +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + +#if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U)) + /* Make sure to re-initialize the ring bufferIndex */ + ringBufferIndex[uartDmaHandle->instance] = 0U; +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) + LPUART_TransferAbortSendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); +#elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + + return kStatus_HAL_UartDmaSuccess; +} +#endif /* HAL_UART_DMA_ENABLE */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h new file mode 100644 index 0000000000..278a90d148 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h @@ -0,0 +1,828 @@ +/* + * Copyright 2018-2020 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_UART_ADAPTER_H__ +#define __HAL_UART_ADAPTER_H__ + +#include "fsl_common.h" +#if defined(SDK_OS_FREE_RTOS) +#include "FreeRTOS.h" +#endif + +/*! + * @addtogroup UART_Adapter + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define UART_ADAPTER_NON_BLOCKING_MODE (1U) +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define UART_ADAPTER_NON_BLOCKING_MODE (0U) +#else +#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE +#endif +#endif + +#if defined(__GIC_PRIO_BITS) +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (25U) +#endif +#else +#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#endif +#else +/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. + * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum + * priority is 3 (2^2 - 1). So, the default value is 3. + */ +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (3U) +#endif +#endif +#endif + +#ifndef HAL_UART_ADAPTER_LOWPOWER +#define HAL_UART_ADAPTER_LOWPOWER (0U) +#endif /* HAL_UART_ADAPTER_LOWPOWER */ + +/*! @brief Enable or disable uart hardware FIFO mode (1 - enable, 0 - disable) */ +#ifndef HAL_UART_ADAPTER_FIFO +#define HAL_UART_ADAPTER_FIFO (1U) +#endif /* HAL_UART_ADAPTER_FIFO */ + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#ifndef HAL_UART_DMA_ENABLE +#define HAL_UART_DMA_ENABLE (1U) +#endif +#endif + +#ifndef HAL_UART_DMA_ENABLE +#define HAL_UART_DMA_ENABLE (0U) +#endif /* HAL_UART_DMA_ENABLE */ + +/*! @brief Enable or disable uart DMA adapter int mode (1 - enable, 0 - disable) */ +#ifndef HAL_UART_DMA_INIT_ENABLE +#define HAL_UART_DMA_INIT_ENABLE (1U) +#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */ + +/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */ +#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT +#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U) +#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */ + +/*! @brief Definition of uart adapter handle size. */ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U) +#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U) +#else +#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U) +#endif + +/*! @brief Definition of uart dma adapter handle size. */ +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#define HAL_UART_DMA_HANDLE_SIZE (124U + HAL_UART_ADAPTER_LOWPOWER * 36U) +#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +#define HAL_UART_DMA_HANDLE_SIZE (144U + HAL_UART_ADAPTER_LOWPOWER * 36U) +#else +#error This SOC does not have DMA or EDMA available! +#endif +#endif /* HAL_UART_DMA_ENABLE */ + +/*! + * @brief Defines the uart handle + * + * This macro is used to define a 4 byte aligned uart handle. + * Then use "(hal_uart_handle_t)name" to get the uart handle. + * + * The macro should be global and could be optional. You could also define uart handle by yourself. + * + * This is an example, + * @code + * UART_HANDLE_DEFINE(uartHandle); + * @endcode + * + * @param name The name string of the uart handle. + */ +#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#define UART_DMA_HANDLE_DEFINE(name) \ + uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#endif + +/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */ +#ifndef HAL_UART_TRANSFER_MODE +#define HAL_UART_TRANSFER_MODE (0U) +#endif + +/*! @brief The handle of uart adapter. */ +typedef void *hal_uart_handle_t; + +/*! @brief The handle of uart dma adapter. */ +typedef void *hal_uart_dma_handle_t; + +/*! @brief UART status */ +typedef enum _hal_uart_status +{ + kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */ + kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */ + kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */ + kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */ + kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */ + kStatus_HAL_UartBaudrateNotSupport = + MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */ + kStatus_HAL_UartProtocolError = MAKE_STATUS( + kStatusGroup_HAL_UART, + 6), /*!< Error occurs for Noise, Framing, Parity, etc. + For transactional transfer, The up layer needs to abort the transfer and then starts again */ + kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */ +} hal_uart_status_t; + +/*! @brief UART parity mode. */ +typedef enum _hal_uart_parity_mode +{ + kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */ + kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */ +} hal_uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _hal_uart_stop_bit_count +{ + kHAL_UartOneStopBit = 0U, /*!< One stop bit */ + kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */ +} hal_uart_stop_bit_count_t; + +/*! @brief UART configuration structure. */ +typedef struct _hal_uart_config +{ + uint32_t srcClock_Hz; /*!< Source clock */ + uint32_t baudRate_Bps; /*!< Baud rate */ + hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the + SOC corresponding RM. + Invalid instance value will cause initialization failure. */ +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif +} hal_uart_config_t; + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +/*! @brief UART DMA status */ +typedef enum _hal_uart_dma_status +{ + kStatus_HAL_UartDmaSuccess = 0U, + kStatus_HAL_UartDmaRxIdle = (1U << 1U), + kStatus_HAL_UartDmaRxBusy = (1U << 2U), + kStatus_HAL_UartDmaTxIdle = (1U << 3U), + kStatus_HAL_UartDmaTxBusy = (1U << 4U), + kStatus_HAL_UartDmaIdleline = (1U << 5U), + kStatus_HAL_UartDmaError = (1U << 6U), +} hal_uart_dma_status_t; + +typedef struct _dma_mux_configure_t +{ + union + { + struct + { + uint8_t dma_mux_instance; + uint32_t rx_request; + uint32_t tx_request; + } dma_dmamux_configure; + }; +} dma_mux_configure_t; +typedef struct _dma_channel_mux_configure_t +{ + union + { + struct + { + uint32_t dma_rx_channel_mux; + uint32_t dma_tx_channel_mux; + } dma_dmamux_configure; + }; +} dma_channel_mux_configure_t; + +typedef struct _hal_uart_dma_config_t +{ + uint8_t uart_instance; + uint8_t dma_instance; + uint8_t rx_channel; + uint8_t tx_channel; + void *dma_mux_configure; + void *dma_channel_mux_configure; +} hal_uart_dma_config_t; +#endif /* HAL_UART_DMA_ENABLE */ + +/*! @brief UART transfer callback function. */ +typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam); + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +typedef struct _dma_callback_msg +{ + hal_uart_dma_status_t status; + uint8_t *data; + uint32_t dataSize; +} hal_dma_callback_msg_t; + +/*! @brief UART transfer callback function. */ +typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle, + hal_dma_callback_msg_t *msg, + void *callbackParam); +#endif /* HAL_UART_DMA_ENABLE */ + +/*! @brief UART transfer structure. */ +typedef struct _hal_uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} hal_uart_transfer_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with the UART handle and the user configuration structure. + * + * This function configures the UART module with user-defined settings. The user can configure the configuration + * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by + * the caller. Example below shows how to use this API to configure the UART. + * @code + * UART_HANDLE_DEFINE(g_UartHandle); + * hal_uart_config_t config; + * config.srcClock_Hz = 48000000; + * config.baudRate_Bps = 115200U; + * config.parityMode = kHAL_UartParityDisabled; + * config.stopBitCount = kHAL_UartOneStopBit; + * config.enableRx = 1; + * config.enableTx = 1; + * config.enableRxRTS = 0; + * config.enableTxCTS = 0; + * config.instance = 0; + * HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config); + * @endcode + * + * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #UART_HANDLE_DEFINE(handle); + * or + * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param uart_config Pointer to user-defined configuration structure. + * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_HAL_UartSuccess UART initialization succeed + */ +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess UART de-initialization succeed + */ +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle); + +/*! @}*/ + +/*! + * @name Blocking bus Operations + * @{ + */ + +/*! + * @brief Reads RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the RX register. + * + * @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_HAL_UartError An error occurred while receiving data. + * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data. + * @retval kStatus_HAL_UartSuccess Successfully received all data. + */ +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully sent all data. + */ +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length); + +/*! @}*/ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +/*! + * @name Transactional + * @note The transactional API and the functional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When any status of the UART changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART driver. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure, see #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure. See #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#else + +/*! + * @name Functional API with non-blocking mode. + * @note The functional API and the transactional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART adapter. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART adapter notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param reCount Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param seCount Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#endif +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + +/*! + * @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure. + * + * This function configures the UART dma module with user-defined settings. The user can configure the configuration + * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated + * by the caller. Example below shows how to use this API to configure the UART. + * @code + * + * Init TimerManager, only used in UART without Idleline interrupt + * timer_config_t timerConfig; + * timerConfig.srcClock_Hz = 16000000; + * timerConfig.instance = 0; + * TM_Init(&timerConfig); + * + * Init the DMA module + * DMA_Init(DMA0); + * + * Define a uart dma handle + * UART_HANDLE_DEFINE(g_uartHandle); + * UART_DMA_HANDLE_DEFINE(g_UartDmaHandle); + * + * Configure uart settings + * hal_uart_config_t uartConfig; + * uartConfig.srcClock_Hz = 48000000; + * uartConfig.baudRate_Bps = 115200; + * uartConfig.parityMode = kHAL_UartParityDisabled; + * uartConfig.stopBitCount = kHAL_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * uartConfig.enableRxRTS = 0; + * uartConfig.enableTxCTS = 0; + * uartConfig.instance = 0; + * + * Init uart + * HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig); + * + * Configure uart dma settings + * hal_uart_dma_config_t dmaConfig; + * dmaConfig.uart_instance = 0; + * dmaConfig.dma_instance = 0; + * dmaConfig.rx_channel = 0; + * dmaConfig.tx_channel = 1; + * + * Init uart dma + * HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig); + * @endcode + * + * @param handle UART handle pointer. + * @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #UART_DMA_HANDLE_DEFINE(handle); + * or + * uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param dmaConfig Pointer to user-defined configuration structure. + * @retval kStatus_HAL_UartDmaError UART dma initialization failed. + * @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed. + */ +hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, + hal_uart_dma_handle_t dmaHandle, + hal_uart_dma_config_t *dmaConfig); + +/*! + * @brief Deinitializes a UART DMA instance. + * + * This function will abort uart dma receive/send transfer and deinitialize UART. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed + */ +hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle); + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART DMA module. + * When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartDmaSuccess Successfully install the callback. + */ +hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle, + hal_uart_dma_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an dma method. + * + * This function receives data using an dma method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART DMA driver. + * When all data is received, the UART DMA adapter notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle. + * + * When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function, + * and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline + * interrupt(like usart), it will use a software idleline detection method with the help of TimerManager. + * + * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API. + * + * @param handle UART handle pointer. + * @param data data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @param receiveAll Idleline interrupt will not end transfer process if set true. + * @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive. + * @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished. + */ +hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle, + uint8_t *data, + size_t length, + bool receiveAll); + +/*! + * @brief Transmits a buffer of data using an dma method. + * + * This function sends data using an dma method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register by DMA, the UART DMA driver calls the callback + * function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter. + * + * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API. + * + * @param handle UART handle pointer. + * @param data data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished. + */ +hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param reCount Receive bytes count. + * @retval kStatus_HAL_UartDmaError An error occurred. + * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount. + */ +hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the DMA method. + * + * @param handle UART handle pointer. + * @param seCount Send bytes count. + * @retval kStatus_HAL_UartDmaError An error occurred. + * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount. + */ +hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); + +/*! + * @brief Aborts the DMA-driven data receiving. + * + * This function aborts the DMA-driven data receiving. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving. + */ +hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the DMA-driven data sending. + * + * This function aborts the DMA-driven data sending. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle); +#endif /* HAL_UART_DMA_ENABLE */ + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess Successful operation. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess Successful operation. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle); + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param handle UART handle pointer. + */ +void HAL_UartIsrFunction(hal_uart_handle_t handle); +#endif + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* __HAL_UART_ADAPTER_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c new file mode 100644 index 0000000000..fa595e8511 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c @@ -0,0 +1,1101 @@ +/* + * Copyright 2018 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_usart.h" +#include "fsl_flexcomm.h" + +#include "fsl_adapter_uart.h" + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#include "fsl_component_timer_manager.h" +#include "fsl_usart_dma.h" +#endif /* HAL_UART_DMA_ENABLE */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_dma_receive_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; + volatile uint32_t timeout; + volatile bool receiveAll; +} hal_uart_dma_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_dma_send_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; + volatile uint32_t timeout; +} hal_uart_dma_send_state_t; + +typedef struct _hal_uart_dma_state +{ + struct _hal_uart_dma_state *next; + uint8_t instance; /* USART instance */ + hal_uart_dma_transfer_callback_t dma_callback; + void *dma_callback_param; + usart_dma_handle_t dmaHandle; + dma_handle_t txDmaHandle; + dma_handle_t rxDmaHandle; + hal_uart_dma_receive_state_t dma_rx; + hal_uart_dma_send_state_t dma_tx; +} hal_uart_dma_state_t; + +typedef struct _uart_dma_list +{ + TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle); + hal_uart_dma_state_t *dma_list; + volatile int8_t activeCount; +} hal_uart_dma_list_t; + +static hal_uart_dma_list_t s_dmaHandleList; +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_receive_state +{ + volatile uint8_t *buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_send_state +{ + volatile uint8_t *buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_send_state_t; +#endif +/*! @brief uart state structure. */ +typedef struct _hal_uart_state +{ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + hal_uart_transfer_callback_t callback; + void *callbackParam; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + usart_handle_t hardwareHandle; +#endif + hal_uart_receive_state_t rx; + hal_uart_send_state_t tx; +#endif + uint8_t instance; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + hal_uart_dma_state_t *dmaHandle; +#endif /* HAL_UART_DMA_ENABLE */ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + hal_uart_config_t config; +#endif +} hal_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +/* Array of USART IRQ number. */ +static const IRQn_Type s_UsartIRQ[] = USART_IRQS; +#endif + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \ + (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))) +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus = kStatus_HAL_UartError; + switch (status) + { + case kStatus_Success: + uartStatus = kStatus_HAL_UartSuccess; + break; + case kStatus_USART_TxBusy: + uartStatus = kStatus_HAL_UartTxBusy; + break; + case kStatus_USART_RxBusy: + uartStatus = kStatus_HAL_UartRxBusy; + break; + case kStatus_USART_TxIdle: + uartStatus = kStatus_HAL_UartTxIdle; + break; + case kStatus_USART_RxIdle: + uartStatus = kStatus_HAL_UartRxIdle; + break; + case kStatus_USART_BaudrateNotSupport: + uartStatus = kStatus_HAL_UartBaudrateNotSupport; + break; + case kStatus_USART_NoiseError: + case kStatus_USART_FramingError: + case kStatus_USART_ParityError: + uartStatus = kStatus_HAL_UartProtocolError; + break; + default: + /* This comments for MISRA C-2012 Rule 16.4 */ + break; + } + return uartStatus; +} +#else +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + if (kStatus_Success == status) + { + return kStatus_HAL_UartSuccess; + } + else + { + return kStatus_HAL_UartError; + } +} +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + assert(callbackParam); + + uartHandle = (hal_uart_state_t *)callbackParam; + + if (kStatus_HAL_UartProtocolError == uartStatus) + { + if (0U != uartHandle->hardwareHandle.rxDataSize) + { + uartStatus = kStatus_HAL_UartError; + } + } + + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); + } +} + +#else +static void HAL_UartInterruptHandle(USART_Type *base, void *handle) +{ + hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle; + uint32_t status; + uint8_t instance; + + if (NULL == uartHandle) + { + return; + } + instance = uartHandle->instance; + + status = USART_GetStatusFlags(s_UsartAdapterBase[instance]); + + /* Receive data register full */ + if ((0U != (USART_FIFOSTAT_RXNOTEMPTY_MASK & status)) && + (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))) + { + if (NULL != uartHandle->rx.buffer) + { + uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]); + if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) + { + USART_DisableInterrupts(s_UsartAdapterBase[instance], + USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); + uartHandle->rx.buffer = NULL; + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); + } + } + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != (USART_FIFOSTAT_TXNOTFULL_MASK & status)) && + (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))) + { + if (NULL != uartHandle->tx.buffer) + { + USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); + if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) + { + USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK); + uartHandle->tx.buffer = NULL; + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); + } + } + } + } + +#if 1 + USART_ClearStatusFlags(s_UsartAdapterBase[instance], status); +#endif +} + +static void HAL_UartInterruptHandle_Wrapper(void *base, void *handle) +{ + HAL_UartInterruptHandle((USART_Type *)base, handle); +} +#endif + +#endif + +static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *config) +{ + usart_config_t usartConfig; + status_t status; + + assert(handle); + assert(config); + assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *))); + assert(s_UsartAdapterBase[config->instance]); + assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t)); + + USART_GetDefaultConfig(&usartConfig); + usartConfig.baudRate_Bps = config->baudRate_Bps; + + if ((0U != config->enableRxRTS) || (0U != config->enableTxCTS)) + { + usartConfig.enableHardwareFlowControl = true; + } + + if (kHAL_UartParityEven == config->parityMode) + { + usartConfig.parityMode = kUSART_ParityEven; + } + else if (kHAL_UartParityOdd == config->parityMode) + { + usartConfig.parityMode = kUSART_ParityOdd; + } + else + { + usartConfig.parityMode = kUSART_ParityDisabled; + } + + if (kHAL_UartTwoStopBit == config->stopBitCount) + { + usartConfig.stopBitCount = kUSART_TwoStopBit; + } + else + { + usartConfig.stopBitCount = kUSART_OneStopBit; + } + usartConfig.enableRx = (bool)config->enableRx; + usartConfig.enableTx = (bool)config->enableTx; + usartConfig.txWatermark = kUSART_TxFifo0; + usartConfig.rxWatermark = kUSART_RxFifo1; + + status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz); + + if (kStatus_Success != status) + { + return HAL_UartGetStatus(status); + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t status; + + /* Init serial port */ + status = HAL_UartInitCommon(handle, uart_config); + if (kStatus_HAL_UartSuccess != status) + { + return status; + } + + uartHandle = (hal_uart_state_t *)handle; + uartHandle->instance = uart_config->instance; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + uartHandle->dmaHandle = NULL; +#endif /* HAL_UART_DMA_ENABLE */ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + (void)memcpy(&uartHandle->config, uart_config, sizeof(hal_uart_config_t)); +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + USART_TransferCreateHandle(s_UsartAdapterBase[uart_config->instance], &uartHandle->hardwareHandle, + (usart_transfer_callback_t)HAL_UartCallback, handle); +#else + /* Enable interrupt in NVIC. */ + FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[uart_config->instance], HAL_UartInterruptHandle_Wrapper, handle); + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uart_config->instance], HAL_UART_ISR_PRIORITY); + (void)EnableIRQ(s_UsartIRQ[uart_config->instance]); +#endif + +#endif + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + + USART_Deinit(s_UsartAdapterBase[uartHandle->instance]); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + if (NULL != uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } +#endif + + status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + if (NULL != uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } +#endif + + (void)USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle) +{ + assert(handle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle) +{ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + hal_uart_state_t *uartHandle; + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + + (void)HAL_UartInit(handle, &uartHandle->config); +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK); +#endif +#endif + return kStatus_HAL_UartSuccess; +} + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (usart_transfer_t *)transfer, NULL); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (usart_transfer_t *)transfer); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = + USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +#else + +/* None transactional API with non-blocking mode. */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } + + uartHandle->rx.bufferLength = length; + uartHandle->rx.bufferSofar = 0; + uartHandle->rx.buffer = data; + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } + uartHandle->tx.bufferLength = length; + uartHandle->tx.bufferSofar = 0; + uartHandle->tx.buffer = (volatile uint8_t *)data; + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(reCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + *reCount = uartHandle->rx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(seCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + *seCount = uartHandle->tx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], + USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); + uartHandle->rx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK); + uartHandle->tx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +#endif + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 + DisableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif + USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); +#if 0 + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif +} + +#else + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 + DisableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif + HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle); +#if 0 + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif +} + +#endif + +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +static void USART_DMACallbacks(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) +{ + hal_uart_dma_state_t *uartDmaHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + hal_dma_callback_msg_t msg; + assert(handle); + + uartDmaHandle = (hal_uart_dma_state_t *)userData; + + if (NULL != uartDmaHandle->dma_callback) + { + if (kStatus_HAL_UartTxIdle == uartStatus) + { + msg.status = kStatus_HAL_UartDmaTxIdle; + msg.data = uartDmaHandle->dma_tx.buffer; + msg.dataSize = uartDmaHandle->dma_tx.bufferLength; + uartDmaHandle->dma_tx.buffer = NULL; + } + else if (kStatus_HAL_UartRxIdle == uartStatus) + { + msg.status = kStatus_HAL_UartDmaRxIdle; + msg.data = uartDmaHandle->dma_rx.buffer; + msg.dataSize = uartDmaHandle->dma_rx.bufferLength; + uartDmaHandle->dma_rx.buffer = NULL; + } + + uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); + } +} + +static void TimeoutTimer_Callbcak(void *param) +{ + hal_uart_dma_list_t *uartDmaHandleList; + hal_uart_dma_state_t *uartDmaHandle; + hal_dma_callback_msg_t msg; + uint32_t newReceived = 0U; + + uartDmaHandleList = &s_dmaHandleList; + uartDmaHandle = uartDmaHandleList->dma_list; + + while (NULL != uartDmaHandle) + { + if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll)) + { + /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */ + USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, + &msg.dataSize); + newReceived = msg.dataSize - uartDmaHandle->dma_rx.bufferSofar; + uartDmaHandle->dma_rx.bufferSofar = msg.dataSize; + + /* 1, If it is in idle state. */ + if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) + { + uartDmaHandle->dma_rx.timeout++; + if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT) + { + /* HAL_UartDMAAbortReceive(uartDmaHandle); */ + USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->dmaHandle); + msg.data = uartDmaHandle->dma_rx.buffer; + msg.status = kStatus_HAL_UartDmaIdleline; + uartDmaHandle->dma_rx.buffer = NULL; + uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); + } + } + /* 2, If got new data again. */ + if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) + { + uartDmaHandle->dma_rx.timeout = 0U; + } + } + + uartDmaHandle = uartDmaHandle->next; + } +} + +hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, + hal_uart_dma_handle_t dmaHandle, + hal_uart_dma_config_t *dmaConfig) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + assert(dmaHandle); + assert(HAL_UART_DMA_HANDLE_SIZE >= sizeof(hal_uart_dma_state_t)); + + /* DMA init process. */ + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle; + + uartHandle->dmaHandle = uartDmaHandle; + + uartDmaHandle->instance = dmaConfig->uart_instance; + + DMA_Type *dmaBases[] = DMA_BASE_PTRS; + DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel); + DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel); + + DMA_CreateHandle(&uartDmaHandle->txDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel); + DMA_CreateHandle(&uartDmaHandle->rxDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel); + + /* Timeout timer init. */ + if (0U == s_dmaHandleList.activeCount) + { + s_dmaHandleList.dma_list = uartDmaHandle; + uartDmaHandle->next = NULL; + s_dmaHandleList.activeCount++; + + timer_status_t timerStatus; + timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle); + assert(kStatus_TimerSuccess == timerStatus); + + timerStatus = + TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, NULL); + assert(kStatus_TimerSuccess == timerStatus); + + (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1); + + (void)timerStatus; + } + else + { + uartDmaHandle->next = s_dmaHandleList.dma_list; + s_dmaHandleList.dma_list = uartDmaHandle; + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + hal_uart_dma_state_t *prev; + hal_uart_dma_state_t *curr; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + uartHandle->dmaHandle = NULL; + + assert(uartDmaHandle); + + /* Abort rx/tx */ + /* Here we should not abort before create transfer handle. */ + if (NULL != uartDmaHandle->dmaHandle.txDmaHandle) + { + USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + } + if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle) + { + USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + } + + /* Disable rx/tx channels */ + /* Here we should not disable before create transfer handle. */ + if (NULL != uartDmaHandle->dmaHandle.txDmaHandle) + { + DMA_DisableChannel(uartDmaHandle->txDmaHandle.base, uartDmaHandle->txDmaHandle.channel); + } + if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle) + { + DMA_DisableChannel(uartDmaHandle->rxDmaHandle.base, uartDmaHandle->rxDmaHandle.channel); + } + + /* Remove handle from list */ + prev = NULL; + curr = s_dmaHandleList.dma_list; + while (curr != NULL) + { + if (curr == uartDmaHandle) + { + /* 1, if it is the first one */ + if (prev == NULL) + { + s_dmaHandleList.dma_list = curr->next; + } + /* 2, if it is the last one */ + else if (curr->next == NULL) + { + prev->next = NULL; + } + /* 3, if it is in the middle */ + else + { + prev->next = curr->next; + } + break; + } + + prev = curr; + curr = curr->next; + } + + /* Reset all handle data. */ + (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t)); + + s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0; + if (0 == s_dmaHandleList.activeCount) + { + (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle); + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle, + hal_uart_dma_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + uartDmaHandle->dma_callback = callback; + uartDmaHandle->dma_callback_param = callbackParam; + + USART_TransferCreateHandleDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, + USART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txDmaHandle, + &uartDmaHandle->rxDmaHandle); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle, + uint8_t *data, + size_t length, + bool receiveAll) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + usart_transfer_t xfer; + + assert(handle); + assert(data); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (NULL == uartDmaHandle->dma_rx.buffer) + { + uartDmaHandle->dma_rx.buffer = data; + uartDmaHandle->dma_rx.bufferLength = length; + uartDmaHandle->dma_rx.timeout = 0U; + uartDmaHandle->dma_rx.receiveAll = receiveAll; + } + else + { + /* Already in reading process. */ + return kStatus_HAL_UartDmaRxBusy; + } + + xfer.data = data; + xfer.dataSize = length; + + USART_TransferReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + usart_transfer_t xfer; + + assert(handle); + assert(data); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (NULL == uartDmaHandle->dma_tx.buffer) + { + uartDmaHandle->dma_tx.buffer = data; + uartDmaHandle->dma_tx.bufferLength = length; + uartDmaHandle->dma_tx.bufferSofar = 0U; + uartDmaHandle->dma_tx.timeout = 0U; + } + else + { + /* Already in writing process. */ + return kStatus_HAL_UartDmaTxBusy; + } + + xfer.data = data; + xfer.dataSize = length; + + USART_TransferSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (kStatus_Success != USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->dmaHandle, reCount)) + { + return kStatus_HAL_UartDmaError; + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + /* No get send count API */ + return kStatus_HAL_UartDmaError; +} + +hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + + return kStatus_HAL_UartDmaSuccess; +} +#endif /* HAL_UART_DMA_ENABLE */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.c b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.c new file mode 100644 index 0000000000..d0dcc4b69f --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + if ((alignbytes == 0U) || (alignbytes >= SIZE_MAX)) + { + return NULL; + } + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.h b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.h new file mode 100644 index 0000000000..33ed0c8eb0 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common.h @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022,2024-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) + +/*! @name Driver version */ +/*! @{ */ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) +/*! @} */ + +/*! @name Debug console type definition. */ +/*! @{ */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ +/*! @} */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */ + kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */ + kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */ + kStatusGroup_AUDMIX = 111, /*!< Group number for AUDMIX status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ + kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */ + kStatusGroup_AON_POWER = 169, /*!< Group number for AON_POWER status codes. */ + kStatusGroup_AON_COMMON = 170, /*!< Group number for AON_COMMON status codes. */ + kStatusGroup_ENDAT3 = 171, /*!< Group number for ENDAT3 status codes. */ + kStatusGroup_HIPERFACE = 172, /*!< Group number for HIPERFACE status codes. */ + kStatusGroup_NPX = 173, /*!< Group number for NPX status codes. */ + kStatusGroup_ELA_CSEC = 174, /*!< Group number for ELA_CSEC status codes. */ + kStatusGroup_FLEXIO_T_FORMAT= 175, /*!< Group number for T-format status codes. */ + kStatusGroup_FLEXIO_A_FORMAT= 176, /*!< Group number for A-format status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +#ifdef __ZEPHYR__ +#include +#else +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +/*! Computes the minimum of \a a and \a b. */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +/*! Computes the maximum of \a a and \a b. */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/*! @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif +#endif /* __ZEPHYR__ */ + +/*! @name UINT16_MAX/UINT32_MAX value */ +/*! @{ */ +#if !defined(UINT16_MAX) +/*! Max value of uint16_t type. */ +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +/*! Max value of uint32_t type. */ +#define UINT32_MAX ((uint32_t)-1) +#endif +/*! @} */ + +/*! Macro to get upper 32 bits of a 64-bit value */ +#if !defined(UINT64_H) +#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL)) +#endif + +/*! Macro to get lower 32 bits of a 64-bit value */ +#if !defined(UINT64_L) +#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL)) +#endif + +/*! + * @def SUPPRESS_FALL_THROUGH_WARNING() + * + * For switch case code block, if case section ends without "break;" statement, there wil be + * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + * case section which misses "break;"statement. + */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XTENSA__) +#include "fsl_common_dsp.h" +#elif defined(__riscv) +#include "fsl_common_riscv.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* FSL_COMMON_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common_arm.c b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.c similarity index 57% rename from platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common_arm.c rename to platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.c index 27c7005246..1008bdd5a5 100644 --- a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common_arm.c +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021,2023,2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,6 +21,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #undef __VECTOR_TABLE #endif + if (((int32_t)irq + 16) < 0) + { + return MSDK_INVALID_IRQ_HANDLER; + } + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; @@ -116,7 +121,7 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt) #endif /* FSL_FEATURE_POWERLIB_EXTEND */ #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#if defined(DWT) +#if MSDK_HAS_DWT_CYCCNT /* Use WDT. */ void MSDK_EnableCpuCycleCounter(void) { @@ -142,7 +147,7 @@ uint32_t MSDK_GetCpuCycleCount(void) } #endif /* defined(DWT) */ -#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT)) +#if !(defined(SDK_DELAY_USE_DWT) && MSDK_HAS_DWT_CYCCNT) /* Use software loop. */ #if defined(__CC_ARM) /* This macro is arm v5 specific */ /* clang-format off */ @@ -159,11 +164,11 @@ static void DelayLoop(uint32_t count) { __ASM volatile(" MOV X0, %0" : : "r"(count)); __ASM volatile( - "loop: \n" + "loop%=: \n" " SUB X0, X0, #1 \n" " CMP X0, #0 \n" - " BNE loop \n" + " BNE loop%= \n" : : : "r0"); @@ -176,7 +181,7 @@ static void DelayLoop(uint32_t count) { __ASM volatile(" MOV R0, %0" : : "r"(count)); __ASM volatile( - "loop: \n" + "loop%=: \n" #if defined(__GNUC__) && !defined(__ARMCC_VERSION) " SUB R0, R0, #1 \n" #else @@ -184,7 +189,7 @@ static void DelayLoop(uint32_t count) #endif " CMP R0, #0 \n" - " BNE loop \n" + " BNE loop%= \n" : : : "r0"); @@ -212,7 +217,7 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) assert(count <= UINT32_MAX); -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ +#if (defined(SDK_DELAY_USE_DWT) && MSDK_HAS_DWT_CYCCNT) /* Use DWT for better accuracy */ MSDK_EnableCpuCycleCounter(); /* Calculate the count ticks. */ @@ -232,13 +237,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) { } #else +#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55)) + /* + * Cortex-A53/A55 execution throughput: + * - SUB/CMP: 2 instructions per cycle + * - BNE: 1 instruction per cycle + * So, each loop takes 2 CPU cycles. + */ + count = count / 2U; +#elif (__CORTEX_M == 7) /* Divide value may be different in various environment to ensure delay is precise. * Every loop count includes three instructions, due to Cortex-M7 sometimes executes * two instructions in one period, through test here set divide 1.5. Other M cores use * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does * not matter because other instructions outside while loop is enough to fill the time. */ -#if (__CORTEX_M == 7) count = count / 3U * 2U; #else count = count / 4U; @@ -247,3 +260,110 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) #endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ } } + +#if defined(FSL_FEATURE_MEASURE_CRITICAL_SECTION) && FSL_FEATURE_MEASURE_CRITICAL_SECTION +/* Use shall define their own IDs, FSL_FEATURE_CRITICAL_SECTION_MAX_ID and FSL_FEATURE_CRITICAL_SECTION_INVALID_ID + for the critical sections if want to use the critical section measurement. + */ +#ifndef FSL_FEATURE_CRITICAL_SECTION_MAX_ID +#define FSL_FEATURE_CRITICAL_SECTION_MAX_ID 0xFFU +#endif + +#ifndef FSL_FEATURE_CRITICAL_SECTION_INVALID_ID +#define FSL_FEATURE_CRITICAL_SECTION_INVALID_ID 0U +#endif + +typedef struct +{ + uint32_t id; /*!< The id of the critical section, defined by user. */ + uint32_t startTime; /*!< The timestamp for the start of the critical section. */ + uint32_t dur_max[FSL_FEATURE_CRITICAL_SECTION_MAX_ID]; /*!< The maximum duration of the section's previous executions. */ + uint32_t execution_times[FSL_FEATURE_CRITICAL_SECTION_MAX_ID]; /*!< How many times the section is executed. */ + getTimestamp_t getTimestamp; /*!< Function to get the current time stamp. */ +} critical_section_measurement_t; + +static critical_section_measurement_t s_critical_section_measurement_context; + +/*! + * brief Initialize the context of the critical section measurement and assign + * the function to get the current timestamp. + * + * param func The function to get the current timestamp. + */ +void InitCriticalSectionMeasurementContext(getTimestamp_t func) +{ + assert(func != NULL); + + (void)memset(&s_critical_section_measurement_context, 0, sizeof(critical_section_measurement_t)); + + s_critical_section_measurement_context.getTimestamp = func; +} + +/*! + * brief Disable the global IRQ with critical section ID + * + * Extended function of DisableGlobalIRQ. Apart from the standard operation, also check + * the id of the protected critical section and mark the begining for timer. + * User is required to provided the primask register for the EnableGlobalIRQEx. + * + * param id The id for critical section. + * return Current primask value. + */ +uint32_t DisableGlobalIRQEx(uint32_t id) +{ + uint32_t primask = DisableGlobalIRQ(); + if (primask != 0U) + { +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Check for the critical section id. */ + assert(id != FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); + assert(id < FSL_FEATURE_CRITICAL_SECTION_MAX_ID); + assert(s_critical_section_measurement_context.id == FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); +#endif + if (s_critical_section_measurement_context.getTimestamp != NULL) + { + s_critical_section_measurement_context.id = id; + s_critical_section_measurement_context.startTime = s_critical_section_measurement_context.getTimestamp(); + } + } + return primask; +} + +/*! + * brief Enable the global IRQ and calculate the execution time of critical section + * + * Extended function of EnableGlobalIRQ. Apart from the standard operation, also + * marks the exit of the critical section and calculate the execution time for the section. + * User is required to use the DisableGlobalIRQEx and EnableGlobalIRQEx in pair. + * + * param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQEx(). + */ +void EnableGlobalIRQEx(uint32_t primask) +{ + if (primask != 0U) + { +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Check for the critical section id. */ + assert(s_critical_section_measurement_context.id != FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); + assert(s_critical_section_measurement_context.id < FSL_FEATURE_CRITICAL_SECTION_MAX_ID); +#endif + if (s_critical_section_measurement_context.getTimestamp != NULL) + { + /* Calculate the critical section duration. */ + uint32_t dur = s_critical_section_measurement_context.getTimestamp() - s_critical_section_measurement_context.startTime; + if (dur > s_critical_section_measurement_context.dur_max[s_critical_section_measurement_context.id]) + { + s_critical_section_measurement_context.dur_max[s_critical_section_measurement_context.id] = dur; + } + s_critical_section_measurement_context.execution_times[s_critical_section_measurement_context.id]++; + } +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Exit the critical section, set the id to invalid. In this case when entering critical + section again DisableGlobalIRQEx has to be called first to avoid assertion. */ + s_critical_section_measurement_context.id = FSL_FEATURE_CRITICAL_SECTION_INVALID_ID; +#endif + } + EnableGlobalIRQ(primask); +} +#endif /* FSL_FEATURE_MEASURE_CRITICAL_SECTION */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.h b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.h new file mode 100644 index 0000000000..72211b6239 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/common/fsl_common_arm.h @@ -0,0 +1,1198 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/*! + * @def SDK_ATOMIC_LOCAL_ADD(addr, val) + * Add value \a val from the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SUB(addr, val) + * Subtract value \a val to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SET(addr, bits) + * Set the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits) + * Clear the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) + * Toggle the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) + * For the variable at address \a address, clear the bits specifiled by \a clearBits + * and set the bits specifiled by \a setBits. + + * @def SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) + * For the variable at address \a address, check whether the value equal to \a expected. If value same as \a expected + * then update \a newValue to address and return \b true , else return \b false . + * + * @def SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) + * For the variable at address \a address, set as \a newValue value and return old value. + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) + +#define SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalCompareAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(expected), (uint8_t)(newValue)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalCompareAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(expected), (uint16_t)(newValue)) : \ + _SDK_AtomicLocalCompareAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(expected), (uint32_t)(newValue)))) + +#define SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalTestAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(newValue)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalTestAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(newValue)) : \ + _SDK_AtomicLocalTestAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(newValue)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) \ + _SDK_AtomicLocalCompareAndSet((uint32_t *)addr, (uint32_t)expected, (uint32_t)newValue) + +#define SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) \ + _SDK_AtomicTestAndSet((uint32_t *)addr, (uint32_t)newValue) + +#endif +/*! @} */ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/*! @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/*! @} */ + +/*! @name Alignment variable definition macros */ +/*! @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @name Non-cacheable region definition macros + * + * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable + * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + * + * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + * + * @{ + */ + +/*! + * @def AT_NONCACHEABLE_SECTION(var) + * Define a variable \a var, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) + * Define a variable \a var, and place it in non-cacheable section, the start address + * of the variable is aligned to \a alignbytes. + * + * @def AT_NONCACHEABLE_SECTION_INIT(var) + * Define a variable \a var with initial value, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) + * Define a variable \a var with initial value, and place it in non-cacheable section, + * the start address of the variable is aligned to \a alignbytes. + */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#if defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +#define MCUX_CS "//" +#else +#define MCUX_CS "@" +#endif + +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/*! @} */ + +/*! + * @name Cache line region definition macros + * + * For initialized non-zero cache line variables, please use "AT_CACHE_LINE_SECTION_INIT(var) ={xx};" + * For zero-inited cache line variables, please use "AT_CACHE_LINE_SECTION(var);" + * + * @note This section is applicable to cached memory only, say external sdram, cached ocram, etc. + * Please avoid to use this section for none-cached memory, say TCM. + * So only those targets, which utilize the cached memory, say flexspi_nor_sdram_debug, support + * this kind of section. + * @{ + */ + +/*! + * @def AT_CACHE_LINE_SECTION(var) + * Define a variable \a var, which is cache line size aligned and be placed in CacheLineData section. + * + * @def AT_CACHE_LINE_SECTION_INIT(var) + * Define a variable \a var with initial value, which is cache line size aligned and be placed in CacheLineData.init section. + */ + +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define CACHE_LINE_DATA SDK_L1DCACHE_ALIGN +#elif defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define CACHE_LINE_DATA SDK_L2CACHE_ALIGN +#endif + +#if (defined(__ICCARM__)) +#define AT_CACHE_LINE_SECTION(var) CACHE_LINE_DATA(var) @"CacheLineData" +#define AT_CACHE_LINE_SECTION_INIT(var) CACHE_LINE_DATA(var) @"CacheLineData.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if (defined(__CC_ARM)) +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData"), zero_init)) CACHE_LINE_DATA(var) +#else +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData"))) CACHE_LINE_DATA(var) +#endif +#define AT_CACHE_LINE_SECTION_INIT(var) __attribute__((section("CacheLineData.init"))) CACHE_LINE_DATA(var) + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData,\"aw\",%nobits @"))) CACHE_LINE_DATA(var) +#define AT_CACHE_LINE_SECTION_INIT(var) __attribute__((section("CacheLineData.init"))) CACHE_LINE_DATA(var) + +#else +#error Toolchain not supported. +#endif + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ + +/*! + * @def AT_QUICKACCESS_SECTION_CODE(func) + * Place function in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA(var) + * Place data in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) + * Place data in a section which can be accessed quickly by core, and the variable + * address is set to align with \a alignbytes. + */ +#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_DISABLE) && (FSL_SDK_DRIVER_QUICK_ACCESS_DISABLE + 0)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(var) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#elif (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* QuickAccess section macro */ +/*! @} */ + +/*! + * @name Ram Function + * @{ + * + * @def RAMFUNCTION_SECTION_CODE(func) + * Place function in ram. + */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @def MSDK_REG_SECURE_ADDR(x) + * Convert the register address to the one used in secure mode. + * + * @def MSDK_REG_NONSECURE_ADDR(x) + * Convert the register address to the one used in non-secure mode. + */ + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +#define MSDK_REG_SECURE_ADDR(x) ((uintptr_t)(x) | (0x1UL << 28)) +#define MSDK_REG_NONSECURE_ADDR(x) ((uintptr_t)(x) & ~(0x1UL << 28)) +#else +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) +#endif + +/*! + * @brief The chip supports DWT CYCCNT or not. + */ +#if (defined(DWT) && defined(DWT_CTRL_CYCCNTENA_Msk)) +#define MSDK_HAS_DWT_CYCCNT 1 +#else +#define MSDK_HAS_DWT_CYCCNT 0 +#endif + +/*! + * @brief Invalid IRQ handler address. + */ +#define MSDK_INVALID_IRQ_HANDLER UINT32_MAX + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) +void IRQSTEER_EnableInterrupt(int32_t instIdx, IRQn_Type irq); +void IRQSTEER_DisableInterrupt(int32_t instIdx, IRQn_Type irq); +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) + int32_t irqsteerInstIdx = (int32_t)((interrupt + 1 - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM); + + IRQSTEER_EnableInterrupt(irqsteerInstIdx, interrupt); +#else + status = kStatus_Fail; +#endif + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) + int32_t irqsteerInstIdx = (int32_t)((interrupt - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM); + + IRQSTEER_DisableInterrupt(irqsteerInstIdx, interrupt); +#else + status = kStatus_Fail; +#endif + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to Enable. + * @param priNum Priority number set to interrupt controller register. + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); + GIC_EnableIRQ(interrupt); +#else + NVIC_SetPriority(interrupt, priNum); + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Set the IRQ priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); +#else + NVIC_SetPriority(interrupt, priNum); +#endif + } + + return status; +} + +/*! + * @brief Clear the pending IRQ flag. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The flag which IRQ to clear. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_ClearPendingIRQ(interrupt); +#else + NVIC_ClearPendingIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t mask; + +#if defined(CPSR_I_Msk) + mask = __get_CPSR() & CPSR_I_Msk; +#elif defined(DAIF_I_BIT) + mask = __get_DAIF() & DAIF_I_BIT; +#else + mask = __get_PRIMASK(); +#endif + __disable_irq(); + + return mask; +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#elif defined(DAIF_I_BIT) + if (0UL == primask) + { + __enable_irq(); + } +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address, if the input @p irq is invalid, then + * return value is @ref MSDK_INVALID_IRQ_HANDLER. + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if MSDK_HAS_DWT_CYCCNT +/*! + * @brief Enable the counter to get CPU cycles. + */ +void MSDK_EnableCpuCycleCounter(void); + +/*! + * @brief Get the current CPU cycle count. + * + * @return Current CPU cycle count. + */ +uint32_t MSDK_GetCpuCycleCount(void); +#endif + +#if defined(FSL_FEATURE_MEASURE_CRITICAL_SECTION) && (FSL_FEATURE_MEASURE_CRITICAL_SECTION != 0) +typedef uint32_t (*getTimestamp_t)(void); /*!< Function to get the current time stamp. */ + +/*! + * @rief Initialize the context of the critical section measurement and assign + * the function to get the current timestamp. + * + * @param getTimestamp The function to get the current timestamp. + */ +void InitCriticalSectionMeasurementContext(getTimestamp_t func); + +/*! + * @brief Disable the global IRQ with critical section ID + * + * Extended function of DisableGlobalIRQ. Apart from the standard operation, also check + * the id of the protected critical section and mark the begining for timer. + * User is required to provided the primask register for the EnableGlobalIRQEx. + * + * @param id The id for critical section. + * @return Current primask value. + */ +uint32_t DisableGlobalIRQEx(uint32_t id); + +/*! + * @brief Enable the global IRQ and calculate the execution time of critical section + * + * Extended function of EnableGlobalIRQ. Apart from the standard operation, also + * marks the exit of the critical section and calculate the execution time for the section. + * User is required to use the DisableGlobalIRQEx and EnableGlobalIRQEx in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQEx(). + */ +void EnableGlobalIRQEx(uint32_t primask); +#endif + + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ +static inline bool _SDK_AtomicLocalCompareAndSet1Byte(volatile uint8_t *addr, uint8_t expected, uint8_t newValue) +{ + uint8_t s_actual; + + do + { + s_actual = __LDREXB(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXB((newValue), (addr))); + + return true; + +} + +static inline bool _SDK_AtomicLocalCompareAndSet2Byte(volatile uint16_t *addr, uint16_t expected, uint16_t newValue) +{ + uint16_t s_actual; + + do + { + s_actual = __LDREXH(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXH((newValue), (addr))); + + return true; +} + +static inline bool _SDK_AtomicLocalCompareAndSet4Byte(volatile uint32_t *addr, uint32_t expected, uint32_t newValue) +{ + uint32_t s_actual; + + do + { + s_actual = __LDREXW(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXW((newValue), (addr))); + + return true; +} + +static inline uint8_t _SDK_AtomicLocalTestAndSet1Byte(volatile uint8_t *addr, uint8_t newValue) +{ + uint8_t s_old; + + do + { + s_old = __LDREXB(addr); + } while (__STREXB((newValue), (addr))); + + return s_old; +} + +static inline uint16_t _SDK_AtomicLocalTestAndSet2Byte(volatile uint16_t *addr, uint16_t newValue) +{ + uint16_t s_old; + + do + { + s_old = __LDREXH(addr); + } while (__STREXH((newValue), (addr))); + + return s_old; +} + +static inline uint32_t _SDK_AtomicLocalTestAndSet4Byte(volatile uint32_t *addr, uint32_t newValue) +{ + uint32_t s_old; + + do + { + s_old = __LDREXW(addr); + } while (__STREXW((newValue), (addr))); + + return s_old; +} + +#else +static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue) +{ + uint32_t s_atomicOldInt; + uint32_t s_actual; + + s_atomicOldInt = DisableGlobalIRQ(); + + s_actual = *addr; + if (s_actual == expected) + { + *addr = newValue; + EnableGlobalIRQ(s_atomicOldInt); + return true; + } + else + { + EnableGlobalIRQ(s_atomicOldInt); + return false; + } +} + +static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue) +{ + uint32_t s_atomicOldInt = DisableGlobalIRQ(); + + uint32_t oldValue = (uint32_t)(*addr); + *addr = newValue; + + EnableGlobalIRQ(s_atomicOldInt); + return oldValue; +} + +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.c b/platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.c new file mode 100644 index 0000000000..7ae86c0f3b --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.c @@ -0,0 +1,678 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024-2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers to real ISRs function pointer installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (MSDK_REG_SECURE_ADDR(s_ctimerBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + /* Make sure clear possible DMA request. */ + base->IR = 0xFFU; + base->IR = 0xFFU; + /* Setup the cimer mode and count select */ + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#else + /* Make sure clear possible DMA request. */ + base->IR = 0xFU; + base->IR = 0xFU; +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + * If PWM pulse width register value is larger than 0xFFFFFFFF. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + assert(dutyCyclePercent <= 100U); + + uint32_t reg; + uint32_t period; + uint64_t pulsePeriod; + uint64_t prescaleValue; + uint64_t timerClock; + uint32_t index = CTIMER_GetInstance(base); + + prescaleValue = (uint64_t)base->PR + 1U; + timerClock = (uint64_t)srcClock_Hz / prescaleValue; + if (timerClock < pwmFreq_Hz) + { + return kStatus_Fail; + } + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the match channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = ((uint32_t)timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = (uint64_t)period + 1U; + } + else + { + pulsePeriod = ((uint64_t)period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; + + /* + * Only occurs when duty cyle is 0 and PWM period is 0xFFFFFFFF. + * CTimer cannot output 0% duty cyle PWM in this case. + */ + if (pulsePeriod > 0xFFFFFFFFU) + { + return kStatus_Fail; + } + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = (uint32_t)pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for PWM pulse channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + * return kStatus_Success on success + * kStatus_Fail If PWM pulse width register value is larger than 0xFFFFFFFF. + */ +status_t CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) +{ + uint32_t period; + uint64_t pulsePeriod; + assert(dutyCyclePercent <= 100U); + + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = (uint64_t)period + 1U; + } + else + { + pulsePeriod = ((uint64_t)period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* + * Only occurs when duty cyle is 0 and PWM period is 0xFFFFFFFF. + * CTimer cannot output 0% duty cyle PWM in this case. + */ + if (pulsePeriod > 0xFFFFFFFFU) + { + return kStatus_Fail; + } + + /* Update dutycycle */ + base->MR[matchChannel] = (uint32_t)pulsePeriod; + + return kStatus_Success; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + if (config->enableCounterReset) + { + reg |= (CTIMER_MCR_MR0R_MASK << ((uint32_t)matchChannel * 3U)); + } + + if (config->enableCounterStop) + { + reg |= (CTIMER_MCR_MR0S_MASK << ((uint32_t)matchChannel * 3U)); + } + + if (config->enableInterrupt) + { + reg |= (CTIMER_MCR_MR0I_MASK << ((uint32_t)matchChannel * 3U)); + } + + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + + if (config->outPinInitState) + { + reg |= (CTIMER_EMR_EM0_MASK << (uint32_t)matchChannel); + } + + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * This function configures CTimer Callback in following modes: + * - Single Callback: + * cb_func should be pointer to callback function pointer + * For example: + * ctimer_callback_t ctimer_callback = pwm_match_callback; + * CTIMER_RegisterCallBack(CTIMER, &ctimer_callback, kCTIMER_SingleCallback); + * + * - Multiple Callback: + * cb_func should be pointer to array of callback function pointers + * Each element corresponds to Interrupt Flag in IR register. + * For example: + * ctimer_callback_t ctimer_callback_table[] = { + * ctimer_match0_callback, NULL, NULL, ctimer_match3_callback, NULL, NULL, NULL, NULL}; + * CTIMER_RegisterCallBack(CTIMER, &ctimer_callback_table[0], kCTIMER_MultipleCallback); + * + * param base Ctimer peripheral base address + * param cb_func Pointer to callback function pointer + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER5) +void CTIMER5_DriverIRQHandler(void); +void CTIMER5_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(5); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER6) +void CTIMER6_DriverIRQHandler(void); +void CTIMER6_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(6); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER7) +void CTIMER7_DriverIRQHandler(void); +void CTIMER7_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(7); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.h b/platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.h new file mode 100644 index 0000000000..d356bb3bc1 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/ctimer/fsl_ctimer.h @@ -0,0 +1,702 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024-2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CTIMER_H_ +#define FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*!< Version 2.3.3 */ +/*! @} */ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1UL << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1UL << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1UL << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1UL << 3) /*!< External match 3 */ +} ctimer_external_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + * If PWM pulse width register value is larger than 0xFFFFFFFF. + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + * @return kStatus_Success on success + * kStatus_Fail If PWM pulse width register value is larger than 0xFFFFFFFF. + */ +status_t CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * This function configures CTimer Callback in following modes: + * - Single Callback: + * cb_func should be pointer to callback function pointer + * For example: + * ctimer_callback_t ctimer_callback = pwm_match_callback; + * CTIMER_RegisterCallBack(CTIMER, &ctimer_callback, kCTIMER_SingleCallback); + * + * - Multiple Callback: + * cb_func should be pointer to array of callback function pointers + * Each element corresponds to Interrupt Flag in IR register. + * For example: + * ctimer_callback_t ctimer_callback_table[] = { + * ctimer_match0_callback, NULL, NULL, ctimer_match3_callback, NULL, NULL, NULL, NULL}; + * CTIMER_RegisterCallBack(CTIMER, &ctimer_callback_table[0], kCTIMER_MultipleCallback); + * + * @param base Ctimer peripheral base address + * @param cb_func Pointer to callback function pointer + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +/*! + * @brief Setup the timer prescale value. + * + * Specifies the maximum value for the Prescale Counter. + * + * @param base Ctimer peripheral base address + * @param prescale Prescale value + */ +static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale) +{ + base->PR = CTIMER_PR_PRVAL(prescale); +} + +/*! + * @brief Get capture channel value. + * + * Get the counter/timer value on the corresponding capture channel. + * + * @param base Ctimer peripheral base address + * @param capture Select capture channel + * + * @return The timer count capture value. + */ +static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture) +{ + return base->CR[capture]; +} + +/*! + * @brief Enable reset match channel. + * + * Set the specified match channel reset operation. + * + * @param base Ctimer peripheral base address + * @param match match channel used + * @param enable Enable match channel reset operation. + */ +static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } +} + +/*! + * @brief Enable stop match channel. + * + * Set the specified match channel stop operation. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable match channel stop operation. + */ +static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Enable reload channel falling edge. + * + * Enable the specified match channel reload match shadow value. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable . + */ +static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +/*! + * @brief Enable capture channel rising edge. + * + * Sets the specified capture channel for rising edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable rising edge capture. + */ +static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +/*! + * @brief Enable capture channel falling edge. + * + * Sets the specified capture channel for falling edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable falling edge capture. + */ +static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Set the specified match shadow channel. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param matchvalue Reload the value of the corresponding match register. + */ +static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue) +{ + base->MSR[match] = matchvalue; +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_CTIMER_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.c b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.c new file mode 100644 index 0000000000..cbb558085e --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.c @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if (MSDK_REG_SECURE_ADDR((uintptr_t)(uint8_t*)base) == MSDK_REG_SECURE_ADDR(s_flexcommBaseAddrs[i])) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); + return i; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + uint32_t idx = FLEXCOMM_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = flexcommHandle; + s_flexcommIrqHandler[instance] = handler; + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void); +void FLEXCOMM0_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM0); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void); +void FLEXCOMM1_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM1); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void); +void FLEXCOMM2_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM2); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void); +void FLEXCOMM3_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM3); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void); +void FLEXCOMM4_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM4); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void); +void FLEXCOMM5_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM5); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void); +void FLEXCOMM6_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM6); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void); +void FLEXCOMM7_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM7); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void); +void FLEXCOMM8_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM8); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void); +void FLEXCOMM9_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM9); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void); +void FLEXCOMM10_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM10); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void); +void FLEXCOMM11_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM11); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void); +void FLEXCOMM12_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM12); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void); +void FLEXCOMM13_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM13); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void); +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void); +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM15); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void); +void FLEXCOMM16_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM16); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.h b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.h new file mode 100644 index 0000000000..3b4669a3d1 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCOMM_H_ +#define FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexCOMM driver version 2.0.2. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @} */ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_FLEXCOMM_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.c b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.c new file mode 100644 index 0000000000..4b40d71dc4 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.c @@ -0,0 +1,2116 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" +#endif + +/*! @brief Common sets of flags used by the driver's transactional layer internally. */ +enum _i2c_flag_constants +{ + kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, + kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, +}; + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and + * `flexcomm_i2c_slave_irq_handler_t`. + */ +typedef union i2c_to_flexcomm +{ + flexcomm_i2c_master_irq_handler_t i2c_master_handler; + flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} i2c_to_flexcomm_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Waits for Master Pending status bit to set and check for bus error status. + * + * @param base The I2C peripheral base address. + * @return Bus status. + */ +static status_t I2C_PendingStatusWait(I2C_Type *base); + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param xfer The I2C transfer configuration structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Resets the slave hardware state machine. + * According to documentation, after disabling slave to rest the slave hardware state machine, the register + * configuration remains unchanged. + * @param base The I2C peripheral base address. + */ +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); + +/*! + * @brief Compute CLKDIV + * + * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. + * This setting is used by hardware during slave clock stretching. + * + * @param base The I2C peripheral base address. + * @return status of the operation + */ +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); + +/*! + * @brief Poll wait for the SLVPENDING flag. + * + * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. + * + * @param base The I2C peripheral base address. + * @return status register at time the SLVPENDING bit is read as set + */ +static uint32_t I2C_SlavePollPending(I2C_Type *base); + +/*! + * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). + * + * Sets the event type to transfer structure and invokes the event callback, if it has been + * enabled by eventMask. + * + * @param base The I2C peripheral base address. + * @param handle The I2C slave handle for non-blocking APIs. + * @param event The I2C slave event to invoke. + */ +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); + +/*! + * @brief Handle slave address match event. + * + * Called by Slave interrupt routine to ACK or NACK the matched address. + * It also determines master direction (read or write). + * + * @param base The I2C peripheral base address. + * @return true if the matched address is ACK'ed + * @return false if the matched address is NACK'ed + */ +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. + * @param txSize Size of txData buffer in bytes. + * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL + * if slave TX only. + * @param rxSize Size of rxData buffer in bytes. + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask); + +/*! + * @brief Execute master transfer software state machine until FIFOs are exhausted. + * + * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState + * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> + * kWaitForCompletionState + * + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief Checks the slave response to master's start signal. + * + * @param base I2C peripheral base address. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. + */ +static status_t I2C_MasterCheckStartResponse(I2C_Type *base); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The I2C peripheral base address. + * return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t i; + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) + { + if (MSDK_REG_SECURE_ADDR((uint32_t)base) == MSDK_REG_SECURE_ADDR(s_i2cBaseAddrs[i])) + { + break; + } + } + assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); + return i; +} + +/*! + * brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->baudRate_Bps = 100000U; + masterConfig->enableTimeout = false; + masterConfig->timeout_Ms = 35; +} + +/*! + * brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(base, masterConfig->enableMaster); + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + if (masterConfig->enableTimeout) + { + base->CFG |= I2C_CFG_TIMEOUTEN_MASK; + } + else + { + base->CFG &= ~I2C_CFG_TIMEOUTEN_MASK; + } + I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); +} + +/*! + * brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base) +{ + I2C_MasterEnable(base, false); +} + +/*! + * brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * param base The I2C peripheral base address. + * return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base) +{ + uint32_t statusMask = base->STAT; + if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_MasterIdleFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; + } + return statusMask; +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I2C peripheral base address. + * param srcClock_Hz I2C functional clock frequency in Hertz. + * param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t scl, divider; + uint32_t mindivider; + uint32_t err, best_err; + uint32_t best_scl = 0U; + uint32_t best_div = 0U; + +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + /* + * RFT1717/RFT1437: workaround for hardware bug when using DMA + * I2C peripheral clock frequency has to be fixed at 8MHz + * source clock is 32MHz or 48MHz so divider is a round integer value + */ + best_div = srcClock_Hz / 8000000U; + best_scl = 8000000U / baudRate_Bps; + + if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) + { + best_scl = best_scl + 1U; + } + + /* + * Fallback to usual baudrate computation method, when: + * 1.Master SCL frequency does not fit in workaround range, + * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz + */ + if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) + { +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + + /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ + /* This is required in RM in order to generate 400kHz baudrate */ + mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; + /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, + update mindivider */ + if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) + { + mindivider = srcClock_Hz / 4U / baudRate_Bps; + } + /* Calculate the ideal div and scl value*/ + best_err = 0U; + for (divider = mindivider; divider <= 0x10000U; divider++) + { + /* Calculte ideal scl value, round up the value */ + scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; + + /* adjust it if it is out of range */ + scl = (scl > 18U) ? 18U : scl; + + /* calculate error */ + err = srcClock_Hz - (baudRate_Bps * scl * divider); + if ((err < best_err) || (best_err == 0U)) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if ((err == 0U) || (scl <= 4U)) + { + /* either exact value was found + or scl is at its min (it would be even smaller in the next iteration for sure) */ + break; + } + } +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + } +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); + if (best_scl % 2U == 0U) + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } + else + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } +} + +/*! + * brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * param base The I2C peripheral base address. + * param timeout_Ms Timeout value in millisecond. + * param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) +{ + assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); + + /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times + the I2C functional clock, we only need to calculate the high bits. */ + uint32_t clkDivider = (base->CLKDIV & I2C_CLKDIV_DIVVAL_MASK) >> I2C_CLKDIV_DIVVAL_SHIFT; + uint32_t timeoutValue = ((uint32_t)timeout_Ms * (srcClock_Hz / (clkDivider + 1UL)) / 16UL / 100UL + 5UL) / 10UL; + + if (timeoutValue > 0x1000UL) + { + timeoutValue = 0x1000UL; + } + timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; + base->TIMEOUT = timeoutValue; +} + +static status_t I2C_PendingStatusWait(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint32_t status; + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + do + { + status = I2C_GetStatusFlags(base); + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + result = kStatus_I2C_EventTimeout; + } + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + result = kStatus_I2C_SclLowTimeout; + } +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + if (result != kStatus_Success) + { + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); + break; + } +#endif +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); + + if (waitTimes == 0U) + { +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); +#endif + return kStatus_I2C_Timeout; + } +#else + } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); +#endif + + if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) + { + result = kStatus_I2C_ArbitrationLost; + } + + if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) + { + result = kStatus_I2C_StartStopError; + } + + /* Clear controller state. */ + I2C_ClearStatusFlags( + base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); + + return result; +} + +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) + { + return result; + } + + /* Write Address and RW bit to data register */ + base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); + /* Start the transfer */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + + return kStatus_Success; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) + { + return result; + } + + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + return kStatus_Success; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was sent successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + uint32_t master_state; + status_t err; + + const uint8_t *buf = (const uint8_t *)txBuff; + + assert(txBuff != NULL); + + err = kStatus_Success; + while (txSize != 0U) + { + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_TXREADY: + /* ready to send next byte */ + base->MSTDAT = *buf++; + txSize--; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + err = kStatus_I2C_Nak; + /* Issue nack signal when nacked by slave. */ + (void)I2C_MasterStop(base); + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + +#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Nak; + } +#endif + + if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Initiate stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + if (err != kStatus_Success) + { + return err; + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was received successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + uint32_t master_state; + status_t err; + + uint8_t *buf = (uint8_t *)(rxBuff); + + assert(rxBuff != NULL); + + err = kStatus_Success; + while (rxSize != 0U) + { + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_RXREADY: + /* ready to send next byte */ + *(buf++) = (uint8_t)base->MSTDAT; + if (--rxSize != 0U) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) + { + /* initiate NAK and stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + } + } + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + return kStatus_Success; +} + +static status_t I2C_MasterCheckStartResponse(I2C_Type *base) +{ + /* Wait for start signal to be transmitted. */ + status_t result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + return result; + } + + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + uint32_t subaddress; + uint8_t subaddrBuf[4]; + i2c_direction_t direction; + int i; + + assert(xfer != NULL); + + /* Enable the master function and disable the slave function. */ + I2C_MasterEnable(base, true); + I2C_SlaveEnable(base, false); + + /* If start signal is requested, send start signal. */ + if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + if ((xfer->subaddressSize) != 0U) + { + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + /* Send subaddress. */ + result = + I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + } + else if (xfer->direction == kI2C_Read) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + } + } + else + { + /* Empty else block to avoid MISRA 14.1 violation. */ + } + } + } + } + + if (result == kStatus_Success) + { + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) + { + /* Transmit data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else + { + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) + { + /* Receive Data. */ + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + } + } + + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param xfer The pointer to the transfer descriptor. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Enable the master function and disable the slave function. */ + I2C_MasterEnable(base, true); + I2C_SlaveEnable(base, false); + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + /* Clear error flags. */ + I2C_ClearStatusFlags(base, (uint32_t)((uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_CommonAllClearFlags)); + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success + * retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * retval kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + status_t result = kStatus_Success; + uint32_t master_state; + + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Wait until module is ready */ + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + handle->state = (uint8_t)kIdleState; + return result; + } + + /* Get the state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until the STOP is completed */ + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + handle->state = (uint8_t)kIdleState; + return result; + } + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + handle->checkAddrNack = false; + } + return kStatus_Success; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + struct _i2c_master_transfer *transfer; + + handle->transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytes = transfer->dataSize; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + handle->checkAddrNack = false; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (uint8_t)kReceiveDataBeginState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0U) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; + } + + return kStatus_Success; +} + +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + status_t err; + + transfer = &(handle->transfer); + bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) +#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ + || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) +#endif + ; + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) + { + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + return kStatus_I2C_ArbitrationLost; + } + + if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) + { + I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + return kStatus_I2C_StartStopError; + } + + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); +#endif + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); +#endif + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + + return kStatus_I2C_SclLowTimeout; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) + { + return kStatus_I2C_Busy; + } + + /* Get the hardware state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || + ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) && (ignoreNak != true))) + { + /* Slave NACKed last byte, issue stop and return error */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) + { + return kStatus_I2C_Addr_Nak; + } + else /* Otherwise just return kStatus_I2C_Nak */ + { + return kStatus_I2C_Nak; + } + } + + err = kStatus_Success; + switch (handle->state) + { + case (uint8_t)kStartState: + if (handle->remainingSubaddr != 0U) + { + /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; + handle->state = (uint8_t)kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; + } + else + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; + } + /* Send start condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + break; + + case (uint8_t)kTransmitSubaddrState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + /* Most significant subaddress byte comes first */ + base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--(handle->remainingSubaddr) != 0U) + { + /* There are still subaddress bytes to be transmitted */ + break; + } + if (handle->remainingBytes != 0U) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kTransmitDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + base->MSTDAT = *(handle->buf)++; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--handle->remainingBytes == 0U) + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + handle->transferCount++; + break; + + case (uint8_t)kReceiveDataBeginState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + (void)base->MSTDAT; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + handle->state = (uint8_t)kReceiveDataState; + break; + + case (uint8_t)kReceiveDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + *(handle->buf)++ = (uint8_t)base->MSTDAT; + if (--handle->remainingBytes != 0U) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + /* No more data expected, issue NACK and STOP right away */ + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; + } + handle->transferCount++; + break; + + case (uint8_t)kStopState: + handle->checkAddrNack = false; + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + + case (uint8_t)kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I2C_RunTransferStateMachine(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ +} + +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) +{ + uint32_t dataSetupTime_ns; + + switch ((uint8_t)(busSpeed)) + { + case (uint8_t)kI2C_SlaveStandardMode: + dataSetupTime_ns = 250U; + break; + + case (uint8_t)kI2C_SlaveFastMode: + dataSetupTime_ns = 100U; + break; + + case (uint8_t)kI2C_SlaveFastModePlus: + dataSetupTime_ns = 50U; + break; + + case (uint8_t)kI2C_SlaveHsMode: + dataSetupTime_ns = 10U; + break; + + default: + dataSetupTime_ns = 0U; + break; + } + + if (0U == dataSetupTime_ns) + { + return kStatus_InvalidArgument; + } + + /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ + *divVal = srcClock_Hz / 1000U; + *divVal = (*divVal) * dataSetupTime_ns; + *divVal = (*divVal) / 1000000U; + + if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) + { + *divVal = I2C_CLKDIV_DIVVAL_MASK; + } + + return kStatus_Success; +} + +static uint32_t I2C_SlavePollPending(I2C_Type *base) +{ + uint32_t stat; + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + stat = base->STAT; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); + + if (waitTimes == 0U) + { + return (uint32_t)kStatus_I2C_Timeout; + } +#else + } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif + + return stat; +} + +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) +{ + uint32_t eventMask = handle->transfer.eventMask; + handle->transfer.event = event; + if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) + { + handle->callback(base, &handle->transfer, handle->userData); + + size_t txSize = handle->transfer.txSize; + size_t rxSize = handle->transfer.rxSize; + /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ + if (false == handle->isBusy) + { + if (((handle->transfer.txData != NULL) && (txSize != 0U)) || + ((handle->transfer.rxData != NULL) && (rxSize != 0U))) + { + handle->isBusy = true; + } + } + + /* Clear the transferred count now that we have a new buffer. */ + if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) + { + handle->transfer.transferredCount = 0; + } + } +} + +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint8_t addressByte0; + size_t txSize; + size_t rxSize; + + addressByte0 = (uint8_t)base->SLVDAT; + + /* store the matched address */ + handle->transfer.receivedAddress = addressByte0; + + /* R/nW */ + if ((addressByte0 & 1U) != 0U) + { + txSize = handle->transfer.txSize; + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + txSize = handle->transfer.txSize; + /* NACK if we have no data in this transfer. */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants to read, so slave transmit is next state */ + handle->slaveFsm = kI2C_SlaveFsmTransmit; + } + else + { + rxSize = handle->transfer.rxSize; + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + rxSize = handle->transfer.rxSize; + /* NACK if we have no data in this transfer */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants write, so slave receive is next state */ + handle->slaveFsm = kI2C_SlaveFsmReceive; + } + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + return true; +} + +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask) +{ + assert(handle != NULL); + + status_t status; + status = kStatus_Success; + + /* Enable the slave function and disable the master function. */ + I2C_MasterEnable(base, false); + I2C_SlaveEnable(base, true); + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + status = kStatus_I2C_Busy; + } + + /* Save transfer into handle. */ + handle->transfer.txData = (const uint8_t *)txData; + handle->transfer.txSize = txSize; + handle->transfer.rxData = (uint8_t *)rxData; + handle->transfer.rxSize = rxSize; + handle->transfer.transferredCount = 0; + handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; + handle->isBusy = true; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* Clear w1c flags. */ + base->STAT |= 0u; + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + return status; +} + +/*! + * brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param txData Pointer to data to send to master. + * param txSize Size of txData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); +} + +/*! + * brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param rxData Pointer to data to store data from master. + * param rxSize Size of rxData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); +} + +/*! + * brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * param base The I2C peripheral base address. + * param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * param address The slave address to be stored to the address register for matching. + * param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable) +{ + base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); +} + +/*! + * brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a + * address0.address member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + i2c_slave_config_t mySlaveConfig = {0}; + + /* default config enables slave address 0 match to general I2C call address zero */ + mySlaveConfig.enableSlave = true; + mySlaveConfig.address1.addressDisable = true; + mySlaveConfig.address2.addressDisable = true; + mySlaveConfig.address3.addressDisable = true; + + *slaveConfig = mySlaveConfig; +} + +/*! + * brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * param base The I2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + status_t status; + uint32_t divVal = 0; + + /* configure data setup time used when slave stretches clock */ + status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); + if (kStatus_Success != status) + { + return status; + } + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + + /* I2C Clock Divider register */ + base->CLKDIV = divVal; + + /* set Slave address */ + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, + slaveConfig->address0.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, + slaveConfig->address1.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, + slaveConfig->address2.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, + slaveConfig->address3.addressDisable); + + /* set Slave address 0 qual */ + base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); + + /* set Slave enable */ + base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); + + return status; +} + +/*! + * brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been sent. + * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + const uint8_t *buf = txBuff; + uint32_t stat; + bool slaveAddress; + bool slaveTransmit; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); + + /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ + if (!(slaveAddress || slaveTransmit)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* send bytes up to txSize */ + while (txSize != 0U) + { + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); + + if (!slaveTransmit) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Write 8 bits of data to the SLVDAT register */ + base->SLVDAT = I2C_SLVDAT_DATA(*buf); + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + txSize--; + + if (txSize != 0U) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been received. + * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + uint8_t *buf = rxBuff; + uint32_t stat; + bool slaveAddress; + bool slaveReceive; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); + + /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ + if (!(slaveAddress || slaveReceive)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* receive bytes up to rxSize */ + while (rxSize != 0U) + { + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); + + if (!slaveReceive) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Read 8 bits of data from the SLVDAT register */ + *buf = (uint8_t)base->SLVDAT; + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + rxSize--; + + if (rxSize != 0U) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* initialize fsm */ + handle->slaveFsm = kI2C_SlaveFsmAddressMatch; + + /* store pointer to handle into transfer struct */ + handle->transfer.handle = handle; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); +} + +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * retval kStatus_Success + * retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + /* Set the SLVEN bit to 0 in the CFG register. */ + I2C_SlaveEnable(base, false); + + handle->isBusy = false; + handle->transfer.txSize = 0U; + handle->transfer.rxSize = 0U; +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint32_t i2cStatus = base->STAT; + uint8_t tmpdata; + size_t txSize; + size_t rxSize; + + if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); + I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); + } + + /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ + if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) + { + bool slaveAddress = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + + if (slaveAddress) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); + (void)I2C_SlaveAddressIRQ(base, handle); + } + else + { + switch (handle->slaveFsm) + { + case kI2C_SlaveFsmReceive: + { + bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_RX); + + if (slaveReceive) + { + rxSize = handle->transfer.rxSize; + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + rxSize = handle->transfer.rxSize; + /* receive a byte */ + if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) + { + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + tmpdata = (uint8_t)base->SLVDAT; + *(handle->transfer.rxData) = tmpdata; + (handle->transfer.rxSize)--; + (handle->transfer.rxData)++; + (handle->transfer.transferredCount)++; + } + + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; + /* is this last transaction for this transfer? allow next transaction */ + if ((0U == rxSize) && (0U == txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + case kI2C_SlaveFsmTransmit: + { + bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_TX); + + if (slaveTransmit) + { + txSize = handle->transfer.txSize; + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + txSize = handle->transfer.txSize; + /* transmit a byte */ + if ((handle->transfer.txData != NULL) && (txSize != 0U)) + { + base->SLVDAT = *(handle->transfer.txData); + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + (handle->transfer.txSize)--; + (handle->transfer.txData)++; + (handle->transfer.transferredCount)++; + } + + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; + /* is this last transaction for this transfer? allow next transaction */ + if ((0U == rxSize) && (0U == txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + default: + /* incorrect state, slv_abort()? */ + break; + } + } + } +} diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.h b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.h new file mode 100644 index 0000000000..9913fcc53c --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/i2c/fsl_i2c.h @@ -0,0 +1,1155 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I2C_H_ +#define FSL_I2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define I2C_CFG_MASK 0x1f + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief I2C driver version. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ +#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK +#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ + 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ +#endif + +/* definitions for MSTCODE bits in I2C Status register STAT */ +#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ + +/* definitions for SLVSTATE bits in I2C Status register STAT */ +#define I2C_STAT_SLVST_ADDR (0) +#define I2C_STAT_SLVST_RX (1) +#define I2C_STAT_SLVST_TX (2) + +/*! @brief I2C status return codes. */ +enum +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ + kStatus_I2C_Nak = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_I2C_InvalidParameter = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ + kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ + kStatus_I2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ + kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ + kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ + kStatus_I2C_Timeout = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, + 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ + kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ + kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! + * @brief I2C status flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_status_flags +{ + kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ + kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ + kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ + kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ + kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ + kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ + kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ + kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 + = yes, 1 = no). bit 11 */ + kI2C_SlaveSelected = + I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ + kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event + took place, w1c). bit 15 */ + kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ + kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ + kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ + kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ + kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ + kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ + kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ + kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ + kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ + kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ + kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ + kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ + kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ + + /* All master flags that can be cleared by software */ + kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, + /* All slave flags that can be cleared by software */ + kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, + /* All common flags that can be cleared by software */ + kI2C_CommonAllClearFlags = + kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, +}; + +/*! + * @brief I2C interrupt enable. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_interrupt_enable +{ + kI2C_MasterPendingInterruptEnable = + I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ + kI2C_MasterArbitrationLostInterruptEnable = + I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ + kI2C_MasterStartStopErrorInterruptEnable = + I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ + kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ + kI2C_SlaveNotStretchingInterruptEnable = + I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when + this interrupt occurs. */ + kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ + kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ + kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ + kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ + kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ + kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ + + /* All master interrupt sources */ + kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | + kI2C_MasterStartStopErrorInterruptEnable, + /* All slave interrupt sources */ + kI2C_SlaveAllInterruptEnable = + kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, + /* All common interrupt sources */ + kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | + kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | + kI2C_SclTimeoutInterruptEnable, +}; +/*! @} */ + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0U, /*!< Master transmit. */ + kI2C_Read = 1U /*!< Master receive. */ +} i2c_direction_t; + +/*! + * @brief Structure with settings to initialize the I2C master module. + * + * This structure holds configuration settings for the I2C peripheral. To initialize this + * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ + bool enableTimeout; /*!< Enable internal timeout function. */ + uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ +} i2c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief I2C master transfer typedef */ +typedef struct _i2c_master_transfer i2c_master_transfer_t; + +/*! @brief I2C master handle typedef */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to I2C_MasterTransferCreateHandle(). + * + * @param base The I2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i2c_master_transfer::flags field. + */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i2c_transfer_states +{ + kIdleState = 0, + kTransmitSubaddrState, + kTransmitDataState, + kReceiveDataBeginState, + kReceiveDataState, + kReceiveLastDataState, + kStartState, + kStopState, + kWaitForCompletionState +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. + */ +struct _i2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available + options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ + i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ +/*! @brief I2C slave address register. */ +typedef enum _i2c_slave_address_register +{ + kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ + kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ + kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ + kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ +} i2c_slave_address_register_t; + +/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ +typedef struct _i2c_slave_address +{ + uint8_t address; /*!< 7-bit Slave address SLVADR. */ + bool addressDisable; /*!< Slave address disable SADISABLE. */ +} i2c_slave_address_t; + +/*! @brief I2C slave address match options. */ +typedef enum _i2c_slave_address_qual_mode +{ + kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ + kI2C_QualModeExtend = + 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ +} i2c_slave_address_qual_mode_t; + +/*! @brief I2C slave bus speed options. */ +typedef enum _i2c_slave_bus_speed +{ + kI2C_SlaveStandardMode = 0U, + kI2C_SlaveFastMode = 1U, + kI2C_SlaveFastModePlus = 2U, + kI2C_SlaveHsMode = 3U, +} i2c_slave_bus_speed_t; + +/*! + * @brief Structure with settings to initialize the I2C slave module. + * + * This structure holds configuration settings for the I2C slave peripheral. To initialize this + * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_slave_config +{ + i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ + i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ + uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ + i2c_slave_bus_speed_t + busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must + provide sufficient data setup time to the master before releasing the stretched clock. + This is accomplished by inserting one clock time of CLKDIV at that point. + The #busSpeed value is used to configure CLKDIV + such that one clock time is greater than the tSU;DAT value noted + in the I2C bus specification for the I2C mode that is being used. + If the #busSpeed mode is unknown at compile time, use the longest data setup time + kI2C_SlaveStandardMode (250 ns) */ + bool enableSlave; /*!< Enable slave mode. */ +} i2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ + kI2C_SlaveDeselectedEvent = + 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | + kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave transfer structure */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint8_t *rxData; /*!< Transfer buffer for receive data */ + const uint8_t *txData; /*!< Transfer buffer for transmit data */ + size_t txSize; /*!< Transfer size */ + size_t rxSize; /*!< Transfer size */ + size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ +} i2c_slave_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the I2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the I2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief I2C slave software finite state machine states. + */ +typedef enum _i2c_slave_fsm +{ + kI2C_SlaveFsmAddressMatch = 0u, + kI2C_SlaveFsmReceive = 2u, + kI2C_SlaveFsmTransmit = 3u, +} i2c_slave_fsm_t; + +/*! + * @brief I2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_slave_handle +{ + volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ + volatile bool isBusy; /*!< Whether transfer is busy. */ + volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*! @{ */ + +/*! + * @brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the I2C master peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +static inline void I2C_MasterReset(I2C_Type *base) +{ +} + +/*! + * @brief Enables or disables the I2C module as master. + * + * @param base The I2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified I2C as master. + */ +static inline void I2C_MasterEnable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; + } + else + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; + } +} + +/*! @} */ + +/*! @name Status */ +/*! @{ */ +/*! + * @brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see @ref _i2c_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base); + +/*! + * @brief Clears the I2C status flag state. + * + * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see + * the clearable flags. Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in + * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass + * the result of a previous call to I2C_GetStatusFlags(). + * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. + */ +static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Only deal with the clearable flags */ + statusMask &= + ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); + base->STAT = statusMask; +} + +/*! + * @brief Clears the I2C master status flag state. + * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags + * The following status register flags can be cleared: + * - #kI2C_MasterArbitrationLostFlag + * - #kI2C_MasterStartStopErrorFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_GetStatusFlags(). + * @see _i2c_status_flags. + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just master status flags */ + base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); +} + +/*! @} */ + +/*! @name Interrupts */ +/*! @{ */ + +/*! + * @brief Enables the I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENSET = interruptMask; +} + +/*! + * @brief Disables the I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) +{ + return base->INTSTAT; +} + +/*! @} */ + +/*! @name Bus operations */ +/*! @{ */ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I2C peripheral base address. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + * @param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * @param base The I2C peripheral base address. + * @param timeout_Ms Timeout value in millisecond. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) +{ + /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ + return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); +} + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + return I2C_MasterStart(base, address, direction); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/*! @} */ + +/*! @name Non-blocking */ +/*! @{ */ + +/*! + * @brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param xfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! @} */ + +/*! @name IRQ handler */ +/*! @{ */ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); + +/*! @} */ + +/*! @} */ /* end of i2c_master_driver */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*! @{ */ + +/*! + * @brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a + * address0.address member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * @param base The I2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * @param base The I2C peripheral base address. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * @param address The slave address to be stored to the address register for matching. + * @param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable); + +/*! + * @brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Enables or disables the I2C module as slave. + * + * @param base The I2C peripheral base address. + * @param enable True to enable or flase to disable. + */ +static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) +{ + /* Set or clear the SLVEN bit in the CFG register. */ + if (enable) + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_SLVEN_MASK; + } + else + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_SLVEN_MASK; + } +} + +/*! @} */ /* end of Slave initialization and deinitialization */ + +/*! @name Slave status */ +/*! @{ */ + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: + * - slave deselected flag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_SlaveGetStatusFlags(). + * @see _i2c_slave_flags. + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just slave status flags */ + base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; +} + +/*! @} */ /* end of Slave status */ + +/*! @name Slave bus operations */ +/*! @{ */ + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been sent. + * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been received. + * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! @} */ /* end of Slave bus operations */ + +/*! @name Slave non-blocking */ +/*! @{ */ + +/*! + * @brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param txData Pointer to data to send to master. + * @param txSize Size of txData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); + +/*! + * @brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param rxData Pointer to data to store data from master. + * @param rxSize Size of rxData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. + * + * @param base The I2C peripheral base address. + * @param transfer The I2C slave transfer. + * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) +{ + return transfer->receivedAddress; +} + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! @} */ /* end of Slave non-blocking */ + +/*! @name Slave IRQ handler */ +/*! @{ */ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! @} */ /* end of Slave IRQ handler */ + +/*! @} */ /* end of i2c_slave_driver */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I2C_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.c b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.c new file mode 100644 index 0000000000..35abce34ce --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.c @@ -0,0 +1,1077 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020,2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" +#endif + +/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ + +#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) +#define SPI_FIFO_DEPTH(base) 4 +#else +#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) +#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ + +/* Convert transfer count to transfer bytes. dataWidth is a + * range <0,15>. Range <8,15> represents 2B transfer */ +#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) +#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) +#else +#if (defined(FSL_FEATURE_SPI_SSEL_COUNT) && (FSL_FEATURE_SPI_SSEL_COUNT == 2)) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK)) +#else +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) +#endif /* FSL_FEATURE_SPI_SSEL_COUNT == 2 */ +#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and + * `flexcomm_spi_slave_irq_handler_t`. + */ +typedef union spi_to_flexcomm +{ + flexcomm_spi_master_irq_handler_t spi_master_handler; + flexcomm_spi_slave_irq_handler_t spi_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} spi_to_flexcomm_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief internal SPI config array */ +static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; + +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + uint32_t i; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) + { + if (MSDK_REG_SECURE_ADDR((uint32_t)base) == MSDK_REG_SECURE_ADDR(s_spiBaseAddrs[i])) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); + return i; +} + +/*! + * brief Set up the dummy data. + * + * param base SPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +/*! + * brief Returns the configurations. + * + * param base SPI peripheral address. + * return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base) +{ + uint32_t instance; + instance = SPI_GetInstance(base); + return &g_configs[instance]; +} + +/*! + * brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + endcode + * + * param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableLoopback = false; + config->enableMaster = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->baudRate_Bps = 500000U; + config->dataWidth = kSPI_Data8Bits; + config->sselNum = kSPI_Ssel0; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; +} + +/*! + * brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to master configuration structure + * param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; + + /* assert params */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to SPI mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + if (kStatus_Success != result) + { + return result; + } + + /* set divider */ + result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + + /* get instance number */ + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmpConfig |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmpConfig |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmpConfig |= SPI_CFG_LSBF(config->direction); + /* master mode */ + tmpConfig |= SPI_CFG_MASTER(1); + /* loopback */ + tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + g_configs[instance].sselNum = config->sselNum; + /* enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmpConfig; + + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableMaster); + return kStatus_Success; +} + +/*! + * brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + endcode + * + * param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->dataWidth = kSPI_Data8Bits; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; +} + +/*! + * brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; + + /* assert params */ + assert(!((NULL == base) || (NULL == config))); + if ((NULL == base) || (NULL == config)) + { + return kStatus_InvalidArgument; + } + /* configure flexcomm to SPI, enable clock gate */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + if (kStatus_Success != result) + { + return result; + } + + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmpConfig |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmpConfig |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmpConfig |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + /* empty and enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmpConfig; + + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableSlave); + return kStatus_Success; +} + +/*! + * brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base) +{ + /* Assert arguments */ + assert(NULL != base); + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | + SPI_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); + base->CFG &= ~(SPI_CFG_ENABLE_MASK); +} + +/*! + * brief Enables the DMA request from SPI txFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; + } +} + +/*! + * brief Enables the DMA request from SPI rxFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; + } +} + +/*! + * brief Sets the baud rate for SPI transfer. This is only used in master. + * + * param base SPI base pointer + * param baudrate_Bps baud rate needed in Hz. + * param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t tmpDiv; + + /* assert params */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* calculate baudrate, round up the result */ + tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; + if (tmpDiv > 0xFFFFU) + { + return kStatus_SPI_BaudrateNotSupport; + } + base->DIV &= ~SPI_DIV_DIVVAL_MASK; + base->DIV |= SPI_DIV_DIVVAL(tmpDiv); + return kStatus_Success; +} + +/*! + * brief Writes a data into the SPI data register. + * + * param base SPI base pointer + * param data needs to be write. + * param configFlags transfer configuration options ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) +{ + uint32_t control = 0U; + uint32_t instance; + + /* check params */ + assert(NULL != base); + /* get and check instance */ + instance = SPI_GetInstance(base); + + /* set data width */ + control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); + /* set sssel */ + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); + /* mask configFlags */ + control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); + /* control should not affect lower 16 bits */ + assert(0U == (control & 0xFFFFU)); + base->FIFOWR = data | control; +} + +/*! + * brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback Callback function. + * param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + /* check 'base' */ + assert(NULL != base); + /* check 'handle' */ + assert(NULL != handle); + + uint32_t instance; + spi_to_flexcomm_t handler; + + /* get flexcomm instance by 'base' param */ + instance = SPI_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Initialize the handle */ + if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) + { + handler.spi_master_handler = SPI_MasterTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + } + else + { + handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + } + + handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); + /* in slave mode, the sselNum is not important */ + handle->sselNum = (uint8_t)(g_configs[instance].sselNum); + handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->callback = callback; + handle->userData = userData; + + /* Enable SPI NVIC */ + (void)EnableIRQ(s_spiIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * param base SPI base pointer + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Timeout The transfer timed out and was aborted. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + uint32_t instance; + uint32_t tx_ctrl = 0U, last_ctrl = 0U; + uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; + uint32_t toReceiveCount = 0; + const uint8_t *txData; + uint8_t *rxData; + uint32_t fifoDepth; +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif + + /* check params */ + assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + fifoDepth = SPI_FIFO_DEPTH(base); + txData = xfer->txData; + rxData = xfer->rxData; + txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; + rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; + + instance = SPI_GetInstance(base); + dataWidth = (uint32_t)(g_configs[instance].dataWidth); + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) + { + return kStatus_InvalidArgument; + } + + /* clear tx/rx errors and empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); + /* set width of data - range asserted at entry */ + tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + /* end of transfer */ + last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + /* last index of loop */ + while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) + { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif + /* if rxFIFO is not empty */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (rxRemainingBytes != 0U) + { + *(rxData++) = (uint8_t)tmp32; + rxRemainingBytes--; + /* read 16 bits at once */ + if (dataWidth > 8U) + { + *(rxData++) = (uint8_t)(tmp32 >> 8); + rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + toReceiveCount -= 1U; + } + /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) + { + /* txBuffer is not empty */ + if (txRemainingBytes != 0U) + { + tmp32 = *(txData++); + txRemainingBytes--; + /* write 16 bit at once */ + if (dataWidth > 8U) + { + tmp32 |= ((uint32_t)(*(txData++))) << 8U; + txRemainingBytes--; + } + if (txRemainingBytes == 0U) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + toReceiveCount += 1U; + } + } + /* wait if TX FIFO of previous transfer is not empty */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + /* check params */ + assert( + !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); + if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) + { + return kStatus_InvalidArgument; + } + + /* Check if SPI is busy */ + if (handle->state == (uint32_t)kStatus_SPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + /* set count */ + handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; + handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; + handle->totalByteCount = xfer->dataSize; + /* other options */ + handle->toReceiveCount = 0; + handle->configFlags = xfer->configFlags; + /* Set the SPI state to busy */ + handle->state = (uint32_t)kStatus_SPI_Busy; + /* clear FIFOs when transfer starts */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * param base SPI base pointer + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer != NULL); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer != NULL); + assert(handle != NULL); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +/*! + * brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint32_t)kStatus_SPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->rxRemainingBytes; + return kStatus_Success; +} + +/*! + * brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupt requests*/ + base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); + /* Empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + + handle->state = (uint32_t)kStatus_SPI_Idle; + handle->txRemainingBytes = 0U; + handle->rxRemainingBytes = 0U; +} + +static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) +{ + uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; + bool loopContinue; + uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); + size_t txRemainingBytes; + size_t rxRemainingBytes; + uint8_t toReceiveCount; + + /* check params */ + assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); + + fifoDepth = SPI_FIFO_DEPTH(base); + /* select slave to talk with */ + tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); + /* set width of data */ + tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + /* end of transfer */ + last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + do + { + loopContinue = false; + + /* rxFIFO is not empty */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (handle->rxRemainingBytes != 0U) + { + /* low byte must go first */ + *(handle->rxData++) = (uint8_t)tmp32; + handle->rxRemainingBytes--; + /* read 16 bits at once */ + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) + { + *(handle->rxData++) = (uint8_t)(tmp32 >> 8); + handle->rxRemainingBytes--; + } + } + + /* decrease number of data expected to receive */ + handle->toReceiveCount -= 1; + loopContinue = true; + } + + /* - txFIFO is not full + * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO + * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer + */ + txRemainingBytes = handle->txRemainingBytes; + rxRemainingBytes = handle->rxRemainingBytes; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || + (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) + { + /* txBuffer is not empty */ + if ((txRemainingBytes != 0U) && (handle->txData != NULL)) + { + /* low byte must go first */ + tmp32 = *(handle->txData++); + handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; + /* write 16 bit at once */ + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) + { + tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; + handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; + } + /* last transfer */ + if (handle->txRemainingBytes == 0U) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + /* increase number of expected data to receive */ + handle->toReceiveCount += 1; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + loopContinue = true; + } + } while (loopContinue); +} + +/*! + * brief Interrupts the handler for the SPI. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert((NULL != base) && (NULL != handle)); + size_t txRemainingBytes; + uint8_t toReceiveCount; + + /* IRQ behaviour: + * - first interrupt is triggered by empty txFIFO. The transfer function + * then tries empty rxFIFO and fill txFIFO interleaved that results to + * strategy to process as many items as possible. + * - the next IRQs can be: + * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. + * txIRQ from empty txFIFO which requires to refill txFIFO. + * - last interrupt is triggered by empty txFIFO. The last state is + * known by empty rxBuffer and txBuffer. If there is nothing to receive + * or send - both operations have been finished and interrupts can be + * disabled. + */ + + /* Data to send or read or expected to receive */ + if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) + { + /* Transmit or receive data */ + SPI_TransferHandleIRQInternal(base, handle); + /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and + * enable txIRQ to confirm when txFIFO becomes empty */ + if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) + { + base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; + } + else + { + uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); + /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, + * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) + { + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; + } + /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. + * Cannot clear rxFIFO, txFIFO might be still active */ + if (rxRemainingCount == 0U) + { + txRemainingBytes = handle->txRemainingBytes; + if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && + (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) + { + base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | + SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); + } + } + else + { + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); + } + } + } + } + else + { + /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; + base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | + SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); + /* set idle state and call user callback */ + handle->state = (uint32_t)kStatus_SPI_Idle; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, handle->state, handle->userData); + } + } +} diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.h b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.h new file mode 100644 index 0000000000..2a2cc8de9a --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/spi/fsl_spi.h @@ -0,0 +1,758 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020,2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_SPI_H_ +#define FSL_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief SPI driver version. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +/*! @} */ +/*! @brief SPI default SSEL COUNT*/ +#if !(defined(FSL_FEATURE_SPI_SSEL_COUNT) || defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE)) +#define FSL_FEATURE_SPI_SSEL_COUNT (4U) +#endif + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0x00U) +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) +#define SPI_CTRLMASK (0xFFFF0000U) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) +#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) +#define SPI_DEASSERT_ALL (0xF0000UL) + +#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) + +#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) +#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief SPI transfer option.*/ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ +} spi_xfer_option_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief txFIFO watermark values */ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ + kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ + kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ + kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ + kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ + kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ + kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ + kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ +} spi_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ + kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ + kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ + kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ + kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ + kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ + kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ + kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ +} spi_rxfifo_watermark_t; + +/*! @brief Transfer data width */ +typedef enum _spi_data_width +{ + kSPI_Data4Bits = 3, /*!< 4 bits data width */ + kSPI_Data5Bits = 4, /*!< 5 bits data width */ + kSPI_Data6Bits = 5, /*!< 6 bits data width */ + kSPI_Data7Bits = 6, /*!< 7 bits data width */ + kSPI_Data8Bits = 7, /*!< 8 bits data width */ + kSPI_Data9Bits = 8, /*!< 9 bits data width */ + kSPI_Data10Bits = 9, /*!< 10 bits data width */ + kSPI_Data11Bits = 10, /*!< 11 bits data width */ + kSPI_Data12Bits = 11, /*!< 12 bits data width */ + kSPI_Data13Bits = 12, /*!< 13 bits data width */ + kSPI_Data14Bits = 13, /*!< 14 bits data width */ + kSPI_Data15Bits = 14, /*!< 15 bits data width */ + kSPI_Data16Bits = 15, /*!< 16 bits data width */ +} spi_data_width_t; + +/*! @brief Slave select */ +typedef enum _spi_ssel +{ + kSPI_Ssel0 = 0, /*!< Slave select 0 */ + kSPI_Ssel1 = 1, /*!< Slave select 1 */ + kSPI_Ssel2 = 2, /*!< Slave select 2 */ + kSPI_Ssel3 = 3, /*!< Slave select 3 */ +} spi_ssel_t; + +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), +#if ((defined(FSL_FEATURE_SPI_SSEL_COUNT) && (FSL_FEATURE_SPI_SSEL_COUNT > 2)) || \ + (defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && \ + (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE))) + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), +#endif +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) + kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), +#else +#if (defined(FSL_FEATURE_SPI_SSEL_COUNT) && (FSL_FEATURE_SPI_SSEL_COUNT == 2)) + kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh), +#else + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), +#endif /* FSL_FEATURE_SPI_SSEL_COUNT == 2 */ +#endif /* FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE */ + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +} spi_slave_config_t; + +/*! @brief SPI transfer status.*/ +enum +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ + kStatus_SPI_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ + kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ +}; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ + kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_statusflags +{ + kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ + kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ + kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ + kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ +}; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + const uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ + size_t dataSize; /*!< Transfer bytes */ +} spi_transfer_t; + +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + const uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + +/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ +typedef struct _spi_config +{ + spi_data_width_t dataWidth; + spi_ssel_t sselNum; +} spi_config_t; + +/*! @brief Master handle type */ +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle type */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI slave callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + const uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ + volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count + and sent count should be the same to complete the transfer, if the sent count is + x and the received count is y, toReceiveCount is x-y. */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ + uint32_t configFlags; /*!< Additional option to control transfer */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enable or disable the SPI Master or Slave + * @param base SPI base pointer + * @param enable or disable ( true = enable, false = disable) + */ +static inline void SPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= SPI_CFG_ENABLE_MASK; + } + else + { + base->CFG &= ~SPI_CFG_ENABLE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. + */ +static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFOSTAT; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENSET = irqs; +} + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENCLR = irqs; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA request from SPI txFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable); + +/*! + * @brief Enables the DMA request from SPI rxFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ +/*! + * @brief Returns the configurations. + * + * @param base SPI peripheral address. + * @return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base); + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudrate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + * @param configFlags transfer configuration options @ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +static inline uint32_t SPI_ReadData(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFORD; +} + +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + return SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); +} + +/*! + * @brief SPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_SPI_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.c b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.c new file mode 100644 index 0000000000..3e61b2e14a --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.c @@ -0,0 +1,1314 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +/*! + * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` + */ +typedef union usart_to_flexcomm +{ + flexcomm_usart_irq_handler_t usart_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} usart_to_flexcomm_t; + +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + uint32_t i; + + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) + { + if (MSDK_REG_SECURE_ADDR((uint32_t)base) == MSDK_REG_SECURE_ADDR(s_usartBaseAddrs[i])) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); + return i; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + USART_SetRxTimeoutConfig(base, &(config->rxTimeout)); +#endif + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | + USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + if (config->enableMode32k) + { + if ((9600U % config->baudRate_Bps) == 0U) + { + base->BRG = 9600U / config->baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + + /* Don't wait for TX idle when peripheral is disabled. */ + if ((base->CFG & (USART_CFG_ENABLE_MASK)) != 0U) + { +#if UART_RETRY_TIMES + uint32_t waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif + { + } + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + base->FIFORXTIMEOUTCFG = 0U; +#endif +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->enableMode32k = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; + config->enableHardwareFlowControl = false; +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + config->rxTimeout.enable = false; + config->rxTimeout.resetCounterOnEmpty = true; + config->rxTimeout.resetCounterOnReceive = true; + config->rxTimeout.counter = 0U; + config->rxTimeout.prescaler = 0U; +#endif +} +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG +/*! + * brief Calculate the USART instance RX timeout prescaler and counter. + * + * This function for calculate the USART RXFIFO timeout config. This function is used to calculate + * suitable prescaler and counter for target_us. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t config; + * config.rxWatermark = kUSART_RxFifo2; + * config.rxTimeout.enable = true; + * config.rxTimeout.resetCounterOnEmpty = true; + * config.rxTimeout.resetCounterOnReceive = true; + * USART_CalcTimeoutConfig(200, &config.rxTimeout.prescaler, &config.rxTimeout.counter, + * CLOCK_GetFreq(kCLOCK_BusClk)); + * endcode + * param target_us Time for rx timeout unit us. + * param rxTimeoutPrescaler The prescaler to be setted after function. + * param rxTimeoutcounter The counter to be setted after function. + * param srcClock_Hz The clockSrc for rx timeout. + */ +void USART_CalcTimeoutConfig(uint32_t target_us, + uint8_t *rxTimeoutPrescaler, + uint32_t *rxTimeoutcounter, + uint32_t srcClock_Hz) +{ + uint32_t counter = 0U; + uint32_t perscalar = 0U, calculate_us = 0U, us_diff = 0U, min_diff = 0xffffffffUL; + /* find the suitable value */ + for (perscalar = 0U; perscalar < 256U; perscalar++) + { + counter = target_us * (srcClock_Hz / 1000000UL) / (16U * (perscalar + 1U)); + calculate_us = 16U * (perscalar + 1U) * counter / (srcClock_Hz / 1000000UL); + us_diff = (calculate_us > target_us) ? (calculate_us - target_us) : (target_us - calculate_us); + if (us_diff == 0U) + { + *rxTimeoutPrescaler = (uint8_t)perscalar; + *rxTimeoutcounter = counter; + break; + } + else + { + if (min_diff > us_diff) + { + min_diff = us_diff; + *rxTimeoutPrescaler = (uint8_t)perscalar; + *rxTimeoutcounter = counter; + } + } + } +} +/*! + * brief Sets the USART instance RX timeout config. + * + * This function configures the USART RXFIFO timeout config. This function is used to config + * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init. + * + * param base USART peripheral base address. + * param config pointer to receive timeout configuration structure. + */ +void USART_SetRxTimeoutConfig(USART_Type *base, const usart_rx_timeout_config *config) +{ + base->FIFORXTIMEOUTCFG = 0U; + base->FIFORXTIMEOUTCFG = USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW((config->resetCounterOnReceive) ? 0U : 1U) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE((config->resetCounterOnEmpty) ? 0U : 1U) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(config->enable) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(config->counter) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(config->prescaler); +} +#endif + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate, allowed_error; + + /* check arguments */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) + { + if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1U; + } + } + else + { + /* Actual baud rate must be within 3% of desired baud rate based on the calculated OSR and BRG value */ + allowed_error = ((baudrate_Bps / 100U) * 3U); + + for (osrval = best_osrval; osrval >= 4U; osrval--) + { + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + * Break if the best baudrate's diff is in the allowed error range and the osrval is below 8, + * only use lower osrval if the baudrate cannot be obtained with an osrval of 8 or above. */ + if ((osrval <= 8U) && (best_diff <= allowed_error)) + { + break; + } + + brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; + if (brgval > 0xFFFFU) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated OSR and BRG value */ + baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff > allowed_error) + { + return kStatus_USART_BaudrateNotSupport; + } + + /* value over range */ + if (best_brgval > 0xFFFFU) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * param base USART peripheral base address. + * param baudRate_Bps USART baudrate to be set.. + * param enableMode32k true is 32k mode, false is normal mode. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + base->CFG &= ~(USART_CFG_ENABLE_MASK); + if (enableMode32k) + { + base->CFG |= USART_CFG_MODE32K_MASK; + if ((9600U % baudRate_Bps) == 0U) + { + base->BRG = 9600U / baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + base->CFG &= ~(USART_CFG_MODE32K_MASK); + result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + base->CFG |= USART_CFG_ENABLE_MASK; + return result; +} + +/*! + * brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base USART peripheral base address. + * param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set USART 9-bit mode, disable parity. */ + temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); + temp |= (uint32_t)USART_CFG_DATALEN(0x2U); + base->CFG = temp; + } + else + { + /* Set USART to 8-bit mode. */ + base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); + base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); + } +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base USART peripheral base address. + * param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address) +{ + assert(base != NULL); + base->FIFOWR = ((uint32_t)address | 0x100UL); +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_InvalidArgument Invalid argument. + * retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + /* Check whether txFIFO is enabled */ + if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return kStatus_InvalidArgument; + } + for (; length > 0U; length--) + { + /* Loop until txFIFO get some space for new data */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) + { + return kStatus_Fail; + } + for (; length > 0U; length--) + { + /* loop until rxFIFO have some data to read */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) +#else + while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) +#endif + { + } +#if UART_RETRY_TIMES + if (waitTimes == 0U) + { + status = kStatus_USART_Timeout; + break; + } +#endif + /* check rxFIFO statusFlag */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + status = kStatus_USART_RxError; + break; + } + /* check receive statusFlag */ + statusFlag = base->STAT; + /* Clear all status flags */ + base->STAT |= statusFlag; + if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) + { + status = kStatus_USART_ParityError; + } + if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) + { + status = kStatus_USART_FramingError; + } + if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) + { + status = kStatus_USART_NoiseError; + } + + if (kStatus_Success == status) + { + *data = (uint8_t)base->FIFORD; + data++; + } + else + { + break; + } + } + return status; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + + uint32_t instance = 0; + usart_to_flexcomm_t handler; + handler.usart_master_handler = USART_TransferHandleIRQ; + + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) + { + return kStatus_InvalidArgument; + } + + uint32_t globalMask = DisableGlobalIRQ(); + + /* Return error if current TX busy. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + EnableGlobalIRQ(globalMask); + return kStatus_USART_TxBusy; + } + else + { + handle->txState = (uint8_t)kUSART_TxBusy; + uint32_t usartMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, usartMask); + EnableGlobalIRQ(globalMask); + + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + USART_EnableInterrupts(base, usartMask | (uint32_t)kUSART_TxLevelInterruptEnable); + } + + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize - + ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) + { + return kStatus_InvalidArgument; + } + + /* Enable address detect when address match is enabled. */ + if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) + { + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + + uint32_t globalMask = DisableGlobalIRQ(); + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + EnableGlobalIRQ(globalMask); + return kStatus_USART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kUSART_RxBusy; + uint32_t usartMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, usartMask); + EnableGlobalIRQ(globalMask); + + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + } + else + { + handle->rxState = (uint8_t)kUSART_RxIdle; + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + + /* Enable RX interrupt. */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; + } + + /* Re-enable USART IRQ. */ + USART_EnableInterrupts(base, usartMask); + + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + + /* When using ring buffer and we received everything, call user callback. */ + if (handle->rxRingBuffer != NULL && bytesToReceive == 0U) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + bool sendEnabled = (handle->txDataSize != 0U); + uint8_t rxdata; + size_t tmpsize; + + /* If RX overrun. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) + { + /* Clear tx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxError, handle->userData); + } + } + /* If noise error. */ + if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_RXNOISEINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); + } + } + /* If framing error. */ + if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_FRAMERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); + } + } + /* If parity error. */ + if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_PARITYERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); + } + } + while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || + (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) + { + /* Receive data */ + if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) + { + /* Clear address detect when RXFIFO has data. */ + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize != 0U) + { + rxdata = (uint8_t)base->FIFORD; + *handle->rxData = rxdata; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + if (0U == handle->rxDataSize) + { + if (NULL == handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = (uint8_t)kUSART_RxIdle; + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer != NULL) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + rxdata = (uint8_t)base->FIFORD; + handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; + /* Increase handle->rxRingBufferHead. */ + if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0U; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + + base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; + } + } + } + + /* Tx idle and the interrupt is enabled. */ + if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kUSART_TxIdle; + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + tmpsize = handle->rxDataSize; + + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) + { + base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); + } + } +} diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.h b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.h new file mode 100644 index 0000000000..f2101470b0 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.h @@ -0,0 +1,977 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023, 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_USART_H_ +#define FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief USART driver version. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 8, 5)) +/*! @} */ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Retry times for waiting flag. + * + * Defining to zero means to keep waiting for the flag until it is assert/deassert in blocking transfer, + * otherwise the program will wait until the UART_RETRY_TIMES counts down to 0, + * if the flag still remains unchanged then program will return kStatus_USART_Timeout. + * It is not advised to use this macro in formal application to prevent any hardware error + * because the actual wait period is affected by the compiler and optimization. + */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U +#endif + +/*! @brief Error codes for the USART driver. */ +enum +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +#if UART_RETRY_TIMES + kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ +#endif +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), + kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsChangeInterruptEnable = + (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ + kUSART_RxBreakChangeInterruptEnable = + (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ + kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ + kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ + kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ + kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ + kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutInterruptEnable = (USART_FIFOINTENSET_RXTIMEOUT_MASK), /*!< Receive timeout detected. */ +#endif + kUSART_AllInterruptEnables = + kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | + kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | + kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | + kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutInterruptEnable | +#endif + kUSART_AutoBaudErrorInterruptEnable, +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TXERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ + kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ + kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ + kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ + kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ + kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in + the state of receiver break detection. */ + kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ + kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ + kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ + kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ + kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate + counter timeout before the end of start bit. */ +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutFlag = (USART_FIFOSTAT_RXTIMEOUT_MASK), /*!< RXTIMEOUT bit, sets if RX FIFO Timeout. */ +#endif + kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | + kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutFlag | +#endif + kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, +}; + +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG +/*! @brief USART receive timeout configuration structure. */ +typedef struct _usart_rx_timeout_config +{ + bool enable; /*!< Enable RX timeout */ + bool resetCounterOnEmpty; /*!< Enable RX timeout counter reset when RX FIFO becames empty. */ + bool resetCounterOnReceive; /*!< Enable RX timeout counter reset when RX FIFO receives data from the transmitter + side. */ + uint32_t counter; /*!< RX timeout counter*/ + uint8_t prescaler; /*!< RX timeout prescaler*/ +} usart_rx_timeout_config; +#endif + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ + bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + usart_rx_timeout_config rxTimeout; /*!< rx timeout configuration */ +#endif +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for usart interrupt handler. */ +typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG +/*! + * @brief Calculate the USART instance RX timeout prescaler and counter. + * + * This function for calculate the USART RXFIFO timeout config. This function is used to calculate + * suitable prescaler and counter for target_us. + * @code + * usart_config_t config; + * config.rxWatermark = kUSART_RxFifo2; + * config.rxTimeout.enable = true; + * config.rxTimeout.resetCounterOnEmpty = true; + * config.rxTimeout.resetCounterOnReceive = true; + * USART_CalcTimeoutConfig(200U, &config.rxTimeout.prescaler, &config.rxTimeout.counter, + * CLOCK_GetFreq(kCLOCK_BusClk)); + * @endcode + * @param target_us Time for rx timeout unit us. + * @param rxTimeoutPrescaler The prescaler to be setted after function. + * @param rxTimeoutcounter The counter to be setted after function. + * @param srcClock_Hz The clockSrc for rx timeout. + */ +void USART_CalcTimeoutConfig(uint32_t target_us, + uint8_t *rxTimeoutPrescaler, + uint32_t *rxTimeoutcounter, + uint32_t srcClock_Hz); +/*! + * @brief Sets the USART instance RX timeout config. + * + * This function configures the USART RXFIFO timeout config. This function is used to config + * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init. + * + * @param base USART peripheral base address. + * @param config pointer to receive timeout configuration structure. + */ +void USART_SetRxTimeoutConfig(USART_Type *base, const usart_rx_timeout_config *config); +#endif +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * @param base USART peripheral base address. + * @param baudRate_Bps USART baudrate to be set.. + * @param enableMode32k true is 32k mode, false is normal mode. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base USART peripheral base address. + * @param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable); + +/*! + * @brief Set the USART slave address. + * + * This function configures the address for USART module that works as slave in 9-bit data mode. When the address + * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is + * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This + * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. + * To un-address a slave, just send an address frame with unmatched address. + * + * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) +{ + /* Configure match address. */ + base->ADDR = (uint32_t)address; +} + +/*! + * @brief Enable the USART match address feature. + * + * @param base USART peripheral base address. + * @param match true to enable match address, false to disable. + */ +static inline void USART_EnableMatchAddress(USART_Type *base, bool match) +{ + /* Configure match address enable bit. */ + if (match) + { + base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + else + { + base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return (base->FIFOSTAT & 0xFF0000FFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags. + * The mask is a logical OR of enumeration members. See @ref kUSART_AllClearFlags. + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllClearFlags; + /* Clear the clearable status in STAT register. */ + base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENSET = mask & 0xF00000FUL; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENCLR = mask & 0xFUL; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + uint32_t globalMask = DisableGlobalIRQ(); + + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } + + EnableGlobalIRQ(globalMask); +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + uint32_t globalMask = DisableGlobalIRQ(); + + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } + + EnableGlobalIRQ(globalMask); +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} + +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); +} +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return (uint8_t)base->FIFORD; +} + +/*! + * @brief Gets the rx FIFO data count. + * + * @param base USART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t USART_GetRxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base USART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t USART_GetTxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); +} + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_USART_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.c b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.c new file mode 100644 index 0000000000..15b4714d3a --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.c @@ -0,0 +1,691 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_iap.h" +#include "fsl_iap_ffr.h" +#include "fsl_iap_kbp.h" +#include "fsl_iap_skboot_authenticate.h" +#include "fsl_device_registers.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iap1" +#endif + +#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ + defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) + +#else +#error "No valid CPU defined!" + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t get_cfpa_higher_version(flash_config_t *config); + +/*! + * @name flash and ffr Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*programCommand)(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + status_t (*verifyProgramCommand)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); +} function_command_option_t; + +/* + *!@brief Structure of version property. + * + *!@ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint32_t bugfix : 8; /*!< bugfix version [7:0] */ + uint32_t minor : 8; /*!< minor version [15:8] */ + uint32_t major : 8; /*!< major version [23:16] */ + uint32_t name : 8; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers. */ +#if defined(__cplusplus) + StandardVersion() : version(0) + { + } + StandardVersion(uint32_t version) : version(version) + { + } +#endif +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version1FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + uint32_t reserved[3]; /*! Reserved for future use */ + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version1_flash_driver_interface_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version0FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version0_flash_driver_interface_t; + +typedef union flashDriverInterface +{ + const version1_flash_driver_interface_t *version1FlashDriver; + const version0_flash_driver_interface_t *version0FlashDriver; +} flash_driver_interface_t; + +/*! @}*/ + +/*! + * @name Bootloader API and image authentication Structure + * @{ + */ + +/*! @brief Interface for Bootloader API functions. */ +typedef struct _kb_interface +{ + /*!< Initialize the API. */ + status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); + status_t (*kb_deinit_function)(kb_session_ref_t *session); + status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); +} kb_interface_t; + +//! @brief Interface for image authentication API +typedef struct _skboot_authenticate_interface +{ + skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + void (*skboot_hashcrypt_irq_handler)(void); +} skboot_authenticate_interface_t; +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ + standard_version_t bootloader_version; /*!< Bootloader version number. */ + const char *copyright; /*!< Copyright string. */ + const uint32_t reserved0; /*!< Do NOT use. */ + flash_driver_interface_t flashDriver; + const kb_interface_t *kbApi; /*!< Bootloader API. */ + const uint32_t reserved1[4]; /*!< Do NOT use. */ + const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ +} bootloader_tree_t; + +/******************************************************************************* + * Prototype + ******************************************************************************/ +static uint32_t get_rom_api_version(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! Get pointer to flash driver API table in ROM. */ +#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver +#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver +#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) +#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) +#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t get_rom_api_version(void) +{ + if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) + { + return 1u; + } + else + { + return 0u; + } +} + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + status_t status; + /* Initialize the clock to 96MHz */ + config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; + if (get_rom_api_version() == 1u) + { + status = VERSION1_FLASH_API_TREE->flash_init(config); + } + else + { + status = VERSION0_FLASH_API_TREE->flash_init(config); + } + + if (config->PFlashTotalSize == 0xA0000U) + { + config->PFlashTotalSize -= 17U * config->PFlashPageSize; + } + + return status; +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + uint32_t core_frequency = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + /* Flash ERASE operations must be performed with a system clock below or equal to 100 MHz.*/ + if (core_frequency > 100000000U) + { + return (status_t)kStatus_FLASH_EraseFrequencyError; + } + + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); + } + else + { + return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes) +{ + uint32_t core_frequency = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + /* Flash PROGRAM operations must be performed with a system clock below or equal to 100 MHz.*/ + if (core_frequency > 100000000U) + { + return (status_t)kStatus_FLASH_ProgramFrequencyError; + } + + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ + return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + if (get_rom_api_version() == 0u) + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } + else + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) + { + runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; + } + else + { + runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; + } + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ + return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); +} +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +static status_t get_cfpa_higher_version(flash_config_t *config) +{ + uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; + uint32_t versionPing = 0U; + uint32_t versionPong = 0U; + + /* Get the CFPA ping page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 1U; + status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPing = pageData[1]; + + /* Get the CFPA pong page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 2U; + status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPong = pageData[1]; + + /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ + if (versionPing > versionPong) + { + config->ffrConfig.cfpaPageVersion = versionPing; + config->ffrConfig.cfpaPageOffset = 1U; + } + else + { + config->ffrConfig.cfpaPageVersion = versionPong; + config->ffrConfig.cfpaPageOffset = 2U; + } + return (int32_t)kStatus_FLASH_Success; +} + +/*! + * Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + status_t status; + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + status = VERSION0_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + status = VERSION1_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } +} + +/*! + * Enable firewall for all flash banks. + */ +status_t FFR_Lock_All(flash_config_t *config) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_lock_all(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_lock_all(config); + } +} + +/*! + * APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } +} + +/*! + * See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } +} + +/*! + * APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } +} + +/*! + * This routine writes the 3 pages allocated for Key store data, + * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } +} + +/*! + * APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } +} + +/*! + * APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } +} + +/******************************************************************************** + * Bootloader API + *******************************************************************************/ +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); +} + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the @a context parameter can be reused for another operation + * by calling rom_init() again. + */ +status_t kb_deinit(kb_session_ref_t *session) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); +} + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param context Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success The operation has completed successfully. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); +} + +/******************************************************************************** + * Image authentication API + *******************************************************************************/ + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, + isSignVerified); +} + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); +} + +/******************************************************************************** + * runBootloader API + *******************************************************************************/ +void BOOTLOADER_UserEntry(void *arg) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->runBootloader(arg); +} +/******************************************************************************** + * EOF + *******************************************************************************/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.h b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.h new file mode 100644 index 0000000000..f6c49c48af --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap.h @@ -0,0 +1,569 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_IAP_H_ +#define FSL_IAP_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ +}; + +/*! @} */ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Flash IP Type. */ +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) +#endif +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) +#endif + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ + kStatus_FLASH_EraseFrequencyError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x2A), /*!< Core frequency is over 100MHZ. */ + kStatus_FLASH_ProgramFrequencyError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x2B), /*!< Core frequency is over 100MHZ. */ + +}; +/*! @} */ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*! @} */ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1, /*! ECC is off */ +}; + +/* set flash Controller timing before flash init */ +enum _flash_freq_tag +{ + kSysToFlashFreq_lowInMHz = 12u, + kSysToFlashFreq_defaultInMHz = 96u, +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; +} flash_config_t; + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | +| Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | +*/ + +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! @} */ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be 512bytes-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the appropriate number of flash sectors based on the desired + * start address and length were erased successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! @} */ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * 512bytes-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully + * into flash based on desired start address and length. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + +/*! @} */ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. need be 512bytes-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the desired data have been successfully programed into specified FLASH region. + * + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*! @} */ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure + */ +void BOOTLOADER_UserEntry(void *arg); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* __FLASH_FLASH_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_ffr.h b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_ffr.h new file mode 100644 index 0000000000..74b1e361fc --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_ffr.h @@ -0,0 +1,388 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_IAP_FFR_H_ +#define FSL_IAP_FFR_H_ + +#include "fsl_iap.h" + +/*! + * @addtogroup flash_ifr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash IFR version + * @{ + */ +/*! @brief Flash IFR driver version for SDK*/ +#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +/*! @} */ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) + +/*! @brief flash ffr page offset. */ +enum _flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ + kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ + + kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ + + kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ +}; + +/*! @brief flash ffr page number. */ +enum _flash_ffr_page_num +{ + kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ + kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ + kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ + + kFfrPageNum_CMPA_Cfg = 1, + kFfrPageNum_CMPA_Key = 3, + kFfrPageNum_NMPA_Romcp = 2, + + kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, + kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), +}; + +enum _flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1192u, +}; + +typedef enum _cfpa_cfg_cmpa_prog_process +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct _cfpa_cfg_iv_code +{ + uint32_t keycodeHeader; + uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; +} cfpa_cfg_iv_code_t; + +typedef struct _cfpa_cfg_info +{ + uint32_t header; /*!< [0x000-0x003] */ + uint32_t version; /*!< [0x004-0x007 */ + uint32_t secureFwVersion; /*!< [0x008-0x00b */ + uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ + uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ + uint8_t reserved0[4]; /*!< [0x014-0x017] */ + uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ + uint32_t vendorUsage; /*!< [0x01c-0x01f] */ + uint32_t dcfgNsPin; /*!< [0x020-0x013] */ + uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ + uint32_t enableFaMode; /*!< [0x028-0x02b] */ + uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ + cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ + uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +typedef struct _cmpa_cfg_info +{ + uint32_t bootCfg; /*!< [0x000-0x003] */ + uint32_t spiFlashCfg; /*!< [0x004-0x007] */ + struct + { + uint16_t vid; + uint16_t pid; + } usbId; /*!< [0x008-0x00b] */ + uint32_t sdioCfg; /*!< [0x00c-0x00f] */ + uint32_t dcfgPin; /*!< [0x010-0x013] */ + uint32_t dcfgDflt; /*!< [0x014-0x017] */ + uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ + uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ + uint32_t princeBaseAddr; /*!< [0x020-0x023] */ + uint32_t princeSr[3]; /*!< [0x024-0x02f] */ + uint8_t reserved0[32]; /*!< [0x030-0x04f] */ + uint32_t rotkh[8]; /*!< [0x050-0x06f] */ + uint8_t reserved1[368]; /*!< [0x070-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cmpa_cfg_info_t; + +typedef struct _cmpa_key_store_header +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +typedef struct _nmpa_cfg_info +{ + uint16_t fro32kCfg; /*!< [0x000-0x001] */ + uint8_t reserved0[6]; /*!< [0x002-0x007] */ + uint8_t sysCfg; /*!< [0x008-0x008] */ + uint8_t reserved1[7]; /*!< [0x009-0x00f] */ + struct + { + uint32_t data; + uint32_t reserved[3]; + } GpoInitData[3]; /*!< [0x010-0x03f] */ + uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ + uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ + uint32_t deviceType; /*!< [0x060-0x063] */ + uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ + uint32_t finalTestDate; /*!< [0x068-0x06b] */ + uint32_t finalTestTime; /*!< [0x06c-0x06f] */ + uint32_t uuid[4]; /*!< [0x070-0x07f] */ + uint8_t reserved2[32]; /*!< [0x080-0x09f] */ + uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ + uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ + uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ + uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ + uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ + uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ + uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ + uint32_t bod; /*!< [0x0f0-0x0f3] */ + uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ + uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ + uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ + uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ + uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ +} nmpa_cfg_info_t; + +typedef struct _ffr_key_store +{ + uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum _ffr_key_type +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum _ffr_bank_type +{ + kFFR_BankTypeBank0_NMPA = 0x00U, + kFFR_BankTypeBank1_CMPA = 0x01U, + kFFR_BankTypeBank2_CFPA = 0x02U +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Lock_All(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data, + * + * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + * 2.Optional routines to set individual data members (activation code, key codes etc) to construct + * the key store structure in RAM before committing it to IFR/FFR. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. + * that will be written to 'customer factory page'. + * + * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + * 3. keyIndex specifies which key code is read. + */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /*! FSL_FLASH_FFR_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_kbp.h b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_kbp.h new file mode 100644 index 0000000000..d2ab6f814e --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_kbp.h @@ -0,0 +1,245 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_IAP_KBP_H_ +#define FSL_IAP_KBP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kb_driver + * @{ + */ +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief ROM API status group number */ +#define kStatusGroup_RomApi (108U) + +/*! @brief ROM API status codes. */ +enum +{ + kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ + kStatus_RomApiNeedMoreData = + MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ + kStatus_RomApiBufferSizeNotEnough = + MAKE_STATUS(kStatusGroup_RomApi, + 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ + kStatus_RomApiInvalidBuffer = + MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ +}; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum _kb_operation +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ + kRomLoadImage = 2, /*!< Load SB file.*/ + kRomOperationCount = 3, +} kb_operation_t; + +/*! + * @brief Security constraint flags, Security profile flags. + */ +enum _kb_security_profile +{ + kKbootMinRSA4096 = (1 << 16), +}; + +/*! + * @brief Memory region definition. + */ +typedef struct _kb_region +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief User-provided options passed into kb_init(). + * + * The buffer field is a pointer to memory provided by the caller for use by + * Kboot during execution of the operation. Minimum size is the size of each + * certificate in the chain plus 432 bytes additional per certificate. + * + * The profile field is a mask that specifies which features are required in + * the SB file or image being processed. This includes the minimum AES and RSA + * key sizes. See the _kb_security_profile enum for profile mask constants. + * The image being loaded or authenticated must match the profile or an error will + * be returned. + * + * minBuildNumber is an optional field that can be used to prevent version + * rollback. The API will check the build number of the image, and if it is less + * than minBuildNumber will fail with an error. + * + * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes + * value at the beginning of a signed image. It should be set to the length of + * the SB file. If verifying an image in flash, it can be set to the internal + * flash size or a large number like 0x10000000. + * + * userRHK can optionally be used by the user to override the RHK in IFR. If + * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of + * the root certificate's RSA public key. + * + * The regions field points to an array of memory regions that the SB file being + * loaded is allowed to access. If regions is NULL, then all memory is + * accessible by the SB file. This feature is required to prevent a malicious + * image from erasing good code or RAM contents while it is being loaded, only + * for us to find that the image is inauthentic when we hit the end of the + * section. + * + * overrideSBBootSectionID lets the caller override the default section of the + * SB file that is processed during a kKbootLoadSB operation. By default, + * the section specified in the firstBootableSectionID field of the SB header + * is loaded. If overrideSBBootSectionID is non-zero, then the section with + * the given ID will be loaded instead. + * + * The userSBKEK field lets a user provide their own AES-256 key for unwrapping + * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point + * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. + * After kb_init() returns, the caller should zero out the data pointed to by + * userSBKEK, as the API will have installed the key in the CAU3. + */ + +typedef struct _kb_load_sb +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct _kb_authenticate +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct _kb_options +{ + uint32_t version; /*!< Should be set to kKbootApiVersion.*/ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! + * @brief Interface to memory operations for one region of memory. + */ +typedef struct _memory_region_interface +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +/*! + * @brief Structure of a memory map entry. + */ +typedef struct _memory_map_entry +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +typedef struct _kb_opaque_session_ref +{ + kb_options_t context; + bool cau3Initialized; + memory_map_entry_t *memoryMap; +} kb_session_ref_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + * + * @retval #kStatus_Success API was executed successfully. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the + * operation. + * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. + * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. + * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the + * keystore + * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the context parameter can be reused for another operation + * by calling rom_init() again. + * + * @retval #kStatus_Success API was executed successfully + */ +status_t kb_deinit(kb_session_ref_t *session); + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param session Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. + * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for + * use by Kboot during execution of the operation. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* FSL_IAP_KBP_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_skboot_authenticate.h b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_skboot_authenticate.h new file mode 100644 index 0000000000..8098a2653c --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/iap1/fsl_iap_skboot_authenticate.h @@ -0,0 +1,77 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_IAP_SKBOOT_AUTHENTICATE_H_ +#define FSL_IAP_SKBOOT_AUTHENTICATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup skboot_authenticate + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief SKBOOT return status*/ +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ + kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = + 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusFail = + 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ +} skboot_status_t; + +/*! @brief Secure bool flag*/ +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ + kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ + kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ + kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ + kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ +} secure_bool_t; + +/******************************************************************************* + * Externs + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.c b/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.c new file mode 100644 index 0000000000..be100d5e9e --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ +/*! + * @brief Enable GPIO port clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ + GPIO_EnablePortClock(base, port); + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + GPIO_EnablePortClock(base, port); + + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1UL << pin; +#else + base->DIR[port] &= ~(1UL << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1UL << pin); + } + else + { + base->SET[port] = (1UL << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1UL << pin; +#else + base->DIR[port] |= 1UL << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); + + base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if ((uint32_t)kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1UL << pin; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1UL << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.h b/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.h new file mode 100644 index 0000000000..4485603af3 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPC GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) +/*! @} */ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*! @{ */ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*! @} */ + +/*! @name GPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*! @} */ +/*! @name GPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*! @} */ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*! @} */ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*! @} */ +/*! @name GPIO Mask Operations */ +/*! @{ */ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_iocon/fsl_iocon.h b/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_iocon/fsl_iocon.h new file mode 100644 index 0000000000..db8f30bf6e --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/lpc_iocon/fsl_iocon.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_IOCON_H_ +#define FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*! @{ */ +/*! @brief IOCON driver version. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @} */ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint8_t port; /* Pin port */ + uint8_t pin; /* Pin number */ + uint8_t ionumber; /* IO number */ + uint16_t modefunc; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_IOCON_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.c b/platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.c new file mode 100644 index 0000000000..b21864be95 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2022-2023 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_assert.h" +#include "fsl_debug_console.h" + +/* User can implement its own asser handler (dump logs, registers, etc) by reimplementing the function fsl_assert_hook() */ +__attribute__ ((weak)) int fsl_assert_hook(const char *failedExpr, const char *file, int line) +{ + (void)failedExpr; + (void)file; + (void)line; + + return 0; +} + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#else + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#endif + + (void)fsl_assert_hook(failedExpr, file, line); + + for (;;) + { +#ifdef CoreDebug_DHCSR_C_DEBUGEN_Msk + if (1U == (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)) +#endif /* CoreDebug_DHCSR_C_DEBUGEN_Msk */ + { + __BKPT(0); + } + } +} +#elif (defined(__GNUC__)) +#if defined(__REDLIB__) +void __assertion_failed(char *failedExpr) +{ + const char *file = NULL; + int line = -1; + + (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr); + + (void)fsl_assert_hook(failedExpr, file, line); + + for (;;) + { +#ifdef CoreDebug_DHCSR_C_DEBUGEN_Msk + if (1U == (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)) +#endif /* CoreDebug_DHCSR_C_DEBUGEN_Msk */ + { + __BKPT(0); + } + } +} +#else +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, + func); + + (void)fsl_assert_hook(failedExpr, file, line); + + for (;;) + { +#ifdef CoreDebug_DHCSR_C_DEBUGEN_Msk + if (1U == (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)) +#endif /* CoreDebug_DHCSR_C_DEBUGEN_Msk */ + { + __BKPT(0); + } + } +} +#endif /* defined(__REDLIB__) */ +#else /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ + +#if (defined(__DSC__) && defined(__CW__)) + +void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line) +{ + PRINTF("\r\nASSERT ERROR\r\n"); + PRINTF(" File : %s\r\n", file); + PRINTF(" Function : %s\r\n", func); /*compiler not support func name yet*/ + PRINTF(" Line : %u\r\n", (uint32_t)line); + PRINTF(" failedExpr: %s\r\n", failedExpr); +#ifdef CoreDebug_DHCSR_C_DEBUGEN_Msk + if (1U == (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)) +#endif /* CoreDebug_DHCSR_C_DEBUGEN_Msk */ + { + asm(DEBUGHLT); + } +} + +#endif /* (defined(__DSC__) && defined (__CW__)) */ + +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.h b/platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.h new file mode 100644 index 0000000000..ab19736d43 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/assert/fsl_assert.h @@ -0,0 +1,50 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ASSERT_H_ +#define _FSL_ASSERT_H_ + +/*! + * @addtogroup assert + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + + +/*! + * @brief Assert hook that can be redifined + * + * @param failedExpr Expression that caused the assert + * @param file File where the exception occured. + * @param line Line on the file where the exception occured. + */ +int fsl_assert_hook(const char *failedExpr, const char *file, int line); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ + diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c new file mode 100644 index 0000000000..1efdbbbbdf --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c @@ -0,0 +1,1417 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif + +#ifdef SDK_OS_FREE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#endif + +#include "fsl_debug_console_conf.h" +#include "fsl_str.h" + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +#include "fsl_debug_console.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +#define DEBUG_CONSOLE_FUNCTION_PREFIX +#else +#define DEBUG_CONSOLE_FUNCTION_PREFIX static +#endif + +/*! @brief character backspace ASCII value */ +#define DEBUG_CONSOLE_BACKSPACE 127U + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +static SemaphoreHandle_t s_debugConsoleReadSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadSemaphoreStatic; +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadWaitSemaphoreStatic; +#endif +#endif + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static volatile bool s_debugConsoleReadWaitSemaphore; +#endif + +#else + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +/* semaphore definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +/* mutex semaphore */ +/* clang-format off */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex, stack) ((mutex) = xSemaphoreCreateMutexStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) +#endif +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \ + do \ + { \ + if(NULL != (mutex)) \ + { \ + vSemaphoreDelete(mutex); \ + (mutex) = NULL; \ + } \ + } while(false) + +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreGive(mutex); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ +} + +/* Binary semaphore */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary,stack) ((binary) = xSemaphoreCreateBinaryStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) +#endif +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \ + do \ + { \ + if(NULL != (binary)) \ + { \ + vSemaphoreDelete((binary)); \ + (binary) = NULL; \ + } \ + } while(false) +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY)) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL)) + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) + +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) (void)(mutex) +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) + +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) (void)(binary) +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) (void)(binary) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + { \ + while (!(binary)) \ + { \ + } \ + (binary) = false; \ + } +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \ + do \ + { \ + (binary) = true; \ + } while(false) +#else +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (void)(binary) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (void)(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +/* clang-format on */ + +/* add other implementation here + *such as : + * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) + */ + +#else + +#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* receive state structure */ +typedef struct _debug_console_write_ring_buffer +{ + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; + uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; +} debug_console_write_ring_buffer_t; +#endif + +typedef struct _debug_console_state_struct +{ + serial_handle_t serialHandle; /*!< serial manager handle */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + SERIAL_MANAGER_HANDLE_DEFINE(serialHandleBuffer); + debug_console_write_ring_buffer_t writeRingBuffer; + uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer2); + SERIAL_MANAGER_READ_HANDLE_DEFINE(serialReadHandleBuffer); +#else + SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(serialHandleBuffer); + SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(serialReadHandleBuffer); +#endif +} debug_console_state_struct_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console state information. */ +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0)) +AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState); +#else +static debug_console_state_struct_t s_debugConsoleState; +#endif +serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch); +int DbgConsole_SendData(uint8_t *ch, size_t size); +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); +int DbgConsole_ReadLine(uint8_t *buf, size_t size); +int DbgConsole_ReadCharacter(uint8_t *ch); + +#if ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +static status_t DbgConsole_SerialManagerPerformTransfer(debug_console_state_struct_t *ioState) +{ + serial_manager_status_t ret = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t startIndex; + uint32_t regPrimask; + + regPrimask = DisableGlobalIRQ(); + if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) + { + if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) + { + sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; + startIndex = ioState->writeRingBuffer.ringTail; + } + else + { + sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; + startIndex = ioState->writeRingBuffer.ringTail; + if (0U != ioState->writeRingBuffer.ringHead) + { + ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer2[0]), + &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength); + sendDataLength = ioState->writeRingBuffer.ringHead - 0U; + startIndex = 0U; + } + } + ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), + &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength); + } + EnableGlobalIRQ(regPrimask); + return (status_t)ret; +} + +static void DbgConsole_SerialManagerTxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + (void)DbgConsole_SerialManagerPerformTransfer(ioState); + } + else if (kStatus_SerialManager_Canceled == status) + { + ioState->writeRingBuffer.ringTail = 0U; + ioState->writeRingBuffer.ringHead = 0U; + } + else + { + /*MISRA rule 16.4*/ + } +} + +static void DbgConsole_SerialManagerTx2Callback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + /* Empty block*/ + } + else if (kStatus_SerialManager_Canceled == status) + { + /* Empty block*/ + } + else + { + /*MISRA rule 16.4*/ + } +} + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +static void DbgConsole_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + if (kStatus_SerialManager_Notify == status) + { + } + else if (kStatus_SerialManager_Success == status) + { + /* release s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); + } + else + { + /*MISRA rule 16.4*/ + } +} +#endif + +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + return (status_t)kStatus_Fail; +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + serial_manager_status_t status = kStatus_SerialManager_Error; + +/* recieve one char every time */ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + status = + SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + status = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + if (kStatus_SerialManager_Success != status) + { + status = (serial_manager_status_t)kStatus_Fail; + } + else + { + /* wait s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); + status = (serial_manager_status_t)kStatus_Success; + } + return (status_t)status; +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + +#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ + + return (status_t)kStatus_Fail; + +#endif /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (1 != DbgConsole_SendDataReliable(ch, 1U)) + { + return (status_t)kStatus_Fail; + } + } + + if ((!isGetChar) && (index != NULL)) + { + if (DEBUG_CONSOLE_BACKSPACE == *ch) + { + if ((*index >= 2)) + { + *index -= 2; + } + else + { + *index = 0; + } + } + } + + return (status_t)kStatus_Success; +} +#endif + +int DbgConsole_SendData(uint8_t *ch, size_t size) +{ + status_t status; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t sendDataLength; + int txBusy = 0; +#endif + assert(NULL != ch); + assert(0U != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + txBusy = 1; + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + if (sendDataLength < size) + { + EnableGlobalIRQ(regPrimask); + return -1; + } + for (int i = 0; i < (int)size; i++) + { + s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; + if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) + { + s_debugConsoleState.writeRingBuffer.ringHead = 0U; + } + } + + status = (status_t)kStatus_SerialManager_Success; + + if (txBusy == 0) + { + status = DbgConsole_SerialManagerPerformTransfer(&s_debugConsoleState); + } + EnableGlobalIRQ(regPrimask); +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); +#endif + return (((status_t)kStatus_Success == status) ? (int)size : -1); +} + +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + serial_manager_status_t status = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t totalLength = size; + int sentLength; +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + serial_manager_status_t status; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + assert(NULL != ch); + + if (0U == size) + { + return 0; + } + + if (NULL == g_serialHandle) + { + return 0; + } + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + do + { + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + + if ((sendDataLength > 0U) && ((sendDataLength >= totalLength) || + (totalLength >= (s_debugConsoleState.writeRingBuffer.ringBufferSize - 1U)))) + { + if (sendDataLength > totalLength) + { + sendDataLength = totalLength; + } + + sentLength = DbgConsole_SendData(&ch[size - totalLength], (size_t)sendDataLength); + if (sentLength > 0) + { + totalLength = totalLength - (uint32_t)sentLength; + } + } + EnableGlobalIRQ(regPrimask); + + if (totalLength != 0U) + { + status = (serial_manager_status_t)DbgConsole_Flush(); + if (kStatus_SerialManager_Success != status) + { + break; + } + } + } while (totalLength != 0U); + return ((int)size - (int)totalLength); +#else /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + return DbgConsole_SendData(ch, size); +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + status = + SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); + return ((kStatus_SerialManager_Success == status) ? (int)size : -1); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +} + +int DbgConsole_ReadLine(uint8_t *buf, size_t size) +{ + int i = 0; + + assert(buf != NULL); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + do + { + /* recieve one char every time */ + if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) + { + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + i = -1; + break; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) + { + /* End of Line. */ + if (0 == i) + { + buf[i] = (uint8_t)'\0'; + continue; + } + else + { + break; + } + } + i++; + } while (i < (int)size); + + /* get char should not add '\0'*/ + if (i == (int)size) + { + buf[i] = (uint8_t)'\0'; + } + else + { + buf[i + 1] = (uint8_t)'\0'; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return i; +} + +int DbgConsole_ReadCharacter(uint8_t *ch) +{ + int ret; + + assert(ch); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + /* read one character */ + if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return ret; +} + +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (size_t)(*indicator)); + *indicator = 0; + } + + buf[*indicator] = dbgVal; + (*indicator)++; + } +} +#endif + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) +#include "board.h" +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG_UART_INSTANCE, + .clockRate = BOARD_DEBUG_UART_CLK_FREQ, + .baudRate = BOARD_DEBUG_UART_BAUDRATE, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1U, + .enableTx = 1U, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif +}; +#endif +#endif +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + serial_manager_config_t serialConfig = {0}; + serial_manager_status_t status = kStatus_SerialManager_Success; + +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U)) +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serial_port_uart_config_t uartConfig = { + .instance = instance, + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1, + .enableTx = 1, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif + }; +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serial_port_usb_cdc_config_t usbCdcConfig = { + .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serial_port_swo_config_t swoConfig = { + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .port = instance, + .protocol = kSerialManager_SwoProtocolNrz, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serial_port_virtual_config_t serialPortVirtualConfig = { + .controllerIndex = (serial_port_virtual_controller_index_t)instance, + }; +#endif + + serialConfig.type = device; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; + serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; + serialConfig.blockType = kSerialManager_NonBlocking; +#else + serialConfig.blockType = kSerialManager_Blocking; +#endif + + if (kSerialPort_Uart == device) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) + serialConfig.portConfig = (void *)&uartConfig; +#else + serialConfig.portConfig = &uartConfig; +#endif +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_UsbCdc == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serialConfig.portConfig = &usbCdcConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Swo == device) + { +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serialConfig.portConfig = &swoConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Virtual == device) + { +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serialConfig.portConfig = &serialPortVirtualConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else + { + status = kStatus_SerialManager_Error; + } + + if (kStatus_SerialManager_Error != status) + { + (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; +#endif + + s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; + status = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + + assert(kStatus_SerialManager_Success == status); + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +#if configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore, &s_debugConsoleReadSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) && configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore, &s_debugConsoleReadWaitSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#endif + + { + status = + SerialManager_OpenWriteHandle(s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); + status = SerialManager_OpenWriteHandle( + s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0])); + assert(kStatus_SerialManager_Success == status); + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0]), + DbgConsole_SerialManagerTx2Callback, &s_debugConsoleState); +#endif + } + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + status = + SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle, + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallRxCallback( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), + DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); +#endif + } +#endif + + g_serialHandle = s_debugConsoleState.serialHandle; + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_EnterLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_EnterLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_ExitLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_ExitLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + { + if (s_debugConsoleState.serialHandle != NULL) + { +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0])); +#endif + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + } + } +#endif + if (NULL != s_debugConsoleState.serialHandle) + { + if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle)) + { + s_debugConsoleState.serialHandle = NULL; + g_serialHandle = NULL; + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return (status_t)kStatus_Success; +} +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE > DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN))) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + return (status_t)kStatus_Fail; + } + +#else + + while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + if (0U == IS_RUNNING_IN_ISR()) + { + if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) + { + vTaskDelay(1); + } + } + else + { + return (status_t)kStatus_Fail; + } +#endif + } + +#endif + +#endif + return (status_t)kStatus_Success; +} +#endif + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_Vprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg) +{ + int logLength = 0, result = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL != g_serialHandle) + { + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback); + /* print log */ + result = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); + } + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_s, ...) +{ + va_list ap; + int formatResult; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; + + /* scanf log */ + (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, fmt_s); + /* format scanf log */ + formatResult = StrFormatScanf(scanfBuf, fmt_s, ap); + + va_end(ap); + + return formatResult; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingPrintf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_BlockingVprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg) +{ + status_t status; + int logLength = 0, result = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL == g_serialHandle) + { + return 0; + } + + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); +#endif + /* print log */ + status = + (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + (uint8_t *)printBuf, (size_t)logLength); + result = (((status_t)kStatus_Success == status) ? (int)logLength : -1); + + return result; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + uint32_t length = 0; + status_t status = (status_t)kStatus_Fail; + + assert(ch); + + if (NULL == g_serialHandle) + { + return kStatus_Fail; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + if (kStatus_SerialManager_Success == + SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, + &length)) + { + if (length != 0U) + { +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); +#endif + status = (status_t)kStatus_Success; + } + } + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + return status; +#else + return (status_t)kStatus_Fail; +#endif +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + int ret = -1; + uint8_t ch = 0U; + + /* Get char */ + if (DbgConsole_ReadCharacter(&ch) > 0) + { + ret = (int)ch; + } + + return ret; +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size); +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t ret; + if (NULL == buffer) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + ret = 0U; + } + else if ((handle != 1) && (handle != 2)) + { + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. + */ + ret = (size_t)-1; + } + else + { + /* Send data. */ + uint8_t buff[512]; + (void)memcpy(buff, buffer, size); + (void)DbgConsole_SendDataReliable((uint8_t *)buff, size); + + ret = size; + } + return ret; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size); +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (0 != handle) + { + actualSize = -1; + } + else + { + /* Receive data.*/ + for (; size > 0U; size--) + { + (void)DbgConsole_ReadCharacter(&ch); + if (0U == ch) + { + break; + } + + *buffer++ = ch; + actualSize++; + } + } + return (size_t)actualSize; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&ch); + + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + for (; size > 0; size--) + { + if (DbgConsole_ReadCharacter(&ch) < 0) + { + break; + } + + *buffer++ = (char)ch; + actualSize++; + + if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) + { + break; + } + } + + return (actualSize > 0) ? actualSize : -1; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h new file mode 100644 index 0000000000..374148ff85 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support + * to be redefined in project setting. + */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#else +#include +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +static inline int DbgConsole_Disabled(void) +{ + return -1; +} +#define PRINTF(...) DbgConsole_Disabled() +#define SCANF(...) DbgConsole_Disabled() +#define PUTCHAR(...) DbgConsole_Disabled() +#define GETCHAR() DbgConsole_Disabled() +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ + */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module.If the device is kSerialPort_Uart, + * the instance is UART peripheral instance. The UART hardware peripheral + * type is determined by UART adapter. For example, if the instance is 1, + * if the lpuart_adapter.c is added to the current project, the UART periheral + * is LPUART1. + * If the uart_adapter.c is added to the current project, the UART periheral + * is UART1. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart, + * @arg kSerialPort_UsbCdc + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_EnterLowpower(void); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_ExitLowpower(void); + +#else +/*! + * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Init(uint8_t instance, + uint32_t baudRate, + serial_port_type_t device, + uint32_t clkSrcFreq) +{ + (void)instance; + (void)baudRate; + (void)device; + (void)clkSrcFreq; + return (status_t)kStatus_Fail; +} +/*! + * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Deinit(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_EnterLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_ExitLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @param fmt_s Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_s, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingPrintf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Debug console flush. + * + * Call this function to wait the tx buffer empty. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provides a API which will not block current task, if character is + * available return it, otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h new file mode 100644 index 0000000000..fd235b1e54 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h @@ -0,0 +1,160 @@ +/* + * Copyright 2017 - 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +#include "fsl_common.h" + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef SDK_OS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* SDK_OS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c new file mode 100644 index 0000000000..000fafe19b --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c @@ -0,0 +1,1711 @@ +/* + * Copyright 2017, 2020, 2022-2023 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include /* MISRA C-2012 Rule 22.9 */ +#include "fsl_str.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#ifndef MAX_FIELD_WIDTH +#define MAX_FIELD_WIDTH 99U +#endif + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned long long int +#define STR_FORMAT_PRINTF_IVAL_TYPE long long int +#else +#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned int +#define STR_FORMAT_PRINTF_IVAL_TYPE int +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps); + +#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U)) +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); + +#endif /* PRINTF_FLOAT_ENABLE */ + +/*************Code for process formatted data*******************************/ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +static uint8_t PrintGetSignChar(long long int ival, uint32_t flags_used, char *schar) +{ + uint8_t len = 1U; + if (ival < 0) + { + *schar = '-'; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + *schar = '+'; + } + else if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + *schar = ' '; + } + else + { + *schar = '\0'; + len = 0U; + } + } + return len; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint32_t PrintGetWidth(const char **p, va_list *ap) +{ + uint32_t field_width = 0; + uint8_t done = 0U; + char c; + + while (0U == done) + { + c = *(++(*p)); + if ((c >= '0') && (c <= '9')) + { + (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0'); + } +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + else if (c == '*') + { + (field_width) = (uint32_t)va_arg(*ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --(*p); + done = 1U; + } + } + return field_width; +} + +static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width) +{ + const char *p = *s; + uint32_t precision_width = 6U; + uint8_t done = 0U; + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (NULL != valid_precision_width) + { + *valid_precision_width = false; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0U; + done = 0U; + while (0U == done) + { + char c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0'); +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + else if (c == '*') + { + precision_width = (uint32_t)va_arg(*ap, uint32_t); + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = 1U; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } + *s = p; + return precision_width; +} + +static uint32_t PrintIsobpu(const char c) +{ + uint32_t ret = 0U; + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsdi(const char c) +{ + uint32_t ret = 0U; + if ((c == 'd') || (c == 'i')) + { + ret = 1U; + } + return ret; +} + +static void PrintOutputdifFobpu(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + char schar, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + /* Do the ZERO pad. */ + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + } + } + /* The string was built in reverse order, now display in correct order. */ + if ('\0' != schar) + { + cb(buf, count, schar, 1); + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static void PrintOutputxX(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + bool use_caps, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + uint8_t dschar = 0; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + vlen += 2U; + } + cb(buf, count, ' ', (int)field_width - (int)vlen); + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + } + } + + if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + vlen += 2U; + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static uint32_t PrintIsfF(const char c) +{ + uint32_t ret = 0U; + if ((c == 'f') || (c == 'F')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsxX(const char c) +{ + uint32_t ret = 0U; + if ((c == 'x') || (c == 'X')) + { + ret = 1U; + } + return ret; +} + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +static uint32_t PrintCheckFlags(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + bool done = false; + while (false == done) + { + switch (*++p) + { + case '-': + flags_used |= (uint32_t)kPRINTF_Minus; + break; + case '+': + flags_used |= (uint32_t)kPRINTF_Plus; + break; + case ' ': + flags_used |= (uint32_t)kPRINTF_Space; + break; + case '0': + flags_used |= (uint32_t)kPRINTF_Zero; + break; + case '#': + flags_used |= (uint32_t)kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } + *s = p; + return flags_used; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +/* + * Check for the length modifier. + */ +static uint32_t PrintGetLengthFlag(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + break; + case 'z': + if (sizeof(size_t) == sizeof(uint32_t)) + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + } + else if (sizeof(size_t) == (2U * sizeof(uint32_t))) + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + else if (sizeof(size_t) == sizeof(uint16_t)) + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + } + else + { + /* MISRA C-2012 Rule 15.7 */ + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } + *s = p; + return flags_used; +} +#else +static void PrintFilterLengthFlag(const char **s) +{ + const char *p = *s; + char strCh; + + do + { + strCh = *++p; + } while ((strCh == 'h') || (strCh == 'l')); + + *s = --p; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint8_t PrintGetRadixFromobpu(const char c) +{ + uint8_t radix; + + if (c == 'o') + { + radix = 8U; + } + else if (c == 'b') + { + radix = 2U; + } + else if (c == 'p') + { + radix = 16U; + } + else + { + radix = 10U; + } + return radix; +} + +static uint32_t ScanIsWhiteSpace(const char c) +{ + uint32_t ret = 0U; + if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + ret = 1U; + } + return ret; +} + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint32_t count = 0U; + char c; + + c = **s; + while (1U == ScanIsWhiteSpace(c)) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps) +{ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + long long int a; + long long int b; + long long int c; + + unsigned long long int ua; + unsigned long long int ub; + unsigned long long int uc; + unsigned long long int uc_param; +#else + int a; + int b; + int c; + + unsigned int ua; + unsigned int ub; + unsigned int uc; + unsigned int uc_param; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + +#if !(defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0u)) + neg = 0U; +#endif + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + a = 0; + b = 0; + c = 0; + ua = 0ULL; + ub = 0ULL; + uc = 0ULL; + uc_param = 0ULL; +#else + a = 0; + b = 0; + c = 0; + ua = 0U; + ub = 0U; + uc = 0U; + uc_param = 0U; +#endif /* PRINTF_ADVANCED_ENABLE */ + + (void)a; + (void)b; + (void)c; + (void)ua; + (void)ub; + (void)uc; + (void)uc_param; + (void)neg; + /* + * Fix MISRA issue: CID 15972928 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3) + * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump); + */ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != neg) + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + a = *(long long int *)nump; +#else + a = *(int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + b = (long long int)a / (long long int)radix; + c = (long long int)a - ((long long int)b * (long long int)radix); + if (c < 0) + { + uc = (unsigned long long int)c; + uc_param = ~uc; + c = (long long int)uc_param + 1 + (long long int)'0'; + } +#else + b = (int)a / (int)radix; + c = (int)a - ((int)b * (int)radix); + if (c < 0) + { + uc = (unsigned int)c; + uc_param = ~uc; + c = (int)uc_param + 1 + (int)'0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + (int)'0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + ua = *(unsigned long long int *)nump; +#else + ua = *(unsigned int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0U) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0U) + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + ub = (unsigned long long int)ua / (unsigned long long int)radix; + uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix); +#else + ub = ua / (unsigned int)radix; + uc = ua - (ub * (unsigned int)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10U) + { + uc = uc + (unsigned int)'0'; + } + else + { + uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U)) +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (0.0 == r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < (int32_t)precision_width; i++) + { + fractpart *= (double)radix; + } + if (r >= (double)0.0) + { + fa = fractpart + (double)0.5; + if (fa >= pow((double)10, (double)precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow((double)10, (double)precision_width)) + { + intpart--; + } + } + for (i = 0; i < (int32_t)precision_width; i++) + { + fb = fa / (double)radix; + dc = (fa - (double)(long long int)fb * (double)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + uc = ~uc; + c = (int32_t)uc; + c += (int32_t)1; + c += (int32_t)'0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + uc = ~uc; + c = (int32_t)uc; + c += (int32_t)1; + c += (int32_t)'0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +static void StrFormatExaminedi(uint32_t *flags_used, long long int *ival, va_list *ap) +#else +static void StrFormatExaminedi(int *ival, va_list *ap) +#endif +{ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != (*flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + *ival = (long long int)va_arg(*ap, long long int); + } + else if (0U != (*flags_used & (uint32_t)kPRINTF_LengthLongInt)) + { + *ival = (long long int)va_arg(*ap, long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + *ival = (STR_FORMAT_PRINTF_IVAL_TYPE)va_arg(*ap, int); + } +} + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +static void StrFormatExaminexX(uint32_t *flags_used, unsigned long long int *uval, va_list *ap) +#else +static void StrFormatExaminexX(unsigned int *uval, va_list *ap) +#endif +{ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongLongInt)) + { + *uval = (unsigned long long int)va_arg(*ap, unsigned long long int); + } + else if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongInt)) + { + *uval = (unsigned long long int)va_arg(*ap, unsigned long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + *uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(*ap, unsigned int); + } +} + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +static void StrFormatExamineobpu(uint32_t *flags_used, unsigned long long int *uval, va_list *ap) +#else +static void StrFormatExamineobpu(unsigned int *uval, va_list *ap) +#endif +{ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongLongInt)) + { + *uval = (unsigned long long int)va_arg(*ap, unsigned long long int); + } + else if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongInt)) + { + *uval = (unsigned long long int)va_arg(*ap, unsigned long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + *uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(*ap, unsigned int); + } +} +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +static int32_t ConvertPrecisionWidthToLength(bool valid_precision_width, uint32_t precision_width, char *sval) +#else +static int32_t ConvertPrecisionWidthToLength(char *sval) +#endif +{ + int32_t vlen = 0; +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (valid_precision_width) + { + vlen = (int)precision_width; + } + else + { + vlen = (int)strlen(sval); + } +#else + vlen = (int32_t)strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ + + return vlen; +} + +/*! + * brief This function outputs its parameters according to a formatted string. + * + * note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * param[in] fmt Format string for printf. + * param[in] ap Arguments to printf. + * param[in] buf pointer to the buffer + * param cb print callback function pointer + * + * return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + const char *p; + char c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + unsigned int radix = 0; + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + uint32_t flags_used; + char schar; + long long int ival; + unsigned long long int uval = 0; + bool valid_precision_width; +#else + int ival; + unsigned int uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U)) + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + p = fmt; + while (true) + { + if ('\0' == *p) + { + break; + } + c = *p; + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + p++; + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + /* First check for specification modifier flags. */ + flags_used = PrintCheckFlags(&p); +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = PrintGetWidth(&p, &ap); + + /* Next check for the width and precision field separator. */ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width); +#else + precision_width = PrintGetPrecision(&p, &ap, NULL); + (void)precision_width; +#endif + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + /* Check for the length modifier. */ + flags_used |= PrintGetLengthFlag(&p); +#else + /* Filter length modifier. */ + PrintFilterLengthFlag(&p); +#endif + + /* Now we're ready to examine the format. */ + c = *++p; + { + if (1U == PrintIsdi(c)) + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + StrFormatExaminedi(&flags_used, &ival, &ap); +#else + StrFormatExaminedi(&ival, &ap); +#endif + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&ival, 1, 10, use_caps); + vstrp = &vstr[vlen]; +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + vlen += (int)PrintGetSignChar(ival, flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsfF(c)) + { +#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U)) + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((long long int)-1) : ((long long int)fval)), + flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#endif + +#else + (void)va_arg(ap, double); +#endif /* PRINTF_FLOAT_ENABLE */ + } + else if (1U == PrintIsxX(c)) + { + if (c == 'x') + { + use_caps = false; + } +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + StrFormatExaminexX(&flags_used, &uval, &ap); +#else + StrFormatExaminexX(&uval, &ap); +#endif + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, 16, use_caps); + vstrp = &vstr[vlen]; +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + PrintOutputxX(flags_used, field_width, (unsigned int)vlen, use_caps, vstrp, cb, buf, &count); +#else + PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsobpu(c)) + { + if ('p' == c) + { + /* + * Fix MISRA issue: CID 17205581 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA C-2012 + * Rule 11.6) 1.misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void * + * is cast to type uint32_t. + * + * Orignal code: uval = (STR_FORMAT_PRINTF_UVAL_TYPE)(uint32_t)va_arg(ap, void *); + */ + void *pval; + pval = (void *)va_arg(ap, void *); + (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *)); + } + else + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + StrFormatExamineobpu(&flags_used, &uval, &ap); +#else + StrFormatExamineobpu(&uval, &ap); +#endif + } + + radix = PrintGetRadixFromobpu(c); + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, radix, use_caps); + vstrp = &vstr[vlen]; +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (c == 'c') + { + cval = (int32_t)va_arg(ap, int); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (NULL != sval) + { +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + vlen = ConvertPrecisionWidthToLength(valid_precision_width, precision_width, sval); +#else + vlen = ConvertPrecisionWidthToLength(sval); +#endif +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U == (flags_used & (unsigned int)kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', (int)field_width - (int)vlen); + } + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (valid_precision_width) + { + while (('\0' != *sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = (int)precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*sval)) + { + cb(buf, &count, *sval++, 1); + } +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) + if (0U != (flags_used & (unsigned int)kPRINTF_Minus)) + { + cb(buf, &count, ' ', (int)field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + p++; + } + + return (int)count; +} + +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) +static uint8_t StrFormatScanIsFloat(char *c) +{ + uint8_t ret = 0U; + if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) || + ('g' == (*c)) || ('G' == (*c))) + { + ret = 1U; + } + return ret; +} +#endif + +static uint8_t StrFormatScanIsFormatStarting(char *c) +{ + uint8_t ret = 1U; + if ((*c != '%')) + { + ret = 0U; + } + else if (*(c + 1) == '%') + { + ret = 0U; + } + else + { + /*MISRA rule 15.7*/ + } + + return ret; +} + +static uint8_t StrFormatScanGetBase(uint8_t base, const char *s) +{ + if (base == 0U) + { + if (s[0] == '0') + { + if ((s[1] == 'x') || (s[1] == 'X')) + { + base = 16; + } + else + { + base = 8; + } + } + else + { + base = 10; + } + } + return base; +} + +static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg) +{ + uint8_t len; + switch (*p) + { + case '-': + *neg = -1; + len = 1; + break; + case '+': + *neg = 1; + len = 1; + break; + default: + *neg = 1; + len = 0; + break; + } + return len; +} + +static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val) +{ +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + + switch (flag & (uint32_t)kSCANF_LengthMask) + { + case (uint32_t)kSCANF_LengthChar: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(*args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case (uint32_t)kSCANF_LengthShortInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(*args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case (uint32_t)kSCANF_LengthLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case (uint32_t)kSCANF_LengthLongLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + + return 1U; +} + +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) +static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum) +{ +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0U; + } + else +#endif /* SCANF_ADVANCED_ENABLE */ + { + if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble)) + { + *va_arg(*args_ptr, double *) = fnum; + } + else + { + *va_arg(*args_ptr, float *) = (float)fnum; + } + return 1U; + } +} +#endif /* SCANF_FLOAT_ENABLE */ + +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) +static uint8_t strFormatScanfHandleh(uint8_t exitPending, char **c, uint32_t *flag) +{ + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if ((*c)[1] == 'h') + { + (*flag) |= (uint32_t)kSCANF_LengthChar; + *c = *c + 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthShortInt; + } + } + + return exitPending; +} + +static uint8_t strFormatScanfHandlel(uint8_t exitPending, char **c, uint32_t *flag) +{ + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if ((*c)[1] == 'l') + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongInt; + *c = *c + 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongInt; + } + } + + return exitPending; +} +#endif + +static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base) +{ + uint8_t exitPending = 0U; + char *c = *str; + + /* Loop to get full conversion specification. */ + while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask))) + { +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if ('*' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_Suppress)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_Suppress; + } + } + else if ('h' == (*c)) + { + exitPending = strFormatScanfHandleh(exitPending, &c, flag); + } + else if ('l' == (*c)) + { + exitPending = strFormatScanfHandlel(exitPending, &c, flag); + } + else +#endif /* SCANF_ADVANCED_ENABLE */ +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) + if ('L' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble; + } + } + else +#endif /* SCANF_FLOAT_ENABLE */ + if (((*c) >= '0') && ((*c) <= '9')) + { + { + char *p; + errno = 0; + (*field_width) = strtoul(c, &p, 10); + if (0 != errno) + { + *field_width = 0U; + } + c = p - 1; + } + } + else if ('d' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_TypeSinged; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('u' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('o' == (*c)) + { + (*base) = 8U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if (('x' == (*c))) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('X' == (*c)) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('i' == (*c)) + { + (*base) = 0U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) + else if (1U == StrFormatScanIsFloat(c)) + { + (*flag) |= (uint32_t)kSCANF_DestFloat; + } +#endif /* SCANF_FLOAT_ENABLE */ + else if ('c' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestChar; + if (MAX_FIELD_WIDTH == (*field_width)) + { + (*field_width) = 1; + } + } + else if ('s' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestString; + } + else + { + exitPending = 1U; + } + + if (1U == exitPending) + { + break; + } + else + { + c++; + } + } + *str = c; + return exitPending; +} + +static void StrFormatScanfHandleChar( + const char **Cp, uint32_t *field_width, char **buf, uint32_t flag, uint32_t *n_decode, uint32_t *nassigned) +{ +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + uint8_t added = 0; +#endif + while ((0U != ((*field_width)--)) +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + && ('\0' != (**Cp)) +#endif + ) + { +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + (*Cp) = (*Cp) + 1U; + } + else +#endif + { + **buf = **Cp; + (*Cp) = (*Cp) + 1U; + (*buf) = (*buf) + 1U; + +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + added = 1u; +#endif + } + *n_decode = *n_decode + 1U; + } + +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if (1u == added) +#endif + { + *nassigned = *nassigned + 1U; + } +} + +static void StrFormatScanfHandleString( + const char **Sp, uint32_t *field_width, char **buf, uint32_t flag, uint32_t *n_decode, uint32_t *nassigned) +{ +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + uint8_t added = 0; +#endif + while ((0U != ((*field_width)--)) && (**Sp != '\0') && (0U == ScanIsWhiteSpace(**Sp))) + { +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + (*Sp) = (*Sp) + 1U; + } + else +#endif + { + **buf = **Sp; + (*buf) = (*buf) + 1U; + (*Sp) = (*Sp) + 1U; +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + added = 1u; +#endif + } + *n_decode = *n_decode + 1U; + } + +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + if (1u == added) +#endif + { + /* Add NULL to end of string. */ + **buf = '\0'; + *nassigned = *nassigned + 1U; + } +} + +/*! + * brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * param[in] line_ptr The input line of ASCII data. + * param[in] format Format first points to the format string. + * param[in] args_ptr The list of parameters. + * + * return Number of input items converted and assigned. + * retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + uint8_t added = 0U; + + uint8_t exitPending = 0; + + const char *s; +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) + char *s_temp; /* MISRA C-2012 Rule 11.3 */ +#endif + + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while (('\0' != (*c)) && ('\0' != (*p))) + { + /* Ignore all white-spaces in the format strings. */ + if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c))) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if (0U == StrFormatScanIsFormatStarting(c)) + { + if (*c == '%') + { + /* A % followed by another % matches a single %, so skip the first % */ + c++; + } + + /* Ordinary characters. */ + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = MAX_FIELD_WIDTH; + base = 0; + + exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base); + + if (1U == exitPending) + { + /* Format strings are exhausted. */ + break; + } + + /* Matching strings in input streams and assign to argument. */ + if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar) + { + s = (const char *)p; + buf = va_arg(args_ptr, char *); + StrFormatScanfHandleChar(&p, &field_width, &buf, flag, &n_decode, &nassigned); + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString) + { + n_decode += ScanIgnoreWhiteSpace(&p); + buf = va_arg(args_ptr, char *); + StrFormatScanfHandleString(&p, &field_width, &buf, flag, &n_decode, &nassigned); + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + base = StrFormatScanGetBase(base, s); + + added = StrFormatScanCheckSymbol(p, &neg); + n_decode += added; + p += added; + field_width -= added; + + s = p; + if (strlen(p) > field_width) + { + char temp[12]; + char *tempEnd; + (void)memcpy(temp, p, sizeof(temp) - 1U); + temp[sizeof(temp) - 1U] = '\0'; + errno = 0; + val = (int32_t)strtoul(temp, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = p + (tempEnd - temp); + } + else + { + char *tempEnd; + errno = 0; + val = (int32_t)strtoul(p, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = tempEnd; + } + n_decode += (uintptr_t)p - (uintptr_t)s; + + val *= neg; + + nassigned += StrFormatScanFillInteger(flag, &args_ptr, val); + } +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat) + { + n_decode += ScanIgnoreWhiteSpace(&p); + errno = 0; + + fnum = strtod(p, (char **)&s_temp); + s = s_temp; /* MISRA C-2012 Rule 11.3 */ + + /* MISRA C-2012 Rule 22.9 */ + if (0 != errno) + { + break; + } + + if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL)) + { + n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p; + p = s; + nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum); + } + } +#endif /* SCANF_FLOAT_ENABLE */ + else + { + break; + } + } + } + return (int)nassigned; +} diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h new file mode 100644 index 0000000000..5acd12f7b8 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h @@ -0,0 +1,128 @@ +/* + * Copyright 2017 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U)) +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U)) + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0)) + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt b/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt index 43601f8837..0f32d4113c 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt +++ b/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------- # Copyright (c) 2020-2024, Arm Limited. All rights reserved. # Copyright (c) 2020, Linaro. All rights reserved. -# Copyright 2021-2024 NXP. All rights reserved. +# Copyright 2021-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause # @@ -12,10 +12,8 @@ cmake_policy(SET CMP0076 NEW) set(NXP_COMMON_DIR ${CMAKE_CURRENT_LIST_DIR}/../common) # Pull drivers from NXP git -if (TFM_PLATFORM_NXP_HAL_FILE_PATH STREQUAL "DOWNLOAD") +if (TFM_PLATFORM_NXP_HAL_FILE_PATH STREQUAL "LOCAL") set(NXP_HAL_FILE_PATH ${PLATFORM_DIR}/ext/target/nxp) - Message("-- Pulling MCUxpresso NXP SDK drivers from "${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}) - include(pull_drivers.cmake) # Use specified path to NXP hal folder provided by user else() set(NXP_HAL_FILE_PATH ${TFM_PLATFORM_NXP_HAL_FILE_PATH}) @@ -76,13 +74,22 @@ target_include_directories(platform_s ${PLATFORM_DIR}/ext/target/nxp/common/Device/Include ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers + ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/periph ${NXP_HAL_FILE_PATH}/common/Native_Driver ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/common + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/ctimer + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/iap1 + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/lpc_gpio + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/lpc_iocon + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm/usart ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/lists ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/uart ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/str + ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/assert ) target_sources(platform_s @@ -95,7 +102,7 @@ target_sources(platform_s project_template/s/board.c project_template/s/clock_config.c project_template/s/pin_mux.c - ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c + ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c @@ -103,14 +110,14 @@ target_sources(platform_s ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/uart/fsl_adapter_usart.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common_arm.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_ctimer.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_flexcomm.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_gpio.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_usart.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/fsl_assert.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/common/fsl_common.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/common/fsl_common_arm.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/ctimer/fsl_ctimer.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/iap1/fsl_iap.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/assert/fsl_assert.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console/fsl_debug_console.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/str/fsl_str.c $<$:${PLATFORM_DIR}/ext/target/nxp/common/plat_test.c> @@ -149,17 +156,27 @@ if(BL2) ${PLATFORM_DIR}/ext/target/nxp/common ${PLATFORM_DIR}/ext/target/nxp/common/Device/Include ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver + ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/periph ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/common + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/ctimer + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/iap1 + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/lpc_gpio + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/lpc_iocon + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm/usart + PRIVATE . ${PLATFORM_DIR}/ext/target/nxp/common/Device/Config ${PLATFORM_DIR}/ext/target/nxp/common/Device/Include ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager - ${NXP_HAL_FILE_PATH}/common/Native_Driver + ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/lists ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/uart ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/str + ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/assert ) target_sources(platform_bl2 PRIVATE @@ -175,12 +192,13 @@ if(BL2) ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/uart/fsl_adapter_usart.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common_arm.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_flexcomm.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_usart.c - ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/fsl_assert.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/common/fsl_common.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/common/fsl_common_arm.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm/fsl_flexcomm.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/flexcomm/usart/fsl_usart.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/lpc_gpio/fsl_gpio.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/iap1/fsl_iap.c + ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/assert/fsl_assert.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console/fsl_debug_console.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/str/fsl_str.c ) diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h new file mode 100644 index 0000000000..47b81b962b --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h @@ -0,0 +1,97 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + */ + +#if !defined(LPC55S69_cm33_core0_H_) /* Check if memory map has not been already included */ +#define LPC55S69_cm33_core0_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHB_SECURE_CTRL.h" +#include "PERI_ANACTRL.h" +#include "PERI_CASPER.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DBGMAILBOX.h" +#include "PERI_DMA.h" +#include "PERI_FLASH.h" +#include "PERI_FLASH_CFPA.h" +#include "PERI_FLASH_CMPA.h" +#include "PERI_FLASH_KEY_STORE.h" +#include "PERI_FLEXCOMM.h" +#include "PERI_GINT.h" +#include "PERI_GPIO.h" +#include "PERI_HASHCRYPT.h" +#include "PERI_I2C.h" +#include "PERI_I2S.h" +#include "PERI_INPUTMUX.h" +#include "PERI_IOCON.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_OSTIMER.h" +#include "PERI_PINT.h" +#include "PERI_PLU.h" +#include "PERI_PMC.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PRINCE.h" +#include "PERI_PUF.h" +#include "PERI_RNG.h" +#include "PERI_RTC.h" +#include "PERI_SCT.h" +#include "PERI_SDIF.h" +#include "PERI_SPI.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSCTL.h" +#include "PERI_USART.h" +#include "PERI_USB.h" +#include "PERI_USBFSH.h" +#include "PERI_USBHSD.h" +#include "PERI_USBHSH.h" +#include "PERI_USBPHY.h" +#include "PERI_UTICK.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(LPC55S69_cm33_core0_H_) */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_COMMON.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_COMMON.h new file mode 100644 index 0000000000..93a5d9ad5a --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_COMMON.h @@ -0,0 +1,2175 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0_COMMON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + */ + +#if !defined(LPC55S69_CM33_CORE0_COMMON_H_) +#define LPC55S69_CM33_CORE0_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + SDIO_IRQn = 42, /**< SD/MMC */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + PQ_IRQn = 57, /**< PQ interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef LPC55S69_cm33_core0_SERIES +#define LPC55S69_cm33_core0_SERIES +#endif +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core0_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif +/* AHB_SECURE_CTRL Mirror address */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x500AD000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE_NS (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x500AE000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE_NS (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x500AF000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE_NS (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE_NS) +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + #endif + + +/* ANACTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/* CASPER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } +#else + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/* FLASH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/* GINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/* I2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/* IOCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/* PMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/* PRINCE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/* RNG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SDIF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/* SPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/* SYSCTL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/* USART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/* USBFSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/* USBHSD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/* USBHSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* LPC55S69_CM33_CORE0_COMMON_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h new file mode 100644 index 0000000000..8afb581e09 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h @@ -0,0 +1,517 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-05-16 +** Build: b250801 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core0_FEATURES_H_ +#define _LPC55S69_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief LPC_RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Chip Rev 0A Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f) +/* @brief Chip Rev 0A Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f) +/* @brief Chip Rev 0A Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f) +/* @brief Chip Rev 1B Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f) +/* @brief Chip Rev 1B Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f) +/* @brief Chip Rev 1B Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief SW interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) +/* @brief CASPER dedicated RAM offset */ +#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* GINT module features */ + +/* @brief The count of th port which are supported in GINT. */ +#define FSL_FEATURE_GINT_PORT_COUNT (2) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +/* POWERLIB module features */ + +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (648704) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) + +/* RTC module features */ + +/* @brief Has SUBSEC Register (register SUBSEC) */ +#define FSL_FEATURE_RTC_HAS_SUBSEC (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SPI module features */ + +/* @brief SSEL pin count. */ +#define FSL_FEATURE_SPI_SSEL_COUNT (4) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* No feature definitions */ + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* USBPHY module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) + +/* UTICK module features */ + +/* No feature definitions */ + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h new file mode 100644 index 0000000000..e433c2f27d --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h @@ -0,0 +1,97 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core1.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + */ + +#if !defined(LPC55S69_cm33_core1_H_) /* Check if memory map has not been already included */ +#define LPC55S69_cm33_core1_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHB_SECURE_CTRL.h" +#include "PERI_ANACTRL.h" +#include "PERI_CASPER.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DBGMAILBOX.h" +#include "PERI_DMA.h" +#include "PERI_FLASH.h" +#include "PERI_FLASH_CFPA.h" +#include "PERI_FLASH_CMPA.h" +#include "PERI_FLASH_KEY_STORE.h" +#include "PERI_FLEXCOMM.h" +#include "PERI_GINT.h" +#include "PERI_GPIO.h" +#include "PERI_HASHCRYPT.h" +#include "PERI_I2C.h" +#include "PERI_I2S.h" +#include "PERI_INPUTMUX.h" +#include "PERI_IOCON.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_OSTIMER.h" +#include "PERI_PINT.h" +#include "PERI_PLU.h" +#include "PERI_PMC.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PRINCE.h" +#include "PERI_PUF.h" +#include "PERI_RNG.h" +#include "PERI_RTC.h" +#include "PERI_SCT.h" +#include "PERI_SDIF.h" +#include "PERI_SPI.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSCTL.h" +#include "PERI_USART.h" +#include "PERI_USB.h" +#include "PERI_USBFSH.h" +#include "PERI_USBHSD.h" +#include "PERI_USBHSH.h" +#include "PERI_USBPHY.h" +#include "PERI_UTICK.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(LPC55S69_cm33_core1_H_) */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_COMMON.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_COMMON.h new file mode 100644 index 0000000000..83421201e8 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_COMMON.h @@ -0,0 +1,2175 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core1_COMMON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + */ + +#if !defined(LPC55S69_CM33_CORE1_COMMON_H_) +#define LPC55S69_CM33_CORE1_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + SDIO_IRQn = 42, /**< SD/MMC */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + PQ_IRQn = 57, /**< PQ interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S69_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef LPC55S69_cm33_core1_SERIES +#define LPC55S69_cm33_core1_SERIES +#endif +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core1_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif +/* AHB_SECURE_CTRL Mirror address */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x500AD000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE_NS (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x500AE000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE_NS (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x500AF000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE_NS (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE_NS) +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + #endif + + +/* ANACTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/* CASPER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } +#else + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/* FLASH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/* GINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/* I2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/* IOCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/* PMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/* PRINCE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/* RNG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SDIF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/* SPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/* SYSCTL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/* USART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/* USBFSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/* USBHSD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/* USBHSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* LPC55S69_CM33_CORE1_COMMON_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h new file mode 100644 index 0000000000..e1bd5a6bbe --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h @@ -0,0 +1,517 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-05-16 +** Build: b250801 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core1_FEATURES_H_ +#define _LPC55S69_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief LPC_RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Chip Rev 0A Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f) +/* @brief Chip Rev 0A Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f) +/* @brief Chip Rev 0A Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f) +/* @brief Chip Rev 1B Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f) +/* @brief Chip Rev 1B Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f) +/* @brief Chip Rev 1B Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief SW interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) +/* @brief CASPER dedicated RAM offset */ +#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* GINT module features */ + +/* @brief The count of th port which are supported in GINT. */ +#define FSL_FEATURE_GINT_PORT_COUNT (2) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +/* POWERLIB module features */ + +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (648704) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) + +/* RTC module features */ + +/* @brief Has SUBSEC Register (register SUBSEC) */ +#define FSL_FEATURE_RTC_HAS_SUBSEC (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SPI module features */ + +/* @brief SSEL pin count. */ +#define FSL_FEATURE_SPI_SSEL_COUNT (4) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* No feature definitions */ + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* USBPHY module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) + +/* UTICK module features */ + +/* No feature definitions */ + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c new file mode 100644 index 0000000000..7bd90ee6f4 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c @@ -0,0 +1,2176 @@ +/* + * Copyright 2017 - 2021 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ +#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control1 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) + +/* PLL0 SSCG control1 */ +#define PLL0_SSCG_MD_FRACT_P 0U +#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) + +#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll0_Freq; +static uint32_t s_Pll1_Freq; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; +static uint32_t s_PLU_ClkIn_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void); +/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ +static float findPll0MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + assert(connection < kNONE_to_NONE); + + uint8_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = (volatile uint32_t *)(SYSCON_BASE + 0x260U); /* SYSTICKCLKSEL0 offset 0x260 */ + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = (uint8_t)(GET_ID_ITEM_MUX(item) & 0xFFU); + sel = (uint8_t)GET_ID_ITEM_SEL(item); + if (mux == CM_RTCOSC32KCLKSEL) + { + PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); + } + else + { + assert(mux <= CM_SDIOCLKSEL); + pClkSel[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + assert(attachId < kNONE_to_NONE); + + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = (volatile uint32_t *)(SYSCON_BASE + 0x260U); /* SYSTICKCLKSEL0 offset 0x260 */ + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = (uint8_t)GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_RTCOSC32KCLKSEL) + { + actualSel = (uint8_t)(PMC->RTCOSC32K & 0xFFU); + } + else + { + assert(mux <= CM_SDIOCLKSEL); + actualSel = (uint8_t)(pClkSel[mux] & 0xFFU); + } + + /* Consider the combination of two registers */ + assert(actualSel < UINT8_MAX); + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + assert(actualAttachId < kNONE_to_NONE); + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV0); + if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) + { + /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = + SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); + } + else + { + if (reset) + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); + } + } +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1khz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) +{ + assert(divided_by_value < 28U); + PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1hz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) +{ + if (divided_by_value == 0U) /*!< halt */ + { + PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); + } + else + { + PMC->RTCOSC32K |= + (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Enable Analog Control module */ + SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; + /* Power up the FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + + if (iFreq == 96000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); + } + /* always enable + else if (iFreq == 48000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); + }*/ + else + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); + } + return kStatus_Success; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq: Input frequency + * return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ + uint32_t prefetch_enable_mask = SYSCON->FMCCR & SYSCON_FMCCR_PREFEN_MASK; + + if (iFreq <= 11000000UL) + { + /* [0 - 11 MHz] */ + num_wait_states = 0UL; + } + else if (iFreq <= 22000000UL) + { + /* [11 MHz - 22 MHz] */ + num_wait_states = 1UL; + } + else if (iFreq <= 33000000UL) + { + /* [22 MHz - 33 MHz] */ + num_wait_states = 2UL; + } + else if (iFreq <= 44000000UL) + { + /* [33 MHz - 44 MHz] */ + num_wait_states = 3UL; + } + else if (iFreq <= 55000000UL) + { + /* [44 MHz - 55 MHz] */ + num_wait_states = 4UL; + } + else if (iFreq <= 66000000UL) + { + /* [55 MHz - 662 MHz] */ + num_wait_states = 5UL; + } + else if (iFreq <= 77000000UL) + { + /* [66 MHz - 77 MHz] */ + num_wait_states = 6UL; + } + else if (iFreq <= 88000000UL) + { + /* [77 MHz - 88 MHz] */ + num_wait_states = 7UL; + } + else if (iFreq <= 100000000UL) + { + /* [88 MHz - 100 MHz] */ + num_wait_states = 8UL; + } + else if (iFreq <= 115000000UL) + { + /* [100 MHz - 115 MHz] */ + num_wait_states = 9UL; + } + else if (iFreq <= 130000000UL) + { + /* [115 MHz - 130 MHz] */ + num_wait_states = 10UL; + } + else if (iFreq <= 150000000UL) + { + /* [130 MHz - 150 MHz] */ + num_wait_states = 11UL; + } + else + { + /* Above 150 MHz */ + num_wait_states = 12UL; + } + + /*The prefetch bit must be disabled before any flash commands*/ + SYSCON->FMCCR &= ~SYSCON_FMCCR_PREFEN_MASK; + + FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */ + + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | + (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); + + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + + /* Wait until the cmd is completed (without error) */ + while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) + { + ; + } + + /* Adjust FMC waiting time cycles (num_wait_states) */ + SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | + ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); + + /* restore prefetch enable */ + SYSCON->FMCCR |= prefetch_enable_mask; +} + +/* Set EXT OSC Clk */ +/** + * brief Initialize the external osc clock to given frequency. + * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. + * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + if (iFreq > 32000000U) + { + return kStatus_Fail; + } + /* Turn on power for crystal 32 MHz */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + /* Enable clock_in clock for clock module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; + + /* Wait for external osc clock to be valid. */ + while((ANACTRL->XO32M_STATUS & ANACTRL_XO32M_STATUS_XO_READY_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + return kStatus_Success; +} + +/* Set I2S MCLK Clk */ +/** + * brief Initialize the I2S MCLK clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) +{ + s_I2S_Mclk_Freq = iFreq; + return kStatus_Success; +} + +/* Set PLU CLKIN Clk */ +/** + * brief Initialize the PLU CLKIN clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) +{ + s_PLU_ClkIn_Freq = iFreq; + return kStatus_Success; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); +} + +/* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); +} + +/* Get USB1 Clk */ +/*! brief Return Frequency of Usb1 Clock + * return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); +} + +/* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); +} + +/* Get SDIO Clk */ +/*! brief Return Frequency of SDIO Clock + * return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SDIOCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + assert(false); + break; + } + + return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void) +{ + return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + return s_Pll0_Freq; +} + +/* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + return s_Pll1_Freq; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetFro1MFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ + } + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +/* Get PLU CLKIN Clk */ +/*! brief Return Frequency of PLU CLKIN Clock + * return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void) +{ + return s_PLU_ClkIn_Freq; +} + +/* Get FLEXCOMM input clock */ +/*! brief Return Frequency of flexcomm input clock + * param id : flexcomm instance id + * return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t frgMul = 0U; + uint32_t frgDiv = 0U; + + freq = CLOCK_GetFlexCommInputClock(id); + frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; + frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; + return (uint32_t)((((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)) & 0xFFFFFFFFUL); +} + +/* Get HS_LPSI Clk */ +uint32_t CLOCK_GetHsLspiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->HSLSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + volatile uint32_t *pSystickClkDiv; + pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((((volatile uint32_t *)pSystickClkDiv)[(uint32_t)id] & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set FlexComm Clock */ +/** + * brief Set the flexcomm output frequency. + * param id : flexcomm instance id + * freq : output frequency + * return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) +{ + uint32_t input = CLOCK_GetFlexCommClkFreq(id); + uint32_t mul; + + if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0UL; + } + else + { + mul = (uint32_t)(((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)) & 0xFFFFFFFFUL); + SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; + return 1UL; + } +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = + (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL0 output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllsscg[1] = + (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0U; + pllSelI = 0U; + pllSelP = 0U; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)((PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)) & 0xFFFFFFFFUL); + pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ + (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ + (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + assert(s_PllSetupCacheIdx <= UINT32_MAX - 1U); + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL0 output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Set the current PLL0 Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) +{ + s_Pll0_Freq = rate; +} + +/* Return PLL0 output clock rate */ +/*! brief Return PLL0 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL0 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll0_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL0CTRL; + Setup.pllndec = SYSCON->PLL0NDEC; + Setup.pllpdec = SYSCON->PLL0PDEC; + Setup.pllsscg[0] = SYSCON->PLL0SSCG0; + Setup.pllsscg[1] = SYSCON->PLL0SSCG1; + + CLOCK_GetPLL0OutFromSetupUpdate(&Setup); + } + + rate = s_Pll0_Freq; + + return rate; +} + +/* Set PLL0 output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetPLL0InClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL0 output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + uint32_t inRate, clkRate, prediv; + uint32_t pll_lock_wait_time = 0U; + uint32_t max_pll_lock_wait_time = 0U; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + + /* Need wait at least (500us + 400/Fref) (Fref in Hz result in s) to ensure the PLL is stable. + The lock bit could be used to shorten the wait time when freq<20MHZ */ + assert((400000000U / clkRate) <= UINT32_MAX - 500U); + max_pll_lock_wait_time = 500U + (400000000U / clkRate); + + if (clkRate < 20000000UL) + { + pll_lock_wait_time = 0U; + while ((CLOCK_IsPLL0Locked() == false) && (pll_lock_wait_time < max_pll_lock_wait_time)) + { + pll_lock_wait_time += 100U; + SDK_DelayAtLeastUs(100U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else + { + SDK_DelayAtLeastUs(max_pll_lock_wait_time, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetPLL0OutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll0_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + uint32_t pll_lock_wait_time = 0U; + uint32_t max_pll_lock_wait_time = 0U; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + + /* Need wait at least (500us + 400/Fref) (Fref in Hz result in s) to ensure the PLL is + stable. The lock bit could be used to shorten the wait time when freq<20MHZ */ + assert((400000000U / clkRate) <= UINT32_MAX - 500U); + max_pll_lock_wait_time = 500U + (400000000U / clkRate); + + if (clkRate < 20000000UL) + { + pll_lock_wait_time = 0U; + while ((CLOCK_IsPLL0Locked() == false) && (pll_lock_wait_time < max_pll_lock_wait_time)) + { + pll_lock_wait_time += 100U; + SDK_DelayAtLeastUs(100U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else + { + SDK_DelayAtLeastUs(max_pll_lock_wait_time, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + uint32_t pll_lock_wait_time = 0U; + uint32_t max_pll_lock_wait_time = 0U; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL1); + + /* Write PLL setup data */ + SYSCON->PLL1CTRL = pSetup->pllctrl; + SYSCON->PLL1NDEC = pSetup->pllndec; + SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec; + SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec; + SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + + /* Need wait at least (500us + 400/Fref) (Fref in Hz result in s) to ensure the PLL is stable. + The lock bit could be used to shorten the wait time when freq<20MHZ */ + assert((400000000U / clkRate) <= UINT32_MAX - 500U); + max_pll_lock_wait_time = 500U + (400000000U / clkRate); + + if (clkRate < 20000000UL) + { + pll_lock_wait_time = 0U; + while ((CLOCK_IsPLL1Locked() == false) && (pll_lock_wait_time < max_pll_lock_wait_time)) + { + pll_lock_wait_time += 100U; + SDK_DelayAtLeastUs(100U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else + { + SDK_DelayAtLeastUs(max_pll_lock_wait_time, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + + /* Update current programmed PLL rate var */ + s_Pll1_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set PLL0 clock based on the input frequency and multiplier */ +/*! brief Set PLL0 output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + + selr = 0U; + + if (multiply_by >= 8000UL) + { + seli = 1UL; + } + else if (multiply_by >= 122UL) + { + seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63U) + { + seli = 63U; + } + + { + selp = 31U; + } + + if (pdec > 1U) + { + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + } + + mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); + ndec = 0x1U; /* pre divide by 1 (hardcoded) */ + + SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | + SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | + (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); + SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0SSCG1 = + mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = + ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbd0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbhmr0); + CLOCK_DisableClock(kCLOCK_Usbhsl0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else if (kCLOCK_UsbfsSrcPll0 == src) + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL0 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(19U) | SYSCON_PLL0CTRL_SELP(9U), + .pllndec = SYSCON_PLL0NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(5U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(30U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL0Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL0_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB PHY clock */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + volatile uint32_t i; + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool ret = true; + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ + + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); + + /* wait to make sure PHY power is fully up */ + for (i = 0U; i < 100000U; i++) + { + __ASM("nop"); + } + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + + multiplier = (uint16_t)((480000000UL / freq) & 0xFFFFU); + + switch (multiplier) + { + case 15U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 24U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 40U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + ret = false; + break; + } + } + + if (ret) + { + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; + SDK_DelayAtLeastUs(15U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + } + + return ret; +} + +/* Enable USB DEVICE HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + return true; +} + +/* Enable USB HOST HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + + return true; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; +} diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h new file mode 100644 index 0000000000..4a83524cf8 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h @@ -0,0 +1,1508 @@ +/* + * Copyright 2017 - 2021 , 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.3.8. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 8)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for Mailbox. */ +#define MAILBOX_CLOCKS \ + { \ + kCLOCK_Mailbox \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer0 \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick0 \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for COMP */ +#define COMP_CLOCKS \ + { \ + kCLOCK_Comp \ + } +/*! @brief Clock ip name array for SDIO. */ +#define SDIO_CLOCKS \ + { \ + kCLOCK_Sdio \ + } +/*! @brief Clock ip name array for USB1CLK. */ +#define USB1CLK_CLOCKS \ + { \ + kCLOCK_Usb1Clk \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for USBRAM. */ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for HashCrypt. */ +#define HASHCRYPT_CLOCKS \ + { \ + kCLOCK_HashCrypt \ + } +/*! @brief Clock ip name array for PowerQuad. */ +#define POWERQUAD_CLOCKS \ + { \ + kCLOCK_PowerQuad \ + } +/*! @brief Clock ip name array for PLULUT. */ +#define PLULUT_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for CASPER. */ +#define CASPER_CLOCKS \ + { \ + kCLOCK_Casper \ + } +/*! @brief Clock ip name array for ANALOGCTRL. */ +#define ANALOGCTRL_CLOCKS \ + { \ + kCLOCK_AnalogCtrl \ + } +/*! @brief Clock ip name array for HS_LSPI. */ +#define HS_LSPI_CLOCKS \ + { \ + kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for GPIO_SEC. */ +#define GPIO_SEC_CLOCKS \ + { \ + kCLOCK_Gpio_Sec \ + } +/*! @brief Clock ip name array for GPIO_SEC_INT. */ +#define GPIO_SEC_INT_CLOCKS \ + { \ + kCLOCK_Gpio_Sec_Int \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ + } +/*! @brief Clock ip name array for USBH. */ +#define USBH_CLOCKS \ + { \ + kCLOCK_Usbh1 \ + } +#define PLU_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +#define SYSCTL_CLOCKS \ + { \ + kCLOCK_Sysctl \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ + + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ + + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */ + + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */ + + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ + + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ + + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ + + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ + + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ + + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ + + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */ + + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */ + + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ + + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ + + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ + + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ + + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ + + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ + + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ + + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + + kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ + + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ + + kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ + + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ + + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ + + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ + + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ + + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ + + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ + + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ + + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ + + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ + + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ + + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ + + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ + + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ + + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ + + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ + + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ + + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ + + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ + + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ + + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ + + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ + + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ + + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ + + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ + + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ + + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ + + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ + + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ + + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ + + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ + + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ + + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ + + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ + + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ + + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ + + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ + + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ + + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ + + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ + + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ + + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ + + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + + kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */ + + kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ + + kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ + + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ + + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */ + + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ + + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ + + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ + + kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ + + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ + + kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */ + + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ + + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ + + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ + + kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ + + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ + + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ + + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + + kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ + + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ + + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ + + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ + + kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)(((((uint32_t)(connection)&0xF00U) >> 8U) - 1U) & 0xFFU)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0U +#define CM_SYSTICKCLKSEL1 1U +#define CM_TRACECLKSEL 2U +#define CM_CTIMERCLKSEL0 3U +#define CM_CTIMERCLKSEL1 4U +#define CM_CTIMERCLKSEL2 5U +#define CM_CTIMERCLKSEL3 6U +#define CM_CTIMERCLKSEL4 7U +#define CM_MAINCLKSELA 8U +#define CM_MAINCLKSELB 9U +#define CM_CLKOUTCLKSEL 10U +#define CM_PLL0CLKSEL 12U +#define CM_PLL1CLKSEL 13U +#define CM_ADCASYNCCLKSEL 17U +#define CM_USB0CLKSEL 18U +#define CM_FXCOMCLKSEL0 20U +#define CM_FXCOMCLKSEL1 21U +#define CM_FXCOMCLKSEL2 22U +#define CM_FXCOMCLKSEL3 23U +#define CM_FXCOMCLKSEL4 24U +#define CM_FXCOMCLKSEL5 25U +#define CM_FXCOMCLKSEL6 26U +#define CM_FXCOMCLKSEL7 27U +#define CM_HSLSPICLKSEL 28U +#define CM_MCLKCLKSEL 32U +#define CM_SCTCLKSEL 36U +#define CM_SDIOCLKSEL 38U + +#define CM_RTCOSC32KCLKSEL 63U + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ + + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ + + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ + + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ + + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ + + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ + + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ + + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ + + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ + + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ + + kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ + + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ + + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ + + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ + + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ + + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ + + kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ + + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ + + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ + + kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ + + kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ + + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ + + kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ + + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ + + kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ + + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ + + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ + + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ + + kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ + + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ + + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ + + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ + + kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ + + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ + + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ + + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ + + kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ + + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ + + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ + + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ + + kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ + + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ + + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ + + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ + + kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ + + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ + + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ + + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ + + kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ + + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ + + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ + + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ + + kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ + + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ + + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ + + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ + + kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ + + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ + + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ + + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ + + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ + + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ + + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ + + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ + + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ + + kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ + + kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ + + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ + + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ + + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ + + kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */ + + kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */ + + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */ + + kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */ + + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */ + + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ + + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ + + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ + + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ + + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ + + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ + + kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */ + + kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */ + + kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ + + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ + + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ + + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ + + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ + + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ + + kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ + + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ + + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ + + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ + + kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ + + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ + + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ + + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ + + kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ + + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ + + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ + + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ + + kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ + + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ + + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ + + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ + + kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ + + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ + + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ + + kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + + kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */ + + kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ + + kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ + + kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ + + kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ + + kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ + + kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ + + kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ + + kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ + + kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ + + kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ + + kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ + + kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ + + kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ + + kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ + + kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ + + kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ + + kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ + + kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */ + + kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + assert(index < SYSCON_AHBCLKCTRLSET_COUNT); + SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + assert(index < SYSCON_AHBCLKCTRLSET_COUNT); + SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the I2S MCLK clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Initialize the PLU CLKIN clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Setup rtc 1khz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); +/** + * @brief Setup rtc 1hz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); + +/** + * @brief Set the flexcomm output frequency. + * @param id : flexcomm instance id + * @param freq : output frequency + * @return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); + +/*! @brief Return Frequency of flexcomm input clock + * @param id : flexcomm instance id + * @return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of FRO 1MHz + * @return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of Usb1 Clock + * @return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of SDIO Clock + * @return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of PLU CLKIN Clock + * @return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void); +/*! @brief Return Frequency of FlexComm Clock + * @return Frequency of FlexComm Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of High speed SPI Clock + * @return Frequency of High speed SPI Clock + */ +uint32_t CLOCK_GetHsLspiClkFreq(void); +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); +/*! @brief Return Frequency of SystickClock + * @return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Return PLL0 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL0 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); + +/*! @brief Enables and disables PLL0 bypass mode + * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass + * @return PLL0 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) +{ + if (bypass) + { + SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Enables and disables PLL1 bypass mode + * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass + * @return PLL1 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) +{ + if (bypass) + { + SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Store the current PLL0 rate + * @param rate: Current rate of the PLL0 + * @return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7U << SYSCON_PLL0SSCG1_MF_SHIFT) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1 */ + kSS_MR_K1_5 = (2U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1.5 */ + kSS_MR_K2 = (3U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 2 */ + kSS_MR_K3 = (4U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 3 */ + kSS_MR_K4 = (5U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 4 */ + kSS_MR_K6 = (6U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 6 */ + kSS_MR_K8 = (7U << SYSCON_PLL0SSCG1_MR_SHIFT) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< no compensation */ + kSS_MC_RECC = (2U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< recommended setting */ + kSS_MC_MAXC = (3U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ + uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ + uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ + uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB FS clock source definition. */ +typedef enum _clock_usbfs_src +{ + kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ + kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ + kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ + + kCLOCK_UsbfsSrcNone = + SYSCON_USB0CLKSEL_SEL(7) /*!WAKEUPINT. They are NOT restored by the + * API. + * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk + * of Dead Lock). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + * reset) + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); + +/** + * @brief + * @param + * @return + */ +static void lf_set_dcdc_power_profile_low(void) +{ +#define DCDC_POWER_PROFILE_LOW_0_ADDRS (0x9FCE0U) +#define DCDC_POWER_PROFILE_LOW_1_ADDRS (0x9FCE4U) + + uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); + uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + PMC->DCDC0 = dcdcTrimValue0 >> 1; + PMC->DCDC1 = dcdcTrimValue1; + } +} + +/** + * @brief Configures and enters in low power mode + * @param : p_lowpower_cfg + * @return Nothing + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) +{ + lowpower_driver_interface_t *s_lowpowerDriver; + /* Judging the core and call the corresponding API base address*/ + if (0UL == Chip_GetVersion()) + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); + } + else + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); + } + /* PMC clk set to 12 MHZ */ + p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; + + /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP + * POWER DOWN) and Hardware Pin reset */ + PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | + PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); + + /* SRAM uses Voltage Scaling in all Low Power modes */ + PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); + + /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined + * parameter. */ + p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | + (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); + + /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ + SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ + lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ + + (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); + + /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = + * 0 */ + PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & + (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); +} + +/** + * @brief + * @param + * @return + */ +static bool int32_MultiplyOverflow(int32_t a, int32_t b) { + if (a == 0 || b == 0) return false; + if (a > 0 && b > 0) return a > INT32_MAX / b; + if (a < 0 && b < 0) return a < INT32_MAX / b; + return a < INT32_MIN / b || b < INT32_MIN / a; +} + +/** + * @brief + * @param + * @return + */ +static bool int32_AddOverflow(int32_t a, int32_t b) { + if ((b > 0) && (a > INT32_MAX - b)) return true; + if ((b < 0) && (a < INT32_MIN - b)) return true; + return false; +} + + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * @param None + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void) +{ + /* Judging the core and call the corresponding API base address*/ + lowpower_driver_interface_t *s_lowpowerDriver; + if (0UL == Chip_GetVersion()) + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); + } + else + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); + } + (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); +}; + +/** + * brief PMC Deep Sleep function call + * return nothing + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl) +{ + static LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t dcdc_voltage; + uint32_t pmc_reset_ctrl; + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ + + lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during + * deep-sleep */ + exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; + } + + /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references + * will stay powered, Shut down ROM */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & + ~(uint32_t)kPDRUNCFG_PD_BIAS) | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; + + /* Voltage control in DeepSleep Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* CPU Wake up & Interrupt sources control */ + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; + + /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ + if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) + { + lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; + } + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODCORERESETENABLE_MASK)) + { + /* BoD CORE reset is activated, so make sure BoD Core won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE; + } + if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) + { + /* BoD VBAT reset is activated, so make sure BoD VBAT won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT; + } + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC power Down function call + * return nothing + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint64_t wakeup_src_int; + uint32_t pmc_reset_ctrl; + + uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ + + /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point + * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); + + /* CPU0 retention Ctrl. + * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the + * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2) If required by customer, + * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area + */ + lv_low_power_mode_cfg.CPURETCTRL = + (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | + ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & + LOWPOWER_CPURETCTRL_MEMBASE_MASK); + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* CPU retention is required: store Analog Controller Registers */ + analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; + analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; + analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; + analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; + analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; + analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; + analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; + analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; + analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; + analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; + analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; + analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; + } + + /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, + * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ + wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT | + WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + /* Disable BoD VBAT and BoD Core resets */ + PMC->RESETCTRL = + pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for + instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the + stack used to call this function shall be preserved during low power ***/ + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; + + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* Restore Analog Controller Registers */ + ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; + ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; + ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; + ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; + ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; + ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; + ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; + ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; + ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; + ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; + ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; + ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; + } +} + +/** + * brief PMC Deep Sleep Power Down function call + * return nothing + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t pmc_reset_ctrl; + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ + + /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; + * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | + (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; + + /* SRAM retention control during DEEPPOWERDOWN */ + sram_retention_ctrl = + sram_retention_ctrl & + (~(LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 | LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 | LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); + + /* SRAM retention control during DEEPPOWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); + + lv_low_power_mode_cfg.WAKEUPINT = + wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | + WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER */ + lv_low_power_mode_cfg.WAKEUPSRC = + wakeup_interrupts & + (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | + WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ + + /* Wake up I/O sources */ + lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + /* Save the configuration of the PMC RESETCTRL register */ + pmc_reset_ctrl = PMC->RESETCTRL; + /* Disable BoD VBAT and BoD Core resets */ + PMC->RESETCTRL = + pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); + + /* Disable LDO MEM bleed current */ + // PMC->MISCCTRL |= PMC_MISCCTRL_DISABLE_BLEED_MASK; + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC Sleep function call + * return nothing + */ +void POWER_EnterSleep(void) +{ + uint32_t pmsk; + pmsk = __get_PRIMASK(); + __disable_irq(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + __set_PRIMASK(pmsk); +} + +/** + * @brief Get Digital Core logic supply source to be used during Deep Sleep. + * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep + * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used + * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h + + * @return Nothing + */ +static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) +{ + *dcdc_voltage = (uint32_t)V_DCDC_0P950; /* Default value */ + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode */ + PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ + *dcdc_voltage = + (uint32_t)V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ + } +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) +{ +#define FLASH_NMPA_LDO_AO_ADDRS (0x9FCF4U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) + + uint32_t ldo_ao_trim, voltage; + uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; + + ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); + + switch (p_lp_mode) + { + case LOWPOWER_CFG_LPMODE_DEEPSLEEP: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; + assert(lv_v_ldo_pmu >= 2UL); + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P900; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; + } + } + break; + + case LOWPOWER_CFG_LPMODE_POWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; + assert(lv_v_ldo_pmu >= 2UL); + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; + assert(lv_v_ldo_pmu >= 2UL); + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + default: + /* Should never reach this point */ + lv_v_ldo_pmu = (uint32_t)V_AO_1P100; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; + break; + } + + /* The Memories Voltage settings below are for voltage scaling */ + voltage = + (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ + (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ + ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ + ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ + ((uint32_t)V_DEEPSLEEP_0P900 + << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ + (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ + ; + + return (voltage); +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) +{ + uint32_t wake_up_type; + uint32_t misc_ctrl_reg; + uint8_t use_external_pullupdown = 0; + + /* Configure Pull up & Pull down based on the required wake-up edge */ + CLOCK_EnableClock(kCLOCK_Iocon); + + misc_ctrl_reg = 0UL; + + /* Wake-up I/O 0 */ + wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[8]:WAKEUPIOCTRL[8]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 1 */ + wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[9]:WAKEUPIOCTRL[9]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 2 */ + wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[10]:WAKEUPIOCTRL[10]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 3 */ + wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[11]:WAKEUPIOCTRL[11]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + + PMC->MISCCTRL = (PMC->MISCCTRL & 0xFFFFF0FFUL) | misc_ctrl_reg; + PMC->WAKEUPIOCTRL = p_wakeup_io_ctrl & 0xFFFUL; + + /* + * Defined according to : + * - LOWPOWER_WAKEUPIOSRC_ in fsl_power.h + * - LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_<...> in fsl_power.h + */ + return (p_wakeup_io_ctrl & 0xFFFUL); +} + +/** + * @brief + * @param + * @return + */ +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) +{ + uint16_t uint16Tmp; + + /* Compensate for discontinuity in the capacitor banks */ + if (u8OscCap < 64U) + { + if (u8OscCap >= u8CapBankDiscontinuity) + { + u8OscCap -= u8CapBankDiscontinuity; + } + else + { + u8OscCap = 0U; + } + } + else + { + assert(u8CapBankDiscontinuity <= 127U); + if (u8OscCap <= (127U - u8CapBankDiscontinuity)) + { + uint16Tmp = u8OscCap + u8CapBankDiscontinuity; + u8OscCap = (uint8_t)(uint16Tmp & 0xFFU); + } + else + { + u8OscCap = 127U; + } + } + return u8OscCap; +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_system_voltage(uint32_t system_voltage_mv) +{ + /* + * Set system voltage + */ + uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ + uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ + uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ + + if (system_voltage_mv <= 950UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P950; + lv_ldo_ao = (uint32_t)V_AO_0P960; + lv_ldo_ao_boost = (uint32_t)V_AO_1P010; + } + else if (system_voltage_mv <= 975UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P975; + lv_ldo_ao = (uint32_t)V_AO_0P980; + lv_ldo_ao_boost = (uint32_t)V_AO_1P030; + } + else if (system_voltage_mv <= 1000UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P000; + lv_ldo_ao = (uint32_t)V_AO_1P000; + lv_ldo_ao_boost = (uint32_t)V_AO_1P050; + } + else if (system_voltage_mv <= 1025UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P025; + lv_ldo_ao = (uint32_t)V_AO_1P030; + lv_ldo_ao_boost = (uint32_t)V_AO_1P080; + } + else if (system_voltage_mv <= 1050UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P050; + lv_ldo_ao = (uint32_t)V_AO_1P060; + lv_ldo_ao_boost = (uint32_t)V_AO_1P110; + } + else if (system_voltage_mv <= 1075UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P075; + lv_ldo_ao = (uint32_t)V_AO_1P080; + lv_ldo_ao_boost = (uint32_t)V_AO_1P130; + } + else if (system_voltage_mv <= 1100UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P100; + lv_ldo_ao = (uint32_t)V_AO_1P100; + lv_ldo_ao_boost = (uint32_t)V_AO_1P150; + } + else if (system_voltage_mv <= 1125UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P125; + lv_ldo_ao = (uint32_t)V_AO_1P130; + lv_ldo_ao_boost = (uint32_t)V_AO_1P160; + } + else if (system_voltage_mv <= 1150UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P150; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else if (system_voltage_mv <= 1175UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P175; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else + { + lv_dcdc = (uint32_t)V_DCDC_1P200; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + + /* Set up LDO Always-On voltages */ + PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | + PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); + + /* Set up DCDC voltage */ + PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ +#define FLASH_NMPA_BASE (0x9FC00u) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // (0x9FCE0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // (0x9FCE4U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) // (0x9FCE8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) // (0x9FCECU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) // (0x9FCD8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) // (0x9FCDCU) + + const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; + const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; + + uint32_t dcdcTrimValue0; + uint32_t dcdcTrimValue1; + + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_LOW: + /* Low */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "MEDIUM" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "HIGH" + "\n"); +#endif + } + break; + + default: + /* Low */ + PMC->DCDC0 = PMC_DCDC0_DEFAULT; + PMC->DCDC1 = PMC_DCDC1_DEFAULT; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + break; + } +} + +/** + * @brief + * @param + * @return + */ +static lowpower_process_corner_enum lowpower_get_part_process_corner(void) +{ +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) + + lowpower_process_corner_enum part_process_corner; + uint32_t pvt_ringo_hz; + uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); + uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); + + /* + * Check that the PVT Monitors Trimmings in flash are valid. + */ + if (0UL != (pvt_ringo_0 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_0 = pvt_ringo_0 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_0 = PROCESS_NNN_AVG_HZ; + } + + if (0UL != (pvt_ringo_1 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_1 = pvt_ringo_1 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_1 = PROCESS_NNN_AVG_HZ; + } + + if (pvt_ringo_1 <= pvt_ringo_0) + { + pvt_ringo_hz = pvt_ringo_1; + } + else + { + pvt_ringo_hz = pvt_ringo_0; + } + + /* + * Determine the process corner based on the value of the Ring Oscillator frequency + */ + if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) + { + /* SSS Process Corner */ + part_process_corner = PROCESS_CORNER_SSS; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "SSS" + "\n"); +#endif + } + else + { + if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) + { + /* NNN Process Corner */ + part_process_corner = PROCESS_CORNER_NNN; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "NNN" + "\n"); +#endif + } + else + { + /* FFF Process Corner */ + part_process_corner = PROCESS_CORNER_FFF; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "FFF" + "\n"); +#endif + } + } + + return (part_process_corner); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ + /* Get Sample Process Corner */ + lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); + + switch (part_process_corner) + { + case PROCESS_CORNER_SSS: + /* Slow Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + case PROCESS_CORNER_FFF: + /* Fast Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + default: + /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); + break; + } // switch(dcdc_power_profile) + break; + } + } // switch(part_process_corner) +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz) +{ + if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) + { + /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); + } + else + { + if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) + { + /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); + } + else + { + /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); + } + } +} + +void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + int64_t i64Tmp; + + /* Enable and set LDO, if not already done */ + POWER_SetXtal16mhzLdo(); + /* Get Cal values from Flash */ + u32XOTrimValue = GET_16MXO_TRIM(); + /* Check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* This field is 1 bit */ + u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 20; // gain in LSB/pF + ibXin = -9; // offset in LSB + iaXout_x4 = 20; // gain in LSB/pF + ibXout = -13; // offset in LSB + u8XOSlave = 0; + } + /* In & out load cap calculation with derating */ + i64Tmp = 2 * (int64_t)pi32_16MfXtalIecLoadpF_x100 - (int64_t)pi32_16MfXtalNPcbParCappF_x100 + + 39 * ((int64_t)XO_SLAVE_EN - (int64_t)u8XOSlave) - 15; + assert((i64Tmp <= INT32_MAX) && (i64Tmp >= INT32_MIN)); + iXOCapInpF_x100 = (int32_t)i64Tmp; + i64Tmp = 2 * (int64_t)pi32_16MfXtalIecLoadpF_x100 - (int64_t)pi32_16MfXtalPPcbParCappF_x100 - 21; + assert((i64Tmp <= INT32_MAX) && (i64Tmp >= INT32_MIN)); + iXOCapOutpF_x100 = (int32_t)i64Tmp; + + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + assert(!int32_MultiplyOverflow(iXOCapInpF_x100, iaXin_x4)); + assert(!int32_AddOverflow(iXOCapInpF_x100 * iaXin_x4, ibXin * 400)); + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + assert((i32Tmp >= 0) && (i32Tmp <= UINT8_MAX)); + u8XOCapInCtrl = (uint8_t)i32Tmp; + + assert(!int32_MultiplyOverflow(iXOCapOutpF_x100, iaXout_x4)); + assert(!int32_AddOverflow(iXOCapOutpF_x100 * iaXout_x4, ibXout * 400)); + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + assert((i32Tmp >= 0) && (i32Tmp <= UINT8_MAX)); + u8XOCapOutCtrl = (uint8_t)i32Tmp; + + /* Read register and clear fields to be written */ + u32RegVal = ANACTRL->XO32M_CTRL; + u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); + /* Configuration of 32 MHz XO output buffers */ +#if (XO_SLAVE_EN == 0) + u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); +#else + u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; +#endif + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; + /* Write back to register */ + ANACTRL->XO32M_CTRL = u32RegVal; +} + +void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + int64_t i64Tmp; + /* Get Cal values from Flash */ + u32XOTrimValue = GET_32KXO_TRIM(); + /* check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 16; // gain in LSB/pF + ibXin = 12; // offset in LSB + iaXout_x4 = 16; // gain in LSB/pF + ibXout = 11; // offset in LSB + } + + /* In & out load cap calculation with derating */ + i64Tmp = 2 * (int64_t)pi32_32kfXtalIecLoadpF_x100 - (int64_t)pi32_32kfXtalNPcbParCappF_x100 - 130; + assert((i64Tmp <= INT32_MAX) && (i64Tmp >= INT32_MIN)); + iXOCapInpF_x100 = (int32_t)i64Tmp; + i64Tmp = 2 * (int64_t)pi32_32kfXtalIecLoadpF_x100 - (int64_t)pi32_32kfXtalPPcbParCappF_x100 - 41; + assert((i64Tmp <= INT32_MAX) && (i64Tmp >= INT32_MIN)); + iXOCapOutpF_x100 = (int32_t)i64Tmp; + + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + assert(!int32_MultiplyOverflow(iXOCapInpF_x100, iaXin_x4)); + assert(!int32_AddOverflow(iXOCapInpF_x100 * iaXin_x4, ibXin * 400)); + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + assert((i32Tmp >= 0) && (i32Tmp <= UINT8_MAX)); + u8XOCapInCtrl = (uint8_t)i32Tmp; + + assert(!int32_MultiplyOverflow(iXOCapOutpF_x100, iaXout_x4)); + assert(!int32_AddOverflow(iXOCapOutpF_x100 * iaXout_x4, ibXout * 400)); + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + assert((i32Tmp >= 0) && (i32Tmp <= UINT8_MAX)); + u8XOCapOutCtrl = (uint8_t)i32Tmp; + + /* Read register and clear fields to be written */ + u32RegVal = PMC->XTAL32K; + u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); + + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; + + /* Write back to register */ + PMC->XTAL32K = u32RegVal; +} + +void POWER_SetXtal16mhzLdo(void) +{ + uint32_t temp; + const uint32_t u32Mask = + (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); + + const uint32_t u32Value = + (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); + + /* Enable & set-up XTAL 32 MHz clock LDO */ + temp = ANACTRL->LDO_XO32M; + + if ((temp & u32Mask) != u32Value) + { + temp &= ~u32Mask; + + /* + * Enable the XTAL32M LDO + * Adjust the output voltage level, 0x5 for 1.1V + * Adjust the biasing current, 0x2 value + * Stability configuration, 0x1 default mode + */ + temp |= u32Value; + + ANACTRL->LDO_XO32M = temp; + + /* Delay for LDO to be up */ + // CLOCK_uDelay(20); + } + + /* Enable LDO XO32M */ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; +} + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause) +{ + uint32_t reset_cause_reg; + uint32_t boot_mode_reg; + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; +#else /* LPC55S69/28 */ + reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; +#endif + + /* + * Prioritize interrupts source with respect to their critical level + */ +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) + { /* Code Watchdog Reset */ + *p_reset_cause = kRESET_CAUSE_CDOGRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else +#endif + { + if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) + { /* Watchdog Timer Reset */ + *p_reset_cause = kRESET_CAUSE_WDTRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) + { /* ARM System Reset */ + *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; + + if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ + { + *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + + /* + * Prioritise Reset causes, starting from the strongest (Power On Reset) + */ + if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) + { /* Power On Reset */ + *p_reset_cause = kRESET_CAUSE_POR; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) + { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ + *p_reset_cause = kRESET_CAUSE_BODRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) + { /* Hardware Pin Reset */ + *p_reset_cause = kRESET_CAUSE_PADRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) + { /* Software triggered Reset */ + *p_reset_cause = kRESET_CAUSE_SWRRESET; + } + else + { /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + } + } + } + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ + { + /* + * 1- First, save wakeup_io_cause register ... + */ + *p_wakeupio_cause = PMC->WAKEIOCAUSE; + + if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; + + switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) + { + case 1: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; + break; + case 2: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; + break; + case 3: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; + break; + case 4: + *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; + break; + case 5: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; + break; + case 6: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; + break; + case 7: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; + break; + default: + /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + break; + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* + * 2- Next, transfer the control of the 4 wake-up pins + * to IOCON (instead of the Power Management Controller) + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP and POWER-DOWN */ + { + *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; + + /* + * The control of the 4 wake-up pins is already in IOCON, + * so there is nothing special to do. + */ + + if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; + } + else /* POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; + + } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ + + } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ + + } /* if ( boot_mode == 0 ) POWER-UP */ + + } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ +} diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h new file mode 100644 index 0000000000..429d6f6f89 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h @@ -0,0 +1,610 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 2.0.1. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; + +/** + * @brief Analog components power modes control during low power modes + */ +typedef enum pd_bits +{ + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVBAT = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTAL32M = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USB0_PHY = (1UL << 11), + kPDRUNCFG_PD_USB1_PHY = (1UL << 12), + kPDRUNCFG_PD_COMP = (1UL << 13), + kPDRUNCFG_PD_TEMPSENS = (1UL << 14), + kPDRUNCFG_PD_GPADC = (1UL << 15), + kPDRUNCFG_PD_LDOMEM = (1UL << 16), + kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), + kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), + kPDRUNCFG_PD_LDOGPADC = (1UL << 19), + kPDRUNCFG_PD_LDOXO32M = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + kPDRUNCFG_PD_RNG = (1UL << 22), + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/*! @brief BOD VBAT level */ +typedef enum _power_bod_vbat_level +{ + kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ + kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ + kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ + kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ + kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ + kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ + kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ + kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ + kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ + kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ + kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ + kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ + kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ + kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ + kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ + kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ + kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ + kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ + kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ + kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ + kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ + kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ + kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ + kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ + kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ + kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ +} power_bod_vbat_level_t; + +/*! @brief BOD Hysteresis control */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; + +/*! @brief BOD core level */ +typedef enum _power_bod_core_level +{ + kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ + kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ + kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ + kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ + kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ + kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ + kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ + kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ +} power_bod_core_level_t; + +/** + * @brief Device Reset Causes + */ +typedef enum _power_device_reset_cause +{ + kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ + kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ + kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ + kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ + kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ + kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ + kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ + /* Reset causes in DEEP-POWER-DOWN low power mode */ + kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ + kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ + kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish + which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish + which of these 3 events occured first) */ + /* Miscallenous */ + kRESET_CAUSE_NOT_RELEVANT = + 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ + kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an + application point of view. */ +} power_device_reset_cause_t; + +/** + * @brief Device Boot Modes + */ +typedef enum _power_device_boot_mode +{ + kBOOT_MODE_POWER_UP = + 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ + kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ + kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ + kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ +} power_device_boot_mode_t; + +/** + * @brief SRAM instances retention control during low power modes + */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ + (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ + (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ + (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ + (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ + (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \ + (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ + (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ + (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \ + (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \ + (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \ + (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \ + (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \ + (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \ + (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ + (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \ + (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ + +/** + * @brief Low Power Modes Wake up sources + */ +#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +// reserved (1ULL << 25) +// reserved (1ULL << 26) +#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +// reserved (1ULL << 39) +// reserved (1ULL << 40) +// reserved (1ULL << 41) +#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ +// reserved (1ULL << 43) +// reserved (1ULL << 44) +// reserved (1ULL << 45) +// reserved (1ULL << 46) +#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_VIO (1ULL << 53) +#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ +#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ +#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ +#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ +#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ +// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) +// reserved WAKEUP_PVTVF0_RED (1ULL << 61) +// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) +#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ + +/** + * @brief Sleep Postpone + */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS \ + (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ + peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_SDMA0 \ + (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA1 \ + (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ + (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ + LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ + +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ +/** + * @brief Wake up I/O sources + */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ + +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ + +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ + +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ + 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ + 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ + 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ + 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ + +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ + (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ + (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ + (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ + (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + PMC->PDRUNCFGSET0 = (uint32_t)en; +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + PMC->PDRUNCFGCLR0 = (uint32_t)en; +} + +/*! + * @brief set BOD VBAT level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodVbatReset VBAT brown out detect reset + */ +static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) +{ + PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | + PMC_BODVBAT_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset ? 1UL : 0UL); +} + +#if defined(PMC_BODCORE_TRIGLVL_MASK) +/*! + * @brief set BOD core level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodCoreReset core brown out detect reset + */ +static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) +{ + PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | + PMC_BODCORE_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset ? 1UL : 0UL); +} +#endif + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * This MUST BE EXECUTED outside the Flash: + * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is + * preferable to have all functions defined in this file implemented in ROM. + * + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void); + +/** + * @brief Configures and enters in DEEP-SLEEP low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param hardware_wake_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl); + +/** + * @brief Configures and enters in POWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are + RESERVED. + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance + containing the stack used to call this function WILL BE preserved during low power (via parameter + "sram_retention_ctrl") + * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ + +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl); + +/** + * @brief Configures and enters in DEEPPOWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param wakeup_io_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if + DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl); + +/** + * @brief Configures and enters in SLEEP low power mode + * @return Nothing + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz); + +/** + * @brief Sets board-specific trim values for 16MHz XTAL + * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @return none + * @note Following default Values can be used: + * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 + * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100); +/** + * @brief Sets board-specific trim values for 32kHz XTAL + * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + + * @return none + * @note Following default Values can be used: + * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 + * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100); +/** + * @brief Enables and sets LDO for 16MHz XTAL + * + * @return none + */ +extern void POWER_SetXtal16mhzLdo(void); + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause); +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_POWER_H_ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c new file mode 100644 index 0000000000..33c04fc88c --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + assert(regIndex < SYSCON_PRESETCTRLSET_COUNT); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + assert(regIndex < SYSCON_PRESETCTRLSET_COUNT); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h new file mode 100644 index 0000000000..70bb1bc777 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ + kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ + kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define AES_RSTS \ + { \ + kAES_RST_SHIFT_RSTn \ + } /* Reset bits for AES peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define OTP_RSTS \ + { \ + kOTP_RST_SHIFT_RSTn \ + } /* Reset bits for OTP peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn, kGPIOSECINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SDIO_RST \ + { \ + kSDIO_RST_SHIFT_RSTn \ + } /* Reset bits for SDIO peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define SPIFI_RSTS \ + { \ + kSPIFI_RST_SHIFT_RSTn \ + } /* Reset bits for SPIFI peripheral */ +#define USB0D_RST \ + { \ + kUSB0D_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define USB1H_RST \ + { \ + kUSB1H_RST_SHIFT_RSTn \ + } /* Reset bits for USB1H peripheral */ +#define USB1D_RST \ + { \ + kUSB1D_RST_SHIFT_RSTn \ + } /* Reset bits for USB1D peripheral */ +#define USB1RAM_RST \ + { \ + kUSB1RAM_RST_SHIFT_RSTn \ + } /* Reset bits for USB1RAM peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ +#define CAPT_RSTS_N \ + { \ + kCAP0_RST_SHIFT_RSTn \ + } /* Reset bits for CAPT peripheral */ +#define PLU_RSTS_N \ + { \ + kPLULUT_RST_SHIFT_RSTn \ + } /* Reset bits for PLU peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define POWERQUAD_RSTS \ + { \ + kPOWERQUAD_RST_SHIFT_RSTn \ + } /* Reset bits for Powerquad peripheral */ +#define CASPER_RSTS \ + { \ + kCASPER_RST_SHIFT_RSTn \ + } /* Reset bits for Casper peripheral */ +#define HASHCRYPT_RSTS \ + { \ + kHASHCRYPT_RST_SHIFT_RSTn \ + } /* Reset bits for Hashcrypt peripheral */ +#define PUF_RSTS \ + { \ + kPUF_RST_SHIFT_RSTn \ + } /* Reset bits for PUF peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; +#define USB1RAM_RSTS USB1RAM_RST +#define USB1H_RSTS USB1H_RST +#define USB1D_RSTS USB1D_RST +#define USB0HSL_RSTS USB0HSL_RST +#define USB0HMR_RSTS USB0HMR_RST +#define USB0D_RSTS USB0D_RST +#define SDIO_RSTS SDIO_RST + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h new file mode 100644 index 0000000000..c936ea7f36 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ADC.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ADC.h new file mode 100644 index 0000000000..a45f4cc5d0 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ADC.h @@ -0,0 +1,1204 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for ADC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_ADC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for ADC + * + * CMSIS Peripheral Access Layer for ADC + */ + +#if !defined(PERI_ADC_H_) +#define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Size of Registers Arrays */ +#define ADC_TCTRL_COUNT 16u +#define ADC_FCTRL_COUNT 2u +#define ADC_GCC_COUNT 2u +#define ADC_GCR_COUNT 2u +#define ADC_CMD_COUNT 15u +#define ADC_CV_COUNT 4u +#define ADC_RESFIFO_COUNT 2u +#define ADC_CAL_GAR_COUNT 33u +#define ADC_CAL_GBR_COUNT 33u + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[ADC_TCTRL_COUNT]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[ADC_FCTRL_COUNT]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[ADC_GCC_COUNT]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[ADC_GCR_COUNT]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[ADC_CMD_COUNT]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[ADC_RESFIFO_COUNT]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[ADC_CAL_GAR_COUNT]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[ADC_CAL_GBR_COUNT]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_9[2680]; + __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) + +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) + +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) + +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) + +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) + +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) + +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) + +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) + +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name TST - ADC Test Register */ +/*! @{ */ + +#define ADC_TST_CST_LONG_MASK (0x1U) +#define ADC_TST_CST_LONG_SHIFT (0U) +/*! CST_LONG - Calibration Sample Time Long + * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. + * 0b1..Increased sample time. 67 ADCK cycles total sample time. + */ +#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) + +#define ADC_TST_FOFFM_MASK (0x100U) +#define ADC_TST_FOFFM_SHIFT (8U) +/*! FOFFM - Force M-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on MDAC. + */ +#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) + +#define ADC_TST_FOFFP_MASK (0x200U) +#define ADC_TST_FOFFP_SHIFT (9U) +/*! FOFFP - Force P-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on PDAC. + */ +#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) + +#define ADC_TST_FOFFM2_MASK (0x400U) +#define ADC_TST_FOFFM2_SHIFT (10U) +/*! FOFFM2 - Force M-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on MDAC. + */ +#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) + +#define ADC_TST_FOFFP2_MASK (0x800U) +#define ADC_TST_FOFFP2_SHIFT (11U) +/*! FOFFP2 - Force P-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on PDAC. + */ +#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) + +#define ADC_TST_TESTEN_MASK (0x800000U) +#define ADC_TST_TESTEN_SHIFT (23U) +/*! TESTEN - Enable test configuration + * 0b0..Normal operation. Test configuration not enabled. + * 0b1..Hardware BIST Test in progress. + */ +#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_ADC_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_AHB_SECURE_CTRL.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_AHB_SECURE_CTRL.h new file mode 100644 index 0000000000..9ddb40cbba --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_AHB_SECURE_CTRL.h @@ -0,0 +1,3472 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for AHB_SECURE_CTRL +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_AHB_SECURE_CTRL.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for AHB_SECURE_CTRL + * + * CMSIS Peripheral Access Layer for AHB_SECURE_CTRL + */ + +#if !defined(PERI_AHB_SECURE_CTRL_H_) +#define PERI_AHB_SECURE_CTRL_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Size of Registers Arrays */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT 3u +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT 4u +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_COUNT 2u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_COUNT 2u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_COUNT 2u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_COUNT 2u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_COUNT 1u +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_COUNT 1u +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT 12u +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT 12u + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_COUNT]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_COUNT]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[AHB_SECURE_CTRL_SEC_CTRL_RAMX_COUNT]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_COUNT]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM0[AHB_SECURE_CTRL_SEC_CTRL_RAM0_COUNT]; + uint8_t RESERVED_1[8]; + struct { /* offset: 0x70, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_COUNT]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM1[AHB_SECURE_CTRL_SEC_CTRL_RAM1_COUNT]; + uint8_t RESERVED_2[8]; + struct { /* offset: 0x90, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_COUNT]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM2[AHB_SECURE_CTRL_SEC_CTRL_RAM2_COUNT]; + uint8_t RESERVED_3[8]; + struct { /* offset: 0xB0, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_COUNT]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM3[AHB_SECURE_CTRL_SEC_CTRL_RAM3_COUNT]; + uint8_t RESERVED_4[8]; + struct { /* offset: 0xD0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_COUNT]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM4[AHB_SECURE_CTRL_SEC_CTRL_RAM4_COUNT]; + uint8_t RESERVED_5[12]; + struct { /* offset: 0xF0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_COUNT]; + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + uint8_t RESERVED_7[8]; + struct { /* offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT10[AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_COUNT]; + uint8_t RESERVED_8[12]; + struct { /* offset: 0x160, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_COUNT]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[AHB_SECURE_CTRL_SEC_CTRL_USB_HS_COUNT]; + uint8_t RESERVED_9[3212]; + __I uint32_t SEC_VIO_ADDR[AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_10[80]; + __I uint32_t SEC_VIO_MISC_INFO[AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_11[80]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_12[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ + __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ + uint8_t RESERVED_14[36]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_15[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_16[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) + +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) +/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) +/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) +/*! MAILBOX_RULE - Inter CPU communication Mailbox + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) +/*! SDIO_RULE - SDMMC card interface + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - security violation address for AHB port */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0010..CPU1 Data. + * 0b0011..CPU1 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1000..SDIO. + * 0b1001..PowerQuad. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b0..Pin state is blocked to non-secure world. + * 0b1..Pin state is readable by non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) +/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) +/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) +/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) +/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) +/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) +/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) +/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) +/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) +/*! UTICK_IRQ - Micro Tick Timer interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) +/*! MRT_IRQ - Multi-Rate Timer interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) +/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) +/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) +/*! SCT_IRQ - SCTimer/PWM interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) +/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) +/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) +/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) +/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) +/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) +/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) +/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) +/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) +/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) +/*! ADC_IRQ - General Purpose ADC interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) +/*! ACMP_IRQ - Analog Comparator interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) +/*! USB0_IRQ - USB Full Speed Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) +/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) +/*! MAILBOX_IRQ - Mailbox interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) +/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) +/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) +/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) +/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) +/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) +/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) +/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) +/*! SDIO_IRQ - SDIO Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) +/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) +/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) +/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) +/*! USB1_IRQ - USB High Speed Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) +/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) +/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) +/*! PLU_IRQ - Programmable Look-Up Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) +/*! SEC_VIO_IRQ - Security Violation interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) +/*! SHA_IRQ - HASH-AES interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) +/*! CASPER_IRQ - CASPER interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) +/*! PUFKEY_IRQ - PUF interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) +/*! PQ_IRQ - Power Quad interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) +/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) +/*! LSPI_HS_IRQ - High Speed SPI interrupt + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) +/*! SDIO - SDIO. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) +/*! PQ - Power Quad. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) +/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) +/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b00..Secure and Priviledge user access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b11..Non-secure and Non-priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. + * 0b01..Restricted mode. + * 0b10..Writable. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b01..Restricted mode. + * 0b10..Secure control registers can be written. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b01..Restricted mode. + * 0b10..Disable check. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b01..Restricted mode. + * 0b10..Disable check. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b01..Restricted mode. + * 0b10..Disable check. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b01..Disable abort fort secure checker. + * 0b10..Enable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b01..Simple master in tier mode. + * 0b10..Simple master in strict mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b01..Smart master in tier mode. + * 0b10..Smart master in strict mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b01..IDAU is disable. + * 0b10..IDAU is enabled. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b01..Restricted mode. + * 0b10..Secure control registers can be written. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b01..Enabled (restricted mode) + * 0b10..Disable check. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b01..Enabled (restricted mode) + * 0b10..Disable check. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b01..Enabled (restricted mode) + * 0b10..Disable check. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b01..Disable abort fort secure checker. + * 0b10..Enable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b01..Simple master in tier mode. + * 0b10..Simple master in strict mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b01..Smart master in tier mode. + * 0b10..Smart master in strict mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b01..IDAU is disable. + * 0b10..IDAU is enabled. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_AHB_SECURE_CTRL_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ANACTRL.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ANACTRL.h new file mode 100644 index 0000000000..c0ae093766 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_ANACTRL.h @@ -0,0 +1,934 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for ANACTRL +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_ANACTRL.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for ANACTRL + * + * CMSIS Peripheral Access Layer for ANACTRL + */ + +#if !defined(PERI_ANACTRL_H_) +#define PERI_ANACTRL_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_4[100]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ + uint8_t RESERVED_5[72]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ + __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ + +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) + +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit + * when the measurement cycle has completed and there is valid capture data in the CAPVAL field + * (bits 30:0). + */ +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ + +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) +/*! ENA_48MHZCLK - 48 MHz clock control. + * 0b0..Reserved. + * 0b1..48 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +/*! DAC_TRIM - Frequency trim. */ +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) + +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, + * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF + * packets. + */ +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. */ +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. */ +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ + +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses + * the threshold voltage of a SLVT transistor, this output signal will go high. It is also + * possible to observe the clk_valid signal. + */ +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ + +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ +/*! @{ */ + +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - Xo in slave mode. */ +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ +/*! @{ */ + +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) + +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) + +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) + +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) + +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) */ +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) + +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) + +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) */ +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) + +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) + +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) */ +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ + +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. */ +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. */ +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name AUX_BIAS - AUX_BIAS */ +/*! @{ */ + +#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) +#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) +/*! VREF1VENABLE - Control output of 1V reference voltage. + * 0b0..Output of 1V reference voltage buffer is bypassed. + * 0b1..Output of 1V reference voltage is enabled. + */ +#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) + +#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) +#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) +/*! ITRIM - current trimming control word. */ +#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) + +#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) +#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) +/*! PTATITRIM - current trimming control word for ptat current. */ +#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) +#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) +/*! VREF1VTRIM - voltage trimming control word. */ +#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) +/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. */ +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) +/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) +/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) + +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +/*! usb_id_ext - Override value for ID if using external detectors. */ +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) +/*! @} */ + +/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +/*! trim_usbphy_tx_d_cal - . */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +/*! trim_usbphy_tx_cal45dp - . */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +/*! trim_usbphy_tx_cal45dm - . */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +/*! trim_usb2_refbias_tst - . */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +/*! trim_usb2_refbias_vbgadj - . */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +/*! trim_pll_ctrl0_div_sel - . */ +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_ANACTRL_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CASPER.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CASPER.h new file mode 100644 index 0000000000..df622f6807 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CASPER.h @@ -0,0 +1,486 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for CASPER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CASPER.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CASPER + * + * CMSIS Peripheral Access Layer for CASPER + */ + +#if !defined(PERI_CASPER_H_) +#define PERI_CASPER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ + +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) + +#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code + * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed + * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + */ +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) + +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) + +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees + * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 + * bit operation. Ideally not in the same RAM as the AB values + */ +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ + +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. */ +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) + +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. */ +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) + +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) + +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally + * not in the same RAM as the AB and CD values + */ +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) + +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ + +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one + * op - does not iterate, write N means N control pairs to load + */ +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) + +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) + +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +/*! CTRLOFF - DWord Offset of CTRL pair to load next. */ +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ + +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) + +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) + +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ + +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ + +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ + +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ + +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ + +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ + +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ + +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ + +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ + +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ + +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ + +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ + +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values */ +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ + +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values */ +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ + +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) + +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CASPER_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CRC.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CRC.h new file mode 100644 index 0000000000..0a2f024c83 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CRC.h @@ -0,0 +1,243 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for CRC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CRC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CRC + * + * CMSIS Peripheral Access Layer for CRC + */ + +#if !defined(PERI_CRC_H_) +#define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ + +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial */ +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) + +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) */ +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) + +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA */ +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) + +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM */ +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) + +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM */ +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ + +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with + * selected bit order and 1's complement pre-processes. A write access to this register will + * overrule the CRC calculation in progresses. + */ +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ + +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. */ +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ + +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with + * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and + * accept back-to-back transactions. + */ +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CRC_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CTIMER.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CTIMER.h new file mode 100644 index 0000000000..2dff9ef7cb --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_CTIMER.h @@ -0,0 +1,657 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for CTIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CTIMER.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CTIMER + * + * CMSIS Peripheral Access Layer for CTIMER + */ + +#if !defined(PERI_CTIMER_H_) +#define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Size of Registers Arrays */ +#define CTIMER_MR_COUNT 4u +#define CTIMER_CR_COUNT 4u +#define CTIMER_MSR_COUNT 4u + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[CTIMER_MR_COUNT]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[CTIMER_CR_COUNT]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[CTIMER_MSR_COUNT]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0. */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1. */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2. */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3. */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event. */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event. */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event. */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event. */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value. */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale counter value. */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value. */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value. */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value. */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins + * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the + * capture-edge event specified in bits 7:5 occurs. + */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ + +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +/*! SHADOW - Timer counter match shadow value. */ +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + +/* Backward compatibility for bitfield SHADOW */ +#define CTIMER_MSR_MATCH_SHADOW_MASK CTIMER_MSR_SHADOW_MASK +#define CTIMER_MSR_MATCH_SHADOW_SHIFT CTIMER_MSR_SHADOW_SHIFT +#define CTIMER_MSR_MATCH_SHADOW CTIMER_MSR_SHADOW + + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CTIMER_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DBGMAILBOX.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DBGMAILBOX.h new file mode 100644 index 0000000000..a18acfcbf0 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DBGMAILBOX.h @@ -0,0 +1,245 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for DBGMAILBOX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_DBGMAILBOX.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for DBGMAILBOX + * + * CMSIS Peripheral Access Layer for DBGMAILBOX + */ + +#if !defined(PERI_DBGMAILBOX_H_) +#define PERI_DBGMAILBOX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DBGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DBGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ + +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation */ +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) */ +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) */ +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) */ +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to + * this bit will cause a soft reset for DM. + */ +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is + * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + */ +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ + +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +/*! REQ - Request Value */ +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ + +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - The Return value from ROM. */ +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ + +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification value. */ +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DBGMAILBOX_Register_Masks */ + + +/*! + * @} + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DBGMAILBOX_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DMA.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DMA.h new file mode 100644 index 0000000000..b6777ba2e1 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_DMA.h @@ -0,0 +1,740 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for DMA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_DMA.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for DMA + * + * CMSIS Peripheral Access Layer for DMA + */ + +#if !defined(PERI_DMA_H_) +#define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(DMA_REQUEST_SOURCE_T_) +#define DMA_REQUEST_SOURCE_T_ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ + kDma0RequestHashCrypt = 0U, /**< HashCrypt */ + kDma1RequestHashCrypt = 0U, /**< HashCrypt */ +} dma_request_source_t; + +/* @} */ +#endif /* DMA_REQUEST_SOURCE_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Size of Registers Arrays */ +#define DMA_COMMON_COUNT 1u +#define DMA_CHANNEL_COUNT 23u + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[DMA_COMMON_COUNT]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10, irregular array, not all indices are valid */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10, irregular array, not all indices are valid */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10, irregular array, not all indices are valid */ + uint8_t RESERVED_0[4]; + } CHANNEL[DMA_CHANNEL_COUNT]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ + +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ + +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ + +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the + * table must begin on a 512 byte boundary. + */ +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + */ +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears + * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits + * are reserved. + */ +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + */ +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + */ +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is + * not active. 1 = error interrupt is active. + */ +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The + * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = + * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n + * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are + * reserved. + */ +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt A is not active. 1 = the DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt B is not active. 1 = the DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits + * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the + * VALIDPENDING control bit for DMA channel n + */ +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number + * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = + * sets the TRIG bit for DMA channel n. + */ +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. + * 1 = aborts DMA operations on channel n. + */ +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when + * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). + * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many + * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that + * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: + * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = + * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The + * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even + * multiple of the burst size. + */ +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority + * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + */ +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (23U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes + * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller + * uses this bit field during transfer to count down. Hence, it cannot be used by software to read + * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 + * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of + * 1,024 transfers will be performed. + */ +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (23U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DMA_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH.h new file mode 100644 index 0000000000..e62b88867c --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH.h @@ -0,0 +1,421 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for FLASH +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FLASH.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FLASH + * + * CMSIS Peripheral Access Layer for FLASH + */ + +#if !defined(PERI_FLASH_H_) +#define PERI_FLASH_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Size of Registers Arrays */ +#define FLASH_DATAW_COUNT 4u + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[FLASH_DATAW_COUNT]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ + +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. */ +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ + +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. */ +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. */ +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. */ +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ + +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. */ +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ + +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ + +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. */ +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) + +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. */ +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) + +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. */ +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) + +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. */ +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. */ +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) + +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. */ +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) + +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. */ +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) + +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. */ +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. */ +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) + +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. */ +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) + +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. */ +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) + +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. */ +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) + +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. */ +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) + +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. */ +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) + +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. */ +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. */ +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) + +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. */ +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) + +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. */ +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) + +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. */ +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. */ +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) + +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. */ +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) + +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. */ +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) + +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. */ +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ + +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. */ +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) + +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. */ +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. */ +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. */ +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FLASH_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CFPA.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CFPA.h new file mode 100644 index 0000000000..00b8a725b0 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CFPA.h @@ -0,0 +1,639 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for FLASH_CFPA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FLASH_CFPA.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FLASH_CFPA + * + * CMSIS Peripheral Access Layer for FLASH_CFPA + */ + +#if !defined(PERI_FLASH_CFPA_H_) +#define PERI_FLASH_CFPA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Size of Registers Arrays */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_PRINCE_REGION0_IV_CODE_PRINCE_REGION0_IV_CODE_COUNT 14u +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_PRINCE_REGION0_IV_CODE_CORE_PRINCE_REGION0_IV_BODY_COUNT 12u +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_PRINCE_REGION1_IV_CODE_PRINCE_REGION1_IV_CODE_COUNT 14u +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_PRINCE_REGION1_IV_CODE_CORE_PRINCE_REGION1_IV_BODY_COUNT 12u +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_PRINCE_REGION2_IV_CODE_PRINCE_REGION2_IV_CODE_COUNT 14u +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_PRINCE_REGION2_IV_CODE_CORE_PRINCE_REGION2_IV_BODY_COUNT 12u +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT 56u +#define FLASH_CFPA_SHA256_DIGEST_COUNT 8u + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< offset: 0x0 */ + __IO uint32_t VERSION; /**< offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[FLASH_CFPA_PRINCE_REGION0_IV_CODE_PRINCE_REGION0_IV_CODE_PRINCE_REGION0_IV_CODE_COUNT]; /**< array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[FLASH_CFPA_PRINCE_REGION0_IV_CODE_PRINCE_REGION0_IV_CODE_CORE_PRINCE_REGION0_IV_BODY_COUNT]; /**< array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[FLASH_CFPA_PRINCE_REGION1_IV_CODE_PRINCE_REGION1_IV_CODE_PRINCE_REGION1_IV_CODE_COUNT]; /**< array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[FLASH_CFPA_PRINCE_REGION1_IV_CODE_PRINCE_REGION1_IV_CODE_CORE_PRINCE_REGION1_IV_BODY_COUNT]; /**< array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[FLASH_CFPA_PRINCE_REGION2_IV_CODE_PRINCE_REGION2_IV_CODE_PRINCE_REGION2_IV_CODE_COUNT]; /**< array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[FLASH_CFPA_PRINCE_REGION2_IV_CODE_PRINCE_REGION2_IV_CODE_CORE_PRINCE_REGION2_IV_BODY_COUNT]; /**< array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[FLASH_CFPA_CUSTOMER_DEFINED_COUNT]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[FLASH_CFPA_SHA256_DIGEST_COUNT]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - */ +/*! @{ */ + +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - */ +/*! @{ */ + +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - */ +/*! @{ */ + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) +/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) + +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] */ +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ + +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ + +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FLASH_CFPA_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CMPA.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CMPA.h new file mode 100644 index 0000000000..e0d21d4d6d --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_CMPA.h @@ -0,0 +1,713 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for FLASH_CMPA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FLASH_CMPA.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FLASH_CMPA + * + * CMSIS Peripheral Access Layer for FLASH_CMPA + */ + +#if !defined(PERI_FLASH_CMPA_H_) +#define PERI_FLASH_CMPA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Size of Registers Arrays */ +#define FLASH_CMPA_ROTKH_COUNT 8u +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT 56u +#define FLASH_CMPA_SHA256_DIGEST_COUNT 8u + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< offset: 0x4 */ + __IO uint32_t USB_ID; /**< offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ROTKH[FLASH_CMPA_ROTKH_COUNT]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[FLASH_CMPA_CUSTOMER_DEFINED_COUNT]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[FLASH_CMPA_SHA256_DIGEST_COUNT]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_ISP + * 0b010..UART ISP + * 0b011..SPI Slave ISP + * 0b100..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b01..96MHz FRO + * 0b10..48MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle + * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO + * pin + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) +/*! @} */ + +/*! @name USB_ID - */ +/*! @{ */ + +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) + +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name CC_SOCU_PIN - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. */ +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] */ +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name CC_SOCU_DFLT - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] */ +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ +/*! @{ */ + +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +/*! RSA4K - Use RSA4096 keys only. + * 0b00..Allow RSA2048 and higher + * 0b01..RSA4096 only + * 0b10..RSA4096 only + * 0b11..RSA4096 only + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) +/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +/*! SKIP_DICE - Skip DICE computation + * 0b00..Enable DICE + * 0b01..Disable DICE + * 0b10..Disable DICE + * 0b11..Disable DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +/*! TZM_IMAGE_TYPE - TrustZone-M mode + * 0b00..TZ-M image mode is taken from application image header + * 0b01..TZ-M disabled image, boots to non-secure mode + * 0b10..TZ-M enabled image, boots to secure mode + * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +/*! BLOCK_SET_KEY - Block PUF key code generation + * 0b00..Allow PUF Key Code generation + * 0b01..Disable PUF Key Code generation + * 0b10..Disable PUF Key Code generation + * 0b11..Disable PUF Key Code generation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +/*! BLOCK_ENROLL - Block PUF enrollement + * 0b00..Allow PUF enroll operation + * 0b01..Disable PUF enroll operation + * 0b10..Disable PUF enroll operation + * 0b11..Disable PUF enroll operation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +/*! SEC_BOOT_EN - Secure boot enable + * 0b00..Plain image (internal flash with or without CRC) + * 0b01..Boot signed images. (internal flash, RSA signed) + * 0b10..Boot signed images. (internal flash, RSA signed) + * 0b11..Boot signed images. (internal flash, RSA signed) + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +/*! ADDR0_PRG - Programmable portion of the base address of region 0 */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +/*! ADDR1_PRG - Programmable portion of the base address of region 1 */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +/*! ADDR2_PRG - Programmable portion of the base address of region 2 */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) +/*! LOCK_REG0 - Lock PRINCE region0 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) +/*! LOCK_REG1 - Lock PRINCE region1 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 32kHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 16MHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ + +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FLASH_CMPA_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_KEY_STORE.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_KEY_STORE.h new file mode 100644 index 0000000000..e001593288 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLASH_KEY_STORE.h @@ -0,0 +1,582 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for FLASH_KEY_STORE +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FLASH_KEY_STORE.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FLASH_KEY_STORE + * + * CMSIS Peripheral Access Layer for FLASH_KEY_STORE + */ + +#if !defined(PERI_FLASH_KEY_STORE_H_) +#define PERI_FLASH_KEY_STORE_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Size of Registers Arrays */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT 298u +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_SBKEY_KEY_CODE_SBKEY_KEY_CODE_COUNT 14u +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_SBKEY_KEY_CODE_CORE_SBKEY_BODY_COUNT 12u +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_USER_KEK_KEY_CODE_USER_KEK_KEY_CODE_COUNT 14u +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_USER_KEK_KEY_CODE_CORE_USER_KEK_BODY_COUNT 12u +#define FLASH_KEY_STORE_UDS_KEY_CODE_UDS_KEY_CODE_UDS_KEY_CODE_COUNT 14u +#define FLASH_KEY_STORE_UDS_KEY_CODE_UDS_KEY_CODE_CORE_UDS_BODY_COUNT 12u +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_PRINCE_REGION0_KEY_CODE_PRINCE_REGION0_KEY_CODE_COUNT 14u +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_PRINCE_REGION0_KEY_CODE_CORE_PRINCE_REGION0_BODY_COUNT 12u +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_PRINCE_REGION1_KEY_CODE_PRINCE_REGION1_KEY_CODE_COUNT 14u +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_PRINCE_REGION1_KEY_CODE_CORE_PRINCE_REGION1_BODY_COUNT 12u +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_PRINCE_REGION2_KEY_CODE_PRINCE_REGION2_KEY_CODE_COUNT 14u +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_PRINCE_REGION2_KEY_CODE_CORE_PRINCE_REGION2_BODY_COUNT 12u + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[FLASH_KEY_STORE_ACTIVATION_CODE_COUNT]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[FLASH_KEY_STORE_SBKEY_KEY_CODE_SBKEY_KEY_CODE_SBKEY_KEY_CODE_COUNT]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[FLASH_KEY_STORE_SBKEY_KEY_CODE_SBKEY_KEY_CODE_CORE_SBKEY_BODY_COUNT]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[FLASH_KEY_STORE_USER_KEK_KEY_CODE_USER_KEK_KEY_CODE_USER_KEK_KEY_CODE_COUNT]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[FLASH_KEY_STORE_USER_KEK_KEY_CODE_USER_KEK_KEY_CODE_CORE_USER_KEK_BODY_COUNT]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[FLASH_KEY_STORE_UDS_KEY_CODE_UDS_KEY_CODE_UDS_KEY_CODE_COUNT]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[FLASH_KEY_STORE_UDS_KEY_CODE_UDS_KEY_CODE_CORE_UDS_BODY_COUNT]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_PRINCE_REGION0_KEY_CODE_PRINCE_REGION0_KEY_CODE_COUNT]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_PRINCE_REGION0_KEY_CODE_CORE_PRINCE_REGION0_BODY_COUNT]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_PRINCE_REGION1_KEY_CODE_PRINCE_REGION1_KEY_CODE_COUNT]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_PRINCE_REGION1_KEY_CODE_CORE_PRINCE_REGION1_BODY_COUNT]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_PRINCE_REGION2_KEY_CODE_PRINCE_REGION2_KEY_CODE_COUNT]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_PRINCE_REGION2_KEY_CODE_CORE_PRINCE_REGION2_BODY_COUNT]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ + +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ + +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . */ +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . */ +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +/*! FIELD - . */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FLASH_KEY_STORE_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLEXCOMM.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLEXCOMM.h new file mode 100644 index 0000000000..884ebd8e21 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_FLEXCOMM.h @@ -0,0 +1,265 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for FLEXCOMM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FLEXCOMM.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FLEXCOMM + * + * CMSIS Peripheral Access Layer for FLEXCOMM + */ + +#if !defined(PERI_FLEXCOMM_H_) +#define PERI_FLEXCOMM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ + +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID. */ +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ + +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +/*! APERTURE - size aperture for the register port on the bus (APB or AHB). */ +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) + +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. */ +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) + +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. */ +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) + +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. */ +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FLEXCOMM_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GINT.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GINT.h new file mode 100644 index 0000000000..17d4d16b92 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GINT.h @@ -0,0 +1,237 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for GINT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_GINT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for GINT + * + * CMSIS Peripheral Access Layer for GINT + */ + +#if !defined(PERI_GINT_H_) +#define PERI_GINT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Size of Registers Arrays */ +#define GINT_PORT_POL_COUNT 2u +#define GINT_PORT_ENA_COUNT 2u + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[GINT_PORT_POL_COUNT]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[GINT_PORT_ENA_COUNT]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ + +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ + +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n + * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to + * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin + * contributes to the group interrupt. + */ +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ + +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the + * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is + * enabled and contributes to the grouped interrupt. + */ +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_GINT_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GPIO.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GPIO.h new file mode 100644 index 0000000000..37319caf13 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_GPIO.h @@ -0,0 +1,363 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for GPIO +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_GPIO.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for GPIO + * + * CMSIS Peripheral Access Layer for GPIO + */ + +#if !defined(PERI_GPIO_H_) +#define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Size of Registers Arrays */ +#define GPIO_B_COUNT 2u +#define GPIO_B_B_COUNT 32u +#define GPIO_W_COUNT 2u +#define GPIO_W_W_COUNT 32u +#define GPIO_DIR_COUNT 2u +#define GPIO_MASK_COUNT 2u +#define GPIO_PIN_COUNT 2u +#define GPIO_MPIN_COUNT 2u +#define GPIO_SET_COUNT 2u +#define GPIO_CLR_COUNT 2u +#define GPIO_NOT_COUNT 2u +#define GPIO_DIRSET_COUNT 2u +#define GPIO_DIRCLR_COUNT 2u +#define GPIO_DIRNOT_COUNT 2u + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[GPIO_B_COUNT][GPIO_B_B_COUNT]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1, irregular array, not all indices are valid */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[GPIO_W_COUNT][GPIO_W_W_COUNT]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[GPIO_DIR_COUNT]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[GPIO_MASK_COUNT]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[GPIO_PIN_COUNT]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[GPIO_MPIN_COUNT]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[GPIO_SET_COUNT]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[GPIO_CLR_COUNT]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[GPIO_NOT_COUNT]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[GPIO_DIRSET_COUNT]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[GPIO_DIRCLR_COUNT]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[GPIO_DIRNOT_COUNT]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4, irregular array, not all indices are valid */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, + * except that pins configured as analog I/O always read as 0. One register for each port pin. + * Supported pins depends on the specific device and package. Write: loads the pin's output bit. + * One register for each port pin. Supported pins depends on the specific device and package. + */ +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is + * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be + * read. Writing any value other than 0 will set the output bit. One register for each port pin. + * Supported pins depends on the specific device and package. + */ +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = input. 1 = output. + */ +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = + * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = + * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit + * not affected. + */ +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. + * 1 = Read: pin is high; write: set output bit. + */ +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK + * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 + * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit + * if the corresponding bit in the MASK register is 0. + */ +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ + +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output + * bit; write: set output bit. + */ +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = No operation. 1 = Clear output bit. + */ +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = no operation. 1 = Toggle output bit. + */ +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Set direction bit. + */ +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Clear direction bit. + */ +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends + * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + */ +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_GPIO_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_HASHCRYPT.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_HASHCRYPT.h new file mode 100644 index 0000000000..8904ef8858 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_HASHCRYPT.h @@ -0,0 +1,595 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for HASHCRYPT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_HASHCRYPT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for HASHCRYPT + * + * CMSIS Peripheral Access Layer for HASHCRYPT + */ + +#if !defined(PERI_HASHCRYPT_H_) +#define PERI_HASHCRYPT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Size of Registers Arrays */ +#define HASHCRYPT_ALIAS_COUNT 7u +#define HASHCRYPT_DIGEST0_COUNT 8u +#define HASHCRYPT_MASK_COUNT 4u + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[HASHCRYPT_ALIAS_COUNT]; /**< array offset: 0x24, array step: 0x4 */ + __I uint32_t DIGEST0[HASHCRYPT_DIGEST0_COUNT]; /**< array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[HASHCRYPT_MASK_COUNT]; /**< array offset: 0x90, array step: 0x4 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ +/*! @{ */ + +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) + +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) + +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) + +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) + +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB + * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For + * cryptographic swapping, see the CRYPTCFG register. + */ +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ + +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) + +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) + +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) + +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) + +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) + +#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) +#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from + * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, + * it has to compute the full ICB, quicker when not 0. + */ +#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ + +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) + +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) + +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ + +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +/*! WAITING - Write 1 to clear mask. */ +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) + +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +/*! DIGEST - Write 1 to clear mask. */ +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) + +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +/*! ERROR - Write 1 to clear mask. */ +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ + +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER - Enables mastering. + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) + +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks + * to copy starting at MEMADDR. This register will decrement after each block is copied, ending + * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA + * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set + * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) + * blocks to hash. + */ +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ + +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will + * advance as it processes the words. If it fails with a bus error, the register will contain + * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be + * able to address SPIFI. + */ +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ + +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - */ +/*! @{ */ + +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/*! @name DIGEST0 - */ +/*! @{ */ + +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. */ +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) +/*! @} */ + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ + +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read + * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). */ +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). */ +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) + +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. + * Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) + +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) + +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) + +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) + +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for + * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if + * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other + * use CTR should use ECB directly and do its own XOR and so on. + */ +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) + +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". */ +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) + +#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) +#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) +/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the + * counter is assumed to occupy the low order bits of the IV. + * 0b00..32 bits of the IV/ctr are used (from 127:96) + * 0b01..64 bits of the IV/ctr are used (from 127:64) + * 0b10..96 bits of the IV/ctr are used (from 127:32) + * 0b11..All 128 bits of the IV/ctr are used + */ +#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) +/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new + * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + * 0b00..8 blocks + * 0b01..16 blocks + * 0b10..32 blocks + * 0b11..64 blocks + */ +#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ + +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit */ +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) + +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +/*! DMA - 1 if DMA is connected */ +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) + +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +/*! AHB - 1 if AHB Master is enabled */ +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) + +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +/*! AES - 1 if AES 128 included */ +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) + +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +/*! AESKEY - 1 if AES 192 and 256 also included */ +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) + +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +/*! SECRET - 1 if AES Secret key available */ +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) + +#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) +#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +/*! ICB - 1 if ICB over AES included */ +#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ + +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) + +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 */ +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - */ +/*! @{ */ + +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +/*! MASK - A random word. */ +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_HASHCRYPT_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2C.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2C.h new file mode 100644 index 0000000000..8dbaa89d88 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2C.h @@ -0,0 +1,972 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for I2C +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_I2C.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for I2C + * + * CMSIS Peripheral Access Layer for I2C + */ + +#if !defined(PERI_I2C_H_) +#define PERI_I2C_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Size of Registers Arrays */ +#define I2C_SLVADR_COUNT 4u + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[I2C_SLVADR_COUNT]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ + +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ + +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ + +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding + * bit in the INTENSET register if implemented. + */ +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. */ +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. */ +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear. */ +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. */ +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear. */ +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear. */ +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear. */ +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear. */ +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. */ +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. */ +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ + +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum + * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + */ +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C + * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, + * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A + * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after + * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the + * I2C function clock. + */ +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ + +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that + * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = + * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is + * divided by 65,536 before use. + */ +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. */ +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. */ +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. */ +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. */ +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status. */ +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. */ +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. */ +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. */ +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. */ +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event time-out Interrupt flag. */ +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL time-out Interrupt flag. */ +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ + +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ + +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register. Read: read the most recently received data for the Master + * function. Write: transmit data using the Master function. + */ +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ + +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register. Read: read the most recently received data for the Slave + * function. Write: transmit data using the Slave function. + */ +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ + +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. */ +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ + +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to + * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is + * set to 1 will cause an automatic match of the corresponding bit of the received address when it + * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for + * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 + * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + */ +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ + +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. */ +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. */ +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. */ +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. */ +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. */ +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_I2C_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2S.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2S.h new file mode 100644 index 0000000000..e743d5bdf1 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_I2S.h @@ -0,0 +1,812 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for I2S +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_I2S.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for I2S + * + * CMSIS Peripheral Access Layer for I2S + */ + +#if !defined(PERI_I2S_H_) +#define PERI_I2S_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) + +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or + * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received + * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the + * I2S: Determines the size of data transfers between the FIFO and the I2S + * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of + * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse + * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to + * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = + * data is 32 bits in length + */ +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the + * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported + * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is + * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in + * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger + * than DATALEN in order for the WS pulse to be generated correctly. + */ +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. Defines the location within the frame of the data for this channel + * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION + * defines the location of data in both the left phase and right phase, starting one clock after + * the WS edge. In other modes, POSITION defines the location of data within the entire frame. + * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The + * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels + * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit + * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS + * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + */ +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ + +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ + +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The + * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. + * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is + * divided by 4,096. + */ +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. */ +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. */ +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. */ +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. */ +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. */ +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. */ +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. */ +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. */ +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. */ +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. */ +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. */ +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. */ +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. */ +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. */ +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation, starting at 0. */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation, starting at 0. */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +/*! ID - Unique module identifier for this IP block. */ +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_I2S_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_INPUTMUX.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_INPUTMUX.h new file mode 100644 index 0000000000..702bf82b80 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_INPUTMUX.h @@ -0,0 +1,704 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for INPUTMUX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_INPUTMUX.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for INPUTMUX + * + * CMSIS Peripheral Access Layer for INPUTMUX + */ + +#if !defined(PERI_INPUTMUX_H_) +#define PERI_INPUTMUX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Size of Registers Arrays */ +#define INPUTMUX_SCT0_INMUX_COUNT 7u +#define INPUTMUX_TIMER0CAPTSEL_COUNT 4u +#define INPUTMUX_TIMER1CAPTSEL_COUNT 4u +#define INPUTMUX_TIMER2CAPTSEL_COUNT 4u +#define INPUTMUX_PINTSEL_COUNT 8u +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT 23u +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT 4u +#define INPUTMUX_TIMER3CAPTSEL_COUNT 4u +#define INPUTMUX_TIMER4CAPTSEL_COUNT 4u +#define INPUTMUX_PINTSECSEL_COUNT 2u +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT 10u +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT 4u + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[INPUTMUX_SCT0_INMUX_COUNT]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[INPUTMUX_TIMER0CAPTSEL_COUNT]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[INPUTMUX_TIMER1CAPTSEL_COUNT]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[INPUTMUX_TIMER2CAPTSEL_COUNT]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[INPUTMUX_PINTSEL_COUNT]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[INPUTMUX_DMA0_ITRIG_INMUX_COUNT]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[INPUTMUX_DMA0_OTRIG_INMUX_COUNT]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[INPUTMUX_TIMER3CAPTSEL_COUNT]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[INPUTMUX_TIMER4CAPTSEL_COUNT]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[INPUTMUX_PINTSECSEL_COUNT]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[INPUTMUX_DMA1_ITRIG_INMUX_COUNT]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[INPUTMUX_DMA1_OTRIG_INMUX_COUNT]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ + +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ + +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ + +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_INPUTMUX_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_IOCON.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_IOCON.h new file mode 100644 index 0000000000..be24a28ade --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_IOCON.h @@ -0,0 +1,292 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for IOCON +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_IOCON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for IOCON + * + * CMSIS Peripheral Access Layer for IOCON + */ + +#if !defined(PERI_IOCON_H_) +#define PERI_IOCON_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Size of Registers Arrays */ +#define IOCON_PIO_COUNT 2u +#define IOCON_PIO_PIO_COUNT 32u + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[IOCON_PIO_COUNT][IOCON_PIO_PIO_COUNT]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ + +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. + * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed + * (enabled). For the other pins, analog switch is open (disabled). + * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) + +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. + * 0b1..Filter disabled. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in I2C mode. + * 0b0..Disabled. IO is in open drain cell. + * 0b1..Enabled. Pull resistor is conencted. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Switch between GPIO mode and I2C mode. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_IOCON_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MAILBOX.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MAILBOX.h new file mode 100644 index 0000000000..1a8ba120c3 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MAILBOX.h @@ -0,0 +1,231 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for MAILBOX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_MAILBOX.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MAILBOX + * + * CMSIS Peripheral Access Layer for MAILBOX + */ + +#if !defined(PERI_MAILBOX_H_) +#define PERI_MAILBOX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Size of Registers Arrays */ +#define MAILBOX_MBOXIRQ_COUNT 2u + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[MAILBOX_MBOXIRQ_COUNT]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ + +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +/*! EX - Cleared when read, set when written. See usage description above. */ +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_MAILBOX_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MRT.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MRT.h new file mode 100644 index 0000000000..ecf3b36aea --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_MRT.h @@ -0,0 +1,356 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for MRT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_MRT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MRT + * + * CMSIS Peripheral Access Layer for MRT + */ + +#if !defined(PERI_MRT_H_) +#define PERI_MRT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Size of Registers Arrays */ +#define MRT_CHANNEL_COUNT 4u + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[MRT_CHANNEL_COUNT]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT + * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to + * this bit field starts the timer immediately. If the timer is running, writing a zero to this + * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer + * stops at the end of the time interval. + */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn + * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval + * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn + * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields + * returns -1 (0x00FF FFFF). + */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is + * positioned such that it can be used as an offset from the MRT base address in order to access + * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See + * text above for more details. + */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_MRT_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_OSTIMER.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_OSTIMER.h new file mode 100644 index 0000000000..d12de41332 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_OSTIMER.h @@ -0,0 +1,277 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for OSTIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_OSTIMER.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for OSTIMER + * + * CMSIS Peripheral Access Layer for OSTIMER + */ + +#if !defined(PERI_OSTIMER_H_) +#define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits + * EVTIMER. Note: There is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Capture Low Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Capture High Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Match Low Register */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central + * EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Match High Register */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared + * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and + * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes + * to clear this bit are asynchronous. It should be done before a new match value is written into + * the MATCH_L/H registers. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will + * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests + * due to the OSTIMER_INTR flag are blocked. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In + * typical applications it should not be necessary to test this bit. [1] + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_OSTIMER_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PINT.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PINT.h new file mode 100644 index 0000000000..ce9950a434 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PINT.h @@ -0,0 +1,692 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for PINT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PINT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PINT + * + * CMSIS Peripheral Access Layer for PINT + */ + +#if !defined(PERI_PINT_H_) +#define PERI_PINT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt + * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the + * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable + * rising edge or level interrupt. + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n + * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit + * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level + * interrupt. + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. + * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt + * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active + * interrupt level HIGH. + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n + * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable + * falling edge interrupt. + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n + * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or + * falling edge interrupt disabled. + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read + * 0: No rising edge has been detected on this pin since Reset or the last time a one was written + * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the + * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read + * 0: No falling edge has been detected on this pin since Reset or the last time a one was + * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or + * the last time a one was written to this bit. Write 1: clear falling edge detection for this + * pin. + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts + * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for + * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this + * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. + * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field + * indicates that the corresponding product term is matched by the current state of the appropriate + * inputs. + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PINT_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PLU.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PLU.h new file mode 100644 index 0000000000..b1bf8192e0 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PLU.h @@ -0,0 +1,345 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for PLU +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PLU.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PLU + * + * CMSIS Peripheral Access Layer for PLU + */ + +#if !defined(PERI_PLU_H_) +#define PERI_PLU_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Size of Registers Arrays */ +#define PLU_LUT_INP_COUNT 5u +#define PLU_LUT_COUNT 26u +#define PLU_LUT_T_COUNT 26u +#define PLU_OUTPUT_MUX_COUNT 8u + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP_MUX[PLU_LUT_INP_COUNT]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[PLU_LUT_COUNT]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[PLU_LUT_T_COUNT]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[PLU_OUTPUT_MUX_COUNT]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP_MUX - LUTn input x MUX */ +/*! @{ */ + +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..The output of LUT0. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) + +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ + +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. */ +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) +/*! @} */ + +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ + +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. */ +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ +/*! @{ */ + +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) */ +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) + +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR */ +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) + +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +/*! INTR_CLEAR - Write to clear wakeint_latched */ +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ + +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PLU_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PMC.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PMC.h new file mode 100644 index 0000000000..5dafcb7186 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PMC.h @@ -0,0 +1,1172 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for PMC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PMC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PMC + * + * CMSIS Peripheral Access Layer for PMC + */ + +#if !defined(PERI_PMC_H_) +#define PERI_PMC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + uint8_t RESERVED_3[16]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_5[8]; + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_6[16]; + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_7[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_8[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_9[8]; + __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_10[4]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'OSTIMER' */ + uint8_t RESERVED_11[24]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_12[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_13[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ + uint8_t RESERVED_14[8]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP SLEEP low power mode. + * 0b10..Latest IC boot was from POWER DOWN low power mode. + * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) +/*! @} */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) +#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) +/*! BODVBATRESETENABLE - BOD VBAT reset enable. + * 0b0..BOD VBAT reset is disable. + * 0b1..BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) +#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) +/*! BODCORERESETENABLE - BOD CORE reset enable. + * 0b0..BOD CORE reset is disable. + * 0b1..BOD CORE reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) + +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) +/*! @} */ + +/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) + +#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) +#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) +/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) + +#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) +#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) +/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) + +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ +/*! @{ */ + +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. + */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) + +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_XTAL32K_IREF_MASK (0x6U) +#define PMC_XTAL32K_IREF_SHIFT (1U) +/*! IREF - reference output current selection inputs. */ +#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) + +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Test Mode. */ +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + +#define PMC_XTAL32K_IBIAS_MASK (0x30U) +#define PMC_XTAL32K_IBIAS_SHIFT (4U) +/*! IBIAS - bias current selection inputs. */ +#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) + +#define PMC_XTAL32K_AMPL_MASK (0xC0U) +#define PMC_XTAL32K_AMPL_SHIFT (6U) +/*! AMPL - oscillator amplitude selection inputs. */ +#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) + +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. */ +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. */ +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) + +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) +/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) + +#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) +#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +/*! CAPTESTSTART - Start test. */ +#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) + +#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) +#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +/*! CAPTESTENABLE - Enable signal for cap test. */ +#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) + +#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) +#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..Oscillator output pin (osc_out). + * 0b1..Oscillator input pin (osc_in). + */ +#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). */ +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ + +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. */ +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) + +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) +#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) +/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. + * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. + * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. + */ +#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) + +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) +/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. + * 0b0..LDO MEM High Z mode is disabled. + * 0b1..LDO MEM High Z mode is enabled. + */ +#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) + +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) + +#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) +#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) +/*! MISCCTRL_3_8 - Reserved. */ +#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode */ +#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode */ +#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode */ +#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode */ +#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) + +#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) +#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) +/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the + * Low Power Software only in DEEP SLEEP low power mode. + * 0b0..LDO_MEM bleed current is enabled. + * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared + * after wake up from Deep SLeep low power mode. + */ +#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) + +#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) +#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) +/*! MISCCTRL_13_14 - Reserved. */ +#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) + +#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) +#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) +/*! WAKUPIO_RST - WAKEUP IO event detector reset control. + * 0b0..Wakeup IO is not reset. + * 0b1..Wakeup IO is reset. + */ +#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. */ +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. */ +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. */ +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +/*! CLK1HZDIVHALT - Halts the divider counter. */ +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. */ +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. */ +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) + +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. */ +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) + +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). */ +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) + +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. */ +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) + +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) + +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) + +#define PMC_SRAMCTRL_RM_MASK (0x1CU) +#define PMC_SRAMCTRL_RM_SHIFT (2U) +/*! RM - Read Margin control settings. */ +#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) + +#define PMC_SRAMCTRL_WM_MASK (0xE0U) +#define PMC_SRAMCTRL_WM_SHIFT (5U) +/*! WM - Write Margin control settings. */ +#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) + +#define PMC_SRAMCTRL_WRME_MASK (0x100U) +#define PMC_SRAMCTRL_WRME_SHIFT (8U) +/*! WRME - Write read margin enable. */ +#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PMC_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_POWERQUAD.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_POWERQUAD.h new file mode 100644 index 0000000000..6ec59b65ab --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_POWERQUAD.h @@ -0,0 +1,543 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for POWERQUAD +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_POWERQUAD.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for POWERQUAD + * + * CMSIS Peripheral Access Layer for POWERQUAD + */ + +#if !defined(PERI_POWERQUAD_H_) +#define PERI_POWERQUAD_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Size of Registers Arrays */ +#define POWERQUAD_GPREG_COUNT 16u +#define POWERQUAD_COMPREGS_COUNT 8u + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ + __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ + __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ + __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[POWERQUAD_GPREG_COUNT]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[POWERQUAD_COMPREGS_COUNT]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Base address register for output region */ +/*! @{ */ + +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +/*! outbase - Base address register for the output region */ +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output format */ +/*! @{ */ + +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +/*! out_scaler - Output Scaler value (for scaled 'q31' formats) */ +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Base address register for temp region */ +/*! @{ */ + +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +/*! tmpbase - Base address register for the temporary region */ +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temp format */ +/*! @{ */ + +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) */ +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Base address register for input A region */ +/*! @{ */ + +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +/*! inabase - Base address register for the input A region */ +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A format */ +/*! @{ */ + +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) + +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) + +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) */ +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Base address register for input B region */ +/*! @{ */ + +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +/*! inbbase - Base address register for the input B region */ +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B format */ +/*! @{ */ + +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) + +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) */ +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) + +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) */ +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - PowerQuad Control register */ +/*! @{ */ + +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +/*! decode_opcode - opcode specific to decode_machine */ +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) + +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA */ +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) + +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +/*! inst_busy - Instruction busy signal when high indicates processing is on */ +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length register */ +/*! @{ */ + +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = + * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = + * inst_length[20:16] + */ +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Pre-scale register */ +/*! @{ */ + +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +/*! cppre_in - co-processor scaling of input */ +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) + +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +/*! cppre_out - co-processor fixed point output */ +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +/*! cppre_sat - 1 : forces sub-32 bit saturation */ +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +/*! cppre_sat8 - 0 = 8bits, 1 = 16bits */ +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Misc register */ +/*! @{ */ + +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +/*! inst_misc - Misc register. For Matrix : Used for scale factor */ +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory register */ +/*! @{ */ + +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +/*! cursory - 1 : Enable cursory mode */ +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +/*! cordic_x - Cordic input x */ +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic input Y register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +/*! cordic_y - Cordic input y */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic input Z register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +/*! cordic_z - Cordic input z */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ +/*! @{ */ + +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +/*! OVERFLOW - overflow */ +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +/*! NAN - nan */ +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) + +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +/*! FIXEDOVERFLOW - fixed_pt_overflow */ +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +/*! UNDERFLOW - underflow */ +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +/*! BUSERROR - bus_error */ +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - INTERRUPT enable register */ +/*! @{ */ + +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +/*! intr_oflow - 1 : Enable interrupt on Floating point overflow */ +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +/*! intr_nan - 1 : Enable interrupt on Floating point NaN */ +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) + +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow */ +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) + +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation */ +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +/*! intr_berr - 1: Enable interrupt on AHBM Buss Error */ +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) + +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +/*! intr_comp - 1: Enable interrupt on instruction completion */ +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable register */ +/*! @{ */ + +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +/*! event_oflow - 1 : Enable event trigger on Floating point overflow */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +/*! event_nan - 1 : Enable event trigger on Floating point NaN */ +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) + +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +/*! event_fixed - 1: Enable event trigger on Fixed point Overflow */ +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) + +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +/*! event_uflow - 1 : Enable event trigger on Subnormal truncation */ +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +/*! event_berr - 1: Enable event trigger on AHBM Buss Error */ +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) + +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +/*! event_comp - 1: Enable event trigger on instruction completion */ +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - INTERRUPT STATUS register */ +/*! @{ */ + +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit */ +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General purpose register bank N. */ +/*! @{ */ + +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +/*! gpreg - General purpose register bank */ +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/*! @name COMPREGS_COMPREG - Compute register bank */ +/*! @{ */ + +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +/*! compreg - Compute register bank */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_POWERQUAD_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PRINCE.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PRINCE.h new file mode 100644 index 0000000000..365ede601a --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PRINCE.h @@ -0,0 +1,380 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for PRINCE +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PRINCE.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PRINCE + * + * CMSIS Peripheral Access Layer for PRINCE + */ + +#if !defined(PERI_PRINCE_H_) +#define PERI_PRINCE_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ + +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Encryption Enable. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. */ +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. */ +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ + +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. */ +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. */ +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. */ +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. */ +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. */ +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. */ +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. */ +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. */ +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. */ +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. */ +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. */ +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. */ +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PRINCE_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PUF.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PUF.h new file mode 100644 index 0000000000..a609ad5501 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_PUF.h @@ -0,0 +1,799 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for PUF +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PUF.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PUF + * + * CMSIS Peripheral Access Layer for PUF + */ + +#if !defined(PERI_PUF_H_) +#define PERI_PUF_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Size of Registers Arrays */ +#define PUF_KEYMASK_COUNT 4u + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[28]; + __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_6[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __IO uint32_t IDXBLK_L; /**< offset: 0x20C */ + __IO uint32_t IDXBLK_H_DP; /**< offset: 0x210 */ + __O uint32_t KEYMASK[PUF_KEYMASK_COUNT]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_7[48]; + __IO uint32_t IDXBLK_H; /**< offset: 0x254 */ + __IO uint32_t IDXBLK_L_DP; /**< offset: 0x258 */ + __I uint32_t SHIFT_STATUS; /**< offset: 0x25C */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ + +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +/*! zeroize - Begin Zeroize operation for PUF and go to Error state */ +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +/*! enroll - Begin Enroll operation */ +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +/*! start - Begin Start operation */ +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +/*! GENERATEKEY - Begin Set Intrinsic Key operation */ +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +/*! SETKEY - Begin Set User Key operation */ +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +/*! GETKEY - Begin Get Key operation */ +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ + +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +/*! KEYIDX - Key index for Set Key operations */ +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ + +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +/*! KEYSIZE - Key size for Set Key operations */ +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ + +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +/*! busy - Indicates that operation is in progress */ +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Last operation was successful */ +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +/*! error - PUF is in the Error state and no operations can be performed */ +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Request for next part of key */ +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Next part of key is available */ +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Request for next part of AC/KC */ +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Next part of AC/KC is available */ +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ + +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +/*! ALLOWENROLL - Enroll operation is allowed */ +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +/*! ALLOWSTART - Start operation is allowed */ +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +/*! ALLOWSETKEY - Set Key operations are allowed */ +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +/*! ALLOWGETKEY - Get Key operation is allowed */ +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ + +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +/*! KEYIN - Key input data */ +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ + +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +/*! CODEIN - AC/KC input data */ +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ + +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +/*! CODEOUT - AC/KC output data */ +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ + +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register */ +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ + +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +/*! KEYOUT - Key output data */ +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ + +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit */ +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name VERSION - PUF version register. */ +/*! @{ */ + +#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) +#define PUF_VERSION_VERSION_SHIFT (0U) +/*! VERSION - Version of the PUF module. */ +#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ + +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) + +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) + +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) */ +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ + +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +/*! READY - Triggers on falling edge of busy, write 1 to clear */ +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears */ +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears */ +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears */ +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears */ +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears */ +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears */ +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name PWRCTRL - PUF RAM Power Control */ +/*! @{ */ + +#define PUF_PWRCTRL_RAMON_MASK (0x1U) +#define PUF_PWRCTRL_RAMON_SHIFT (0U) +/*! RAMON - Power on the PUF RAM. */ +#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) + +#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) +#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +/*! RAMSTAT - PUF RAM status. */ +#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ + +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. */ +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) + +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. */ +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, + * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) + +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, + * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) + +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, + * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) + +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, + * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ + +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + */ +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) + +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + */ +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) + +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + */ +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) + +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + */ +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ + +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. */ +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) + +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. */ +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) + +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. */ +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) + +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. */ +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK_L - */ +/*! @{ */ + +#define PUF_IDXBLK_L_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 */ +#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) + +#define PUF_IDXBLK_L_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 */ +#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) + +#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 */ +#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) + +#define PUF_IDXBLK_L_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 */ +#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) + +#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 */ +#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) + +#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 */ +#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) + +#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 */ +#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) + +#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 0 to 7 PUF key indexes */ +#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_H_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 */ +#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) + +#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 */ +#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) + +#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 */ +#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) + +#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 */ +#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) + +#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 */ +#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) + +#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 */ +#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) + +#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 */ +#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) + +#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 */ +#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/*! @name IDXBLK_H - */ +/*! @{ */ + +#define PUF_IDXBLK_H_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 */ +#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) + +#define PUF_IDXBLK_H_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 */ +#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) + +#define PUF_IDXBLK_H_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 */ +#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) + +#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 */ +#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) + +#define PUF_IDXBLK_H_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 */ +#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) + +#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 */ +#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) + +#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 */ +#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) + +#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 */ +#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) + +#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 8 to 15 PUF key indexes */ +#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_L_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 */ +#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) + +#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 */ +#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) + +#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 */ +#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) + +#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 */ +#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) + +#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 */ +#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) + +#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 */ +#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) + +#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 */ +#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ + +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +/*! KEY0 - Index counter from key 0 shift register */ +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) + +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +/*! KEY1 - Index counter from key 1 shift register */ +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) + +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +/*! KEY2 - Index counter from key 2 shift register */ +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) + +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +/*! KEY3 - Index counter from key 3 shift register */ +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PUF_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RNG.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RNG.h new file mode 100644 index 0000000000..2bd8eb0953 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RNG.h @@ -0,0 +1,288 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for RNG +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_RNG.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for RNG + * + * CMSIS Peripheral Access Layer for RNG + */ + +#if !defined(PERI_RNG_H_) +#define PERI_RNG_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t COUNTER_VAL; /**< offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< offset: 0x14 */ + uint8_t RESERVED_1[4068]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ + +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ + +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock + * frequency for evaluation and certification purposes. + */ +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) + +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. */ +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ + +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +/*! MODE - 00: disabled 01: update once. */ +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) + +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. */ +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) + +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. */ +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) + +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one + * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: + * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this + * field. + */ +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. */ +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. */ +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ + +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. */ +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) + +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +/*! MIN_REV - Minor revision i. */ +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) + +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +/*! MAJ_REV - Major revision i. */ +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) + +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +/*! ID - Identifier. */ +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_RNG_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RTC.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RTC.h new file mode 100644 index 0000000000..337a512a79 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_RTC.h @@ -0,0 +1,344 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for RTC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_RTC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for RTC + * + * CMSIS Peripheral Access Layer for RTC + */ + +#if !defined(PERI_RTC_H_) +#define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Size of Registers Arrays */ +#define RTC_GPREG_COUNT 8u + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[RTC_GPREG_COUNT]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ + +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) + +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) + +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) + +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) + +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) + +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) + +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) + +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) + +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ + +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the + * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + */ +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ + +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial + * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC + * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this + * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after + * the RTC_EN bit is set. + */ +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ + +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads + * a start count value into the wake-up timer and initializes a count-down sequence. Do not write + * to this register while counting is in progress. + */ +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - Sub-second counter register */ +/*! @{ */ + +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is + * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz + * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This + * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is + * disabled and re-enabled. On modules not equipped with a sub-second counter, this register + * will read-back as all zeroes. + */ +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ + +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. */ +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_RTC_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SCT.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SCT.h new file mode 100644 index 0000000000..2123da7443 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SCT.h @@ -0,0 +1,1757 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for SCT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SCT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SCT + * + * CMSIS Peripheral Access Layer for SCT + */ + +#if !defined(PERI_SCT_H_) +#define PERI_SCT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Size of Registers Arrays */ +#define SCT_CAP_MATCH_CAP_CAP_COUNT 16u +#define SCT_CAP_MATCH_MATCH_MATCH_COUNT 16u +#define SCT_CAPCTRL_MATCHREL_CAPCTRL_CAPCTRL_COUNT 16u +#define SCT_CAPCTRL_MATCHREL_MATCHREL_MATCHREL_COUNT 16u +#define SCT_EV_COUNT 16u +#define SCT_OUT_COUNT 10u + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + }; + uint8_t RESERVED_0[40]; + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + }; + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + }; + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[SCT_CAP_MATCH_CAP_CAP_COUNT]; + __IO uint32_t CAP[SCT_CAP_MATCH_CAP_CAP_COUNT]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[SCT_CAP_MATCH_MATCH_MATCH_COUNT]; + __IO uint32_t MATCH[SCT_CAP_MATCH_MATCH_MATCH_COUNT]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[SCT_CAPCTRL_MATCHREL_CAPCTRL_CAPCTRL_COUNT]; + __IO uint32_t CAPCTRL[SCT_CAPCTRL_MATCHREL_CAPCTRL_CAPCTRL_COUNT]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[SCT_CAPCTRL_MATCHREL_MATCHREL_MATCHREL_COUNT]; + __IO uint32_t MATCHREL[SCT_CAPCTRL_MATCHREL_MATCHREL_MATCHREL_COUNT]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EV[SCT_EV_COUNT]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[SCT_OUT_COUNT]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ + +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any + * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at + * any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all + * other bits are reserved. A 1 in one of these bits subjects the corresponding input to + * synchronization to the SCT clock, before it is used to create an event. If an input is known to + * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: + * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input + * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. + * It does not apply to the clock input specified in the CKSEL field. + */ +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto + * LIMIT condition without the need to define an associated event. As with any LIMIT event, this + * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change + * the direction of count in bi-directional mode. Software can write to set or clear this bit at + * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a + * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, + * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to + * change the direction of count in bi-directional mode. Software can write to set or clear this bit + * at any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ + +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. */ +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. */ +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ + +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ + +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ + +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ + +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit + * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ + +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write + * the lower 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write + * the upper 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ + +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable. */ +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable. */ +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ + +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. */ +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. */ +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ + +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, + * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match register. 1 = register operates as capture register. + */ +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit + * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match registers. 1 = register operates as capture registers. + */ +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ + +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the + * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ + +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ + +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) + +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) + +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) + +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) + +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) + +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) + +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMAREQ0 - SCT DMA request 0 register */ +/*! @{ */ + +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) +/*! @} */ + +/*! @name DMAREQ1 - SCT DMA request 1 register */ +/*! @{ */ + +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ + +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are + * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in + * this SCT. + */ +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ + +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ + +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag + * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ + +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was + * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = + * number of outputs in this SCT. + */ +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) + +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE + * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write + * to certain L and H registers can be half successful and half unsuccessful. + */ +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or + * the Output register when the H counter was not halted. + */ +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name CAPL - SCT_CAPL register */ +/*! @{ */ + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) +/*! @} */ + +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) + +/*! @name CAPH - SCT_CAPH register */ +/*! @{ */ + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) +/*! @} */ + +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) + +/*! @name CAP - SCT capture register of capture channel */ +/*! @{ */ + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) + +/*! @name MATCHL - SCT_MATCHL register */ +/*! @{ */ + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) +/*! @} */ + +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) + +/*! @name MATCHH - SCT_MATCHH register */ +/*! @{ */ + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) +/*! @} */ + +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) + +/*! @name MATCH - SCT match value register of match channels */ +/*! @{ */ + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When + * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When + * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ + +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) + * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of + * match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event + * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. + * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When + * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT + * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of + * bits = number of states in this SCT. + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur + * only when the counter selected by the HEVENT bit is running. + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not + * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit + * ingredient of every event. + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on + * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and + * STATEV are both zero, there is no change to the STATE value. + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the + * triggering of this event, then a match is considered to be active whenever the counter value is + * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR + * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active + * during the cycle when the counter is equal to the match value. + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ + +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output + * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ + +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 + * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SCT_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SDIF.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SDIF.h new file mode 100644 index 0000000000..0f41921365 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SDIF.h @@ -0,0 +1,1145 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for SDIF +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SDIF.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SDIF + * + * CMSIS Peripheral Access Layer for SDIF + */ + +#if !defined(PERI_SDIF_H_) +#define PERI_SDIF_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Size of Registers Arrays */ +#define SDIF_RESP_COUNT 4u +#define SDIF_FIFO_COUNT 64u + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[SDIF_RESP_COUNT]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[SDIF_FIFO_COUNT]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +/*! @{ */ + +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +/*! CONTROLLER_RESET - Controller reset. */ +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) + +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +/*! FIFO_RESET - Fifo reset. */ +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) + +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +/*! DMA_RESET - DMA reset. */ +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) + +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +/*! INT_ENABLE - Global interrupt enable/disable bit. */ +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) + +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +/*! READ_WAIT - Read/wait. */ +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) + +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +/*! SEND_IRQ_RESPONSE - Send irq response. */ +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) + +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +/*! ABORT_READ_DATA - Abort read data. */ +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) + +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +/*! SEND_CCSD - Send ccsd. */ +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) + +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. */ +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) + +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. */ +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. */ +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. */ +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. */ +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) + +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +/*! USE_INTERNAL_DMAC - SD/MMC DMA use. */ +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) +/*! @} */ + +/*! @name PWREN - Power Enable register */ +/*! @{ */ + +#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 0. + */ +#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) + +#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) +#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 1. + */ +#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider register */ +/*! @{ */ + +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +/*! CLK_DIVIDER0 - Clock divider-0 value. */ +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) +/*! @} */ + +/*! @name CLKENA - Clock Enable register */ +/*! @{ */ + +#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. */ +#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) + +#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) +#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. */ +#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) + +#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. */ +#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) + +#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) +#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. */ +#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) +/*! @} */ + +/*! @name TMOUT - Time-out register */ +/*! @{ */ + +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +/*! RESPONSE_TIMEOUT - Response time-out value. */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) + +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. */ +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) +/*! @} */ + +/*! @name CTYPE - Card Type register */ +/*! @{ */ + +#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ +#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) + +#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) +#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ +#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) + +#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. */ +#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) + +#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) +#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. */ +#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) +/*! @} */ + +/*! @name BLKSIZ - Block Size register */ +/*! @{ */ + +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +/*! BLOCK_SIZE - Block size. */ +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @} */ + +/*! @name BYTCNT - Byte Count register */ +/*! @{ */ + +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. */ +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name INTMASK - Interrupt Mask register */ +/*! @{ */ + +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +/*! CDET - Card detect. */ +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) + +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +/*! RE - Response error. */ +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) + +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +/*! CDONE - Command done. */ +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) + +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +/*! DTO - Data transfer over. */ +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) + +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. */ +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) + +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. */ +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) + +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. */ +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) + +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. */ +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) + +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +/*! RTO - Response time-out. */ +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) + +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. */ +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) + +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). */ +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) + +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. */ +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) + +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. */ +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) + +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +/*! SBE - Start-bit error. */ +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) + +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +/*! ACD - Auto command done. */ +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) + +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/Write no CRC. */ +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) + +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +/*! SDIO_INT_MASK - Mask SDIO interrupt. */ +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) +/*! @} */ + +/*! @name CMDARG - Command Argument register */ +/*! @{ */ + +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +/*! CMD_ARG - Value indicates command argument to be passed to card. */ +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) +/*! @} */ + +/*! @name CMD - Command register */ +/*! @{ */ + +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +/*! CMD_INDEX - Command index. */ +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) + +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +/*! RESPONSE_EXPECT - Response expect. */ +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) + +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +/*! RESPONSE_LENGTH - Response length. */ +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) + +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +/*! CHECK_RESPONSE_CRC - Check response CRC. */ +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) + +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +/*! DATA_EXPECTED - Data expected. */ +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) + +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +/*! READ_WRITE - read/write. */ +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) + +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +/*! TRANSFER_MODE - Transfer mode. */ +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) + +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +/*! SEND_AUTO_STOP - Send auto stop. */ +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) + +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. */ +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) + +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +/*! STOP_ABORT_CMD - Stop abort command. */ +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) + +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +/*! SEND_INITIALIZATION - Send initialization. */ +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) + +#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) +#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) +/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed + * 0b00000..Command will be execute on SDCARD 0 + * 0b00001..Command will be execute on SDCARD 1 + */ +#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) + +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. */ +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) + +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +/*! READ_CEATA_DEVICE - Read ceata device. */ +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) + +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +/*! CCS_EXPECTED - CCS expected. */ +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) + +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. */ +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) + +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. */ +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) + +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +/*! DISABLE_BOOT - Disable Boot. */ +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) + +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +/*! BOOT_MODE - Boot Mode. */ +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) + +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +/*! VOLT_SWITCH - Voltage switch bit. */ +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) + +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +/*! USE_HOLD_REG - Use Hold Register. */ +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) + +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +/*! START_CMD - Start command. */ +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) +/*! @} */ + +/*! @name RESP - Response register */ +/*! @{ */ + +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +/*! RESPONSE - Bits of response. */ +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) +/*! @} */ + +/*! @name MINTSTS - Masked Interrupt Status register */ +/*! @{ */ + +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. */ +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) + +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +/*! RE - Response error. */ +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) + +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. */ +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) + +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. */ +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) + +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. */ +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) + +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. */ +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) + +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. */ +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) + +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. */ +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) + +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +/*! RTO - Response time-out. */ +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) + +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. */ +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) + +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). */ +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) + +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. */ +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) + +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. */ +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) + +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. */ +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) + +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. */ +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) + +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. */ +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) + +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. */ +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name RINTSTS - Raw Interrupt Status register */ +/*! @{ */ + +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. */ +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) + +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +/*! RE - Response error. */ +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) + +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. */ +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) + +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. */ +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) + +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. */ +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) + +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. */ +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) + +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. */ +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) + +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. */ +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) + +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). */ +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) + +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). */ +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) + +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). */ +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) + +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. */ +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) + +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. */ +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) + +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. */ +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) + +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. */ +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) + +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. */ +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) + +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. */ +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name STATUS - Status register */ +/*! @{ */ + +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. */ +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) + +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. */ +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) + +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +/*! FIFO_EMPTY - FIFO is empty status. */ +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) + +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +/*! FIFO_FULL - FIFO is full status. */ +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) + +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx + * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - + * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp + * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The + * command FSM state is represented using 19 bits. + */ +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) + +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. */ +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) + +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. */ +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) + +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. */ +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) + +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. */ +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) + +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. */ +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) + +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +/*! DMA_ACK - DMA acknowledge signal state. */ +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) + +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +/*! DMA_REQ - DMA request signal state. */ +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) +/*! @} */ + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +/*! @{ */ + +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. */ +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) + +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. */ +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) + +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller + * multiple-transaction-size SRC/DEST_MSIZE. + */ +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) +/*! @} */ + +/*! @name CDETECT - Card Detect register */ +/*! @{ */ + +#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +/*! CARD0_DETECT - Card 0 detect */ +#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) + +#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) +#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +/*! CARD1_DETECT - Card 1 detect */ +#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) +/*! @} */ + +/*! @name WRTPRT - Write Protect register */ +/*! @{ */ + +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +/*! WRITE_PROTECT - Write protect. */ +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) +/*! @} */ + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +/*! @{ */ + +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +/*! @{ */ + +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name DEBNCE - Debounce Count register */ +/*! @{ */ + +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) +/*! @} */ + +/*! @name RST_N - Hardware Reset */ +/*! @{ */ + +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +/*! CARD_RESET - Hardware reset. */ +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) +/*! @} */ + +/*! @name BMOD - Bus Mode register */ +/*! @{ */ + +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +/*! SWR - Software Reset. */ +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) + +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +/*! FB - Fixed Burst. */ +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) + +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +/*! DSL - Descriptor Skip Length. */ +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) + +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +/*! DE - SD/MMC DMA Enable. */ +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) + +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +/*! PBL - Programmable Burst Length. */ +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) +/*! @} */ + +/*! @name PLDMND - Poll Demand register */ +/*! @{ */ + +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +/*! PD - Poll Demand. */ +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) +/*! @} */ + +/*! @name DBADDR - Descriptor List Base Address register */ +/*! @{ */ + +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +/*! SDL - Start of Descriptor List. */ +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) +/*! @} */ + +/*! @name IDSTS - Internal DMAC Status register */ +/*! @{ */ + +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +/*! TI - Transmit Interrupt. */ +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) + +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +/*! RI - Receive Interrupt. */ +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) + +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Interrupt. */ +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) + +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. */ +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) + +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +/*! CES - Card Error Summary. */ +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) + +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary. */ +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) + +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary. */ +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) + +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +/*! EB - Error Bits. */ +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) + +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +/*! FSM - DMAC state machine present state. */ +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) +/*! @} */ + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +/*! @{ */ + +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +/*! TI - Transmit Interrupt Enable. */ +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) + +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +/*! RI - Receive Interrupt Enable. */ +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) + +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Enable. */ +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) + +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. */ +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) + +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +/*! CES - Card Error summary Interrupt Enable. */ +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) + +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary Enable. */ +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) + +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary Enable. */ +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) +/*! @} */ + +/*! @name DSCADDR - Current Host Descriptor Address register */ +/*! @{ */ + +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +/*! HDA - Host Descriptor Address Pointer. */ +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) +/*! @} */ + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +/*! @{ */ + +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +/*! HBA - Host Buffer Address Pointer. */ +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) +/*! @} */ + +/*! @name CARDTHRCTL - Card Threshold Control */ +/*! @{ */ + +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +/*! CARDRDTHREN - Card Read Threshold Enable. */ +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) + +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +/*! BSYCLRINTEN - Busy Clear Interrupt Enable. */ +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) + +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +/*! CARDTHRESHOLD - Card Threshold size. */ +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) +/*! @} */ + +/*! @name BACKENDPWR - Power control */ +/*! @{ */ + +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +/*! BACKENDPWR - Back-end Power control for card application. */ +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) +/*! @} */ + +/*! @name FIFO - SDIF FIFO */ +/*! @{ */ + +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +/*! DATA - SDIF FIFO. */ +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SDIF_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SPI.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SPI.h new file mode 100644 index 0000000000..a5bfa98ad1 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SPI.h @@ -0,0 +1,942 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for SPI +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SPI.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SPI + * + * CMSIS Peripheral Access Layer for SPI + */ + +#if !defined(PERI_SPI_H_) +#define PERI_SPI_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_8[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ + +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ + +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data + * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This + * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI + * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are + * inserted. + */ +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL + * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock + * times are inserted. 0xF = 15 SPI clock times are inserted. + */ +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current + * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 + * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock + * times are inserted. + */ +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between + * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 + * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that + * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 + * SPI clock times. + */ +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ + +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from + * deasserted to asserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a + * slave mode access begins. This flag is cleared by software. + */ +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to + * deasserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become idle. This flag is cleared by software. + */ +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. */ +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current + * transfer when the transmitter finishes any activity already in progress, as if the EOT flag + * had been set prior to the last transmission. This capability is included to support cases where + * it is not known when transmit data is written that it will be the end of a transfer. The bit + * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end + * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + */ +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. + * This means that the transmit holding register is empty and the transmitter is not in the + * process of sending data. + */ +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ + +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ + +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the + * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, + * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results + * in FCLK/65536. + */ +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ + +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. */ +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. */ +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle status flag. */ +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. */ +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. */ +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. */ +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. */ +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. */ +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. */ +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. */ +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. */ +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. */ +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths + * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. + * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data + * transfer is 16 bits in length. + */ +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. */ +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved + * along with received data. The value will reflect the SSEL0 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved + * along with received data. The value will reflect the SSEL1 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved + * along with received data. The value will reflect the SSEL2 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved + * along with received data. The value will reflect the SSEL3 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went + * from deasserted to asserted (i.e., any previous transfer has ended). This information can be + * used to identify the first piece of data in cases where the transfer length is greater than 16 + * bits. + */ +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. */ +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. */ +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. */ +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. */ +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. */ +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of transfer flag. */ +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. */ +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. */ +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. */ +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. */ +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SPI_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCON.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCON.h new file mode 100644 index 0000000000..7a3eb47ded --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCON.h @@ -0,0 +1,3885 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for SYSCON +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SYSCON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SYSCON + * + * CMSIS Peripheral Access Layer for SYSCON + */ + +#if !defined(PERI_SYSCON_H_) +#define PERI_SYSCON_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Size of Registers Arrays */ +#define SYSCON_PRESETCTRL_PRESETCTRLX_PRESETCTRLX_COUNT 3u +#define SYSCON_PRESETCTRLSET_COUNT 3u +#define SYSCON_PRESETCTRLCLR_COUNT 3u +#define SYSCON_AHBCLKCTRL_AHBCLKCTRLX_AHBCLKCTRLX_COUNT 3u +#define SYSCON_AHBCLKCTRLSET_COUNT 3u +#define SYSCON_AHBCLKCTRLCLR_COUNT 3u +#define SYSCON_SYSTICKCLKSEL_SYSTICKCLKSELX_SYSTICKCLKSELX_COUNT 2u +#define SYSCON_CTIMERCLKSEL_CTIMERCLKSELX_CTIMERCLKSELX_COUNT 5u +#define SYSCON_FCCLKSEL_FCCLKSELX_FCCLKSELX_COUNT 8u +#define SYSCON_FLEXFRGCTRL_FLEXFRGXCTRL_FLEXFRGXCTRL_COUNT 8u + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[SYSCON_PRESETCTRL_PRESETCTRLX_PRESETCTRLX_COUNT]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[SYSCON_PRESETCTRLSET_COUNT]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[SYSCON_PRESETCTRLCLR_COUNT]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[SYSCON_AHBCLKCTRL_AHBCLKCTRLX_AHBCLKCTRLX_COUNT]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[SYSCON_AHBCLKCTRLSET_COUNT]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[SYSCON_AHBCLKCTRLCLR_COUNT]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + struct { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264, not available in all instances (available on 7 out of 21) */ + } SYSTICKCLKSEL; + __IO uint32_t SYSTICKCLKSELX[SYSCON_SYSTICKCLKSEL_SYSTICKCLKSELX_SYSTICKCLKSELX_COUNT]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4, irregular array, not all indices are valid */ + }; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[SYSCON_CTIMERCLKSEL_CTIMERCLKSELX_CTIMERCLKSELX_COUNT]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_11[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_12[12]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_13[4]; + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[SYSCON_FCCLKSEL_FCCLKSELX_FCCLKSELX_COUNT]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_16[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_17[4]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + uint8_t RESERVED_18[20]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[SYSCON_FLEXFRGCTRL_FLEXFRGXCTRL_FLEXFRGXCTRL_COUNT]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_19[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_20[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ + uint8_t RESERVED_21[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_22[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_23[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_24[4]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_25[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ + uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ + uint8_t RESERVED_28[52]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_29[252]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_30[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_31[364]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ + uint8_t RESERVED_32[248]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + uint8_t RESERVED_33[4]; + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_34[520]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_35[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_36[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_37[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ + uint8_t RESERVED_38[16]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_39[16]; + __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4, not available in all instances (available on 7 out of 21) */ + uint8_t RESERVED_40[32]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ + +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) +/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) +/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +/*! PRI_USB_FS - USB-FS.(USB0) */ +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +/*! PRI_SDMA0 - DMA0 controller priority. */ +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +/*! PRI_SDIO - SDIO. */ +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +/*! PRI_PQ - PQ (HW Accelerator). */ +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) + +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) +/*! PRI_HASH_AES - HASH_AES. */ +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +/*! PRI_USB_HS - USB-HS.(USB1) */ +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +/*! PRI_SDMA1 - DMA1 controller priority. */ +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Initial value for the Systick timer. */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Initial value for the Systick timer. */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ +/*! @{ */ + +#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) + +#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. */ +#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) + +#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. */ +#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) + +#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. */ +#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) + +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) +/*! SCTIPU_RST - SCTIPU reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0 DEV reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + +#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) +/*! SDIO_RST - SDIO reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1 Host reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1 dev reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1 RAM reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1 PHY reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0 Host Master reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0 Host Slave reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) + +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) + +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) + +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) + +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) + +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b0..Bloc is not reset. + * 0b1..Bloc is reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ + +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + * 0b01011010000000000000000000000001..Generate a software reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) + +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0 DEV. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + +#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) +/*! SDIO - Enables the clock for the SDIO. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1 Host. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1 dev. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1 RAM. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1 PHY. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) + +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) + +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) + +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) + +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b0..Disable Clock. + * 0b1..Enable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU1 source select. + * 0b000..System Tick 1 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (2U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..PLL1 clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ + +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ + +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ + +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ + +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ + +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ + +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..Reserved. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ + +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SDIOCLKSEL - SDIO clock source select */ +/*! @{ */ + +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - SDIO clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ + +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ + +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ + +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ + +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ + +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ + +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ + +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ + +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. */ +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. */ +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ + +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ + +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) + +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) + +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) + +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0 Clock divider */ +/*! @{ */ + +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ + +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ + +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SDIOCLKDIV - SDIO clock divider */ +/*! @{ */ + +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) + +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) + +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) + +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ + +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. */ +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) + +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b0..Divider is not reset. + * 0b1..Divider is reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) + +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b0..Divider clock is running. + * 0b1..Divider clock is stoped. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) + +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b0..Divider clock is stable. + * 0b1..Clock frequency is not stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ + +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + * 0b00000000000000000000000000000001..update all clock configuration. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register */ +/*! @{ */ + +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. + */ +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. + */ +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. + * 0b0..USB0 Device clock is low. + * 0b1..USB0 Device clock is high. + */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. + * 0b0..USB0 Host clock is low. + * 0b1..USB0 Host clock is high. + */ +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ + +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b0..No action is performed. + * 0b1..Flush the FMC buffer contents. + */ +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b0..input mode. + * 0b1..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. + */ +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. + * 0b0..DEV_NEEDCLK is low. + * 0b1..DEV_NEEDCLK is high. + */ +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. + * 0b0..HOST_NEEDCLK is low. + * 0b1..HOST_NEEDCLK is high. + */ +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +/*! @{ */ + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) + +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + * 0b0..Bypassed. + * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + */ +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + * 0b0..Disable drive delay. + * 0b1..Enable drive delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + * 0b0..Disables sample delay. + * 0b1..Enables sample delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ + +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. */ +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. */ +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. */ +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b0..use PLL. + * 0b1..PLL input clock is sent directly to the PLL output. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. */ +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + * 0b1..modify the bandwidth of the PLL directly. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b0..use the pre-divider. + * 0b1..bypass of the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b0..use the post-divider. + * 0b1..bypass of the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b0..Disable the output clock. + * 0b1..Enable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. */ +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. */ +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b0..skewmode is disable. + * 0b1..skewmode is enable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ + +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. */ +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. */ +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. */ +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). */ +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). */ +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. */ +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ + +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). */ +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. */ +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) */ +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. */ +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ + +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. */ +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. */ +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. */ +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b0..use PLL. + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. */ +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + * 0b1..modify the bandwidth of the PLL directly. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b0..use the pre-divider. + * 0b1..bypass of the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b0..use the post-divider. + * 0b1..bypass of the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b0..disable the output clock. + * 0b1..enable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b0..free running mode is disable. + * 0b1..free running mode is enable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. */ +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b0..skew mode is disable. + * 0b1..skew mode is enable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ + +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. */ +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. */ +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. */ +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). */ +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). */ +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. */ +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) */ +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. */ +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. */ +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. */ +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. */ +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. */ +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. */ +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. */ +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. */ +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name FUNCRETENTIONCTRL - Functional retention control register */ +/*! @{ */ + +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b0..disable functional retention. + * 0b1..enable functional retention. + */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ + +#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) +/*! CPU1CLKEN - CPU1 clock enable. + * 0b0..The CPU1 clock is not enabled. + * 0b1..The CPU1 clock is enabled. + */ +#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) + +#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) +/*! CPU1RSTEN - CPU1 reset. + * 0b0..The CPU1 is not being reset. + * 0b1..The CPU1 is being reset. + */ +#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ + +#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +/*! CPBOOT - Coprocessor Boot Address for CPU1. */ +#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b0..the CPU is not sleeping. + * 0b1..the CPU is sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) +/*! CPU1SLEEPING - The CPU1 sleeping state. + * 0b0..the CPU is not sleeping. + * 0b1..the CPU is sleeping. + */ +#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b0..the CPU is not in lockup. + * 0b1..the CPU is in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) + +#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) +/*! CPU1LOCKUP - The CPU1 lockup state. + * 0b0..the CPU is not in lockup. + * 0b1..the CPU is in lockup. + */ +#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b0..The clock is not enabled. + * 0b1..The clock is enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ + +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b0..interrupt disable. + * 0b1..interrupt enable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ + +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b0..P+ is smaller than P-. + * 0b1..P+ is greater than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) +/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) +/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b0..Automatic clock gating is not overridden. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ + +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, + * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * 0b0000..Any other value than b1010: disable write access to all 6 registers. + * 0b1010..1010: Enable write access to all 6 registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b01..Any other value than b10: invasive debug is disable. + * 0b10..10: Invasive debug is enabled. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ +/*! @{ */ + +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name CPUCFG - CPUs configuration register */ +/*! @{ */ + +#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) +#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) +/*! CPU1ENABLE - Enable CPU1. + * 0b0..CPU1 is disable (Processor in reset). + * 0b1..CPU1 is enable. + */ +#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. */ +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; + + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} + + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SYSCON_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCTL.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCTL.h new file mode 100644 index 0000000000..3b8a5948b0 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_SYSCTL.h @@ -0,0 +1,356 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for SYSCTL +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SYSCTL.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SYSCTL + * + * CMSIS Peripheral Access Layer for SYSCTL + */ + +#if !defined(PERI_SYSCTL_H_) +#define PERI_SYSCTL_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Size of Registers Arrays */ +#define SYSCTL_FCCTRLSEL_COUNT 8u +#define SYSCTL_SHAREDCTRLSET_COUNT 2u + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[SYSCTL_FCCTRLSEL_COUNT]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[SYSCTL_SHAREDCTRLSET_COUNT]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ + +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ + +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ + +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SYSCTL_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USART.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USART.h new file mode 100644 index 0000000000..bb9255c123 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USART.h @@ -0,0 +1,1094 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for USART +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_USART.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for USART + * + * CMSIS Peripheral Access Layer for USART + */ + +#if !defined(PERI_USART_H_) +#define PERI_USART_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ + +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ + +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ + +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of + * receiving data. When 1, indicates that the receiver is not currently in the process of receiving + * data. + */ +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of + * sending data.When 1, indicate that the transmitter is not currently in the process of sending + * data. + */ +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the + * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode + * is enabled. + */ +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. */ +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART + * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + */ +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection + * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also + * be set when this condition occurs because the stop bit(s) for the character would be missing. + * RXBRK is cleared when the Un_RXD pin goes high. + */ +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. */ +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily + * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. + * Cleared by software. + */ +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a + * missing stop bit at the expected location. This could be an indication of a baud rate or + * configuration mismatch with the transmitting source. + */ +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. */ +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to + * determine the value of each received data bit, except in synchronous mode. This acts as a + * noise filter if one sample disagrees. This flag is set when a received data bit contains one + * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or + * loss of synchronization during data reception. + */ +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the + * end of the start bit that is being measured, essentially an auto baud time-out. + */ +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). */ +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. */ +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by + * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + */ +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection + * of a received break condition (break condition asserted or deasserted). + */ +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. */ +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. */ +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. */ +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. */ +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. */ +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ + +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. */ +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ + +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on + * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is + * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART + * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + */ +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ + +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle status. */ +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. */ +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt flag. */ +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. */ +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. */ +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. */ +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. */ +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. */ +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto baud Error Interrupt flag. */ +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ + +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to + * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive + * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + */ +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ + +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is + * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + */ +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. */ +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. */ +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. */ +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. */ +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. */ +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. */ +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. */ +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. */ +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. */ +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. */ +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. */ +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. */ +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. */ +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. */ +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. */ +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. */ +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. */ +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. */ +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USART_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USB.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USB.h new file mode 100644 index 0000000000..e2c8483854 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USB.h @@ -0,0 +1,645 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for USB +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_USB.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for USB + * + * CMSIS Peripheral Access Layer for USB + */ + +#if !defined(PERI_USB_H_) +#define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit + * is set, the device will respond on packets for function address DEV_ADDR. When receiving a + * SetAddress Control Request from the USB host, software must program the new address before + * completing the status phase of the SetAddress Control Request. + */ +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. */ +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this + * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW + * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the + * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + */ +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device + * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and + * the VBUSDEBOUNCED bit is one. + */ +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set + * to 1 when the device hasn't seen any activity on its upstream port for more than 3 + * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and + * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen + * when the device is connected (Connect bit = 1). When the device is not connected or not + * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + */ +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is + * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the + * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend + * bit = 1) and the software writes a zero to this bit, the device will generate a remote + * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this + * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the + * LPM_SUPP bit is equal to one. + */ +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake + * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the + * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset + * is received. Software can use this bit to check if the remote wake-up feature is enabled by the + * host for the LPM transaction. + */ +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up + * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit + * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The + * device is disconnected - The device receives resume signaling on its upstream port. The bit is + * reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On + * a bus reset the device will automatically go to the default state (unconfigured and responding + * to address 0). The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when + * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and + * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + */ +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. + * In case no SOF was received by the device at the beginning of a frame, the frame number + * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC + * error, the frame number returned will be the corrupted frame number as received by the device. + */ +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. */ +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. */ +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. */ +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. */ +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token */ +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB + * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + */ +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and + * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has + * still data pending and LPM is supported, it must set this bit to 1. + */ +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. When HW has + * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An + * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, + * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + */ +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer + * 0. 1: HW is accessing buffer 1. + */ +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: + * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding + * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle + * the EPINUSE bit when it clears the Active bit for the buffer. + */ +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set + * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is + * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a + * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a + * one to it. + */ +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if + * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this + * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can + * clear this bit by writing a one to it. + */ +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit + * and the DCON bit are set. This bit can be used by software when handling isochronous + * endpoints. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device + * Status Change register are set. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt + * routing bit. + */ +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status register + * is returned. + */ +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. */ +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USB_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBFSH.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBFSH.h new file mode 100644 index 0000000000..ff62a42501 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBFSH.h @@ -0,0 +1,751 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for USBFSH +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_USBFSH.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for USBFSH + * + * CMSIS Peripheral Access Layer for USBFSH + */ + +#if !defined(PERI_USBFSH_H_) +#define PERI_USBFSH_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ + +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision. */ +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ + +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. */ +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. */ +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. */ +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. */ +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. */ +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL + * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin + * 1 ms later. + */ +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. */ +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. */ +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ + +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. */ +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. */ +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. */ +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. */ +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. */ +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and + * after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. */ +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. */ +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. */ +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. */ +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, + * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + */ +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. */ +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. */ +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. */ +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. */ +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. */ +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ + +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Base address of the Host Controller Communication Area. */ +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. */ +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. */ +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED. */ +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. */ +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. */ +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ + +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. */ +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ + +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. */ +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. */ +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ + +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining This counter is decremented at each bit time. */ +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval + * whenever FrameRemaining reaches 0. + */ +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ + +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. */ +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ + +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. */ +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ + +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field + * prior to initiating a Low Speed transaction. + */ +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. */ +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. */ +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. */ +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType This bit specifies that the root hub is not a compound device. */ +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. */ +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. */ +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before + * accessing a powered-on port of the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. */ +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control + * command when PowerSwitchingMode is set. + */ +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ + +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; + * thus, this bit is always read as 0. + */ +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. */ +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume + * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected + * interrupt. + */ +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. */ +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. */ +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. */ +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ + +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. */ +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. */ +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. */ +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in + * such a way that overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. */ +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type + * of power switching implemented. + */ +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. */ +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. */ +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. */ +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. */ +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. */ +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. */ +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. */ +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. */ +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - 1: device 0: host. */ +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USBFSH_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSD.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSD.h new file mode 100644 index 0000000000..807f76e4c7 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSD.h @@ -0,0 +1,520 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for USBHSD +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_USBHSD.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for USBHSD + * + * CMSIS Peripheral Access Layer for USBHSD + */ + +#if !defined(PERI_USBHSD_H_) +#define PERI_USBHSD_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. */ +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) + +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. */ +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) + +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. */ +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported:. */ +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. */ +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. */ +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. */ +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. */ +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) + +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: + * full-speed 10b: high-speed 11b: super-speed (reserved for future use). + */ +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. */ +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. */ +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) + +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. */ +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) + +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. */ +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) + +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + * 0b000..Test mode disabled. + * 0b001..Test_J. + * 0b010..Test_K. + * 0b011..Test_SE0_NAK. + * 0b100..Test_Packet. + * 0b101..Test_Force_Enable. + */ +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. */ +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) + +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred:. */ +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) + +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor revision. */ +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) + +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major revision. */ +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) + +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. */ +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. */ +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. */ +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) + +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. */ +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) + +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. + */ +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. + */ +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. */ +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. */ +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. */ +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) + +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. */ +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) + +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. */ +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) + +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. */ +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) + +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. */ +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) + +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. */ +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) + +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. */ +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) + +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. */ +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) + +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. */ +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) + +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. */ +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) + +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. */ +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) + +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +/*! EP5IN - Interrupt status register bit for the EP5 IN direction. */ +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) + +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. */ +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) + +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. */ +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) + +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) + +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. */ +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. */ +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. */ +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. */ +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USBHSD_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSH.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSH.h new file mode 100644 index 0000000000..37313554ed --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBHSH.h @@ -0,0 +1,589 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for USBHSH +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_USBHSH.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for USBHSH + * + * CMSIS Peripheral Access Layer for USBHSH + */ + +#if !defined(PERI_USBHSH_H_) +#define PERI_USBHSH_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_1[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ + +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - Capability Length: This is used as an offset. */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) + +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major + * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + */ +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. */ +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) + +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - This field indicates whether the host controller implementation includes port power control. */ +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) + +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. */ +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ + +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +/*! FLADJ - Frame Length Timing Value. */ +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) + +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. */ +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. */ +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) + +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. */ +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. */ +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) + +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. */ +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) +/*! @} */ + +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ +/*! @{ */ + +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. */ +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) + +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. */ +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) +/*! @} */ + +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ + +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. */ +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ + +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop: 1b = Run. */ +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) + +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. */ +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) + +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +/*! FLS - Frame List Size: This field specifies the size of the frame list. */ +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) + +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host + * controller without affecting the state of the ports. + */ +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) + +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +/*! ATL_EN - ATL List enabled. */ +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) + +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +/*! ISO_EN - ISO List enabled. */ +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) + +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +/*! INT_EN - INT List enabled. */ +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ + +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a + * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a + * result of a J-K transition detected on a suspended port. + */ +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) + +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list + * index rolls over its maximum value to 0. + */ +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) + +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. */ +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) + +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. */ +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) + +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. */ +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) + +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. */ +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ + +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. */ +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) + +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. */ +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) + +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. */ +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) + +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. */ +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) + +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. */ +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) + +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. */ +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ + +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. */ +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) + +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. */ +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) + +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +/*! PED - Port Enabled/Disabled. */ +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) + +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. */ +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) + +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. */ +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) + +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. */ +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) + +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. */ +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) + +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend: Logic 1 means port is in the suspend state. */ +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) + +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset: Logic 1 means the port is in the reset state. */ +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) + +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. */ +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) + +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. */ +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) + +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the + * HCSPARAMS register is logic 0. + */ +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) + +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. */ +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) + +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. */ +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) + +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to + * overcurrent conditions as wake-up events. + */ +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +/*! @} */ + +/*! @name ATLPTDD - Done map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. */ +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATLPTDS - Skip map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISOPTDD - Done map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. */ +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISOPTDS - Skip map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. */ +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INTPTDD - Done map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. */ +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) +/*! @} */ + +/*! @name INTPTDS - Skip map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) +/*! @} */ + +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ + +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. */ +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) + +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +/*! ISO_LAST - This indicates the last PTD in the ISO list. */ +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) + +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +/*! INT_LAST - This indicates the last PTD in the INT list. */ +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. */ +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) + +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. */ +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) + +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. */ +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USBHSH_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBPHY.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBPHY.h new file mode 100644 index 0000000000..d5cda73237 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_USBPHY.h @@ -0,0 +1,1927 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for USBPHY +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_USBPHY.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for USBPHY + * + * CMSIS Peripheral Access Layer for USBPHY + */ + +#if !defined(PERI_USBPHY_H_) +#define PERI_USBPHY_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_1[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + uint8_t RESERVED_2[48]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'ANACTRL' */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) + +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) + +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) + +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) + +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USBPHY_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_UTICK.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_UTICK.h new file mode 100644 index 0000000000..7500231ed5 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_UTICK.h @@ -0,0 +1,301 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for UTICK +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_UTICK.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for UTICK + * + * CMSIS Peripheral Access Layer for UTICK + */ + +#if !defined(PERI_UTICK_H_) +#define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Size of Registers Arrays */ +#define UTICK_CAP_COUNT 4u + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[UTICK_CAP_COUNT]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer + * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any + * value to this register clears this flag. + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower + * than the actual value of the Micro-tick Timer at the moment of the capture event. + */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related + * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_UTICK_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_WWDT.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_WWDT.h new file mode 100644 index 0000000000..fc890311a9 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/periph/PERI_WWDT.h @@ -0,0 +1,273 @@ +/* +** ################################################################### +** Processors: LPC5526JBD100 +** LPC5526JBD64 +** LPC5526JEV98 +** LPC5528JBD100 +** LPC5528JBD64 +** LPC5528JEV59 +** LPC5528JEV98 +** LPC55S26JBD100 +** LPC55S26JBD64 +** LPC55S26JEV98 +** LPC55S28JBD100 +** LPC55S28JBD64 +** LPC55S28JEV59 +** LPC55S28JEV98 +** LPC55S66JBD100_cm33_core0 +** LPC55S66JBD100_cm33_core1 +** LPC55S66JBD64_cm33_core0 +** LPC55S66JBD64_cm33_core1 +** LPC55S66JEV98_cm33_core0 +** LPC55S66JEV98_cm33_core1 +** LPC55S69JBD100_cm33_core0 +** LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core0 +** LPC55S69JEV98_cm33_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250529 +** +** Abstract: +** CMSIS Peripheral Access Layer for WWDT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_WWDT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for WWDT + * + * CMSIS Peripheral Access Layer for WWDT + */ + +#if !defined(PERI_WWDT_H_) +#define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_LPC5526JBD100) || defined(CPU_LPC5526JBD64) || defined(CPU_LPC5526JEV98)) +#include "LPC5526_COMMON.h" +#elif (defined(CPU_LPC5528JBD100) || defined(CPU_LPC5528JBD64) || defined(CPU_LPC5528JEV59) || defined(CPU_LPC5528JEV98)) +#include "LPC5528_COMMON.h" +#elif (defined(CPU_LPC55S26JBD100) || defined(CPU_LPC55S26JBD64) || defined(CPU_LPC55S26JEV98)) +#include "LPC55S26_COMMON.h" +#elif (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV59) || defined(CPU_LPC55S28JEV98)) +#include "LPC55S28_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core0) || defined(CPU_LPC55S66JBD64_cm33_core0) || defined(CPU_LPC55S66JEV98_cm33_core0)) +#include "LPC55S66_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S66JBD100_cm33_core1) || defined(CPU_LPC55S66JBD64_cm33_core1) || defined(CPU_LPC55S66JEV98_cm33_core1)) +#include "LPC55S66_cm33_core1_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) +#include "LPC55S69_cm33_core0_COMMON.h" +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) +#include "LPC55S69_cm33_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by + * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a + * chip reset if WDRESET = 1. + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. + * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the + * WARNINT value is equal to the value of the TV register. This can occur if the value of + * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog time-out value. */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed value should be 0xAA followed by 0x55. */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter timer value. */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog warning interrupt compare value. */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog window value. */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WWDT_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c new file mode 100644 index 0000000000..9f84186d89 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c @@ -0,0 +1,385 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250918 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 2.0 + * @date 2024-10-29 + * @brief Device specific configuration file for LPC55S69_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* PLL0 SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC settings */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1UL; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0UL) + { + mMult = 1UL; + } + return mMult; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +static uint32_t GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0U; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK + | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; +#endif +/* Optionally enable prefetch */ +#if !defined(DONT_ENABLE_FLASH_PREFETCH) + SYSCON->FMCCR |= SYSCON_FMCCR_PREFEN_MASK; +#endif + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + uint64_t workRate1; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + default: /* = 0x03 = FRO 96 MHz (fro_hf) */ + clkRate = GetFroHfFreq(); + break; + } + break; + case 0x01: /* PLL0 clock (pll0_clk)*/ + switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); + clkRate = (uint32_t)((workRate / ((uint64_t)postdiv)) & 0xFFFFFFFFUL); + } + break; + case 0x02: /* PLL1 clock (pll1_clk)*/ + switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); + clkRate = (uint32_t)((workRate1 / ((uint64_t)postdiv)) & 0xFFFFFFFFUL); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h new file mode 100644 index 0000000000..665ac91369 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h @@ -0,0 +1,118 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250918 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 2.0 + * @date 2024-10-29 + * @brief Device specific configuration file for LPC55S69_cm33_core0 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S69_cm33_core0_H_ +#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/config.cmake b/platform/ext/target/nxp/lpcxpresso55s69/config.cmake index b8802e5528..f61e1fb90a 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/config.cmake +++ b/platform/ext/target/nxp/lpcxpresso55s69/config.cmake @@ -1,15 +1,13 @@ #------------------------------------------------------------------------------- # Copyright (c) 2020-2023, Arm Limited. All rights reserved. -# Copyright (c) 2021-2024 NXP +# Copyright 2021-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause # #------------------------------------------------------------------------------- ################################## Dependencies ################################ -set(TFM_PLATFORM_NXP_HAL_FILE_PATH "DOWNLOAD" CACHE STRING "Path to the NXP SDK hal (or DOWNLOAD to fetch automatically)") -set(NXP_SDK_GIT_REP "https://raw.githubusercontent.com/nxp-mcuxpresso/mcux-sdk" CACHE STRING "The repository address of the NXP MCUXpresso SDK") -set(NXP_SDK_GIT_TAG "MCUX_2.15.000" CACHE STRING "The version of the NXP MCUXpresso SDK") +set(TFM_PLATFORM_NXP_HAL_FILE_PATH "LOCAL" CACHE STRING "Path to the NXP SDK hal drivers") ############################ Platform ########################################## set(PLATFORM_DEFAULT_ATTEST_HAL ON CACHE BOOL "Use default attest hal implementation.") diff --git a/platform/ext/target/nxp/lpcxpresso55s69/ns/CMakeLists.txt b/platform/ext/target/nxp/lpcxpresso55s69/ns/CMakeLists.txt index 7ccbcf4b7c..70fee4b47a 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/ns/CMakeLists.txt +++ b/platform/ext/target/nxp/lpcxpresso55s69/ns/CMakeLists.txt @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------- # Copyright (c) 2023-2024, Arm Limited. All rights reserved. -# Copyright 2023-2024 NXP. All rights reserved. +# Copyright 2023-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause # @@ -29,14 +29,14 @@ target_sources(platform_ns Native_Driver/components/serial_manager/fsl_component_serial_manager.c Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c Native_Driver/components/uart/fsl_adapter_usart.c - Native_Driver/drivers/fsl_common.c - Native_Driver/drivers/fsl_common_arm.c - Native_Driver/drivers/fsl_ctimer.c - Native_Driver/drivers/fsl_flexcomm.c - Native_Driver/drivers/fsl_gpio.c - Native_Driver/drivers/fsl_iap.c - Native_Driver/drivers/fsl_usart.c - Native_Driver/utilities/fsl_assert.c + Native_Driver/drivers/common/fsl_common.c + Native_Driver/drivers/common/fsl_common_arm.c + Native_Driver/drivers/ctimer/fsl_ctimer.c + Native_Driver/drivers/flexcomm/fsl_flexcomm.c + Native_Driver/drivers/flexcomm/usart/fsl_usart.c + Native_Driver/drivers/lpc_gpio/fsl_gpio.c + Native_Driver/drivers/iap1/fsl_iap.c + Native_Driver/utilities/assert/fsl_assert.c Native_Driver/utilities/debug_console/fsl_debug_console.c Native_Driver/utilities/str/fsl_str.c $<$:plat_test.c> @@ -53,11 +53,20 @@ target_include_directories(platform_ns Device/Include Device/Config Native_Driver/drivers + Native_Driver/drivers/common + Native_Driver/drivers/ctimer + Native_Driver/drivers/iap1 + Native_Driver/drivers/lpc_gpio + Native_Driver/drivers/lpc_iocon + Native_Driver/drivers/flexcomm + Native_Driver/drivers/flexcomm/usart Native_Driver/components/lists Native_Driver/components/serial_manager Native_Driver/components/uart Native_Driver/utilities/debug_console Native_Driver/utilities/str + Native_Driver/utilities/assert + Native_Driver/periph partition ) diff --git a/platform/ext/target/nxp/lpcxpresso55s69/pull_drivers.cmake b/platform/ext/target/nxp/lpcxpresso55s69/pull_drivers.cmake deleted file mode 100644 index 7a2c7d7108..0000000000 --- a/platform/ext/target/nxp/lpcxpresso55s69/pull_drivers.cmake +++ /dev/null @@ -1,82 +0,0 @@ -#------------------------------------------------------------------------------- -# Copyright (c) 2020-2021, Arm Limited. All rights reserved. -# Copyright (c) 2021-2024, NXP Semiconductors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -#------------------------------------------------------------------------------- - -#========================= Pull MCUxpresso NXP SDK drivers from https://github.com/NXPmicro/mcux-sdk =========================# -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/common/fsl_common.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/common/fsl_common.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common.h) - -#FIXME: Revert after MCUx SDK upadte to CMSISv6 file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/common/fsl_common_arm.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common_arm.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/common/fsl_common_arm.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_common_arm.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/ctimer/fsl_ctimer.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_ctimer.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/ctimer/fsl_ctimer.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_ctimer.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/flexcomm/fsl_flexcomm.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_flexcomm.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/flexcomm/fsl_flexcomm.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_flexcomm.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/lpc_gpio/fsl_gpio.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_gpio.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/lpc_gpio/fsl_gpio.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_gpio.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/iap1/fsl_iap.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/iap1/fsl_iap.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap.h) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/iap1/fsl_iap_kbp.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap_kbp.h) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/iap1/fsl_iap_skboot_authenticate.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap_skboot_authenticate.h) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/iap1/fsl_iap_ffr.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iap_ffr.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/lpc_iocon/fsl_iocon.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_iocon.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/flexcomm/fsl_usart.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_usart.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/drivers/flexcomm/fsl_usart.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/drivers/fsl_usart.h) - -#========================= Pull MCUxpresso NXP SDK components from https://github.com/NXPmicro/mcux-sdk =========================# -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/lists/fsl_component_generic_list.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/lists/fsl_component_generic_list.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/lists/fsl_component_generic_list.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/lists/fsl_component_generic_list.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/serial_manager/fsl_component_serial_manager.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/serial_manager/fsl_component_serial_manager.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/serial_manager/fsl_component_serial_port_internal.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/serial_manager/fsl_component_serial_port_uart.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/serial_manager/fsl_component_serial_port_uart.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/uart/fsl_adapter_uart.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/uart/fsl_adapter_uart.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/components/uart/fsl_adapter_usart.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/components/uart/fsl_adapter_usart.c) - -#========================= Pull MCUxpresso NXP SDK utilities from https://github.com/NXPmicro/mcux-sdk =========================# -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/debug_console/debug_console/fsl_debug_console.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console/fsl_debug_console.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/debug_console/debug_console/fsl_debug_console.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console/fsl_debug_console.h) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/debug_console/debug_console/fsl_debug_console_conf.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/debug_console/str/fsl_str.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/str/fsl_str.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/debug_console/str/fsl_str.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/str/fsl_str.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/assert/fsl_assert.c ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/fsl_assert.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/utilities/assert/fsl_assert.h ${NXP_HAL_FILE_PATH}/common/Native_Driver/utilities/fsl_assert.h) - -#========================= Pull MCUxpresso NXP SDK devices from https://github.com/NXPmicro/mcux-sdk =========================# -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/fsl_device_registers.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/fsl_device_registers.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/LPC55S69_cm33_core0.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/LPC55S69_cm33_core0_features.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/LPC55S69_cm33_core1.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/LPC55S69_cm33_core1_features.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/system_LPC55S69_cm33_core0.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/system_LPC55S69_cm33_core0.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/drivers/fsl_power.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/drivers/fsl_power.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/drivers/fsl_reset.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/drivers/fsl_reset.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h) - -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/drivers/fsl_clock.c ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c) -file(DOWNLOAD ${NXP_SDK_GIT_REP}/${NXP_SDK_GIT_TAG}/devices/LPC55S69/drivers/fsl_clock.h ${NXP_HAL_FILE_PATH}/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h) \ No newline at end of file From e56cc1cb7af011fff0a45e5dfcd06d6c190dc048 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Fri, 28 Nov 2025 13:00:39 +0200 Subject: [PATCH 126/133] [zep fromlist] platform: LPCXpresso55s69: fix unused function warnings In Zephyr we get a build failure on this platform because of the unused-function warning. Declare the affected functions as `static inline` so the compiler doesn't complain if they are unused. Change-Id: Id80e10264284bd5ffec55fc188e2969964a3506f Signed-off-by: Tomi Fontanilles --- .../nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c index 10706cd4ce..b6f24a1485 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.c @@ -400,7 +400,7 @@ static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) * @param * @return */ -static bool int32_MultiplyOverflow(int32_t a, int32_t b) { +static inline bool int32_MultiplyOverflow(int32_t a, int32_t b) { if (a == 0 || b == 0) return false; if (a > 0 && b > 0) return a > INT32_MAX / b; if (a < 0 && b < 0) return a < INT32_MAX / b; @@ -412,7 +412,7 @@ static bool int32_MultiplyOverflow(int32_t a, int32_t b) { * @param * @return */ -static bool int32_AddOverflow(int32_t a, int32_t b) { +static inline bool int32_AddOverflow(int32_t a, int32_t b) { if ((b > 0) && (a > INT32_MAX - b)) return true; if ((b < 0) && (a < INT32_MIN - b)) return true; return false; From a188ec0ff2a784d3e5b5444e3e25d3fce0fb9e60 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Mon, 17 Nov 2025 15:24:08 +0100 Subject: [PATCH 127/133] [zep fromlist] platform: nordic_nrf: update nrfx version to 4.0.1 Use nrfx 4.0.1 release. Change-Id: I838d1ece8bd5ba248e421334bdd6a140d5fc9a6c Signed-off-by: Nikodem Kastelik Signed-off-by: Tomi Fontanilles --- platform/ext/target/nordic_nrf/common/core/config.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/ext/target/nordic_nrf/common/core/config.cmake b/platform/ext/target/nordic_nrf/common/core/config.cmake index 85fc75874c..0b1f1fef7a 100644 --- a/platform/ext/target/nordic_nrf/common/core/config.cmake +++ b/platform/ext/target/nordic_nrf/common/core/config.cmake @@ -9,7 +9,7 @@ #------------------------------------------------------------------------------- set(HAL_NORDIC_PATH "DOWNLOAD" CACHE PATH "Path to the Nordic HAL (or DOWNLOAD to fetch automatically)") -set(HAL_NORDIC_VERSION "nrfx-3.12.1" CACHE STRING "Version of the Nordic HAL to download") +set(HAL_NORDIC_VERSION "nrfx-4.0.1" CACHE STRING "Version of the Nordic HAL to download") set(HAL_NORDIC_REMOTE "https://github.com/zephyrproject-rtos/hal_nordic" CACHE STRING "Remote of the Nordic HAL to download") # Set to FALSE if HAL_NORDIC_VERSION is a SHA. set(HAL_NORDIC_SHALLOW_FETCH CACHE BOOL TRUE "Use shallow fetch to download Nordic HAL.") From dd93b3c3109b404c193958584856bc473d37ec3c Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Tue, 18 Nov 2025 12:08:02 +0100 Subject: [PATCH 128/133] [zep fromlist dirty] {spm, partitions}: include `compiler_ext_defs.h` last Since `compiler_ext_defs.h` should define compiler symbols only if they have not been previously defined, it should be included as the last header to avoid redefine warnigns. Fix in all files. Change-Id: I010b8885b4e1b150ec527f0b246b95a4dab4902a Signed-off-by: Marcin Szymczyk Signed-off-by: Tomi Fontanilles --- secure_fw/partitions/ns_agent_tz/load_info_ns_agent_tz.c | 2 +- secure_fw/partitions/ns_agent_tz/ns_agent_tz.c | 2 +- secure_fw/partitions/ns_agent_tz/ns_agent_tz_v80m.c | 2 +- secure_fw/partitions/ns_agent_tz/psa_api_veneers_v80m.c | 2 +- secure_fw/spm/core/arch/tfm_arch.c | 2 +- secure_fw/spm/core/arch/tfm_arch_v6m_v7m.c | 2 +- secure_fw/spm/core/arch/tfm_arch_v8m_base.c | 2 +- secure_fw/spm/core/arch/tfm_arch_v8m_main.c | 2 +- secure_fw/spm/core/backend_ipc.c | 2 +- secure_fw/spm/core/backend_sfn.c | 2 +- secure_fw/spm/core/psa_interface_svc.c | 2 +- secure_fw/spm/core/psa_interface_thread_fn_call.c | 2 +- secure_fw/spm/core/spm_local_connection.c | 2 +- secure_fw/spm/core/tfm_pools.h | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/secure_fw/partitions/ns_agent_tz/load_info_ns_agent_tz.c b/secure_fw/partitions/ns_agent_tz/load_info_ns_agent_tz.c index e8f94dc825..133cd33cd9 100644 --- a/secure_fw/partitions/ns_agent_tz/load_info_ns_agent_tz.c +++ b/secure_fw/partitions/ns_agent_tz/load_info_ns_agent_tz.c @@ -12,7 +12,6 @@ #include #include -#include "compiler_ext_defs.h" #include "config_impl.h" #include "spm.h" #include "load/partition_defs.h" @@ -24,6 +23,7 @@ */ #include "region_defs.h" #include "tfm_s_linker_alignments.h" +#include "compiler_ext_defs.h" #define TFM_SP_NS_AGENT_NDEPS (0) #define TFM_SP_NS_AGENT_NSERVS (0) diff --git a/secure_fw/partitions/ns_agent_tz/ns_agent_tz.c b/secure_fw/partitions/ns_agent_tz/ns_agent_tz.c index 5ff988109f..eb8c63dafb 100644 --- a/secure_fw/partitions/ns_agent_tz/ns_agent_tz.c +++ b/secure_fw/partitions/ns_agent_tz/ns_agent_tz.c @@ -9,10 +9,10 @@ */ #include -#include "compiler_ext_defs.h" #include "security_defs.h" #include "tfm_arch.h" #include "tfm_hal_platform.h" +#include "compiler_ext_defs.h" __naked void ns_agent_tz_main(uint32_t c_entry) { diff --git a/secure_fw/partitions/ns_agent_tz/ns_agent_tz_v80m.c b/secure_fw/partitions/ns_agent_tz/ns_agent_tz_v80m.c index 27103c9a60..f1cd2664ac 100644 --- a/secure_fw/partitions/ns_agent_tz/ns_agent_tz_v80m.c +++ b/secure_fw/partitions/ns_agent_tz/ns_agent_tz_v80m.c @@ -9,10 +9,10 @@ */ #include -#include "compiler_ext_defs.h" #include "security_defs.h" #include "tfm_arch.h" #include "tfm_hal_platform.h" +#include "compiler_ext_defs.h" __naked void ns_agent_tz_main(uint32_t c_entry) { diff --git a/secure_fw/partitions/ns_agent_tz/psa_api_veneers_v80m.c b/secure_fw/partitions/ns_agent_tz/psa_api_veneers_v80m.c index 1e051af7c4..1993dfb7f9 100644 --- a/secure_fw/partitions/ns_agent_tz/psa_api_veneers_v80m.c +++ b/secure_fw/partitions/ns_agent_tz/psa_api_veneers_v80m.c @@ -8,7 +8,6 @@ #include #include "cmsis_compiler.h" -#include "compiler_ext_defs.h" #include "config_impl.h" #include "security_defs.h" #include "svc_num.h" @@ -17,6 +16,7 @@ #include "psa/client.h" #include "psa/service.h" #include "tfm_arch.h" +#include "compiler_ext_defs.h" /* * This is the veneers of FF-M Client APIs for Armv8.0-m. diff --git a/secure_fw/spm/core/arch/tfm_arch.c b/secure_fw/spm/core/arch/tfm_arch.c index 4779f7f103..4a4ca30ad7 100644 --- a/secure_fw/spm/core/arch/tfm_arch.c +++ b/secure_fw/spm/core/arch/tfm_arch.c @@ -5,12 +5,12 @@ * */ -#include "compiler_ext_defs.h" #include "security_defs.h" #include "tfm_arch.h" #include "tfm_core_trustzone.h" #include "utilities.h" #include "config_impl.h" +#include "compiler_ext_defs.h" #if defined(__ICCARM__) && (CONFIG_TFM_FLOAT_ABI >= 1) #pragma required = tfm_arch_clear_fp_data diff --git a/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.c b/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.c index c922553dcf..9c01e034fd 100644 --- a/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.c +++ b/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.c @@ -6,7 +6,6 @@ */ #include -#include "compiler_ext_defs.h" #include "security_defs.h" #include "utilities.h" #include "spm.h" @@ -14,6 +13,7 @@ #include "tfm_hal_device_header.h" #include "tfm_svcalls.h" #include "svc_num.h" +#include "compiler_ext_defs.h" #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && \ !defined(__ARM_ARCH_7EM__) diff --git a/secure_fw/spm/core/arch/tfm_arch_v8m_base.c b/secure_fw/spm/core/arch/tfm_arch_v8m_base.c index bea45b5252..d7ec304906 100644 --- a/secure_fw/spm/core/arch/tfm_arch_v8m_base.c +++ b/secure_fw/spm/core/arch/tfm_arch_v8m_base.c @@ -9,7 +9,6 @@ */ #include -#include "compiler_ext_defs.h" #include "config_spm.h" #include "security_defs.h" #include "spm.h" @@ -18,6 +17,7 @@ #include "tfm_arch.h" #include "tfm_svcalls.h" #include "utilities.h" +#include "compiler_ext_defs.h" #if !defined(__ARM_ARCH_8M_BASE__) #error "Unsupported ARM Architecture." diff --git a/secure_fw/spm/core/arch/tfm_arch_v8m_main.c b/secure_fw/spm/core/arch/tfm_arch_v8m_main.c index 14f0be7f29..de79b3f1a0 100644 --- a/secure_fw/spm/core/arch/tfm_arch_v8m_main.c +++ b/secure_fw/spm/core/arch/tfm_arch_v8m_main.c @@ -10,7 +10,6 @@ #include -#include "compiler_ext_defs.h" #include "config_spm.h" #include "security_defs.h" #include "region_defs.h" @@ -22,6 +21,7 @@ #include "utilities.h" #include "core_ext.h" #include "ffm/backend.h" +#include "compiler_ext_defs.h" #if !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) #error "Unsupported ARM Architecture." diff --git a/secure_fw/spm/core/backend_ipc.c b/secure_fw/spm/core/backend_ipc.c index 7e9dfb0495..2637ebbd1a 100644 --- a/secure_fw/spm/core/backend_ipc.c +++ b/secure_fw/spm/core/backend_ipc.c @@ -13,7 +13,6 @@ #include "async.h" #include "config_spm.h" #include "critical_section.h" -#include "compiler_ext_defs.h" #include "config_spm.h" #include "ffm/psa_api.h" #include "fih.h" @@ -34,6 +33,7 @@ #include "psa/error.h" #include "internal_status_code.h" #include "sprt_partition_metadata_indicator.h" +#include "compiler_ext_defs.h" #if TFM_PARTITION_NS_AGENT_MAILBOX == 1 #include "psa_manifest/ns_agent_mailbox.h" diff --git a/secure_fw/spm/core/backend_sfn.c b/secure_fw/spm/core/backend_sfn.c index 6e9c3e9bfa..7ffa5adbb6 100644 --- a/secure_fw/spm/core/backend_sfn.c +++ b/secure_fw/spm/core/backend_sfn.c @@ -9,7 +9,6 @@ */ #include -#include "compiler_ext_defs.h" #include "current.h" #include "runtime_defs.h" #include "tfm_hal_platform.h" @@ -24,6 +23,7 @@ #include "spm.h" #include "memory_symbols.h" #include "private/assert.h" +#include "compiler_ext_defs.h" /* SFN Partition state */ #define SFN_PARTITION_STATE_NOT_INITED 0 diff --git a/secure_fw/spm/core/psa_interface_svc.c b/secure_fw/spm/core/psa_interface_svc.c index a93ef6b564..3bd4f0ead4 100644 --- a/secure_fw/spm/core/psa_interface_svc.c +++ b/secure_fw/spm/core/psa_interface_svc.c @@ -6,7 +6,6 @@ */ #include -#include "compiler_ext_defs.h" #include "config_spm.h" #include "runtime_defs.h" #include "svc_num.h" @@ -15,6 +14,7 @@ #include "psa/client.h" #include "psa/lifecycle.h" #include "psa/service.h" +#include "compiler_ext_defs.h" __naked uint32_t psa_framework_version_svc(void) { diff --git a/secure_fw/spm/core/psa_interface_thread_fn_call.c b/secure_fw/spm/core/psa_interface_thread_fn_call.c index 89e9dc86cf..fe6063fcd2 100644 --- a/secure_fw/spm/core/psa_interface_thread_fn_call.c +++ b/secure_fw/spm/core/psa_interface_thread_fn_call.c @@ -6,7 +6,6 @@ */ #include -#include "compiler_ext_defs.h" #include "config_spm.h" #include "ffm/psa_api.h" #include "spm.h" @@ -17,6 +16,7 @@ #include "psa/service.h" #include "runtime_defs.h" #include "tfm_arch.h" +#include "compiler_ext_defs.h" #if defined(__ICCARM__) #pragma required = tfm_arch_thread_fn_call diff --git a/secure_fw/spm/core/spm_local_connection.c b/secure_fw/spm/core/spm_local_connection.c index 6475771b7e..892f1aecd7 100644 --- a/secure_fw/spm/core/spm_local_connection.c +++ b/secure_fw/spm/core/spm_local_connection.c @@ -5,10 +5,10 @@ * */ -#include "compiler_ext_defs.h" #include "internal_status_code.h" #include "spm.h" #include "tfm_arch.h" +#include "compiler_ext_defs.h" #ifdef CONFIG_TFM_CONN_HANDLE_MAX_NUM #pragma message("CONFIG_TFM_CONN_HANDLE_MAX_NUM is not used in SFN model without connection-based services.") diff --git a/secure_fw/spm/core/tfm_pools.h b/secure_fw/spm/core/tfm_pools.h index 3b77513695..e9d58cc5b3 100644 --- a/secure_fw/spm/core/tfm_pools.h +++ b/secure_fw/spm/core/tfm_pools.h @@ -9,8 +9,8 @@ #include #include "psa/error.h" -#include "compiler_ext_defs.h" #include "lists.h" +#include "compiler_ext_defs.h" /* * Pool Instance: From 60c17678dffb19623451b845e303ba20bc44465f Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Fri, 11 Jul 2025 15:47:15 +0200 Subject: [PATCH 129/133] [zep noup] Platform: ext: accelerator: stm: Disable HW acceleration for BL2 stage Disable HW crypto accelerator in STM BL2 stage since embedding them requires their driver integrates through the PSA unified driver API. This is a requirement from TF-M since it moved to MCUBoot 2.2.0. Removing CRYPTO_HW_ACCELERATOR from platform_bl2 is not sufficient to have them disabled in Zephyr TF-M integration so provide a empty config file to ensure BL2 crypto target (bl2_crypto) will not expect HW accelerator resources. We'll be enable to restore them once they comply with PSA driver API. Note that in mainline TF-M, STM HW accelerator driver are currently not embedded in BL2 firmware so this change provides at least the same embedded feature set as mainline TF-M branch 2.2.x. Signed-off-by: Etienne Carriere --- platform/ext/accelerator/stm/CMakeLists.txt | 5 +++++ .../accelerator/stm/bl2_disabled_crypto_accelerator_config.h | 0 2 files changed, 5 insertions(+) create mode 100644 platform/ext/accelerator/stm/bl2_disabled_crypto_accelerator_config.h diff --git a/platform/ext/accelerator/stm/CMakeLists.txt b/platform/ext/accelerator/stm/CMakeLists.txt index 7c6cf6bca4..16509043cc 100644 --- a/platform/ext/accelerator/stm/CMakeLists.txt +++ b/platform/ext/accelerator/stm/CMakeLists.txt @@ -52,6 +52,11 @@ if (BL2) # don't enable any _ALT feature which are going to be deprecated # MBEDTLS_ACCELERATOR_CONFIG_FILE="${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/mbedtls_accelerator_config.h" # MBEDTLS_ACCELERATOR_PSA_CRYPTO_CONFIG_FILE="${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/crypto_accelerator_config.h" + + # Since TF-M 2.2.x and MCUBoot 2.2.0 require BL2 HW crypto + # accelerator to implement the PSA unified driver API, force + # disabling of use of STM HW accelerator in BL2 until they comply. + MBEDTLS_ACCELERATOR_PSA_CRYPTO_CONFIG_FILE="${PLATFORM_DIR}/ext/accelerator/stm/bl2_disabled_crypto_accelerator_config.h" ) endif() include(${PLATFORM_DIR}/ext/target/${TFM_PLATFORM}/accelerator/CMakeLists.txt) diff --git a/platform/ext/accelerator/stm/bl2_disabled_crypto_accelerator_config.h b/platform/ext/accelerator/stm/bl2_disabled_crypto_accelerator_config.h new file mode 100644 index 0000000000..e69de29bb2 From 4a0b1a8e99d618025c5f9ece9b657a6cbb4bf83b Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 30 Sep 2022 13:35:17 +0100 Subject: [PATCH 130/133] [zep noup] build: gcc: Force DWARF v4 This forces DWARF version 4 output so that zephyr debugging and usage still works with the pyelftools library which does not currently support v5. see https://github.com/zephyrproject-rtos/zephyr/issues/50373 Signed-off-by: Jamie McCrae --- toolchain_GNUARM.cmake | 2 ++ 1 file changed, 2 insertions(+) diff --git a/toolchain_GNUARM.cmake b/toolchain_GNUARM.cmake index 27097536fe..46e28b4ab2 100644 --- a/toolchain_GNUARM.cmake +++ b/toolchain_GNUARM.cmake @@ -122,6 +122,8 @@ add_compile_options( -mthumb $<$:-std=c99> $<$:-std=c++11> + # Force DWARF version 4 for zephyr as pyelftools does not support version 5 at present + -gdwarf-4 $<$,$>:-g> $<$,$,$>:-Og> $<$,$>:-Werror> From d9457095f7e48e5d36b21222664a2b2fba88bf6e Mon Sep 17 00:00:00 2001 From: Kevin Townsend Date: Thu, 9 Feb 2023 21:52:21 +0100 Subject: [PATCH 131/133] [zep noup] lib: ext: Disable t_cose and qcbor if not required Avoids including `t_cose` and `qcbor` in the build unless the initial attestation secure partition is enabled via the `TFM_PARTITION_INITIAL_ATTESTATION` flag. This is required to avoid automatically downloading QCBOR at build time -- pulled in as a dependency of t_cose -- unless required. This commit should be reverted once an acceptable upstream solution has been found for this situation, and merged there. Signed-off-by: Kevin Townsend --- lib/ext/CMakeLists.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/ext/CMakeLists.txt b/lib/ext/CMakeLists.txt index 05f6b8f145..aa5525bb7a 100644 --- a/lib/ext/CMakeLists.txt +++ b/lib/ext/CMakeLists.txt @@ -6,8 +6,10 @@ #------------------------------------------------------------------------------- set(FETCHCONTENT_BASE_DIR ${CMAKE_BINARY_DIR}/lib/ext CACHE STRING "" FORCE) -add_subdirectory(qcbor) -add_subdirectory(t_cose) +if(TFM_PARTITION_INITIAL_ATTESTATION) + add_subdirectory(qcbor) + add_subdirectory(t_cose) +endif() add_subdirectory(mbedcrypto) add_subdirectory(cmsis) if(BL2) From bec799426cd9549b75c34aa4a47e9a5a75c3f57b Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 20 Oct 2021 09:05:55 +0200 Subject: [PATCH 132/133] [zep noup] zephyr: module: Add zephyr module file Add zephyr module file to to include CMakeLists.txt and Kconfig located in the zephyr repository. Originally included in: 69dc29a48b707dfe732a57e05a3291ca71138eec but this will change the root folder of the module. Signed-off-by: Joakim Andersson --- zephyr/module.yml | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 zephyr/module.yml diff --git a/zephyr/module.yml b/zephyr/module.yml new file mode 100644 index 0000000000..ffb5db9890 --- /dev/null +++ b/zephyr/module.yml @@ -0,0 +1,5 @@ +name: trusted-firmware-m + +build: + cmake-ext: True + kconfig-ext: True From 1f9dd33d95853a1b4b14d67d0ea6d90c5b35cfa1 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 14 Apr 2025 16:08:22 +0300 Subject: [PATCH 133/133] [zep noup] zephyr: add CPE/PURL security info for 2.2.2 Add CPE and PURL references for use by Zephyr's SPDX generation tool. Signed-off-by: Matt Rodgers Signed-off-by: Tomi Fontanilles --- zephyr/module.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/zephyr/module.yml b/zephyr/module.yml index ffb5db9890..dba9cf3172 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -3,3 +3,8 @@ name: trusted-firmware-m build: cmake-ext: True kconfig-ext: True + +security: + external-references: + - cpe:2.3:o:arm:trusted_firmware-m:2.2.2:-:*:*:*:*:*:* + - pkg:generic/trusted-firmware-m@TF-Mv2.2.2?vcs_url=git%2Bhttps://review.trustedfirmware.org/TF-M/trusted-firmware-m