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feat!: update bindings
1 parent be33128 commit e536e9c

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15 files changed

+82
-52
lines changed

15 files changed

+82
-52
lines changed

‎bindings/dotnet/UnicornEngine/Const/Mips.fs

+4-2
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,10 @@ module Mips =
4141
let UC_CPU_MIPS64_I6500 = 9
4242
let UC_CPU_MIPS64_LOONGSON_2E = 10
4343
let UC_CPU_MIPS64_LOONGSON_2F = 11
44-
let UC_CPU_MIPS64_MIPS64DSPR2 = 12
45-
let UC_CPU_MIPS64_ENDING = 13
44+
let UC_CPU_MIPS64_LOONGSON_3A1000 = 12
45+
let UC_CPU_MIPS64_LOONGSON_3A4000 = 13
46+
let UC_CPU_MIPS64_MIPS64DSPR2 = 14
47+
let UC_CPU_MIPS64_ENDING = 15
4648

4749
// MIPS registers
4850

‎bindings/dotnet/UnicornEngine/Const/Riscv.fs

+7-5
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,17 @@ module Riscv =
1010
// RISCV32 CPU
1111

1212
let UC_CPU_RISCV32_ANY = 0
13-
let UC_CPU_RISCV32_BASE32 = 1
14-
let UC_CPU_RISCV32_SIFIVE_E31 = 2
15-
let UC_CPU_RISCV32_SIFIVE_U34 = 3
16-
let UC_CPU_RISCV32_ENDING = 4
13+
let UC_CPU_RISCV32_BASE = 1
14+
let UC_CPU_RISCV32_IBEX = 2
15+
let UC_CPU_RISCV32_SIFIVE_E31 = 3
16+
let UC_CPU_RISCV32_SIFIVE_E34 = 4
17+
let UC_CPU_RISCV32_SIFIVE_U34 = 5
18+
let UC_CPU_RISCV32_ENDING = 6
1719

1820
// RISCV64 CPU
1921

2022
let UC_CPU_RISCV64_ANY = 0
21-
let UC_CPU_RISCV64_BASE64 = 1
23+
let UC_CPU_RISCV64_BASE = 1
2224
let UC_CPU_RISCV64_SIFIVE_E51 = 2
2325
let UC_CPU_RISCV64_SIFIVE_U54 = 3
2426
let UC_CPU_RISCV64_ENDING = 4

‎bindings/go/unicorn/mips_const.go

+4-2
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,10 @@ const (
3636
CPU_MIPS64_I6500 = 9
3737
CPU_MIPS64_LOONGSON_2E = 10
3838
CPU_MIPS64_LOONGSON_2F = 11
39-
CPU_MIPS64_MIPS64DSPR2 = 12
40-
CPU_MIPS64_ENDING = 13
39+
CPU_MIPS64_LOONGSON_3A1000 = 12
40+
CPU_MIPS64_LOONGSON_3A4000 = 13
41+
CPU_MIPS64_MIPS64DSPR2 = 14
42+
CPU_MIPS64_ENDING = 15
4143

4244
// MIPS registers
4345

‎bindings/go/unicorn/riscv_const.go

+7-5
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,17 @@ const (
55
// RISCV32 CPU
66

77
CPU_RISCV32_ANY = 0
8-
CPU_RISCV32_BASE32 = 1
9-
CPU_RISCV32_SIFIVE_E31 = 2
10-
CPU_RISCV32_SIFIVE_U34 = 3
11-
CPU_RISCV32_ENDING = 4
8+
CPU_RISCV32_BASE = 1
9+
CPU_RISCV32_IBEX = 2
10+
CPU_RISCV32_SIFIVE_E31 = 3
11+
CPU_RISCV32_SIFIVE_E34 = 4
12+
CPU_RISCV32_SIFIVE_U34 = 5
13+
CPU_RISCV32_ENDING = 6
1214

1315
// RISCV64 CPU
1416

1517
CPU_RISCV64_ANY = 0
16-
CPU_RISCV64_BASE64 = 1
18+
CPU_RISCV64_BASE = 1
1719
CPU_RISCV64_SIFIVE_E51 = 2
1820
CPU_RISCV64_SIFIVE_U54 = 3
1921
CPU_RISCV64_ENDING = 4

‎bindings/java/src/main/java/unicorn/MipsConst.java

+4-2
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,10 @@ public interface MipsConst {
3838
public static final int UC_CPU_MIPS64_I6500 = 9;
3939
public static final int UC_CPU_MIPS64_LOONGSON_2E = 10;
4040
public static final int UC_CPU_MIPS64_LOONGSON_2F = 11;
41-
public static final int UC_CPU_MIPS64_MIPS64DSPR2 = 12;
42-
public static final int UC_CPU_MIPS64_ENDING = 13;
41+
public static final int UC_CPU_MIPS64_LOONGSON_3A1000 = 12;
42+
public static final int UC_CPU_MIPS64_LOONGSON_3A4000 = 13;
43+
public static final int UC_CPU_MIPS64_MIPS64DSPR2 = 14;
44+
public static final int UC_CPU_MIPS64_ENDING = 15;
4345

4446
// MIPS registers
4547

‎bindings/java/src/main/java/unicorn/RiscvConst.java

+7-5
Original file line numberDiff line numberDiff line change
@@ -7,15 +7,17 @@ public interface RiscvConst {
77
// RISCV32 CPU
88

99
public static final int UC_CPU_RISCV32_ANY = 0;
10-
public static final int UC_CPU_RISCV32_BASE32 = 1;
11-
public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
12-
public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
13-
public static final int UC_CPU_RISCV32_ENDING = 4;
10+
public static final int UC_CPU_RISCV32_BASE = 1;
11+
public static final int UC_CPU_RISCV32_IBEX = 2;
12+
public static final int UC_CPU_RISCV32_SIFIVE_E31 = 3;
13+
public static final int UC_CPU_RISCV32_SIFIVE_E34 = 4;
14+
public static final int UC_CPU_RISCV32_SIFIVE_U34 = 5;
15+
public static final int UC_CPU_RISCV32_ENDING = 6;
1416

1517
// RISCV64 CPU
1618

1719
public static final int UC_CPU_RISCV64_ANY = 0;
18-
public static final int UC_CPU_RISCV64_BASE64 = 1;
20+
public static final int UC_CPU_RISCV64_BASE = 1;
1921
public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;
2022
public static final int UC_CPU_RISCV64_SIFIVE_U54 = 3;
2123
public static final int UC_CPU_RISCV64_ENDING = 4;

‎bindings/pascal/unicorn/MipsConst.pas

+5-3
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,10 @@ interface
3939
UC_CPU_MIPS64_I6500 = 9;
4040
UC_CPU_MIPS64_LOONGSON_2E = 10;
4141
UC_CPU_MIPS64_LOONGSON_2F = 11;
42-
UC_CPU_MIPS64_MIPS64DSPR2 = 12;
43-
UC_CPU_MIPS64_ENDING = 13;
42+
UC_CPU_MIPS64_LOONGSON_3A1000 = 12;
43+
UC_CPU_MIPS64_LOONGSON_3A4000 = 13;
44+
UC_CPU_MIPS64_MIPS64DSPR2 = 14;
45+
UC_CPU_MIPS64_ENDING = 15;
4446

4547
// MIPS registers
4648

@@ -242,4 +244,4 @@ interface
242244
UC_MIPS_REG_LO3 = 48;
243245

244246
implementation
245-
end.
247+
end.

‎bindings/pascal/unicorn/RiscvConst.pas

+8-6
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,17 @@ interface
88
// RISCV32 CPU
99

1010
UC_CPU_RISCV32_ANY = 0;
11-
UC_CPU_RISCV32_BASE32 = 1;
12-
UC_CPU_RISCV32_SIFIVE_E31 = 2;
13-
UC_CPU_RISCV32_SIFIVE_U34 = 3;
14-
UC_CPU_RISCV32_ENDING = 4;
11+
UC_CPU_RISCV32_BASE = 1;
12+
UC_CPU_RISCV32_IBEX = 2;
13+
UC_CPU_RISCV32_SIFIVE_E31 = 3;
14+
UC_CPU_RISCV32_SIFIVE_E34 = 4;
15+
UC_CPU_RISCV32_SIFIVE_U34 = 5;
16+
UC_CPU_RISCV32_ENDING = 6;
1517

1618
// RISCV64 CPU
1719

1820
UC_CPU_RISCV64_ANY = 0;
19-
UC_CPU_RISCV64_BASE64 = 1;
21+
UC_CPU_RISCV64_BASE = 1;
2022
UC_CPU_RISCV64_SIFIVE_E51 = 2;
2123
UC_CPU_RISCV64_SIFIVE_U54 = 3;
2224
UC_CPU_RISCV64_ENDING = 4;
@@ -291,4 +293,4 @@ interface
291293
UC_RISCV_REG_FT11 = 189;
292294

293295
implementation
294-
end.
296+
end.

‎bindings/python/unicorn/mips_const.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,10 @@
3434
UC_CPU_MIPS64_I6500 = 9
3535
UC_CPU_MIPS64_LOONGSON_2E = 10
3636
UC_CPU_MIPS64_LOONGSON_2F = 11
37-
UC_CPU_MIPS64_MIPS64DSPR2 = 12
38-
UC_CPU_MIPS64_ENDING = 13
37+
UC_CPU_MIPS64_LOONGSON_3A1000 = 12
38+
UC_CPU_MIPS64_LOONGSON_3A4000 = 13
39+
UC_CPU_MIPS64_MIPS64DSPR2 = 14
40+
UC_CPU_MIPS64_ENDING = 15
3941

4042
# MIPS registers
4143

‎bindings/python/unicorn/riscv_const.py

+7-5
Original file line numberDiff line numberDiff line change
@@ -3,15 +3,17 @@
33
# RISCV32 CPU
44

55
UC_CPU_RISCV32_ANY = 0
6-
UC_CPU_RISCV32_BASE32 = 1
7-
UC_CPU_RISCV32_SIFIVE_E31 = 2
8-
UC_CPU_RISCV32_SIFIVE_U34 = 3
9-
UC_CPU_RISCV32_ENDING = 4
6+
UC_CPU_RISCV32_BASE = 1
7+
UC_CPU_RISCV32_IBEX = 2
8+
UC_CPU_RISCV32_SIFIVE_E31 = 3
9+
UC_CPU_RISCV32_SIFIVE_E34 = 4
10+
UC_CPU_RISCV32_SIFIVE_U34 = 5
11+
UC_CPU_RISCV32_ENDING = 6
1012

1113
# RISCV64 CPU
1214

1315
UC_CPU_RISCV64_ANY = 0
14-
UC_CPU_RISCV64_BASE64 = 1
16+
UC_CPU_RISCV64_BASE = 1
1517
UC_CPU_RISCV64_SIFIVE_E51 = 2
1618
UC_CPU_RISCV64_SIFIVE_U54 = 3
1719
UC_CPU_RISCV64_ENDING = 4

‎bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb

+4-2
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,10 @@ module UnicornEngine
3636
UC_CPU_MIPS64_I6500 = 9
3737
UC_CPU_MIPS64_LOONGSON_2E = 10
3838
UC_CPU_MIPS64_LOONGSON_2F = 11
39-
UC_CPU_MIPS64_MIPS64DSPR2 = 12
40-
UC_CPU_MIPS64_ENDING = 13
39+
UC_CPU_MIPS64_LOONGSON_3A1000 = 12
40+
UC_CPU_MIPS64_LOONGSON_3A4000 = 13
41+
UC_CPU_MIPS64_MIPS64DSPR2 = 14
42+
UC_CPU_MIPS64_ENDING = 15
4143

4244
# MIPS registers
4345

‎bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb

+7-5
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,17 @@ module UnicornEngine
55
# RISCV32 CPU
66

77
UC_CPU_RISCV32_ANY = 0
8-
UC_CPU_RISCV32_BASE32 = 1
9-
UC_CPU_RISCV32_SIFIVE_E31 = 2
10-
UC_CPU_RISCV32_SIFIVE_U34 = 3
11-
UC_CPU_RISCV32_ENDING = 4
8+
UC_CPU_RISCV32_BASE = 1
9+
UC_CPU_RISCV32_IBEX = 2
10+
UC_CPU_RISCV32_SIFIVE_E31 = 3
11+
UC_CPU_RISCV32_SIFIVE_E34 = 4
12+
UC_CPU_RISCV32_SIFIVE_U34 = 5
13+
UC_CPU_RISCV32_ENDING = 6
1214

1315
# RISCV64 CPU
1416

1517
UC_CPU_RISCV64_ANY = 0
16-
UC_CPU_RISCV64_BASE64 = 1
18+
UC_CPU_RISCV64_BASE = 1
1719
UC_CPU_RISCV64_SIFIVE_E51 = 2
1820
UC_CPU_RISCV64_SIFIVE_U54 = 3
1921
UC_CPU_RISCV64_ENDING = 4

‎bindings/rust/src/riscv.rs

+4-2
Original file line numberDiff line numberDiff line change
@@ -349,8 +349,10 @@ impl From<RegisterRISCV> for i32 {
349349
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
350350
pub enum Riscv32CpuModel {
351351
UC_CPU_RISCV32_ANY = 0,
352-
UC_CPU_RISCV32_BASE32,
352+
UC_CPU_RISCV32_BASE,
353+
UC_CPU_RISCV32_IBEX,
353354
UC_CPU_RISCV32_SIFIVE_E31,
355+
UC_CPU_RISCV32_SIFIVE_E34,
354356
UC_CPU_RISCV32_SIFIVE_U34,
355357
}
356358

@@ -370,7 +372,7 @@ impl From<&Riscv32CpuModel> for i32 {
370372
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
371373
pub enum Riscv64CpuModel {
372374
UC_CPU_RISCV64_ANY = 0,
373-
UC_CPU_RISCV64_BASE64,
375+
UC_CPU_RISCV64_BASE,
374376
UC_CPU_RISCV64_SIFIVE_E51,
375377
UC_CPU_RISCV64_SIFIVE_U54,
376378
}

‎bindings/zig/unicorn/mips_const.zig

+4-2
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,10 @@ pub const mipsConst = enum(c_int) {
3636
CPU_MIPS64_I6500 = 9,
3737
CPU_MIPS64_LOONGSON_2E = 10,
3838
CPU_MIPS64_LOONGSON_2F = 11,
39-
CPU_MIPS64_MIPS64DSPR2 = 12,
40-
CPU_MIPS64_ENDING = 13,
39+
CPU_MIPS64_LOONGSON_3A1000 = 12,
40+
CPU_MIPS64_LOONGSON_3A4000 = 13,
41+
CPU_MIPS64_MIPS64DSPR2 = 14,
42+
CPU_MIPS64_ENDING = 15,
4143

4244
// MIPS registers
4345

‎bindings/zig/unicorn/riscv_const.zig

+6-4
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,12 @@ pub const riscvConst = enum(c_int) {
55
// RISCV32 CPU
66

77
CPU_RISCV32_ANY = 0,
8-
CPU_RISCV32_BASE32 = 1,
9-
CPU_RISCV32_SIFIVE_E31 = 2,
10-
CPU_RISCV32_SIFIVE_U34 = 3,
11-
CPU_RISCV32_ENDING = 4,
8+
CPU_RISCV32_BASE = 1,
9+
CPU_RISCV32_IBEX = 2,
10+
CPU_RISCV32_SIFIVE_E31 = 3,
11+
CPU_RISCV32_SIFIVE_E34 = 4,
12+
CPU_RISCV32_SIFIVE_U34 = 5,
13+
CPU_RISCV32_ENDING = 6,
1214

1315
// RISCV64 CPU
1416

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