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topperctopperc
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fixup! Remove unnecessary freezes pointed out by nikic.
1 parent 354d1fd commit 3b50859

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3 files changed

+76
-81
lines changed

3 files changed

+76
-81
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7274,7 +7274,6 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
72747274
const APInt &FalseVal = FalseV->getAsAPIntVal();
72757275
if (~TrueVal == FalseVal) {
72767276
SDValue Neg = DAG.getNegative(CondV, DL, VT);
7277-
FalseV = DAG.getFreeze(FalseV);
72787277
return DAG.getNode(ISD::XOR, DL, VT, Neg, FalseV);
72797278
}
72807279
}
@@ -7290,14 +7289,14 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
72907289
// (select x, x, y) -> x | y
72917290
// (select !x, x, y) -> x & y
72927291
if (std::optional<bool> MatchResult = matchSetCC(LHS, RHS, CC, TrueV)) {
7293-
return DAG.getNode(*MatchResult ? ISD::OR : ISD::AND, DL, VT,
7294-
DAG.getFreeze(TrueV), DAG.getFreeze(FalseV));
7292+
return DAG.getNode(*MatchResult ? ISD::OR : ISD::AND, DL, VT, TrueV,
7293+
FalseV);
72957294
}
72967295
// (select x, y, x) -> x & y
72977296
// (select !x, y, x) -> x | y
72987297
if (std::optional<bool> MatchResult = matchSetCC(LHS, RHS, CC, FalseV)) {
7299-
return DAG.getNode(*MatchResult ? ISD::AND : ISD::OR, DL, VT,
7300-
DAG.getFreeze(TrueV), DAG.getFreeze(FalseV));
7298+
return DAG.getNode(*MatchResult ? ISD::AND : ISD::OR, DL, VT, TrueV,
7299+
FalseV);
73017300
}
73027301
}
73037302

‎llvm/test/CodeGen/RISCV/fpclamptosat.ll

Lines changed: 28 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1324,8 +1324,8 @@ define i64 @ustest_f64i64(double %x) {
13241324
; RV32IF-NEXT: # %bb.4: # %entry
13251325
; RV32IF-NEXT: li a0, 1
13261326
; RV32IF-NEXT: .LBB20_5: # %entry
1327-
; RV32IF-NEXT: lw a4, 8(sp)
1328-
; RV32IF-NEXT: lw a3, 12(sp)
1327+
; RV32IF-NEXT: lw a3, 8(sp)
1328+
; RV32IF-NEXT: lw a4, 12(sp)
13291329
; RV32IF-NEXT: and a5, a2, a1
13301330
; RV32IF-NEXT: beqz a5, .LBB20_7
13311331
; RV32IF-NEXT: # %bb.6: # %entry
@@ -1334,18 +1334,17 @@ define i64 @ustest_f64i64(double %x) {
13341334
; RV32IF-NEXT: .LBB20_7:
13351335
; RV32IF-NEXT: snez a1, a0
13361336
; RV32IF-NEXT: .LBB20_8: # %entry
1337-
; RV32IF-NEXT: and a3, a2, a3
1337+
; RV32IF-NEXT: and a4, a2, a4
13381338
; RV32IF-NEXT: or a0, a0, a5
1339-
; RV32IF-NEXT: and a2, a2, a4
1339+
; RV32IF-NEXT: and a2, a2, a3
13401340
; RV32IF-NEXT: bnez a0, .LBB20_10
13411341
; RV32IF-NEXT: # %bb.9:
1342-
; RV32IF-NEXT: snez a0, a3
1343-
; RV32IF-NEXT: snez a1, a2
1344-
; RV32IF-NEXT: or a1, a1, a0
1342+
; RV32IF-NEXT: or a0, a2, a4
1343+
; RV32IF-NEXT: snez a1, a0
13451344
; RV32IF-NEXT: .LBB20_10: # %entry
13461345
; RV32IF-NEXT: neg a1, a1
13471346
; RV32IF-NEXT: and a0, a1, a2
1348-
; RV32IF-NEXT: and a1, a1, a3
1347+
; RV32IF-NEXT: and a1, a1, a4
13491348
; RV32IF-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
13501349
; RV32IF-NEXT: addi sp, sp, 32
13511350
; RV32IF-NEXT: ret
@@ -1404,8 +1403,8 @@ define i64 @ustest_f64i64(double %x) {
14041403
; RV32IFD-NEXT: # %bb.4: # %entry
14051404
; RV32IFD-NEXT: li a0, 1
14061405
; RV32IFD-NEXT: .LBB20_5: # %entry
1407-
; RV32IFD-NEXT: lw a4, 8(sp)
1408-
; RV32IFD-NEXT: lw a3, 12(sp)
1406+
; RV32IFD-NEXT: lw a3, 8(sp)
1407+
; RV32IFD-NEXT: lw a4, 12(sp)
14091408
; RV32IFD-NEXT: and a5, a2, a1
14101409
; RV32IFD-NEXT: beqz a5, .LBB20_7
14111410
; RV32IFD-NEXT: # %bb.6: # %entry
@@ -1414,18 +1413,17 @@ define i64 @ustest_f64i64(double %x) {
14141413
; RV32IFD-NEXT: .LBB20_7:
14151414
; RV32IFD-NEXT: snez a1, a0
14161415
; RV32IFD-NEXT: .LBB20_8: # %entry
1417-
; RV32IFD-NEXT: and a3, a2, a3
1416+
; RV32IFD-NEXT: and a4, a2, a4
14181417
; RV32IFD-NEXT: or a0, a0, a5
1419-
; RV32IFD-NEXT: and a2, a2, a4
1418+
; RV32IFD-NEXT: and a2, a2, a3
14201419
; RV32IFD-NEXT: bnez a0, .LBB20_10
14211420
; RV32IFD-NEXT: # %bb.9:
1422-
; RV32IFD-NEXT: snez a0, a3
1423-
; RV32IFD-NEXT: snez a1, a2
1424-
; RV32IFD-NEXT: or a1, a1, a0
1421+
; RV32IFD-NEXT: or a0, a2, a4
1422+
; RV32IFD-NEXT: snez a1, a0
14251423
; RV32IFD-NEXT: .LBB20_10: # %entry
14261424
; RV32IFD-NEXT: neg a1, a1
14271425
; RV32IFD-NEXT: and a0, a1, a2
1428-
; RV32IFD-NEXT: and a1, a1, a3
1426+
; RV32IFD-NEXT: and a1, a1, a4
14291427
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
14301428
; RV32IFD-NEXT: addi sp, sp, 32
14311429
; RV32IFD-NEXT: ret
@@ -1596,8 +1594,8 @@ define i64 @ustest_f32i64(float %x) {
15961594
; RV32-NEXT: # %bb.4: # %entry
15971595
; RV32-NEXT: li a0, 1
15981596
; RV32-NEXT: .LBB23_5: # %entry
1599-
; RV32-NEXT: lw a4, 8(sp)
1600-
; RV32-NEXT: lw a3, 12(sp)
1597+
; RV32-NEXT: lw a3, 8(sp)
1598+
; RV32-NEXT: lw a4, 12(sp)
16011599
; RV32-NEXT: and a5, a2, a1
16021600
; RV32-NEXT: beqz a5, .LBB23_7
16031601
; RV32-NEXT: # %bb.6: # %entry
@@ -1606,18 +1604,17 @@ define i64 @ustest_f32i64(float %x) {
16061604
; RV32-NEXT: .LBB23_7:
16071605
; RV32-NEXT: snez a1, a0
16081606
; RV32-NEXT: .LBB23_8: # %entry
1609-
; RV32-NEXT: and a3, a2, a3
1607+
; RV32-NEXT: and a4, a2, a4
16101608
; RV32-NEXT: or a0, a0, a5
1611-
; RV32-NEXT: and a2, a2, a4
1609+
; RV32-NEXT: and a2, a2, a3
16121610
; RV32-NEXT: bnez a0, .LBB23_10
16131611
; RV32-NEXT: # %bb.9:
1614-
; RV32-NEXT: snez a0, a3
1615-
; RV32-NEXT: snez a1, a2
1616-
; RV32-NEXT: or a1, a1, a0
1612+
; RV32-NEXT: or a0, a2, a4
1613+
; RV32-NEXT: snez a1, a0
16171614
; RV32-NEXT: .LBB23_10: # %entry
16181615
; RV32-NEXT: neg a1, a1
16191616
; RV32-NEXT: and a0, a1, a2
1620-
; RV32-NEXT: and a1, a1, a3
1617+
; RV32-NEXT: and a1, a1, a4
16211618
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
16221619
; RV32-NEXT: addi sp, sp, 32
16231620
; RV32-NEXT: ret
@@ -1850,8 +1847,8 @@ define i64 @ustest_f16i64(half %x) {
18501847
; RV32-NEXT: # %bb.4: # %entry
18511848
; RV32-NEXT: li a0, 1
18521849
; RV32-NEXT: .LBB26_5: # %entry
1853-
; RV32-NEXT: lw a4, 8(sp)
1854-
; RV32-NEXT: lw a3, 12(sp)
1850+
; RV32-NEXT: lw a3, 8(sp)
1851+
; RV32-NEXT: lw a4, 12(sp)
18551852
; RV32-NEXT: and a5, a2, a1
18561853
; RV32-NEXT: beqz a5, .LBB26_7
18571854
; RV32-NEXT: # %bb.6: # %entry
@@ -1860,18 +1857,17 @@ define i64 @ustest_f16i64(half %x) {
18601857
; RV32-NEXT: .LBB26_7:
18611858
; RV32-NEXT: snez a1, a0
18621859
; RV32-NEXT: .LBB26_8: # %entry
1863-
; RV32-NEXT: and a3, a2, a3
1860+
; RV32-NEXT: and a4, a2, a4
18641861
; RV32-NEXT: or a0, a0, a5
1865-
; RV32-NEXT: and a2, a2, a4
1862+
; RV32-NEXT: and a2, a2, a3
18661863
; RV32-NEXT: bnez a0, .LBB26_10
18671864
; RV32-NEXT: # %bb.9:
1868-
; RV32-NEXT: snez a0, a3
1869-
; RV32-NEXT: snez a1, a2
1870-
; RV32-NEXT: or a1, a1, a0
1865+
; RV32-NEXT: or a0, a2, a4
1866+
; RV32-NEXT: snez a1, a0
18711867
; RV32-NEXT: .LBB26_10: # %entry
18721868
; RV32-NEXT: neg a1, a1
18731869
; RV32-NEXT: and a0, a1, a2
1874-
; RV32-NEXT: and a1, a1, a3
1870+
; RV32-NEXT: and a1, a1, a4
18751871
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
18761872
; RV32-NEXT: addi sp, sp, 32
18771873
; RV32-NEXT: ret

‎llvm/test/CodeGen/RISCV/iabs.ll

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -302,56 +302,56 @@ define i128 @abs128(i128 %x) {
302302
; RV32I-LABEL: abs128:
303303
; RV32I: # %bb.0:
304304
; RV32I-NEXT: lw a2, 12(a1)
305-
; RV32I-NEXT: lw a3, 0(a1)
306-
; RV32I-NEXT: lw a4, 4(a1)
305+
; RV32I-NEXT: lw a3, 4(a1)
306+
; RV32I-NEXT: lw a4, 0(a1)
307307
; RV32I-NEXT: lw a1, 8(a1)
308308
; RV32I-NEXT: bgez a2, .LBB8_2
309309
; RV32I-NEXT: # %bb.1:
310310
; RV32I-NEXT: neg a5, a1
311-
; RV32I-NEXT: snez a6, a4
312-
; RV32I-NEXT: snez a7, a3
313-
; RV32I-NEXT: or a6, a7, a6
314-
; RV32I-NEXT: sltu t0, a5, a6
311+
; RV32I-NEXT: or a6, a4, a3
312+
; RV32I-NEXT: snez a6, a6
313+
; RV32I-NEXT: sltu a7, a5, a6
315314
; RV32I-NEXT: snez a1, a1
316315
; RV32I-NEXT: add a1, a2, a1
317316
; RV32I-NEXT: neg a1, a1
318-
; RV32I-NEXT: sub a2, a1, t0
317+
; RV32I-NEXT: sub a2, a1, a7
319318
; RV32I-NEXT: sub a1, a5, a6
320-
; RV32I-NEXT: neg a4, a4
321-
; RV32I-NEXT: sub a4, a4, a7
319+
; RV32I-NEXT: snez a5, a4
322320
; RV32I-NEXT: neg a3, a3
321+
; RV32I-NEXT: sub a3, a3, a5
322+
; RV32I-NEXT: neg a4, a4
323323
; RV32I-NEXT: .LBB8_2:
324-
; RV32I-NEXT: sw a3, 0(a0)
325-
; RV32I-NEXT: sw a4, 4(a0)
324+
; RV32I-NEXT: sw a4, 0(a0)
326325
; RV32I-NEXT: sw a1, 8(a0)
326+
; RV32I-NEXT: sw a3, 4(a0)
327327
; RV32I-NEXT: sw a2, 12(a0)
328328
; RV32I-NEXT: ret
329329
;
330330
; RV32ZBB-LABEL: abs128:
331331
; RV32ZBB: # %bb.0:
332332
; RV32ZBB-NEXT: lw a2, 12(a1)
333-
; RV32ZBB-NEXT: lw a3, 0(a1)
334-
; RV32ZBB-NEXT: lw a4, 4(a1)
333+
; RV32ZBB-NEXT: lw a3, 4(a1)
334+
; RV32ZBB-NEXT: lw a4, 0(a1)
335335
; RV32ZBB-NEXT: lw a1, 8(a1)
336336
; RV32ZBB-NEXT: bgez a2, .LBB8_2
337337
; RV32ZBB-NEXT: # %bb.1:
338338
; RV32ZBB-NEXT: neg a5, a1
339-
; RV32ZBB-NEXT: snez a6, a4
340-
; RV32ZBB-NEXT: snez a7, a3
341-
; RV32ZBB-NEXT: or a6, a7, a6
342-
; RV32ZBB-NEXT: sltu t0, a5, a6
339+
; RV32ZBB-NEXT: or a6, a4, a3
340+
; RV32ZBB-NEXT: snez a6, a6
341+
; RV32ZBB-NEXT: sltu a7, a5, a6
343342
; RV32ZBB-NEXT: snez a1, a1
344343
; RV32ZBB-NEXT: add a1, a2, a1
345344
; RV32ZBB-NEXT: neg a1, a1
346-
; RV32ZBB-NEXT: sub a2, a1, t0
345+
; RV32ZBB-NEXT: sub a2, a1, a7
347346
; RV32ZBB-NEXT: sub a1, a5, a6
348-
; RV32ZBB-NEXT: neg a4, a4
349-
; RV32ZBB-NEXT: sub a4, a4, a7
347+
; RV32ZBB-NEXT: snez a5, a4
350348
; RV32ZBB-NEXT: neg a3, a3
349+
; RV32ZBB-NEXT: sub a3, a3, a5
350+
; RV32ZBB-NEXT: neg a4, a4
351351
; RV32ZBB-NEXT: .LBB8_2:
352-
; RV32ZBB-NEXT: sw a3, 0(a0)
353-
; RV32ZBB-NEXT: sw a4, 4(a0)
352+
; RV32ZBB-NEXT: sw a4, 0(a0)
354353
; RV32ZBB-NEXT: sw a1, 8(a0)
354+
; RV32ZBB-NEXT: sw a3, 4(a0)
355355
; RV32ZBB-NEXT: sw a2, 12(a0)
356356
; RV32ZBB-NEXT: ret
357357
;
@@ -384,56 +384,56 @@ define i128 @select_abs128(i128 %x) {
384384
; RV32I-LABEL: select_abs128:
385385
; RV32I: # %bb.0:
386386
; RV32I-NEXT: lw a2, 12(a1)
387-
; RV32I-NEXT: lw a3, 0(a1)
388-
; RV32I-NEXT: lw a4, 4(a1)
387+
; RV32I-NEXT: lw a3, 4(a1)
388+
; RV32I-NEXT: lw a4, 0(a1)
389389
; RV32I-NEXT: lw a1, 8(a1)
390390
; RV32I-NEXT: bgez a2, .LBB9_2
391391
; RV32I-NEXT: # %bb.1:
392392
; RV32I-NEXT: neg a5, a1
393-
; RV32I-NEXT: snez a6, a4
394-
; RV32I-NEXT: snez a7, a3
395-
; RV32I-NEXT: or a6, a7, a6
396-
; RV32I-NEXT: sltu t0, a5, a6
393+
; RV32I-NEXT: or a6, a4, a3
394+
; RV32I-NEXT: snez a6, a6
395+
; RV32I-NEXT: sltu a7, a5, a6
397396
; RV32I-NEXT: snez a1, a1
398397
; RV32I-NEXT: add a1, a2, a1
399398
; RV32I-NEXT: neg a1, a1
400-
; RV32I-NEXT: sub a2, a1, t0
399+
; RV32I-NEXT: sub a2, a1, a7
401400
; RV32I-NEXT: sub a1, a5, a6
402-
; RV32I-NEXT: neg a4, a4
403-
; RV32I-NEXT: sub a4, a4, a7
401+
; RV32I-NEXT: snez a5, a4
404402
; RV32I-NEXT: neg a3, a3
403+
; RV32I-NEXT: sub a3, a3, a5
404+
; RV32I-NEXT: neg a4, a4
405405
; RV32I-NEXT: .LBB9_2:
406-
; RV32I-NEXT: sw a3, 0(a0)
407-
; RV32I-NEXT: sw a4, 4(a0)
406+
; RV32I-NEXT: sw a4, 0(a0)
408407
; RV32I-NEXT: sw a1, 8(a0)
408+
; RV32I-NEXT: sw a3, 4(a0)
409409
; RV32I-NEXT: sw a2, 12(a0)
410410
; RV32I-NEXT: ret
411411
;
412412
; RV32ZBB-LABEL: select_abs128:
413413
; RV32ZBB: # %bb.0:
414414
; RV32ZBB-NEXT: lw a2, 12(a1)
415-
; RV32ZBB-NEXT: lw a3, 0(a1)
416-
; RV32ZBB-NEXT: lw a4, 4(a1)
415+
; RV32ZBB-NEXT: lw a3, 4(a1)
416+
; RV32ZBB-NEXT: lw a4, 0(a1)
417417
; RV32ZBB-NEXT: lw a1, 8(a1)
418418
; RV32ZBB-NEXT: bgez a2, .LBB9_2
419419
; RV32ZBB-NEXT: # %bb.1:
420420
; RV32ZBB-NEXT: neg a5, a1
421-
; RV32ZBB-NEXT: snez a6, a4
422-
; RV32ZBB-NEXT: snez a7, a3
423-
; RV32ZBB-NEXT: or a6, a7, a6
424-
; RV32ZBB-NEXT: sltu t0, a5, a6
421+
; RV32ZBB-NEXT: or a6, a4, a3
422+
; RV32ZBB-NEXT: snez a6, a6
423+
; RV32ZBB-NEXT: sltu a7, a5, a6
425424
; RV32ZBB-NEXT: snez a1, a1
426425
; RV32ZBB-NEXT: add a1, a2, a1
427426
; RV32ZBB-NEXT: neg a1, a1
428-
; RV32ZBB-NEXT: sub a2, a1, t0
427+
; RV32ZBB-NEXT: sub a2, a1, a7
429428
; RV32ZBB-NEXT: sub a1, a5, a6
430-
; RV32ZBB-NEXT: neg a4, a4
431-
; RV32ZBB-NEXT: sub a4, a4, a7
429+
; RV32ZBB-NEXT: snez a5, a4
432430
; RV32ZBB-NEXT: neg a3, a3
431+
; RV32ZBB-NEXT: sub a3, a3, a5
432+
; RV32ZBB-NEXT: neg a4, a4
433433
; RV32ZBB-NEXT: .LBB9_2:
434-
; RV32ZBB-NEXT: sw a3, 0(a0)
435-
; RV32ZBB-NEXT: sw a4, 4(a0)
434+
; RV32ZBB-NEXT: sw a4, 0(a0)
436435
; RV32ZBB-NEXT: sw a1, 8(a0)
436+
; RV32ZBB-NEXT: sw a3, 4(a0)
437437
; RV32ZBB-NEXT: sw a2, 12(a0)
438438
; RV32ZBB-NEXT: ret
439439
;

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