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1 parent 0bd9255 commit 284b3caCopy full SHA for 284b3ca
llvm/test/CodeGen/RISCV/pr84200.ll
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
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+
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+; The sub nuw produces poison if the input is not 0 or 1. We must insert a
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+; freeze before converting the sub to AND so that we don't propagate poison.
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+define i64 @foo(i64 %1) {
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+; CHECK-LABEL: foo:
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+; CHECK: # %bb.0: # %entry
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+; CHECK-NEXT: li a1, 1
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+; CHECK-NEXT: sub a1, a1, a0
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+; CHECK-NEXT: sltiu a0, a0, 2
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+; CHECK-NEXT: not a0, a0
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+; CHECK-NEXT: xori a1, a1, 1
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+; CHECK-NEXT: addi a0, a0, -1
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+; CHECK-NEXT: and a0, a0, a1
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+; CHECK-NEXT: ret
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+entry:
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+ %.urem.i = sub nuw i64 1, %1
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+ %.cmp.i = icmp ugt i64 %1, 1
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+ %2 = xor i64 %.urem.i, 1
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+ %3 = select i1 %.cmp.i, i64 0, i64 %2
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+ ret i64 %3
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+}
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